A membrane potential processing method, chip, device, and storage medium

Abstract

The application provides a membrane potential processing method, a chip, a device and a storage medium. The method can be applied to a chip. The chip simulates at least one neuron through at least one computing core included in the chip. The method can comprise: obtaining a synaptic weight of each neuron in the at least one neuron; in the process of obtaining the synaptic weight, obtaining a pre-calculated potential based on a corresponding leakage voltage of the neuron and a first membrane potential determined in a previous membrane potential determination period; and obtaining a second membrane potential of the neuron in a current membrane potential determination period based on the pre-calculated potential and the synaptic weight.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a membrane potential processing method, a chip, a device and a storage medium. BACKGROUND

[0002] In some chips (for example, neuromorphic chips), neurons can be used for neuron networks. The neuron networks include a plurality of neurons, and at least part of the neurons can be connected and communicated with each other through synapses. In such chips, the membrane potential of each neuron needs to be determined periodically.

[0003] In the process of determining the membrane potential of a neuron at a certain time, an input voltage can be obtained based on the synaptic weight and the stimulation voltage (or the voltage after the stimulation voltage is transformed) sent by other neurons connected through synapses, and then a correlation calculation is performed on the first membrane potential determined in the last period and the leakage voltage to obtain the membrane potential. It can be seen that the determination process of the membrane potential is a serial process, and the determination efficiency is low, which affects the performance of the chip. SUMMARY

[0004] Therefore, the present application discloses a membrane potential processing method applied to a chip. The chip simulates at least one neuron through at least one computing core included in the chip. The method can include: obtaining the synaptic weight of each neuron in the at least one neuron; in the process of obtaining the synaptic weight, obtaining a pre-computed potential based on the leakage voltage corresponding to the neuron and the first membrane potential determined in the last membrane potential determination period; and obtaining a second membrane potential of the neuron in the current membrane potential determination period based on the pre-computed potential and the synaptic weight.

[0005] In some embodiments, the synaptic weight is stored in an off-chip storage space corresponding to the chip; and the obtaining of the synaptic weight of each neuron in the at least one neuron includes: obtaining the synaptic weight of each neuron in the at least one neuron from the off-chip storage space.

[0006] In some embodiments, the obtaining of the second membrane potential of the neuron in the current membrane potential determination period based on the pre-computed potential and the synaptic weight includes: in response to the neuron receiving a stimulation voltage sent by other neurons connected through synapses, performing a weighting process on the stimulation voltage based on the synaptic weight to obtain an input voltage received by the neuron in the current membrane potential determination period; and obtaining the second membrane potential based on the input voltage and the pre-computed potential.

[0007] In some embodiments, the determining the second membrane potential of the neuron in the current membrane potential determination period based on the pre-computed potential and the synaptic weight comprises: in response to the neuron not receiving a stimulation voltage sent by another neuron, determining the pre-computed potential as the second membrane potential.

[0008] In some embodiments, the neuron is a neuron in a preset neural network; after the second membrane potential is determined, the method further comprises: updating packet body data of a data packet based on the second membrane potential; the data packet is used to transmit a membrane potential; in response to a potential value indicated by the packet body data being greater than a release threshold of the neuron, generating a stimulation signal based on the data packet and sending the stimulation signal to a neuron following the neuron in the preset neural network.

[0009] The application also provides a chip, which simulates at least one neuron through at least one computing core included in the chip; wherein the computing core is configured to acquire a synaptic weight of each neuron in the at least one neuron; in the process of acquiring the synaptic weight, a pre-computed potential is obtained based on a leakage voltage corresponding to the neuron and a first membrane potential determined in a previous membrane potential determination period; and a second membrane potential of the neuron in a current membrane potential determination period is obtained based on the pre-computed potential and the synaptic weight.

[0010] The application also provides an electronic device. The electronic device comprises a chip. The chip simulates at least one neuron through at least one computing core included in the chip; the computing core is configured to acquire a synaptic weight of each neuron in the at least one neuron; in the process of acquiring the synaptic weight, a pre-computed potential is obtained based on a leakage voltage corresponding to the neuron and a first membrane potential determined in a previous membrane potential determination period; and a second membrane potential of the neuron in a current membrane potential determination period is obtained based on the pre-computed potential and the synaptic weight. The application also provides a storage medium, which stores a program for causing a chip to execute a membrane potential processing method as shown in any one of the preceding embodiments.

[0011] In the scheme as shown in any one of the preceding embodiments, in the process of acquiring the synaptic weight, a pre-computed potential is obtained based on the acquired leakage voltage corresponding to the neuron and the first membrane potential determined in the previous membrane potential determination period, and then the membrane potential of the neuron is determined based on the pre-computed potential and the acquired synaptic weight, so that the time period for acquiring the synaptic weight is used to compute the pre-computed potential, achieving the purpose of parallel processing of acquiring the synaptic weight and computing the pre-computed potential, fully utilizing the processing capacity of the chip, reducing the waiting time, improving the membrane potential determination efficiency, and improving the performance of the chip.

[0012] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application, as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the one or more embodiments or the related art, the drawings needed to be used in the embodiment or the related art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the one or more embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0014] Figure 1 A method flow chart of a membrane potential processing method shown in an embodiment of the present application;

[0015] Figure 2 A flow chart of a membrane potential determination method shown in an embodiment of the present application. DETAILED DESCRIPTION

[0016] The exemplary embodiments will be described in detail herein below with reference to the drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments are not meant to represent all implementations in keeping with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0017] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0018] The present application proposes a membrane potential processing method. In the method, the time period for obtaining the synaptic weight is utilized to calculate the pre-computed potential according to the leakage voltage and the first membrane potential determined in the previous period, so as to achieve the parallel processing of obtaining the synaptic weight and calculating the pre-computed potential, fully utilize the chip processing capacity, reduce the waiting time, improve the membrane potential determination efficiency, and improve the chip performance.

[0019] Please refer to Figure 1 , Figure 1A method flowchart of a membrane potential processing method is shown in the embodiments of the present application. As shown in Figure 1 The method can be applied to a chip. The chip simulates at least one neuron through at least one computing core included in the chip. In some embodiments, the chip can be an AI chip. The AI chip can be a neuromorphic chip (brain-like chip). The chip can be a many-core chip. Each computing core in the many-core chip can simulate at least one neuron.

[0020] The method can include S102-S106.

[0021] In S102, synaptic weights of each neuron in the at least one neuron are obtained.

[0022] The neuron can be connected to other neurons through synapses. The synaptic weight refers to a weight assigned to a synapse connected to the neuron. The weight can be pre-set or obtained through neural network training as a parameter of the neural network. The other neurons can be one or more neurons. The other neurons can be neurons simulated by the chip or other chips.

[0023] The synaptic weight can be stored in a pre-set storage space. The storage space can be a storage space inside the chip or a storage space outside the chip (referred to as off-chip storage space).

[0024] In some embodiments, in S102, the synaptic weight corresponding to the neuron can be obtained from the storage space.

[0025] In some embodiments, the storage space can be an off-chip storage space, and in S102, the synaptic weight of each neuron in the at least one neuron can be obtained from the off-chip storage space. By storing the synaptic weight off-chip, the chip storage space can be released, and the performance of the chip can be improved.

[0026] In S104, during the obtaining of the synaptic weight, a pre-computed potential is obtained based on a leak voltage corresponding to the neuron and a first membrane potential determined in a previous membrane potential determination period.

[0027] The leak voltage is a voltage value for leaking the membrane potential in the membrane potential determination period. For example, it can be a fixedly set voltage value. Alternatively, it can be a voltage value determined in combination with a leak rate and a leak duration. The leak rate is a pre-set constant related to the type of neuron. In S104, the leak rate can be obtained from the space in combination with the leak duration to obtain the leak voltage, or a pre-set value corresponding to the leak voltage can be directly obtained.

[0028] The chip is usually provided with a preset length of time segment, and the clock triggers the determination of the membrane potential of the neuron every time the time segment runs. One time segment corresponds to one membrane potential determination period. The membrane potential determined in each period can be stored in the preset space of the chip. In S104, the first membrane potential can be obtained from the preset space.

[0029] In some embodiments, after obtaining the leakage voltage and the first membrane potential, the difference between the first membrane potential and the leakage voltage can be determined as the pre-computed potential when determining the membrane potential in the current period.

[0030] In S106, the second membrane potential of the neuron in the current membrane potential determination period is obtained based on the pre-computed potential and the synaptic weight.

[0031] In S106, the input voltage received by the neuron can be determined according to the synaptic weight and the stimulation signal (pulse signal) received by the neuron from other neurons. The sum of the input voltage and the pre-computed potential obtained in S104 is determined as the second membrane potential. The other neurons refer to one or more neurons connected to the neuron through synapses. These other neurons can come from the same chip or other chips.

[0032] It should be noted that the first membrane potential refers to the membrane potential determined in the previous period, and the second membrane potential refers to the membrane potential in the current period. The first membrane potential and the second membrane potential are relative concepts. The second membrane potential determined in the current period will be referred to as the first membrane potential in the next period.

[0033] In the foregoing scheme, in the process of obtaining the synaptic weight, the pre-computed potential is obtained based on the leakage voltage corresponding to the neuron and the first membrane potential determined in the previous membrane potential determination period, and then the membrane potential of the neuron is determined based on the pre-computed potential and the obtained synaptic weight, so as to calculate the pre-computed potential by using the time period of obtaining the synaptic weight, so as to achieve the parallel processing of obtaining the synaptic weight and calculating the pre-computed potential, fully utilize the processing capacity of the chip, reduce the waiting time, improve the membrane potential determination efficiency, and improve the performance of the chip.

[0034] In some embodiments, in order to save the computing resources of the chip and improve the performance of the chip, different ways can be used to determine the second membrane potential in S106 according to whether the neuron receives stimulation from other neurons.

[0035] Please refer to Figure 2 , Figure 2 A flowchart of a membrane potential determination method according to an embodiment of the present application is shown. Figure 2The method shown is a detailed description of S106. As shown in Figure 2 The method shown can include S202-S206.

[0036] S202, in response to the neuron receiving a stimulation voltage sent by another neuron connected through a synapse, weighting the stimulation voltage based on the synaptic weight to obtain an input voltage received by the neuron in a current membrane potential determination period.

[0037] In some embodiments, the stimulation voltage can be a pulse voltage, and some corresponding processing can be performed on the stimulation voltage to obtain a calculable voltage. For example, the pulse voltage can be integrated to obtain an integral voltage. Then, the input voltage can be obtained by weighting and summing the stimulation voltages according to the synaptic weights corresponding to the stimulation voltages, respectively.

[0038] S204, obtaining the second membrane potential based on the input voltage and the pre-computed potential.

[0039] In some embodiments, the sum of the input voltage and the pre-computed potential can be determined as the second membrane potential. In this way, the current membrane potential can be accurately obtained when the neuron is stimulated by another neuron.

[0040] S206, in response to the neuron not receiving the stimulation voltage sent by the other neuron, determining the pre-computed potential as the second membrane potential. In this way, when the neuron is not stimulated by another neuron, the input voltage does not need to be calculated, saving the chip computing resources and improving the chip performance.

[0041] In some embodiments, after obtaining the second membrane potential through S102-S106, the second membrane potential can also be stored. In some embodiments, the chip can pre-allocate a membrane potential storage space corresponding to the neuron. The chip can store the second membrane potential in the storage space.

[0042] In some embodiments, the neuron is one neuron in a neural network. The chip (computing core) can include a data packet for transmitting the membrane potential. The chip can update the packet body data of the data packet based on the second membrane potential. In response to the potential value indicated by the packet body data being greater than the release threshold of the neuron, a stimulation signal is generated based on the data packet and sent to a neuron following the neuron in the preset neural network.

[0043] The preset neural network can be formed by a plurality of neurons connected together, and the neurons can have a connection direction. In a case where it is determined that the current membrane potential of the neuron is greater than a release threshold, a stimulation signal (pulse signal) can be generated based on the data packet to the neuron after the neuron, so as to form a stimulation. The neurons can come from the chip or other chips. In this way, the signal is transmitted in the neural network.

[0044] The following will be described in conjunction with a scenario of determining the membrane potential of the brain-like chip.

[0045] The brain-like chip can include 128 computing cores. Each computing core can simulate 1024 neurons. The neurons can be neurons in a spiking neuron network (SNN). The neurons can be connected through synapses. The chip can also allocate a storage space for each neuron. The chip can also include an off-chip storage space, which can store the synaptic weights of the SNN obtained through training.

[0046] The brain-like chip can periodically determine the current membrane potential of each neuron contained therein and store it. The following will be described by taking the determination of the membrane potential of the neuron in the brain-like chip in the current period as an example.

[0047] The brain-like chip can obtain the synaptic weights corresponding to the neuron from the off-chip storage space.

[0048] In the process of obtaining the synaptic weights, the brain-like chip can also obtain the leakage voltage corresponding to the neuron and the membrane potential determined in the previous period from the on-chip storage space based on the correspondence between the neuron type of the neuron and the foregoing correspondence. Then, the difference between the obtained membrane potential in the previous period and the leakage voltage is used to obtain a pre-computed potential.

[0049] In a case where the synaptic weights are obtained, if the neuron is stimulated by other neurons, the input voltage can be obtained by weighting and summing the stimulation signals according to the obtained synaptic weights, and then the membrane potential of the neuron in the current period can be obtained by summing the pre-computed potential.

[0050] If the neuron is not stimulated, the pre-computed potential can be directly determined as the membrane potential of the neuron in the current period.

[0051] In this example, the pre-computed potential can be calculated using the time period for obtaining the synaptic weights, so as to achieve the purpose of parallel processing of obtaining the synaptic weights and calculating the pre-computed potential, fully utilize the processing capacity of the chip, reduce the waiting time, improve the efficiency of determining the membrane potential, and improve the performance of the chip.

[0052] The application further provides a chip. The chip simulates at least one neuron through at least one computing core included in the chip; wherein the computing core is configured to obtain a synaptic weight of each neuron in the at least one neuron; in the process of obtaining the synaptic weight, a pre-computed potential is obtained based on a leakage voltage corresponding to the neuron and a first membrane potential determined in a previous membrane potential determination period; and a second membrane potential of the neuron in a current membrane potential determination period is obtained based on the pre-computed potential and the synaptic weight.

[0053] In the process of obtaining the synaptic weight, a pre-computed potential is obtained based on a leakage voltage corresponding to the neuron and a first membrane potential determined in a previous membrane potential determination period.

[0054] A second membrane potential of the neuron in a current membrane potential determination period is obtained based on the pre-computed potential and the synaptic weight.

[0055] Therefore, the pre-computed potential can be calculated based on the leakage voltage and the first membrane potential determined in the previous period in the time period of obtaining the synaptic weight, so that the purpose of parallel processing of obtaining the synaptic weight and calculating the pre-computed potential is achieved, the processing capability of the chip is fully utilized, the waiting time is reduced, the membrane potential determination efficiency is improved, and the performance of the chip is improved.

[0056] The computing core can also perform the membrane potential processing method shown in any of the preceding embodiments, which will not be described in detail here.

[0057] The application further provides an electronic device. The electronic device includes a chip. The chip simulates at least one neuron through at least one computing core included in the chip; the computing core is configured to obtain a synaptic weight of each neuron in the at least one neuron; in the process of obtaining the synaptic weight, a pre-computed potential is obtained based on a leakage voltage corresponding to the neuron and a first membrane potential determined in a previous membrane potential determination period; and a second membrane potential of the neuron in a current membrane potential determination period is obtained based on the pre-computed potential and the synaptic weight.

[0058] The application provides a storage medium. The storage medium stores a program. The program is configured to enable a chip to perform the membrane potential processing method shown in any of the preceding embodiments.

[0059] Those skilled in the art should understand that one or more embodiments of the application can be provided as a method, a system or a computer program product. Therefore, one or more embodiments of the application can be in the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, one or more embodiments of the application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, optical storage, etc.) containing computer usable program code.

[0060] In the present application, "and / or" means at least one of the two, for example, "A and / or B" includes three schemes: A, B, and "A and B".

[0061] The various embodiments in this disclosure are described in a progressive manner, and the same or similar parts among the various embodiments can be mutually referred to. Each embodiment focuses on the differences from other embodiments. In particular, the data processing device embodiments are described relatively simply because they are substantially similar to the method embodiments, and the relevant parts can be referred to the description of the method embodiments.

[0062] The specific embodiments of the disclosure have been described. Other embodiments are within the scope of the following claims. In some cases, acts or steps recited in the claims can be performed in a different order than the order in which the acts or steps are recited in the embodiments. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0063] Embodiments of the subject matter and the functional operations described in this disclosure can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory program carrier for execution by, or to control the operation of, data processing apparatus. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0064] The processes and logic flows described in this disclosure can be performed by one or more programmable computers executing one or more computer programs to perform the functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), and the apparatus can also be implemented as special purpose logic circuitry.

[0065] Computers suitable for the execution of a computer program include, by way of example, general and / or special purpose microprocessors, or any other kind of central processing system. Generally, a central processing unit will receive instructions and data from a read-only memory and / or a random access memory. The essential elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name just a few.

[0066] Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0067] While this application contains many specific embodiments, these should not be construed as limiting the scope of any disclosures or claims hereof, but rather as merely describing features that can be included in some embodiments. Some features described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented in multiple embodiments or in any suitable sub-combination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a sub-combination or variation of a sub-combination.

[0068] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such order, nor that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system modules and components in the embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged into multiple software products.

[0069] Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0070] The above descriptions are only the preferred embodiment of one or more embodiments of the application, and are not intended to limit one or more embodiments of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the application shall be included in the protection scope of one or more embodiments of the application.

Claims

1. A membrane potential processing method, applied to a chip, characterized in that, The chip simulates at least one neuron through at least one computational core it includes, the method comprising: Obtain the synaptic weights of each neuron in the at least one neuron; In the process of obtaining the synaptic weight, a pre-calculated potential is obtained based on the leakage voltage corresponding to the neuron and the first membrane potential determined in the previous membrane potential determination cycle; Based on the pre-calculated potential and the synaptic weight, the second membrane potential of the neuron in the current membrane potential determination cycle is obtained; The step of obtaining the second membrane potential of the neuron in the current membrane potential determination cycle based on the pre-calculated potential and the synaptic weight includes: In response to the neuron not receiving stimulation voltages from other neurons, the pre-calculated potential is determined as the second membrane potential.

2. The method according to claim 1, characterized in that, The synaptic weights are stored in the off-chip memory space corresponding to the chip; The step of obtaining the synaptic weight of each neuron in the at least one neuron includes: The synaptic weights of each neuron in the at least one neuron are obtained from the off-chip storage space.

3. The method according to claim 1, characterized in that, The step of obtaining the second membrane potential of the neuron in the current membrane potential determination cycle based on the pre-calculated potential and the synaptic weight includes: In response to the neuron receiving a stimulation voltage from other neurons connected via synapses, the stimulation voltage is weighted based on the synaptic weights to obtain the input voltage received by the neuron in the current membrane potential determination period; The second membrane potential is obtained based on the input voltage and the pre-calculated potential.

4. The method according to any one of claims 1-3, characterized in that, The neuron is a neuron in a pre-defined neural network; After determining the second membrane potential, the method further includes: Based on the second membrane potential, the packet body data of the data packet is updated; the data packet is used to transmit the membrane potential. In response to the potential value indicated by the packet data being greater than the release threshold of the neuron, a stimulation signal is generated based on the packet data and sent to the neuron following the neuron in the preset neural network.

5. A chip, characterized in that, The chip simulates at least one neuron through at least one computational core it includes; wherein, The computational kernel is used to obtain the synaptic weights of each neuron in the at least one neuron; In the process of obtaining the synaptic weight, a pre-calculated potential is obtained based on the leakage voltage corresponding to the neuron and the first membrane potential determined in the previous membrane potential determination cycle; Based on the pre-calculated potential and the synaptic weight, the second membrane potential of the neuron in the current membrane potential determination cycle is obtained.

6. An electronic device, characterized in that, The electronic device includes a chip; wherein the chip simulates at least one neuron through at least one computing core included therein; The computational kernel is used to obtain the synaptic weight of each neuron in the at least one neuron; in the process of obtaining the synaptic weight, a pre-calculated potential is obtained based on the leakage voltage corresponding to the neuron and the first membrane potential determined in the previous membrane potential determination cycle; based on the pre-calculated potential and the synaptic weight, the second membrane potential of the neuron in the current membrane potential determination cycle is obtained. The step of obtaining the second membrane potential of the neuron in the current membrane potential determination cycle based on the pre-calculated potential and the synaptic weight includes: In response to the neuron not receiving stimulation voltages from other neurons, the pre-calculated potential is determined as the second membrane potential.

7. A storage medium, characterized in that, The storage medium stores a program for causing the chip to perform the membrane potential processing method as described in any one of claims 1-4.

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