Driving circuit, array substrate and display panel of display panel
By adjusting the connection order and routing of the clock signal lines, the display abnormality caused by excessive temperature in the WOA area of the LCD panel was resolved, achieving the effects of reducing temperature and improving display stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HKC CORP LTD
- Filing Date
- 2023-04-27
- Publication Date
- 2026-07-03
AI Technical Summary
LCD panels with traditional WOA (Wireless Oscillator) routing designs suffer from display abnormalities due to excessively high temperatures.
By adjusting the connection order of the external clock signal lines on the panel and correspondingly adjusting the routing order of the WOA and GDL areas inside the panel, the high-level overlap time between adjacent clock signal lines is made less than the preset time.
This effectively reduces heat accumulation in the WOA area, lowers the overall temperature, avoids display abnormalities, and improves the display stability of the LCD panel.
Smart Images
Figure CN116434716B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more particularly to driving circuits, array substrates, and display panels for display panels. Background Technology
[0002] In an LCD panel (Liquid Crystal Display), the lines connecting the driving COF (Chip On Film) and GDL (Gate Driver Less) regions are called WOA (Wire On Array) traces.
[0003] Currently, LCD panels based on traditional WOA (Wireless Oscillator) routing designs sometimes experience display abnormalities due to excessively high temperatures in the WOA area. Summary of the Invention
[0004] The main objective of this application is to provide a driving circuit, array substrate, and display panel for a display panel, aiming to solve the technical problem of how to reduce the overall temperature of the WOA area and avoid display abnormalities.
[0005] To achieve the above objectives, embodiments of this application provide a driving circuit for a display panel, the driving circuit for the display panel comprising:
[0006] The timing control module includes multiple first interfaces, each of which is used to output scan clock signals in a first order.
[0007] A clock signal line group, the clock signal line group comprising multiple clock signal lines, each of the first interfaces being connected one-to-one to one end of each of the clock signal lines in the first order;
[0008] The scanning driver module includes a second interface with the same number as the first interface. The second interface is used to receive the scanning clock signal. Each second interface is connected one-to-one to the other end of each clock signal line in a second order. There are at least two sets of first and second interfaces with alternating wiring orders in the first and second orders, so that the high-level overlap time between adjacent clock signal lines at the second interface is less than a preset time.
[0009] Optionally, the first interface is the first output starting first interface in a preset timing sequence, and is connected to the first input starting second interface in the second interface via the clock signal line.
[0010] Optionally, the scanning driving module includes:
[0011] An array of traces, comprising the same number of array traces as the second interface, wherein each array trace is connected one-to-one to each of the second interfaces in the second order, such that the high-level overlap time between adjacent array traces is less than a preset time.
[0012] A gate driving unit, wherein the gate driving unit is connected to the array trace group in the first order.
[0013] Optionally, when the scan clock signal is represented by CK, the first order of outputting the scan clock signal is CK1, CK2, CK3, ..., CKn, where n is the number of the first interface, the clock signal line and the second interface, and n is an integer greater than or equal to 4.
[0014] Optionally, when the number of the first interface, the clock signal line and the second interface is 8, the first sequence is CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8.
[0015] Optionally, the second sequence is CK1, CK4, CK7, CK2, CK5, CK8, CK3, CK6.
[0016] Optionally, when the number of the first interface, the clock signal line and the second interface is 16, the first sequence is CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, CK9, CK10, CK11, CK12, CK13, CK14, CK15, CK16.
[0017] In addition, to achieve the above objectives, this application embodiment also provides an array substrate, which includes an effective display area and an ineffective display area, the ineffective display area surrounding the periphery of the effective display area, and the driving circuit of the display panel as described above is disposed in the ineffective display area of the array substrate.
[0018] In addition, to achieve the above objectives, this application embodiment also provides a display panel, the display panel comprising: a color filter substrate, a liquid crystal layer and an array substrate as described above, wherein the liquid crystal layer is disposed between the array substrate and the color filter substrate.
[0019] This application provides a driving circuit, array substrate, and display panel for a display panel. The driving circuit includes: a timing control module comprising multiple first interfaces, each first interface being used to output a scan clock signal in a first order; a clock signal line group comprising multiple clock signal lines, each of the first interfaces being connected one-to-one to one end of each clock signal line in the first order; and a scan driving module comprising the same number of second interfaces as the first interfaces, the second interfaces being used to receive the scan clock signal, each of the second interfaces being connected one-to-one to the other end of each clock signal line in a second order. At least two sets of first and second interfaces with alternating wiring sequences exist, such that the high-level overlap time between adjacent clock signal lines at the second interface is less than a preset time. This application, by changing the connection order of the external clock signal lines and correspondingly adjusting the routing order of the WOA area and GDL area inside the panel, can effectively reduce the heat accumulation of adjacent clock signal lines, lower the overall temperature of the WOA, and thus avoid display abnormalities that may occur with traditional WOA design methods in related technologies. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only a part of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 A schematic diagram of the structure of a driving circuit for a display panel provided in an embodiment of this application;
[0022] Figure 2 A schematic diagram of the structure of a scanning driving module involved in a driving circuit of a display panel provided in an embodiment of this application;
[0023] Figure 3 A schematic diagram comparing the signal pulse periods of a first sequence involved in a driving circuit for a display panel according to an embodiment of this application;
[0024] Figure 4 A schematic diagram comparing the signal pulse periods of a second sequence involved in a driving circuit for a display panel, provided as an embodiment of this application;
[0025] Figure 5 This is a schematic diagram of the structure of an array substrate provided in one embodiment of this application;
[0026] Figure 6This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.
[0027] Explanation of icon numbers:
[0028]
[0029] Detailed Implementation
[0030] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that the embodiments of this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the embodiments of this application with unnecessary detail.
[0031] It should be noted that although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0032] It should also be understood that references to "one embodiment" or "some embodiments" in the specification of embodiments of this application mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0033] Currently, the traditional WOA (Wave Area) routing design in related technologies is as follows: the CK (clock) signal lines are arranged in sequence. When a CK pulse signal is input, the CK signal lines generate heat under the action of current, and the pulse overlap area of adjacent CK signal lines is large (i.e., they are simultaneously in a high-level state for a long time). This causes adjacent CK lines to heat up at the same time, resulting in heat accumulation. Consequently, the temperature of the WOA area becomes too high. In severe cases, this can lead to liquid crystal polarization and cause abnormal display of the LCD panel.
[0034] Based on this, this application provides a driving circuit, array substrate, and display panel for a display panel. The driving circuit of the display panel includes: a timing control module, which includes multiple first interfaces, each first interface being used to output a scan clock signal in a first order; a clock signal line group, which includes multiple clock signal lines, with each first interface connected one end of each clock signal line in the first order; and a scan driving module, which includes the same number of second interfaces as the first interfaces, the second interfaces being used to receive the scan clock signal, and each second interface connected one end of each clock signal line in a second order. At least two sets of first and second interfaces with interleaved wiring sequences exist, such that the high-level overlap time between adjacent clock signal lines at the second interface is less than a preset time. This application, by changing the connection order of the clock signal lines outside the panel and correspondingly adjusting the routing order of the WOA area and GDL area inside the panel, can effectively reduce the heat accumulation of adjacent clock signal lines, lower the overall temperature of the WOA, and thus avoid display abnormalities that may be caused by traditional WOA design methods in related technologies.
[0035] The driving circuit, array substrate, and display panel provided in this application embodiment are specifically described through the following embodiments. First, the driving circuit of the display panel in this application embodiment is described.
[0036] This application provides a driving circuit for a display panel, referring to... Figure 1 , Figure 1 This is a schematic diagram of a driving circuit for a display panel according to an embodiment of this application. In this embodiment, the driving circuit for the display panel includes:
[0037] The timing control module 01 includes a plurality of first interfaces 011, each of which is used to output a scan clock signal in a first order.
[0038] Clock signal line group 02, the clock signal line group 02 includes multiple clock signal lines, and each of the first interfaces 011 is connected to one end of each clock signal line in the first order;
[0039] The scanning driver module 03 includes a second interface 031 with the same number as the first interface 011. The second interface 031 is used to receive the scanning clock signal. Each second interface 031 is connected one-to-one to the other end of each clock signal line in a second order. There are at least two sets of first interface 011 and second interface 031 with alternating wiring orders in the first order and the second order, so that the high-level overlap time between adjacent clock signal lines at the second interface 031 is less than a preset time.
[0040] It should be noted that in this embodiment, the output timing of the timing control module 01 is not changed. The timing control module 01 still generates the scan clock signal according to the default output timing. Based on this, it can be known that the phase difference between adjacent scan clock signals is equal. The clock signal line group 02 includes multiple signal lines for transmitting scan clock signals connected between the timing control module 01 and the scan drive module 03. Figure 1 As can be seen, in this embodiment, both the timing control module 01 and the scan drive module 03 show the same number of data interfaces. In related technologies, the interface numbers connected to both ends of the clock signal line group 02 are completely consistent, i.e., the first first interface 011 of the timing control module 01 is connected to the first second interface 031 of the scan drive module 03, the second first interface 011 of the timing control module 01 is connected to the second second interface 031 of the scan drive module 03, and the last first interface 011 of the timing control module 01 is connected to the last second interface 031 of the scan drive module 03. However, in this embodiment, the order in which the clock signal line group 02 connects to the timing control module 01 and the scan drive module 03 is changed, so that the high-level overlap time between adjacent clock signal lines at the second interface 031 is less than a preset time. The purpose is to solve the problem of display abnormalities caused by overheating in the WOA area in related technologies.
[0041] To address the issue of display abnormalities caused by overheating in the WOA area in related technologies, this embodiment improves the driving circuit of the display panel. Analysis reveals that the overheating in the WOA area is due to the clock signal line group 02 being arranged sequentially. When the timing control module 01 inputs a scan clock signal to the scan drive module 03 via the clock signal line group 02, the clock signal line group 02 generates heat under the influence of current. Furthermore, the pulse overlap area of adjacent clock signal lines is large (i.e., they are simultaneously at a high level for a considerable period), causing adjacent CK lines to heat up simultaneously, resulting in heat accumulation and excessively high WOA area temperature. However, the high-level overlap time of adjacent CK lines cannot be completely avoided. Therefore, this embodiment adjusts the arrangement order of the CK lines to minimize the high-level overlap time of adjacent CK lines, thereby reducing heat accumulation, lowering the overall temperature of the WOA area, and preventing display abnormalities.
[0042] As an example, in this embodiment, it is assumed that there are three clock signal lines, namely CK1, CK2, and CK3, the clock signal period is 8H, the high-level pulse width is 4H, and the phase difference between the clock signal lines arranged in sequence is 1H. Therefore, the preset time can be 3H. In related technologies, the conventional connection method is as follows: interface 011 (number 1) is connected to interface 031 (number 1) via CK1; interface 011 (number 2) is connected to interface 031 (number 2) via CK2; and interface 011 (number 3) is connected to interface 031 (number 3) via CK3. Therefore, in related technologies, the clock signal line sequence at interface 031 is CK1, CK2, CK3, with adjacent clock signal lines CK1... The high-level overlap time between CK2 and CK3 is 3H. According to the first and second interfaces 011 and 031 in this embodiment, which have at least two sets of interleaved wiring sequences, the connection method in this embodiment is that the first interface 011 is connected to the second interface 031 through CK1, the first interface 011 is connected to the second interface 031 through CK2, and the first interface 011 is connected to the second interface 031 through CK3. Therefore, the clock signal line sequence at the second interface 031 in this embodiment is CK1, CK3, CK2, and the high-level overlap time between adjacent clock signal lines CK1 and CK3 is 2H, which is less than 3H.
[0043] In some feasible embodiments, the first interface 011 is the first output starting first interface 011 in a preset timing, and is connected to the first input starting second interface 031 in the second interface 031 through the clock signal line.
[0044] It should be understood that even if the connection order of the clock signal lines needs to be adjusted, the initial timing sequence should be retained as a reference. That is, in this embodiment, the first interface 011 in the timing control module 01, which is used to output the first high-level scan clock signal, and the second interface 031 in the scan drive module 03, which is used to input the scan clock signal, are still connected accordingly. If the first interface 011 and the second interface 031 are numbered sequentially, then the first interface 0111 and the second interface 0311 are connected accordingly. The first interface 011 and the second interface 031 with other serial numbers can be interleaved according to the actual situation.
[0045] In some feasible embodiments, refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a scanning driving module involved in the driving circuit of a display panel according to an embodiment of this application, combined with... Figure 1 and Figure 2 It can be seen that the scanning driving module 03 includes:
[0046] The array trace group 032 includes the same number of array traces as the second interface 031. Each array trace is connected to each of the second interfaces 031 one-to-one in the second order, so that the high-level overlap time between adjacent array traces is less than a preset time.
[0047] A gate driving unit (GDL) circuit is connected to the array trace group 032 in the first order.
[0048] It should be noted that in this embodiment, the array trace group 032 can be regarded as an extension of the clock signal line group 02 in the LCD panel. Therefore, when the second interface 031 of the scan driving module 03 is connected to the clock signal line group 02 in the second order, the array trace group 032 is also arranged in the second order to achieve the technical effect of reducing heat accumulation and lowering the overall temperature of the WOA area. The gate driving unit GDL circuit is used to output the gate driving signal according to the scan clock signal. In order not to change the display effect in the plane, its output timing cannot be changed. Therefore, although the connection method between the gate driving unit GDL circuit and the array trace group 032 still retains the first order, that is, CK1 connects to Gout1 and CK2 connects to Gout2, since the arrangement of the array trace group 032 has changed, in order to ensure the correspondence between the CK signal and Gout, the connection line between the gate driving unit GDL circuit and the array trace group 032 must also be adjusted accordingly.
[0049] As an example, in this embodiment, the clock signal line group includes 8 CK signal lines, therefore the gate drive unit GDL circuit also consists of 8 units per group, totaling 270 groups. Figure 2 Gout2158, Gout2159, and Gout2160 in the diagram correspond to the 6th, 7th, and 8th gate drive output signals of the 270th group of gate drive units (GDL circuit), respectively. Therefore, connecting CK6, CK7, and CK8 accordingly will ensure normal output.
[0050] As an example, the second interface 031 of the scan driver module 03 can be set on a PCBA (Printed Circuit Board Assembly, the entire process of a blank printed circuit board being mounted by SMT or DIP insertion). When the LCD panel receives the CK signal of the second sequence through the second interface 031 of the scan driver module 03 on the PCBA, the CK traces (i.e., array trace group 032) in the WOA area are adjusted according to the second sequence. Corresponding adjustments are also made in the GDL area (including 2160 gate driving units GDL circuits in this embodiment) so as not to affect the normal display of the panel.
[0051] It is understood that the number of the scan clock signal, the first interface 011, the clock signal line, the second interface 031, and the array traces are the same.
[0052] In some feasible embodiments, when the scan clock signal is represented by CK, the first order of outputting the scan clock signal is CK1, CK2, CK3, ..., CKn, where n is the number of the first interface 011, the clock signal line and the second interface 031, and n is an integer greater than or equal to 4.
[0053] In this embodiment, a pulse cycle includes a high-level region and a low-level region of the same period. In order to ensure that the high-level overlap of adjacent CK lines is as small as possible, this embodiment provides the following two examples, which correspond to different interval standards and CK line arrangement orders.
[0054] As an example, when the number of the first interface 011, the clock signal line and the second interface 031 is 8, the first sequence is CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, and the second sequence is CK1, CK4, CK7, CK2, CK5, CK8, CK3, CK6.
[0055] Reference Figure 3 and Figure 4 This embodiment is applicable to products with 8 CK signal lines. The period of the CK signal pulse is 8H, the high-level pulse width is 4H, and the phase difference between adjacent CK signals is 1H. The traditional WOA routing method adopts the following... Figure 3 The first sequence shown involves routing the WOA region. In this case, the high-level overlap time of adjacent CK lines is 3 hours, which can easily cause heat accumulation. The technical solution provided in this embodiment, however, employs... Figure 4The second sequence shown adjusts the arrangement of the CK lines in the WOA region, reducing the high-level overlap time of adjacent CK lines to 1H. This significantly reduces heat accumulation, lowers the overall temperature of the WOA, avoids display abnormalities, and improves the display stability of the LCD panel.
[0056] As an example, when the number of the first interface 011, the clock signal line, and the second interface 031 is 16, the first sequence is CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, CK9, CK10, CK11, CK12, CK13, CK14, CK15, CK16, and the second sequence is CK1, CK5, CK9, CK13, CK2, CK6, CK10, CK14, CK3, CK7, CK11, CK15, CK4, CK8, CK12, CK16.
[0057] This embodiment can be applied to products with 16 CK signal lines. When the period of the CK signal pulse is 8H, the high-level pulse width is 4H, and the phase difference between adjacent CK signals is 1H, the high-level overlap time of adjacent CK lines in the traditional WOA routing method is 3H, which easily causes heat accumulation. However, the technical solution provided in this embodiment uses a second order to adjust the arrangement order of CK lines in the WOA area, so that the high-level overlap time of adjacent CK lines is reduced to 0H, that is, the high-level overlap time of adjacent CK lines is completely staggered, which can significantly reduce heat accumulation, lower the overall temperature of WOA, avoid display abnormality problems, and improve the display stability of LCD panel.
[0058] Furthermore, embodiments of this application also provide an array substrate, referring to... Figure 5 In this embodiment, the array substrate includes an effective display area 101 and an ineffective display area. The ineffective display area surrounds the periphery of the effective display area 101, and the driving circuit 102 of the display panel is located in the ineffective display area of the array substrate.
[0059] In this embodiment, the specific structure of the driving circuit 102 of the display panel is the same as that in the above embodiments. Since the array substrate provided in this embodiment adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.
[0060] In addition, this application embodiment also provides a display panel, referring to Figure 6 The display panel includes an array substrate 100, a color filter substrate 200, and a liquid crystal layer 300, wherein the liquid crystal layer 300 is disposed between the array substrate 100 and the color filter substrate 200.
[0061] As an example, the display panel in this embodiment can be a Tn (Twisted nematic) display panel, an IPS (In-Plane Switching) display panel, a VA (Vertical Alignment) display panel, or an mVA (multi-Domain Vertical Alignment) display panel. Of course, it can also be other types of display panels, such as an OLED (Organic Light-Emitting Diode) display panel.
[0062] As an example, the display panel can be applied to display devices, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and any other products or components with display functions.
[0063] Those skilled in the art will understand that Figure 6 The structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0064] The specific structure of the array substrate 100 in this embodiment refers to the above embodiment. Since the display panel proposed in this embodiment adopts all the technical solutions of all the above embodiments and belongs to the same inventive concept, this embodiment has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.
[0065] It should be noted that the technical solutions of the various embodiments of this application can be combined with each other, but only if they are implemented by those skilled in the art. When the combination of technical solutions is contradictory or cannot be implemented, the user should consider that such combination of technical solutions does not exist and is not within the scope of protection claimed in this application.
[0066] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made based on the content of the specification and drawings of this application under the concept of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A driving circuit for a display panel, characterized in that, The driving circuit of the display panel includes: A timing control module includes multiple first interfaces, each of which is used to output scan clock signals in a first order. The output timing of the timing control module remains unchanged, and the phase difference between adjacent scan clock signals is equal. A clock signal line group, the clock signal line group comprising multiple clock signal lines, each of the first interfaces being connected one-to-one to one end of each of the clock signal lines in the first order; The scanning driver module includes a second interface with the same number as the first interface. The second interface is used to receive the scanning clock signal. Each second interface is connected one-to-one to the other end of each clock signal line in a second order. There are at least two sets of first and second interfaces with interleaved wiring orders in the first and second orders. The second order is configured to minimize the high-level overlap time between adjacent clock signal lines at the second interface. The scanning driver module also includes an array trace group, which is an extension of the clock signal line group in the display panel. The array trace group is arranged in the WOA area of the display panel in the second order to reduce the heat accumulation of adjacent clock signal lines in the WOA area and reduce the overall temperature of the WOA area. The scanning driving module further includes a gate driving unit, which is connected to the array trace group in the first order to ensure that the input timing of the gate driving unit is consistent with the output timing of the timing control module, so as not to change the in-plane display effect of the display panel.
2. The driving circuit for the display panel as described in claim 1, characterized in that, The first interface is the first output interface in the preset timing sequence, and is connected to the first input interface in the second interface via the clock signal line.
3. The driving circuit for the display panel as described in claim 1, characterized in that, The array trace group includes the same number of array traces as the second interface. Each array trace is connected to each of the second interfaces one-to-one in the second order, so that the high-level overlap time between adjacent array traces is less than a preset time.
4. The driving circuit for the display panel as described in claim 1, characterized in that, When the scan clock signal is represented by CK, the first order of outputting the scan clock signal is CK1, CK2, CK3, ..., CKn, where n is the number of the first interface, the clock signal line and the second interface, and n is an integer greater than or equal to 4.
5. The driving circuit for the display panel as described in claim 4, characterized in that, When the number of the first interface, the clock signal line and the second interface is 8, the first sequence is CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8.
6. The driving circuit for the display panel as described in claim 5, characterized in that, The second sequence is CK1, CK4, CK7, CK2, CK5, CK8, CK3, CK6.
7. The driving circuit for the display panel as described in claim 4, characterized in that, When the number of the first interface, the clock signal line, and the second interface is 16, the first sequence is CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, CK9, CK10, CK11, CK12, CK13. CK14, CK15, CK16.
8. The driving circuit for the display panel as described in claim 7, characterized in that, The second sequence is CK1, CK5, CK9, CK13, CK2, CK6, CK10, CK14, CK3, CK7, CK11, CK15, CK4. CK8, CK12, CK16.
9. An array substrate, characterized in that, The array substrate includes an effective display area and an ineffective display area, the ineffective display area surrounding the periphery of the effective display area, and the driving circuit of the display panel as described in any one of claims 1 to 8 is disposed in the ineffective display area of the array substrate.
10. A display panel, characterized in that, The display panel includes: a color filter substrate, a liquid crystal layer, and an array substrate as described in claim 9, wherein the liquid crystal layer is disposed between the array substrate and the color filter substrate.