In-memory computing device, neural network accelerator, electronic device

Abstract

The present disclosure relates to an in-memory computing device, a neural network accelerator and an electronic device, the in-memory computing device comprising: a plurality of read-only memory devices, a plurality of current sources and a control module, wherein a storage end of each read-only memory device is connected to one end of a corresponding current source, the other end of the current source being configured to receive a preset voltage to realize data storage; a control end of each read-only memory device being connected to a corresponding control word line and configured to receive to-be-computed data; an output end of each read-only memory device being configured to output result data through a computing bit line; and the control module being configured to select a corresponding read-only memory device through the control word line to operate and output the result data. The present disclosure utilizes read-only memory devices to implement an in-memory computing device, fully utilizes the high-density characteristics of read-only memory, improves the area efficiency of in-memory computing, and further reduces or even eliminates unnecessary energy consumption caused by memory access.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an in-memory computing device, a neural network accelerator, and an electronic device. Background Technology

[0002] With the rapid development and widespread application of technologies such as artificial intelligence, the Internet of Things, and big data, the demand for data computing and storage is growing exponentially. For example... Figure 1 As shown, the traditional von Neumann architecture separates data storage and computation to maintain the versatility of computing and the flexibility of control. The frequent movement of data between memory and processor has become a key bottleneck limiting the latency, energy efficiency, throughput, and scalability of mainstream computing platforms such as CPUs and GPUs. Therefore, the development of traditional computing platforms lags behind the computing power demands of cutting-edge applications. This situation means that many computing tasks cannot be completed directly on the terminal and need to be transmitted to cloud computing platforms for processing. This increases communication overhead and also violates users' needs for real-time performance, interactivity, and security / privacy.

[0003] To address the above problems, in-memory computing is a feasible solution. For example... Figure 1 As shown, it attempts to integrate storage and computing units, reducing latency and power consumption by minimizing unnecessary data movement, thereby improving the overall system performance and enabling large-scale deployment of terminal computing platforms. For decades, mainstream memory has only been improved to meet storage needs, without optimizing circuitry for computing. Therefore, designing a sizable in-memory computing system requires comprehensive consideration of cost, power consumption, performance, scalability, and reliability, as well as designing suitable data interfaces to achieve the organic integration of computing and storage units.

[0004] Current research in in-memory computing in academia and industry primarily focuses on devices such as Static Random-Access Memory (SRAM) and emerging non-volatile memories (e-NVM), represented by resistive random-access memory (RRAM). SRAM offers faster read / write speeds, lower power consumption, good durability, and mature manufacturing processes. However, significant drawbacks of in-memory computing using SRAM cells include higher static power consumption and lower area efficiency. Furthermore, there is a trade-off between noise margin and storage density in SRAM cells, and read interference limits the bit line voltage swing. To ensure system reliability, many designs have abandoned the most compact 6T SRAM structure, introducing more advanced technologies such as... Figure 2The transistors shown further reduce the area efficiency of SRAM. Compared to SRAM, the in-memory computing units implemented by the new non-volatile memory have advantages such as high area efficiency and low power consumption, but they also have limitations such as immature manufacturing processes, severe mismatch between devices, slow read and write speeds, and poor durability, making them unsuitable for building large-scale in-memory computing systems in the short term.

[0005] Based on their specific implementation methods, in-memory computing can be divided into two main categories: digital in-memory computing and analog in-memory computing. Digital in-memory computing has the advantage of maintaining accuracy comparable to traditional computing platforms, but its disadvantage lies in relatively limited improvements in computing energy efficiency. Analog in-memory computing has the advantage of higher energy efficiency, but its disadvantages include some accuracy loss and additional data conversion overhead. Analog in-memory computing can be further divided into charge domain computing and current domain computing: the former is based on the law of charge conservation, performing weighted summation based on the capacitance value, with the advantage of high matching accuracy, but the disadvantage of introducing capacitor delay costs and area overhead; the latter is based on Kirchhoff's current law, performing weighted summation, with the advantage of faster computation speed, but the disadvantage of relatively lower accuracy.

[0006] In the design of in-memory computing circuits, the area efficiency of the computing unit is a key indicator. On the one hand, the area of ​​the computing unit directly determines the chip's manufacturing cost and commercial potential. On the other hand, because current mainstream neural network algorithms train a large number of parameters, in-memory computing chips need to repeatedly interact with Dynamic Random-Access Memory (DRAM) when running artificial intelligence algorithms, introducing additional latency and power consumption overhead. Therefore, improving the area efficiency of in-memory computing can reduce the number of DRAM accesses, contributing to the improvement of overall system performance. Summary of the Invention

[0007] According to one aspect of this disclosure, an in-memory computing device is provided, the in-memory computing device comprising: a plurality of read-only storage devices, a plurality of current sources, and a control module, wherein,

[0008] Each read-only memory device's storage terminal is connected to one end of a corresponding current source, and the other end of the current source is used to receive a preset voltage to achieve data storage;

[0009] The control terminal of each read-only storage device is connected to the corresponding control word line to receive data to be calculated;

[0010] The output of each read-only memory device is used to output the result data through the calculation bit line;

[0011] The control module is used to select a corresponding read-only storage device for operation via the control word line to output the result data. The operation includes a multiplication operation and a data reading operation. If it is a multiplication operation, the result data is the product of the stored data corresponding to the preset voltage received by the current source and the data to be calculated input by the control word line. If it is a data reading operation, the result data is the stored data corresponding to the preset voltage received by the current source.

[0012] In one possible implementation, the in-memory computing device includes multiple computing modules, each computing module including one read-only memory device, the output of which is directly connected to a corresponding computing bit line, through which the result data is output.

[0013] In one possible implementation, the in-memory computing device includes multiple computing modules, each computing module including two or more read-only memory devices and at least one selection device. The control terminal of the selection device is connected to a corresponding control bit line, the input terminal of the selection device is connected to the output terminal of each read-only memory device, and the output terminal of the selection device is connected to a corresponding computing bit line to output the result data.

[0014] In one possible implementation, the read-only memory devices in the computing module are arranged in a layout of several rows and several columns. The control terminal of each row of read-only memory devices is connected to the same control word line, the output terminal of each column of read-only memory devices is connected to the same selection device, and the output terminal of each selection device is connected to the same computing bit line.

[0015] In one possible implementation, multiple computing modules are electrically connected to form a layout of several rows and several columns, wherein the control word lines of computing modules in the same row are electrically connected, the control bit lines of computing modules in the same column are electrically connected, and the computing bit lines of computing modules in the same column are electrically connected, with the computing bit lines connected via selection devices and power supply voltage.

[0016] In one possible implementation, the operation further includes a multiply-accumulate operation, the result data including the multiply-accumulate result, wherein the control module is further configured to:

[0017] A set of data is input through the control word line, and the control terminal of the corresponding selected device is activated through the control bit line to select the calculation module to participate in the multiplication and accumulation operation. The read-only memory device participating in the calculation within each calculation module is selected through the control word line. The multiplication operation between the input data and the stored data corresponding to the preset voltage received by the current source is completed in each calculation module. The multiplication results obtained by each calculation module are accumulated through the calculation bit line in the form of current and output to obtain the multiplication and accumulation result.

[0018] In one possible implementation, the control module is further configured to:

[0019] Adjust the signal timing of the control word line and control bit line to achieve pipelined operation between different computation bit lines.

[0020] In one possible implementation, the control module is further configured to:

[0021] Controls each computing module to enter either working or idle mode.

[0022] In the aforementioned operating mode, each read-only storage device in the computing module performs the aforementioned operation.

[0023] In the idle mode, no current flows inside the computing module.

[0024] According to one aspect of this disclosure, a neural network accelerator is provided, the chip including the aforementioned in-memory computing device.

[0025] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the neural network accelerator described above.

[0026] The embodiments disclosed herein implement in-memory computation based on read-only memory devices, which makes it possible to store large-scale neural network parameters completely on-chip, thereby eliminating the extra power consumption of repeatedly moving weights between on-chip and off-chip, significantly reducing the energy consumption of on-chip inference operations, and enabling large-scale, energy-efficient deployment of deep learning algorithms on smart terminal devices.

[0027] The embodiments disclosed herein utilize read-only memory devices to implement in-memory computing devices, making full use of the high-density characteristics of read-only memory to improve the area efficiency of in-memory computing, thereby reducing or even eliminating unnecessary energy consumption caused by memory access.

[0028] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0030] Figure 1 A comparative diagram of the von Neumann architecture and in-memory computing architecture is shown;

[0031] Figure 2 A schematic diagram of a circuit symbol for a metal-oxide-semiconductor field-effect transistor according to an embodiment of the present invention is shown;

[0032] Figure 3 A schematic diagram illustrating a typical case of drain-source current versus gate-source voltage in a metal-oxide-semiconductor field-effect transistor according to an embodiment of the present invention is shown.

[0033] Figure 4 A schematic diagram of an in-memory computing device according to an embodiment of the present disclosure is shown.

[0034] Figure 5 A schematic diagram showing an area comparison between the calculation module of this disclosure example and a calculation module in related technologies is illustrated.

[0035] Figure 6a , Figure 6b A schematic diagram of a computing module according to an embodiment of the present disclosure is shown.

[0036] Figure 7a , Figure 7b A schematic diagram is shown of a multiplication operation performed by a computing module of an in-memory computing device according to an embodiment of the present disclosure.

[0037] Figure 8 A schematic diagram of the structure of an in-memory computing device according to an embodiment of the present disclosure is shown.

[0038] Figure 9a , Figure 9b A schematic diagram of an in-memory computing device performing a multiply-accumulate operation according to an embodiment of the present disclosure is shown.

[0039] Figure 10 A schematic diagram is shown of a computing module of an in-memory computing device configured in an idle mode according to an embodiment of the present disclosure.

[0040] Figure 11a and Figure 11b A schematic diagram of pipelined operation of an in-memory computing device according to an embodiment of the present disclosure is shown.

[0041] Figure 12 A schematic diagram of a neural network accelerator according to an embodiment of the present disclosure is shown. Detailed Implementation

[0042] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0043] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0045] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0046] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0047] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0048] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0049] Please see Figure 4, Figure 4 A schematic diagram of an in-memory computing device according to an embodiment of the present disclosure is shown.

[0050] like Figure 4 As shown, the in-memory computing device includes: multiple read-only storage devices 110, multiple current sources 120, and a control module 100, wherein,

[0051] Each read-only storage device 110 has its storage terminal connected to one end of a corresponding current source 120. The other end of the current source 120 is used to receive a preset voltage to realize data storage.

[0052] The control terminal of each read-only memory device 110 is connected to the corresponding control word line WL <n>A connection is used to receive data to be calculated;

[0053] The output of each read-only memory device 110 is used to calculate the bit line CBL. <n>Output the result data;

[0054] The control module 100 is used to control word line WL <n>Select the corresponding read-only storage device 110 for operation to output the result data. The operation includes multiplication and data reading. If it is a multiplication operation, the result data is the stored data corresponding to the preset voltage received by the current source 120 and the control word line WL. <n>The product of the input data to be calculated; if it is a data reading operation, the result data is the stored data corresponding to the preset voltage received by the current source 120.

[0055] This disclosure does not limit the specific implementation of the control module. Exemplarily, the control module may include a processing component. In one example, the processing component includes, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, ASICs, programmable logic controllers, and embedded microcontrollers.

[0056] Read-only memory (ROM) is a type of memory with relatively mature technology, featuring high storage density, non-volatility, and low read power consumption. The embodiments of this disclosure utilize ROM to implement in-memory computation, making it possible to store large-scale neural network parameters completely on-chip. This eliminates the additional power consumption of repeatedly moving weights between on-chip and off-chip, significantly reducing the energy consumption of on-chip inference operations, and enabling large-scale, energy-efficient deployment of deep learning algorithms on smart terminal devices.

[0057] The embodiments disclosed herein utilize read-only memory devices to implement in-memory computing devices, making full use of the high-density characteristics of read-only memory to improve the area efficiency of in-memory computing, thereby reducing or even eliminating unnecessary energy consumption caused by memory access.

[0058] This disclosure does not limit the number of read-only memory devices (ROMs) or the number of current sources in the in-memory computing device, nor does it limit the specific current sources connected to the storage terminals of the ROMs, nor does it limit the magnitude of the preset voltage received by the current sources. The ROMs in the in-memory computing device can be individually configured, that is, one or more ROMs in the in-memory computing device can output calculation results through separate calculation bit lines and be controlled by separate control word lines; or, the ROMs in the in-memory computing device can be jointly configured, that is, two or more ROMs in the in-memory computing device can output calculation results through one calculation bit line or be controlled by the same control word line. This disclosure does not limit the configuration method of the ROMs in the in-memory computing device, and those skilled in the art can configure them according to actual application conditions and needs.

[0059] For example, the in-memory computing device may include multiple computing modules, and each computing module includes at least one read-only storage device. The computing module can be regarded as the basic unit for data storage and computation of the in-memory computing device. Therefore, the minimum size of the computing module in this embodiment is the size of a read-only storage device. Compared with the related technology that uses multiple transistors to implement the computing module, this embodiment can significantly improve area efficiency and increase storage density.

[0060] Please see Figure 5 , Figure 5 A schematic diagram showing an area comparison between the calculation module of this disclosure example and a calculation module in related technologies is illustrated.

[0061] In one example, such as Figure 5 As shown in (a) of this embodiment, the minimum size of the computing module in this disclosure is the size of a read-only storage device. Correspondingly, the minimum normalized area of ​​the computing module in this embodiment is 0.07x, where x can be considered as a unit area (e.g., the normalized area of ​​a 6T structure). Figure 5 As shown in (b), the computing module of the related technology is a 6T structure (including 6 transistors), wherein the normalized area of ​​the computing module of the 6T structure is 1x; Figure 5 As shown in (c), the computing module of the related technology is an 8T structure (including 8 transistors), and it can be seen that the normalized area of ​​the computing module of the 8T structure is 1.5x.

[0062] As described above, the mainstream CMOS in-memory computing circuit design currently uses SRAM as its storage unit, which consists of at least 6 transistors. However, this embodiment, leveraging the characteristics of read-only memory devices, uses only one transistor to store the information of one computing module, thereby improving area efficiency. If each computing module in this embodiment stores 1 bit of information, the area of ​​the computing module is only 0.07 times that of 6T SRAM using the same process. Furthermore, this embodiment has the potential to store multiple bits of information using only one transistor, thus further increasing storage density.

[0063] The read-only memory device in this disclosure can be a metal-oxide-semiconductor field-effect transistor (MOSFET) or a switching device with similar high on / off bit characteristics. The gate of the read-only memory device is connected to a control terminal, and the drain and source are connected to a storage terminal and an output terminal, respectively; alternatively, the drain and source are connected to an output terminal and a storage terminal, respectively. Figure 2 As shown, a metal-oxide-semiconductor field-effect transistor (MOSFET) is a three-terminal device whose impedance characteristics between the drain and source are controlled by the gate potential, exhibiting characteristics such as... Figure 3 The high throughput characteristic is shown.

[0064] It should be noted that, in the embodiments of the present invention, the metal-oxide-semiconductor field-effect transistor is only an example, and all devices with switching characteristics can theoretically be used to build the in-memory computing device proposed in the embodiments of this disclosure.

[0065] In one possible implementation, the in-memory computing device may include multiple computing modules, each computing module may include one of the read-only memory devices, the output of which is directly connected to a corresponding computing bit line, through which the result data is output.

[0066] Please see Figure 6a , Figure 6b , Figure 6a , Figure 6b A schematic diagram of a computing module according to an embodiment of the present disclosure is shown.

[0067] For example, such as Figure 6a As shown, each computing module may include two or more read-only memory devices. The output terminals of each read-only memory device may be connected to the same computing bit line CBL, and the control terminals of each read-only memory device are respectively connected to the corresponding control word line WL<>. Of course, in the computing device, each computing module may include the same or different number of read-only memory devices. This disclosure does not limit this aspect.

[0068] In one possible implementation, such as Figure 6b As shown, the in-memory computing device may include multiple computing modules. Each computing module may include two or more read-only memory devices and at least one selection device. The control terminal of the selection device is connected to a corresponding control bit line, the input terminal of the selection device is connected to the output terminal of each read-only memory device, and the output terminal of the selection device is connected to a corresponding computing bit line. The result data is output through the computing bit line, such as... Figure 6b As shown, the computing module may include read-only memory devices M1-M6, each of which adjusts the impedance characteristics between its drain and source by controlling the gate voltage; for example... Figure 6b As shown, the drains of read-only memory devices M2 and M3 are connected to the source of select device M1, and the gates of read-only memory devices M2 and M5 are connected to the control word line WL. <1> The drains of read-only memory devices M5 and M6 are connected to the source of select device M4, and the gates of read-only memory devices M3 and M6 are connected to the control word line WL. <2> The sources of read-only memory devices M2, M3, M5, and M6 are connected to one end of a current source for a specific operating current, and information is stored through this connection between the read-only memory devices and the current source for the specific operating current; the gate of selection device M1 and the control bit line BL are connected. <1> Connect the gate and control bit line BL of device M4. <2> Connected.

[0069] Of course, the selection device can also be a metal-semiconductor-oxide-semiconductor field-effect transistor or a switching device with similar high on / off bit characteristics, wherein the gate of the selection device is connected to the control terminal, and the drain and source are connected to the storage terminal and the output terminal, respectively, or the drain and source are connected to the output terminal and the storage terminal, respectively.

[0070] For example, each current source can be set in the calculation module, such as... Figure 6b As shown, the computing module, in addition to including read-only memory devices M2, M3, M5, and M6, and selection devices M1 and M4, may also include a current source module. Each current source can be housed within the current source module, which may include one or more current sources with different operating currents. Each current source can be connected to one or more read-only memory devices. This embodiment of the present disclosure, by establishing a many-to-many connection between the current sources and the read-only memory, can reuse the current sources, further reducing the area occupied by the unit circuit, thereby more fully utilizing the high-density characteristics of the read-only memory devices and improving overall area efficiency.

[0071] For example, such as Figure 6b As shown, the control bit line BL<1:2>, control word line WL<1:2>, and calculation bit line CBL can also be used as interfaces of the calculation module and thus be regarded as part of the calculation module. Of course, this disclosure does not limit this.

[0072] In one possible implementation, the read-only memory devices in the computing module are arranged in a layout of several rows and several columns. The control terminals of each row of read-only memory devices are connected to the same control word line, the output terminals of each column of read-only memory devices are connected to the same selection device, and the output terminals of each selection device are connected to the same computing bit line, such as... Figure 6b As shown, the gates and control word lines WL of read-only memory devices M2 and M5 in the same row are... <1> The gates and control word lines WL of the connected, same-row read-only memory devices M3 and M6 are also connected. <2> Connect the gate of device M1 and the control bit line BL. <1> Connect the gate and control bit line BL of device M4. <2> The drains of read-only memory devices M2 and M3 in the same column are connected to the source of selector M1, and the drains of read-only memory devices M5 and M6 in the same column are connected to the source of selector M4.

[0073] This disclosure embodiment can control each storage module to perform multiplication operations (and logical operations), as described below. Figure 6b The structure of the computing module shown is illustrated by way of example.

[0074] Please see Figure 7a , Figure 7b , Figure 7a , Figure 7b A schematic diagram is shown of a multiplication operation performed by a computing module of an in-memory computing device according to an embodiment of the present disclosure.

[0075] In one example, such as Figure 7a As shown, all control bit lines BL<1:2> and control word lines WL<1:2> can be set to V. SS This puts the computing module in idle mode, disconnecting the storage end of the read-only storage device from the computing word line, and eliminating current within the unit circuit.

[0076] In one example, such as Figure 7b As shown, the control word line WL can be... <1> Control word line WL <2> Let them be V respectively IN1 V SS BL control bit line <2> Keep V SS BL control bit line <1> Let V be the value of V. DD To achieve WL <1> Input data V IN1 The multiplication operation of the weight values ​​stored in the read-only memory device M2 results in a current flowing to the calculation bit line CBL, completing the multiplication operation. External circuits can obtain the multiplication calculation result by reading the current on the calculation bit line CBL.

[0077] Please see Figure 8 , Figure 8 A schematic diagram of the structure of an in-memory computing device according to an embodiment of the present disclosure is shown.

[0078] In one possible implementation, such as Figure 8 As shown, multiple computing modules are electrically connected to form a layout of several rows and columns. The control word lines of computing modules in the same row are electrically connected, the control bit lines of computing modules in the same column are electrically connected, and the computing bit lines of computing modules in the same column are electrically connected. The computing bit lines are connected to the power supply voltage through a selection device. For example, each control word line is driven by a word line driver output signal, and each bit line is driven by a bit line driver output signal. Each computing module is connected to the power supply, and the computing bit lines of each computing module output the results through an output detection interface.

[0079] For example, word line drivers and bit line drivers can be located in the control module.

[0080] Please see Figure 9a , Figure 9b , Figure 9a , Figure 9b A schematic diagram of an in-memory computing device performing a multiply-accumulate operation according to an embodiment of the present disclosure is shown.

[0081] In one possible implementation, the operation further includes a multiply-accumulate operation, and the resulting data includes a multiply-accumulate result, wherein the control module can also be used for:

[0082] A set of data is input through the control word line, and the control terminal of the corresponding selected device is activated through the control bit line to select the calculation module to participate in the multiplication and accumulation operation. The read-only memory device participating in the calculation within each calculation module is selected through the control word line. The multiplication operation between the input data and the stored data corresponding to the preset voltage received by the current source is completed in each calculation module. The multiplication results obtained by each calculation module are accumulated through the calculation bit line in the form of current and output to obtain the multiplication and accumulation result.

[0083] For example, when performing a multiplication-accumulation operation, the control word lines and control bit lines of all relevant calculation modules can be set to the lowest level, one or more columns of calculation bit lines can be selected, and a set of data can be input through the control word lines. If the output terminal of the read-only memory connected to the activated control word line is connected to the input terminal of the selection device, the control terminal of the corresponding selection device is activated through the control bit lines, and the read-only memory device participating in the calculation in each unit circuit is selected. The multiplication operation is implemented inside the unit circuit, and the result is accumulated through the calculation bit lines in the form of current. The result of the multiplication-accumulation operation is distinguished by detecting the change in the electrical characteristics of the calculation bit lines.

[0084] In one example, such as Figure 9a As shown, all control bit lines (such as BL) can be... m The <1:2> and control word lines (WL1<1:2>, WL2<1:2>) are both set to low level V. SS This makes the computation bit line CBL m The connected computing module is in idle mode, the storage terminals and control word lines of each read-only memory device are disconnected, and there is no current inside the unit circuit.

[0085] In one example, such as Figure 9b As shown, the computation bit line CBL can be enabled. m The selection device between the power supply and the selection device (applying a high level V to the selection device) DD The control word line WL1 can be used. <1> Control word line WL1 <2> Let them be V respectively IN1 V SS , control bit line BL m <2> Keep V SS , control bit line BL m <1> Let V be the value of V. DD Control word line WL2 <1> Control word line WL2 <2> Let them be V respectively IN2 V SS To implement control word line WL1 <1> The input data and the multiplication operation of the weight values ​​stored in the read-only storage device M2, as well as the control word line WL2 <1> The multiplication operation between the input data and the weight values ​​stored in the read-only memory device M8 results in a current being fed onto the computation bit line CBL. m According to Kirchhoff's current law, the addition is performed to complete the multiplication and accumulation operation, and the bit line CBL is calculated. m The result of the multiplication and accumulation is output in the form of current for external circuitry to read.

[0086] In one possible implementation, the control module is further configured to:

[0087] Controls each computing module to enter either working or idle mode.

[0088] In the aforementioned operating mode, each read-only storage device in the computing module performs the aforementioned operation.

[0089] In the idle mode, no current flows inside the computing module.

[0090] Please see Figure 10 , Figure 10 A schematic diagram is shown of a computing module of an in-memory computing device configured in an idle mode according to an embodiment of the present disclosure.

[0091] In one example, such as Figure 10 As shown, the word lines and bit lines connected to the read-only memory device and the selector switch are all connected to the lowest potential V. SS Because read-only memory devices are non-volatile, this makes the circuit have no static power consumption.

[0092] In the described working mode, the settings for multiplication and multiply-accumulate operations are as previously described and will not be repeated here. For read operations, ... Figure 10 Taking the control module as an example, in this embodiment of the disclosure, the switch of the read-only memory device to be read can be selected and turned on by the control word line, and the corresponding selection switch can be turned on to output the stored data of the read-only memory device through the calculation bit line.

[0093] According to the embodiments disclosed herein, the voltage information of the control word line and control bit line can be reasonably adjusted according to actual computing needs, and the computing module can be selectively activated to participate in the calculation, which can effectively reduce the overall power consumption of the system.

[0094] In one possible implementation, the control module is further configured to:

[0095] Adjust the signal timing of the control word line and control bit line to achieve pipelined operation between different computation bit lines.

[0096] Please see Figure 11a , Figure 11b , Figure 11a and Figure 11b A schematic diagram of pipelined operation of an in-memory computing device according to an embodiment of the present disclosure is shown.

[0097] In one example, such as Figure 11a As shown, the calculation module 1 can be used to perform the operation on the read-only memory device M2 and the control word line WL1, following the example of the multiply-accumulate operation described above. <1> Multiplication operations on input data, read-only memory device M8 and control word line WL2 <1> The multiplication operation of the input data is performed on the bit line CBL. m The corresponding multiplication and accumulation result is obtained, and the multiplication and accumulation result of calculation module 1 is output to the calculation bit line CBL of calculation module 2 through the output detection interface. m+1 ,like Figure 11b As shown, the calculation can be performed using a multiply-accumulate operation. The read-only memory device M12 and control word line WL1 in module 2 can be used for calculation. <1> Multiplication operations on input data, read-only memory device M18 and control word line WL2 <1> The input data multiplication operation, the output detection interface is calculated on the bit line CBL. m+1 The sum of the multiplication and accumulation results of read-only memory devices M12 and M18 and the multiplication and accumulation results of calculation module 1 is obtained, thereby realizing the pipelined operation of calculation module 1 and calculation module 2.

[0098] As can be seen, by reasonably adjusting the signal timing of the control word line and control bit line, the embodiments of this disclosure can realize pipelined operation between multiplication and accumulation operations of different column calculation modules, improve throughput, and improve the utilization of the output detection interface.

[0099] According to one aspect of this disclosure, a neural network accelerator is provided, the chip including the aforementioned in-memory computing device.

[0100] Please see Figure 12 , Figure 12 A schematic diagram of a neural network accelerator according to an embodiment of the present disclosure is shown.

[0101] This neural network accelerator consists of an array circuit composed of computing modules and peripheral circuits such as word line drivers, bit line drivers, and an output detection interface. Weights are stored via read-only memory devices and electrical connections to different current sources. The word line drivers control the word lines to input feature maps and other data. The input data and stored information undergo multiplication and accumulation operations within the array circuit. The output detection interface detects the electrical characteristics of the computation bit lines and converts them into digital signals for output. For example, this device can be used for fixed-point neural network inference operations.

[0102] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the neural network accelerator described above.

[0103] As described above, the embodiments of this disclosure use read-only memory (ROM) devices to store weights. Each computing module requires at least one transistor and has multi-bit storage potential. Compared to the traditional 6T SRAM structure, the storage density is significantly improved, allowing for the storage of more neural network parameters within a limited chip area, effectively reducing unnecessary memory access overhead. The various computing modules of the in-memory computing device of this disclosure can switch between idle and working modes to adapt to different computing load scenarios, improving computing energy efficiency. Furthermore, due to the non-volatility of ROM devices, there is no static power consumption. During system implementation, the in-memory computing device of this disclosure can pipeline multiply-accumulate operations on different computing bit lines, improving the overall system throughput and the utilization rate of the output detection module circuit through time-division multiplexing.

[0104] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.< / n> < / n> < / n> < / n>

Claims

1. An in-memory computing device, characterized in that, The in-memory computing device includes: multiple read-only storage devices, multiple current sources, and a control module, wherein, Each read-only memory device's storage terminal is connected to one end of a corresponding current source, and the other end of the current source is used to receive a preset voltage to achieve data storage; The control terminal of each read-only storage device is connected to the corresponding control word line to receive data to be calculated; The output of each read-only memory device is used to output the result data through the calculation bit line; The control module is used to select a corresponding read-only storage device for operation via the control word line to output the result data. The operation includes a multiplication operation and a data reading operation. If it is a multiplication operation, the result data is the product of the stored data corresponding to the preset voltage received by the current source and the data to be calculated input by the control word line. If it is a data reading operation, the result data is the stored data corresponding to the preset voltage received by the current source.

2. The apparatus according to claim 1, characterized in that, The in-memory computing device includes multiple computing modules, each computing module including a read-only memory device. The output terminal of the read-only memory device is directly connected to the corresponding computing bit line, and the result data is output through the computing bit line.

3. The apparatus according to claim 1, characterized in that, The in-memory computing device includes multiple computing modules. Each computing module includes two or more read-only memory devices and at least one selection device. The control terminal of the selection device is connected to a corresponding control bit line. The input terminal of the selection device is connected to the output terminal of each read-only memory device. The output terminal of the selection device is connected to a corresponding computing bit line, through which the result data is output.

4. The apparatus according to claim 3, characterized in that, The read-only memory devices in the computing module are arranged in a layout of several rows and several columns. The control terminal of each row of read-only memory devices is connected to the same control word line, the output terminal of each column of read-only memory devices is connected to the same selection device, and the output terminal of each selection device is connected to the same computing bit line.

5. The apparatus according to claim 3, characterized in that, Multiple computing modules are electrically connected to form a layout of several rows and columns. The control word lines of computing modules in the same row are electrically connected, the control bit lines of computing modules in the same column are electrically connected, and the computing bit lines of computing modules in the same column are electrically connected. The computing bit lines are connected to the power supply voltage through selection devices.

6. The apparatus according to claim 5, characterized in that, The operation also includes a multiply-accumulate operation, and the result data includes the multiply-accumulate result. The control module is further configured to: A set of data is input through the control word line, and the control terminal of the corresponding selected device is activated through the control bit line to select the calculation module to participate in the multiplication and accumulation operation. The read-only memory device participating in the calculation within each calculation module is selected through the control word line. The multiplication operation between the input data and the stored data corresponding to the preset voltage received by the current source is completed in each calculation module. The multiplication results obtained by each calculation module are accumulated through the calculation bit line in the form of current and output to obtain the multiplication and accumulation result.

7. The apparatus according to any one of claims 3 to 6, characterized in that, The control module is also used for: Adjust the signal timing of the control word line and control bit line to achieve pipelined operation between different computation bit lines.

8. The apparatus according to any one of claims 3 to 6, characterized in that, The control module is also used for: Controls each computing module to enter either working or idle mode. In the aforementioned operating mode, each read-only storage device in the computing module performs the aforementioned operation. In the idle mode, no current flows inside the computing module.

9. A neural network accelerator, characterized in that, The chip includes an in-memory computing device as described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the neural network accelerator as described in claim 9.

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