A redundant path configuration method, architecture, device and storage medium

Abstract

Embodiments of the present application provide a redundant path configuration method, architecture, device and storage medium. According to the configuration requirement, the redundant path relationship of a plurality of configurable nodes in a configurable architecture is determined; based on the configurable architecture, the node type of the plurality of configurable nodes is configured; and according to the node type and the redundant path relationship, the function type of the function port in the configurable node and the port path are configured. The node type of the plurality of configurable nodes in the configurable architecture and the redundant path relationship between the configurable nodes are configurable. That is, in the configurable architecture, the node type of each configurable node can be configured as required, which can meet different configuration requirements of different users. In the configuration process, since hardware development and design and software design are not required, the redundant path design in the architecture can be realized through parameter configuration, which can effectively simplify the configuration difficulty of the redundant path and improve the configuration efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hardware configuration, and particularly relates to a redundant path configuration method, architecture, device and storage medium. BACKGROUND

[0002] With the development of vehicle intelligent technology, in order to realize system reliability and stability, the 802.1AS protocol is used for precise time measurement.

[0003] However, the hardware architecture supporting the 802.1AS protocol has obvious limitations. Each user needs to consider how to realize the redundant path design through software means according to actual needs. When realizing through software means, a large amount of central processing unit (CPU) computing power is usually consumed, and the time accuracy realized through software cannot meet the application requirements or is unstable. If the user wants to realize the redundant path design through hardware means, professional personnel need to pay a high time cost. Therefore, a new solution is urgently needed. SUMMARY

[0004] Embodiments of the present application provide a redundant path configuration method, architecture, device and storage medium, to provide a general and easy-to-implement redundant path configuration scheme.

[0005] Embodiments of the present application provide a redundant path configuration method, including:

[0006] According to the configuration requirement, the redundant path relationship of a plurality of configurable nodes in a configurable architecture is determined;

[0007] Based on the configurable architecture, the node type of the plurality of configurable nodes is configured; the node type includes at least one of a master clock node, a bridge node and an end node;

[0008] According to the node type and the redundant path relationship, the function type of the function port in the configurable node and the port path are configured.

[0009] Optionally, after the node type configuration of the plurality of configurable nodes, the method further includes:

[0010] According to the node type, the configuration information and the register address corresponding to the configurable node are determined;

[0011] Based on the register address, the merging processing is performed to obtain a shared register;

[0012] The configuration information of the plurality of configurable nodes associated with the node identifier is stored into the shared register.

[0013] Optionally, the configurable architecture comprises a first redundant path and a second redundant path.

[0014] After configuring the function type of the function port and the port path of the configurable node, the method further comprises:

[0015] If the master clock node sends a generalized precision time protocol (gPTP) message to the end node, the master clock node sends the gPTP message to the end node through a first bridge node in the first redundant path and a second bridge node in the second redundant path at the same time.

[0016] Optionally, the method further comprises:

[0017] If the first redundant path is broken, the master time node sends the gPTP message to the end node through the second redundant path;

[0018] Sending a first redundant path failure prompt information to a user.

[0019] Optionally, the method further comprises:

[0020] If a new end node is added, the function type of the function port of the new end node and the port path connected with the bridge node are configured according to the bridge node configured in the configurable architecture.

[0021] Associating the node identification of the new end node with the configuration information and storing the node identification into the shared register.

[0022] Embodiments of the application provide a redundant path configuration architecture, which comprises: the node types in the architecture comprise at least a master clock node, an end node and at least two bridge nodes.

[0023] The master clock node is connected with the end node through a first redundant path, wherein the first redundant path comprises a first bridge node used for connecting the master clock node and the end node.

[0024] The master clock node is connected with the end node through a second redundant path, wherein the second redundant path comprises a second bridge node used for connecting the master clock node and the end node.

[0025] The first bridge node is connected with the second bridge node.

[0026] The function type of the function port and the port path of the master clock node, the end node and the at least two bridge nodes are configured based on the node types, the first redundant path and the second redundant path.

[0027] Optionally, the method further comprises:

[0028] The architecture comprises a shared register which is obtained by merging register addresses of the plurality of configurable nodes and is used to store configuration information associated with node identifiers of the plurality of configurable nodes.

[0029] Optionally, the bridge node further comprises a multiplexing module.

[0030] The multiplexing module is configured to perform multiplexing processing on at least one generalized precision time protocol packet based on the obtained hardware differentiation parameters and key parameters.

[0031] The multiplexing-processed generalized precision time protocol packet is transmitted and received through the port path corresponding to the path label of the generalized precision time protocol packet.

[0032] Embodiments of the present application provide a vehicle device, comprising: a vehicle body, a radar and an image acquisition device are installed on the vehicle body, and a memory, a processor, a communication component and a display component are further arranged; the memory is configured to store one or more computer instructions; the processor is configured to execute the one or more computer instructions to perform steps in a redundant path configuration method through the communication component and the display component.

[0033] Embodiments of the present application provide a computer readable storage medium storing a computer program, which can implement steps in a redundant path configuration method when executed.

[0034] In the redundant path configuration method, architecture, device and storage medium provided by the embodiments of the present application, according to configuration requirements, a redundant path relationship of a plurality of configurable nodes in a configurable architecture is determined; based on the configurable architecture, node type configuration is performed on the plurality of configurable nodes; the node type comprises at least one of a master clock node, a bridge node and an end node; and according to the node type and the redundant path relationship, a function type of a function port and a port path in the configurable node are configured. Through the above scheme, the configurable architecture is defined, and the node type of the plurality of configurable nodes in the configurable architecture and the redundant path relationship between the configurable nodes are configurable. After the redundant path relationship and the node type are determined, the function port in each configurable node can be further configured, that is, in the configurable architecture, the node type of each configurable node can be configured according to requirements, which can meet different configuration requirements of different users. In the configuration process, since hardware development and design and software design are not required, the redundant path design in the architecture can be realized through parameter configuration, which can effectively simplify the configuration difficulty of the redundant path and improve the configuration efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0036] Figure 1 A flowchart of a redundant path configuration method provided by an embodiment of the application;

[0037] Figure 2 A schematic diagram of a functional port configuration provided by an embodiment of the application;

[0038] Figure 3 A schematic diagram of a parallel redundant path provided by an embodiment of the application;

[0039] Figure 4 A schematic diagram of a key parameter multiplexing architecture provided by an embodiment of the application;

[0040] Figure 5 A schematic diagram of a gPTP message multiplexing architecture provided by an embodiment of the application;

[0041] Figure 6 A schematic diagram of a redundant path configuration architecture provided by an embodiment of the application;

[0042] Figure 7 A schematic diagram of a terminal device provided by an embodiment of the application. DETAILED DESCRIPTION

[0043] In order to enable persons skilled in the art to better understand the application scheme, the technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application.

[0044] In some of the processes described in this specification, including the methods described in this specification and the accompanying drawings, multiple operations are presented in a specific order. These operations can not be performed in the order presented or in parallel. The sequence of operations, such as 101, 102, etc., is merely used to distinguish different operations from each other, and the sequence number itself does not represent any execution order. In addition, these processes can include more or fewer operations, and the operations can be performed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this paper are used to distinguish different messages, devices, modules, etc., and do not represent the order of sequence, nor do "first" and "second" represent different types.

[0045] In order to make the purposes, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described below in connection with specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0046] In some embodiments of the present application, a redundancy path configuration method of a universal configurable architecture is provided.

[0047] The technical solutions provided by the embodiments of the present application will be described in detail below in connection with the drawings.

[0048] Figure 1 A flowchart of the redundancy path configuration method provided by the embodiments of the present application is shown in FIG. 1, which comprises the following steps. Figure 1

[0049] 101: According to the configuration requirement, determine the redundancy path relationship of a plurality of configurable nodes in the configurable architecture.

[0050] 102: Based on the configurable architecture, configure the node types of the plurality of configurable nodes; the node types comprise at least one of a master clock node, a bridge node and an end node.

[0051] 103: According to the node types and the redundancy path relationship, configure the function types of the function ports in the configurable nodes and the port paths.

[0052] In actual application, the configurable architecture contains a plurality of configurable nodes, and the node types of these configurable nodes can be set at will according to the requirement. It should be noted that these configurable nodes all have physical connection relationship, therefore, the user does not need to consider the design problem of physical connection relationship when using, but can directly determine the redundancy path relationship between the configurable nodes according to the configuration requirement. The redundancy path relationship mentioned here can be understood as that how many end nodes are designed, how many redundancy paths are designed between the master node and the end node, how many bridge nodes are designed in the redundancy path, etc. In each configurable node, there are CPU and 802.1AS device (FPGA / ASIC), and a plurality of function ports (such as Port1, Port2, Port3) connected with the 802.1AS device, and the configurable nodes are physically connected through the function ports, so that the user can very simply realize the function connection (that is, set the enable state of each function port) according to the requirement through configuration.

[0053] ​In determining the redundant path relationship, the link time of each redundant path is calculated according to the link delay, time delay and the like, so that each redundant path has accurate clock synchronization effect.

[0054] After the configuration of the node type in the configurable node is completed, further corresponding function port configuration needs to be performed according to the node type. For example, as shown in Figure 2 The schematic diagram of the function port configuration provided by the embodiment of the present application is shown in FIG. 2. As can be seen from Figure 2 , the table contains the node type (for example, 1 is a GM master clock node, and 0 is a bridge node), the port path of the function port (path 1 enabled, path 2 enabled), the node configuration information (for example, node 1: 100001_100001, node 2: 101110_001010) and the like. According to the above table, the function port connected with multiple bridge nodes is set in the master clock node, the bridge node also needs to set the function port connected with other bridge nodes and end nodes, and the end node needs to set the function port according to the number of redundant paths and the number of bridge nodes.

[0055] Through the above scheme, the user can perform the node type configuration based on the configurable architecture in which the hardware connection relationship has been completed and perform the function port configuration according to the node type, so as to meet the diversified redundant path design requirements of different users without the need of hardware design change or software design, effectively reduce the 802.1AS redundant path design difficulty, and further provide work efficiency.

[0056] In one or more embodiments of the present application, after the node type configuration of the plurality of configurable nodes is performed, the method further includes: determining the configuration information and the register address corresponding to the configurable node according to the node type; performing merging processing based on the register address to obtain a shared register; and storing the configuration information associated with the node identifier of the plurality of configurable nodes into the shared register.

[0057] Suppose that in the architecture configured by the user, there is one master clock node and one end node, and there are two redundant paths between the master clock node and the end node, which are connected through three function ports. There is one bridge node in each redundant path. Each configurable node needs a 13-bit register. In order to ensure the consistency of the system configuration information, the registers of the four configurable nodes are merged into one configuration file, so that the configuration file obtained is applicable to the CPU of each configurable node. The CPU can read and load the corresponding configuration information according to the node identifier, so that the user no longer needs to determine the corresponding register according to the configurable node, and the problem of register allocation error leading to the fact that the configurable node cannot obtain correct configuration information is avoided. Through the above manner, the configuration difficulty can be effectively simplified, and the configuration efficiency is improved.

[0058] In one or more embodiments of the present application, it is assumed that the configurable architecture includes a first redundant path and a second redundant path. After configuring the function type of the functional port in the configurable node and the port path, it is further included that if the master clock node sends the gPTP packet to the end node, the master clock node sends the gPTP packet to the end node through the first bridge node in the first redundant path and the second bridge node in the second redundant path at the same time.

[0059] In practical applications, when designing a redundant path, a parallel redundant path design scheme can be used. For example, Figure 3 A parallel redundant path schematic diagram is provided for embodiments of the present application. As can be seen from Figure 3 When the master clock node has a generalized precision time protocol (gPTP) packet sending requirement, the packet can be sent through two redundant paths at the same time. Due to the use of symmetric design, the influence of the path on time precision can be effectively avoided, so that the end node can obtain the same time synchronization effect. In addition, the parallel redundant path will reduce the number of node hops, which can effectively improve the synchronization precision of the end node of the synchronization path.

[0060] In one or more embodiments of the present application, it is further included that if any of the bridge nodes processes the gPTP packet, the hardware differentiation parameters between the plurality of configurable nodes are determined; the key parameters carried in the gPTP packet and the associated path label are determined; at least one of the gPTP packets is processed based on the hardware differentiation parameters and the key parameters; and the gPTP packet after the multiplexing processing is executed through the port path corresponding to the path label.

[0061] In practical applications, there are two redundant paths. Since the redundant path in 802.1AS is hot backup (clock hot backup), each bridge node (Switch) will continuously receive gPTP packets of the two paths and perform separate operations in the corresponding synchronization calculation module. The operation result is selected and output to the local real-time clock (RTC). Since the port type of the functional port and the corresponding port path are dynamically configurable general architecture, the internal distribution of the data stream can be completed according to the configured port role.

[0062] As Figure 4 A key parameter multiplexing architecture schematic diagram is provided for embodiments of the present application. As can be seen from Figure 4As can be seen from the gPTP packet transmission and reception module, a key parameter is a key variable extracted from the gPTP packet, a gPTP packet reception timestamp, and a gPTP packet transmission timestamp, and the like, which are provided by the packet transmission and reception module and need to be output to the synchronization calculation module of the corresponding redundant path by the multiplexing module. Another key parameter is the hardware differentiation parameter between the nodes in the architecture, such as the time phase deviation, the clock RateRatio, the CorrectTime, and the like, which are provided by the synchronization calculation modules of the two redundant paths and need to be output to the corresponding packet transmission and reception module by the multiplexing module. In summary, the multiplexing module will complete the data exchange between the packet transmission and reception module of the three ports and the synchronization calculation module corresponding to the two redundant paths, and according to the transmission of each key parameter, a path label will be attached, and then the data matching and distribution are performed in combination with the function type and port path information of the function port.

[0063] As Figure 5 The gPTP packet multiplexing architecture provided by the embodiment of the application is shown in the figure. As can be seen from the gPTP packet transmission and reception module, Figure 5 As can be seen from the gPTP packet transmission and reception module, a key parameter is a key variable extracted from the gPTP packet, a gPTP packet reception timestamp, and a gPTP packet transmission timestamp, and the like, which are provided by the packet transmission and reception module and need to be output to the synchronization calculation module of the corresponding redundant path by the multiplexing module. Another key parameter is the hardware differentiation parameter between the nodes in the architecture, such as the time phase deviation, the clock RateRatio, the CorrectTime, and the like, which are provided by the synchronization calculation modules of the two redundant paths and need to be output to the corresponding packet transmission and reception module by the multiplexing module. In summary, the multiplexing module will complete the data exchange between the packet transmission and reception module of the three ports and the synchronization calculation module corresponding to the two redundant paths, and according to the transmission of each key parameter, a path label will be attached, and then the data matching and distribution are performed in combination with the function type and port path information of the function port.

[0064] In one or more embodiments of the application, it further includes: if the first redundant path is broken, the master time node sends the gPTP packet to the end node through the second redundant path; and sends a first redundant path failure prompt information to the user. In actual application, the redundant path configuration architecture can also contain multiple redundant paths, for example, it contains four redundant paths, and when the third redundant path fails, the gPTP packet can be sent to the end node through the first redundant path, the second redundant path, and the fourth redundant path. When the redundant path fails, a failure alarm prompt information can be sent. As an optional solution, it can be prompted in the alarm prompt information which redundant path fails, thereby guiding the staff to quickly solve the problem.

[0065] The two redundant path designs of the scheme allow the failure of any physical link, for example, the failure of a physical link used to connect the first bridge node and the second bridge node, and the other physical links are normally connected. Then, the first bridge node and the end node can complete time synchronization through the first redundant path, the second bridge node can complete time synchronization through the second redundant path, and the failure of other links is similar. In addition, in order to ensure the reliability of time synchronization, when the redundant path fails, the staff needs to be notified in time to troubleshoot the failure as soon as possible.

[0066] In one or more embodiments of the present application, if a new end node is added, the function type of the function port of the new end node and the port path connected to the bridge node are configured according to the bridge node configured in the configurable architecture; the node identifier of the new end node is associated with the configuration information and stored in the shared register.

[0067] As described above, in the configurable architecture, the function ports of each configurable node and the path relationship can be configured as needed. In actual application, when there is a demand to add a new end node, the function ports of the related bridge node and the new end node, the port path, and the configuration information can be configured based on the currently configured architecture. It should be noted that, in order to facilitate the management of the configuration file, the register of the new end node needs to be merged into the existing shared register as a new shared register, and all node configuration information is stored in a configuration file.

[0068] In the same way, if a bridge node fails, a new bridge node can also be added to replace the original failed bridge node. For details, please refer to the above embodiments, which will not be repeated here.

[0069] Based on the same idea, the embodiments of the present application also provide a redundant path configuration architecture. As Figure 6 The schematic diagram of the redundant path configuration architecture provided by the embodiments of the present application is shown in FIG. 1. As can be seen from Figure 6 , the node types contained in the architecture include at least a master clock node 61, an end node 62, and at least two bridge nodes;

[0070] The master clock node 61 is connected to the end node through a first redundant path, wherein the first redundant path contains a first bridge node 63 used to connect the master clock node and the end node;

[0071] The master clock node is connected to the end node through a second redundant path, wherein the second redundant path contains a second bridge node 64 used to connect the master clock node and the end node;

[0072] The first bridge node 63 is connected to the second bridge node 64;

[0073] The function type and port path of the function port of the master clock node 61, the end node 62 and the at least two bridge nodes are configured based on the node type, the first redundant path and the second redundant path.

[0074] As a preferred solution, the two redundant paths can be set in parallel. By sending messages through the two parallel redundant paths at the same time, the number of node hops is reduced, and the synchronization accuracy of the end node of the synchronization path is effectively improved. In actual application, multiple redundant paths in parallel mode can be used to meet the time synchronization requirements of multiple end nodes. Here, only as an example, does not constitute a limitation on the technical solutions of the present application.

[0075] From Figure 6 It can be seen that in each configurable node, there is a CPU and an 802.1AS device (FPGA / ASIC) and three Port ports. Among them, node 1 is the master clock node 61, node 2 and node 3 are bridge nodes, and node 4 is the end node 62. From Figure 6 It can be seen that the master clock node 61 is connected with the Port1 of the first bridge node 63 through the function port Port1, and is connected with the Port1 of the second bridge node 64 through the function port Port3. The function port Port2 of the first bridge node is connected with the function port Port2 of the second bridge node. The function port Port1 of the end node is connected with the function port Port3 of the first bridge node, and the function port Port2 of the end node is connected with the function port Port3 of the second bridge node. In this way, two redundant paths are obtained, the first redundant path includes the master clock node, the first bridge node and the end node, and the second redundant path includes the master clock node, the second bridge node and the end node.

[0076] In one or more embodiments of the present application, the architecture includes a shared register, which is obtained by merging the register addresses of the plurality of configurable nodes, and is used to store configuration information associated with the node identifiers corresponding to the plurality of configurable nodes. The specific implementation of merging the registers of multiple nodes can refer to the above embodiments, which will not be repeated here.

[0077] In actual application, generally, each node is allocated a corresponding register, thereby storing a corresponding configuration file. Since in the architecture, the required redundant path relationship of each user is not completely the same, the user needs to configure the relevant configuration information by himself. If the user wants to configure a large number of configurable nodes contained in the architecture, errors are prone to occur. Therefore, the registers of a plurality of nodes can be merged for processing, a shared register is generated, and the configuration information of all user-configured nodes is stored in the same configuration file. In the configuration file, only the corresponding node identifier needs to be marked for the configuration information of different nodes.

[0078] In one or more embodiments of the present application, the bridge node further comprises a multiplexing module. The multiplexing module is configured to perform multiplexing processing on at least one gPTP packet based on the obtained hardware differentiation parameters and key parameters, and perform transceiving operation on the multiplexing-processed gPTP packet through the port path corresponding to the path label of the gPTP packet.

[0079] Since in the technical solution of the present application, the node type in the architecture can be configured by the user himself, it means that the configuration information and the transmission path of the message are various. In order to avoid errors when configuring the information of each node, the registers of all nodes can be merged, and then the configuration information of a plurality of configurable nodes (such as master clock node, bridge node and end node) can be managed through one configuration file, which can effectively improve the configuration efficiency.

[0080] In some processes described in the above embodiments and the accompanying drawings, a plurality of operations appearing in a specific order are included, but it should be clear that these operations can be executed in the order appearing in this text or in parallel, and the serial numbers of the operations such as 11, 12, etc. are only used to distinguish different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes can include more or fewer operations, and the operations can be executed in sequence or in parallel.

[0081] It should be noted that the "first", "second", etc. in this text are used to distinguish different messages, devices, modules, etc., and do not represent the order, nor do "first" and "second" represent different types.

[0082] Figure 7 is a structural schematic diagram of a terminal device provided by an embodiment of the present application, as shown in Figure 7 The terminal device includes a memory 701 and a processor 702.

[0083] The memory 701 is configured to store computer programs and can be configured to store other various data to support operations on the terminal device. Examples of the data include instructions of any application program or method for operating on the terminal device, contact data, phonebook data, messages, pictures, videos, and the like.

[0084] The memory 701 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a Static Random-Access Memory (SRAM), an Electrically Erasable Programmable read only memory (EEPROM), an Electrical Programmable Read Only Memory (EPROM), a Programmable read-only memory (PROM), a Read-Only Memory (ROM), a magnetic storage, a flash memory, a magnetic disk, or an optical disk.

[0085] The vehicle device further includes a display component 703. The processor 702 is coupled with the memory 701 and is configured to execute computer programs in the memory 701 for:

[0086] According to a configuration requirement, a redundant path relationship of a plurality of configurable nodes in a configurable architecture is determined;

[0087] Based on the configurable architecture, node type configurations of the plurality of configurable nodes are performed; the node type includes at least one of a master clock node, a bridge node, and an end node;

[0088] According to the node type and the redundant path relationship, a function type of a functional port and a port path in the configurable node are configured.

[0089] Optionally, the processor 702 is further configured to, after the node type configurations of the plurality of configurable nodes are performed, determine configuration information and a register address corresponding to the configurable node according to the node type; perform a merging process based on the register address to obtain a shared register; and store the configuration information associated with a node identifier of the plurality of configurable nodes into the shared register.

[0090] Optionally, the configurable architecture includes a first redundant path and a second redundant path. After configuring the function type of the function port and the port path in the configurable node, the processor 702 is further configured to, if the master clock node sends the gPTP packet to the end node, send the gPTP packet to the end node by the first bridge node in the first redundant path and the second bridge node in the second redundant path at the same time.

[0091] The processor 702 is further configured to, if any of the bridge nodes processes the gPTP packet, determine the hardware differentiation parameter between the plurality of configurable nodes.

[0092] Determine the key parameter carried in the gPTP packet and the associated path tag.

[0093] Based on the hardware differentiation parameter and the key parameter, perform multiplexing processing on at least one of the gPTP packets.

[0094] Perform transceiving operation on the multiplexing-processed gPTP packet through the port path corresponding to the path tag.

[0095] The processor 702 is further configured to, if a new end node is added, configure the function type of the function port of the new end node and the port path connected with the bridge node according to the bridge node configured in the configurable architecture.

[0096] Associate the node identifier of the new end node with the configuration information and store it to the shared register.

[0097] The processor 702 is further configured to, if the first redundant path is broken, send the gPTP packet to the end node by the second redundant path.

[0098] Send the first redundant path failure prompt information to the user.

[0099] The memory in the above Figure 7 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0100] The above Figure 7The display component 703 includes a screen, which may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touchscreen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation.

[0101] superior Figure 7 The audio component 704 can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC) configured to receive external audio signals when the device containing the audio component is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals can be further stored in memory or transmitted via a communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals.

[0102] Furthermore, such as Figure 7 As shown, the vehicle equipment also includes other components such as a communication component 705 and a power supply component 706. Figure 7 The diagram only shows some components and does not mean that the vehicle equipment includes only these components. Figure 7 The components shown.

[0103] The above Figure 7 The communication component 705 is configured to facilitate wired or wireless communication between the device containing the communication component and other devices. The device containing the communication component can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G, or 5G, or combinations thereof. In one exemplary embodiment, the communication component receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component may be implemented based on Near Field Communication (NFC), Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra Wideband (UWB), Bluetooth, and other technologies.

[0104] The power supply component 706 provides power to various components of the device in which it resides. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which it resides.

[0105] In the embodiments of the present application, according to configuration requirements, a redundant path relationship of a plurality of configurable nodes in a configurable architecture is determined; based on the configurable architecture, node type configuration is performed on the plurality of configurable nodes; the node type includes at least one of a master clock node, a bridge node, and an end node; and according to the node type and the redundant path relationship, a function type of a function port in the configurable node and a port path are configured. Through the above scheme, the configurable architecture is defined, and the node type of the plurality of configurable nodes in the configurable architecture and the redundant path relationship between the configurable nodes are configurable. After the redundant path relationship and the node type are determined, the function port in each configurable node can be further configured, that is, in the configurable architecture, the node type of each configurable node can be configured according to requirements, and different configuration requirements of different users can be met. In the configuration process, since hardware development and design and software design are not required, the redundant path design in the architecture can be realized through parameter configuration, the configuration difficulty of the redundant path can be effectively simplified, and the configuration efficiency is improved.

[0106] Correspondingly, the embodiment of the present application also provides a computer readable storage medium storing a computer program, and the computer program is executed to implement each step that can be executed by the terminal device in the method embodiment.

[0107] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt a computer program product in the form of being implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program codes.

[0108] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system), and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a means for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one flow or multiple flows and / or blocks Figure 1 The means for implementing the functions specified in one flow or multiple flows and / or blocks

[0109] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the Figure 1 function specified in the flow or flows and / or blocks Figure 1 of the block or blocks.

[0110] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the Figure 1 function specified in the flow or flows and / or blocks Figure 1 of the block or blocks.

[0111] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0112] The memory can include non-persistent memory and / or volatile memory, such as random access memory (RAM) and / or cache memory, non-volatile memory, such as read-only memory (ROM), EPROM, and / or flash memory, etc. The memory is an example of computer readable media.

[0113] Computer readable media includes permanent and non-permanent, moveable and non- moveable media that can be implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disks (DVDs) or other optical storage, magnetic cassettes, magnetic disks storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that is accessible to a computing device. According to the definition herein, computer readable media does not include transitory media, such as modulated data signals and carrier waves.

[0114] It should also be noted that the terms "comprising," "including," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0115] The above description is merely illustrative of the application, and not restrictive. Various modifications and changes can become apparent to those skilled in the art. Incorporating any modification, equivalent substitution, improvement, etc. within the spirit and principle of the application, shall be included in the scope of the claims of the application.

Claims

1. A redundant path configuration method applied to a vehicle device, characterized by, The method comprises: determining a redundant path relationship of a plurality of configurable nodes in a configurable architecture according to configuration requirements, wherein the configurable architecture comprises a first redundant path and a second redundant path; configuring node types of the plurality of configurable nodes based on the configurable architecture; the node types comprise at least one of a master clock node, a bridge node and an end node; configuring function types and port paths of function ports in the configurable nodes according to the node types and the redundant path relationship.

2. The method of claim 1, wherein, After the node types of the plurality of configurable nodes are configured, the method further comprises: determining configuration information and register addresses corresponding to the configurable nodes according to the node types; performing merging processing based on the register addresses to obtain a shared register; storing the configuration information associated with node identifiers of the plurality of configurable nodes into the shared register.

3. The method of claim 1, wherein, After the function types and port paths of the function ports in the configurable nodes are configured, the method further comprises: if the master clock node sends a generalized precision time protocol message to the end node, the master clock node simultaneously sends the generalized precision time protocol message to the end node through a first bridge node in the first redundant path and through a second bridge node in the second redundant path.

4. The method of claim 3, wherein, The method further comprises: if the first redundant path is disconnected, the master clock node sends the generalized precision time protocol message to the end node through the second redundant path; sending a first redundant path failure prompt information to a user.

5. The method of claim 2, wherein, The method further comprises: if a new end node is added, configuring function types of function ports of the new end node and port paths connected with the bridge nodes according to the bridge nodes configured in the configurable architecture; associating a node identifier of the new end node with configuration information and storing the node identifier and the configuration information into the shared register.

6. A redundant path configuration system, characterized by The node types comprised in the system comprise at least a master clock node, an end node and at least two bridge nodes; the master clock node is connected with the end node through a first redundant path, wherein the first redundant path comprises a first bridge node used for connecting with the master clock node and the end node; the master clock node is connected with the end node through a second redundant path, wherein the second redundant path comprises a second bridge node used for connecting with the master clock node and the end node; the first bridge node is connected with the second bridge node; function types and port paths of function ports of the master clock node, the end node and the at least two bridge nodes are configured based on the node types, the first redundant path and the second redundant path.

7. The system of claim 6, wherein, The system further comprises a shared register, which is obtained by merging register addresses of a plurality of configurable nodes and is used for storing configuration information associated with node identifiers corresponding to the plurality of configurable nodes. The bridge node further comprises a multiplexing module; 8. The system of claim 6, wherein, the multiplexing module is used for performing multiplexing processing on at least one generalized precision time protocol message based on obtained hardware differentiation parameters and key parameters. ​ The generalized precision time protocol packet after the multiplexing processing is transmitted and received through the port path corresponding to the path label of the generalized precision time protocol packet.

9. A vehicle apparatus characterized by comprising: The application relates to a vehicle body, wherein a sensor and a monitoring module are mounted on the vehicle body, and a memory, a processor, a communication component and a display component are further arranged on the vehicle body. The memory is configured to store one or more computer instructions. The processor is configured to execute the one or more computer instructions to perform the steps in the method of any one of claims 1-5.

10. A computer readable storage medium storing a computer program, characterized in that, The computer program is executed to implement the steps in the method of any one of claims 1-5.

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