Image sensor and signal reading method thereof

Abstract

The present invention provides an image sensor, comprising a pixel circuit and a control circuit; the pixel circuit comprises a gain control unit, a high gain storage control unit and a low gain storage control unit, the gain control unit receives a gain control signal, and enables the pixel circuit to work in different conversion gain modes; the high gain storage control unit and the low gain storage control unit are arranged in parallel and are both connected to a floating diffusion point; the high gain storage control unit is used to store a high gain reset voltage signal and a high gain image voltage signal in the high conversion gain mode respectively, and the low gain storage control unit is used to store a low gain reset voltage signal and a low gain image voltage signal in the low conversion gain mode respectively; the control circuit is at least used to provide a pixel circuit control signal to the pixel circuit, and the pixel circuit control signal includes the gain control signal. The image sensor provided by the present invention solves the problem of low dynamic range of existing image sensors.

Description

Technical Field

[0001] The present invention relates to the technical field of CMOS image sensors, and in particular to a CMOS image sensor and a signal readout method thereof. Background Art

[0002] The implementation principle of global shutter is that each exposure pixel is accompanied by a storage capacitor, all pixels on the photosensitive array are exposed at the same time, and then the photoelectrons are transferred to the storage capacitor and locked, waiting for subsequent circuit readout. Compared with rolling shutter, the advantage of global shutter is that the exposure time of each row of the image is relatively consistent, and the image will not be offset or skewed when shooting moving objects.

[0003] In some environments with large light differences, dynamic range is a key factor affecting the imaging quality of image sensors; it determines the distribution range of light intensity from the darkest shadow part to the brightest highlight part that the image sensor can accept, that is, it determines the details, layers, and features of the captured image. Therefore, how to improve the dynamic range of image sensors is a technical problem that technicians in this field urgently need to solve. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an image sensor and a signal readout method thereof, so as to solve the problem of low dynamic range of the prior image sensor.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides an image sensor, including a pixel circuit and a control circuit; wherein:

[0006] The pixel circuit at least includes a gain control unit, a high gain storage control unit and a low gain storage control unit:

[0007] The gain control unit receives a gain control signal to enable the pixel circuit to operate in different conversion gain modes, wherein the different conversion gain modes include a high conversion gain mode and a low conversion gain mode;

[0008] The high-gain storage control unit and the low-gain storage control unit are arranged in parallel and are both connected to the floating diffusion point; wherein the high-gain storage control unit is used to store the high-gain reset voltage signal and the high-gain image voltage signal in the high conversion gain mode respectively, and the low-gain storage control unit is used to store the low-gain reset voltage signal and the low-gain image voltage signal in the low conversion gain mode respectively;

[0009] The control circuit is at least used to provide a pixel circuit control signal to the pixel circuit, and the pixel circuit control signal includes the gain control signal.

[0010] Optionally, the high-gain storage control unit includes a high-gain reset voltage signal transmission branch and a high-gain image voltage signal transmission branch, the high-gain reset voltage signal transmission branch is used to transmit and store the high-gain reset voltage signal, and the high-gain image voltage signal transmission branch is used to transmit and store the high-gain image voltage signal; and / or, the low-gain storage control unit includes a low-gain reset voltage signal transmission branch and a low-gain image voltage signal transmission branch, the low-gain reset voltage signal transmission branch is used to transmit and store the low-gain reset voltage signal, and the low-gain image voltage signal transmission branch is used to transmit and store the low-gain image voltage signal.

[0011] Optionally, the high-gain reset voltage signal transmission branch includes a first high-gain control transistor and a first capacitor, the high-gain image voltage signal transmission branch includes a second high-gain control transistor and a second capacitor, and the high-gain storage control unit further includes a third high-gain control transistor; wherein:

[0012] The first connection terminal of the first high gain control transistor and the first connection terminal of the second high gain control transistor are coupled to the floating diffusion point; the gate terminal of the first high gain control transistor is connected to the first connection terminal of the third high gain control transistor, and the second connection terminal is connected to the third reference potential through the first capacitor; the gate terminal of the second high gain control transistor is connected to the second high gain control signal, and the second connection terminal is connected to the fourth reference potential through the second capacitor; the gate terminal of the third high gain control transistor is connected to the third high gain control signal, and the second connection terminal is connected to the fourth reference potential through the second capacitor;

[0013] And / or, the low-gain reset voltage signal transmission branch includes a first low-gain control transistor and a third capacitor, the low-gain image voltage signal transmission branch includes a second low-gain control transistor and a fourth capacitor, and the low-gain storage control unit further includes a third low-gain control transistor; wherein:

[0014] The first connection terminal of the first low gain control transistor and the first connection terminal of the second low gain control transistor are coupled to the floating diffusion point; the gate terminal of the first low gain control transistor is connected to the first connection terminal of the third low gain control transistor, and is connected to the fifth reference potential through the third capacitor; the gate terminal of the second low gain control transistor is connected to the second low gain control signal, and the second connection terminal is connected to the sixth reference potential through the fourth capacitor; the gate terminal of the third low gain control transistor is connected to the third low gain control signal, and the second connection terminal is connected to the sixth reference potential through the fourth capacitor.

[0015] Optionally, the high-gain storage control unit further includes a first high-gain source follower transistor, a second high-gain source follower transistor and a first row selection transistor; wherein:

[0016] The gate terminal of the first high-gain source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to the first variable voltage, and the second connection terminal is connected to the first connection terminal of the first high-gain control transistor and the first connection terminal of the second high-gain control transistor; the gate terminal of the first high-gain control transistor is connected to the first high-gain control signal, the second connection terminal is connected to the first connection terminal of the third high-gain control transistor, and is connected to the third reference potential through the first capacitor; the gate terminal of the second high-gain control transistor is connected to the second high-gain control signal, and the second connection terminal is connected to the fourth reference potential through the second capacitor; the gate terminal of the third high-gain control transistor is connected to the third high-gain control signal, and the second connection terminal is connected to the fourth reference potential through the second capacitor; the gate terminal of the second high-gain source follower transistor is connected to the first connection terminal of the third high-gain control transistor, the first connection terminal is connected to the second power supply voltage, and the second connection terminal is connected to the first connection terminal of the first row selection transistor; the gate terminal of the first row selection transistor is connected to the high-gain row selection signal, and the second connection terminal serves as the output terminal of the high-gain storage control unit;

[0017] The low-gain storage control unit further includes a first low-gain source follower transistor, a second low-gain source follower transistor and a second row selection transistor; wherein:

[0018] The gate terminal of the first low-gain source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to the second variable voltage, and the second connection terminal is connected to the first connection terminal of the first low-gain control transistor and the first connection terminal of the second low-gain control transistor; the gate terminal of the first low-gain control transistor is connected to the first low-gain control signal, the second connection terminal is connected to the first connection terminal of the third low-gain control transistor, and is connected to the fifth reference potential through the third capacitor; the gate terminal of the second low-gain control transistor is connected to the second low-gain control signal, and the second connection terminal is connected to the sixth reference potential through the fourth capacitor; the gate terminal of the third low-gain control transistor is connected to the third low-gain control signal, and the second connection terminal is connected to the sixth reference potential through the fourth capacitor; the gate terminal of the second low-gain source follower transistor is connected to the first connection terminal of the third low-gain control transistor, the first connection terminal is connected to the third power supply voltage, and the second connection terminal is connected to the first connection terminal of the second row selection transistor; the gate terminal of the second row selection transistor is connected to the low-gain row selection signal, and the second connection terminal serves as the output terminal of the low-gain storage control unit.

[0019] Optionally, the first high-gain source follower transistor and the first low-gain source follower transistor are the same source follower transistor, the gate terminal of the shared source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to a variable voltage, and the second connection terminal is respectively connected to the first connection terminal of the first high-gain control transistor, the first connection terminal of the second high-gain control transistor, the first connection terminal of the first low-gain control transistor and the first connection terminal of the second low-gain control transistor.

[0020] Optionally, the pixel circuit further includes: a photosensitivity control unit and a reset unit; wherein,

[0021] The photosensitive control unit is connected between the floating diffusion point and the first reference potential and is controlled by a transmission control signal, and is used to generate exposure charges according to a photoelectric effect and transfer and output the exposure charges according to the transmission control signal;

[0022] The reset unit comprises a reset transistor, a gate terminal of the reset transistor is connected to a reset control signal, a first connection terminal is connected to a first power supply voltage, and a second connection terminal is connected to the floating diffusion point;

[0023] The gain control unit is connected between the second connection terminal of the reset transistor and the floating diffusion point, and is used to adjust the equivalent charge storage capacity of the floating diffusion point according to the gain control signal so that the image sensor works in the different conversion gain modes.

[0024] Optionally, the photosensitivity control unit includes a photoelectric conversion element and a transfer transistor; the output end of the photoelectric conversion element is connected to the first connection end of the transfer transistor, and the other end is connected to the first reference potential; the gate end of the transfer transistor is connected to the transmission control signal, and the second connection end is connected to the floating diffusion point; and / or, the gain control unit includes a gain control transistor and a gain adjustment capacitor; the gate end of the gain control transistor is connected to the gain control signal, the first connection end is connected to the second connection end of the reset transistor, and is connected to the second reference potential through the gain adjustment capacitor, and the second connection end is connected to the floating diffusion point.

[0025] Optionally, the high-gain storage control unit and the low-gain storage control unit correspond to the same or different column lines to respectively realize serial output or parallel output of signals. Optionally, the image sensor further comprises: a readout circuit, the readout circuit comprising a high-gain readout unit and a low-gain readout unit, wherein: the high-gain readout unit is connected to the output end of the high-gain storage control unit, and is used to sequentially read out a high-gain reset voltage signal and a high-gain image voltage signal; the low-gain readout unit is connected to the output end of the low-gain storage control unit, and is used to sequentially read out a low-gain reset voltage signal and a low-gain image voltage signal;

[0026] The control circuit is further configured to provide a readout circuit control signal to the readout circuit.

[0027] Optionally, the high-gain readout unit at least includes a high-gain comparator and a high-gain counter; the first input end of the high-gain comparator is connected to the high-gain preset ramp voltage, the second input end is connected to the output end of the high-gain storage control unit, the output end is connected to the input end of the high-gain counter, and the output end of the high-gain counter serves as the output end of the high-gain readout unit; and / or, the low-gain readout unit includes a low-gain comparator and a low-gain counter; the first input end of the low-gain comparator is connected to the low-gain preset ramp voltage, the second input end is connected to the output end of the low-gain storage control unit, the output end is connected to the input end of the low-gain counter, and the output end of the low-gain counter serves as the output end of the low-gain readout unit; and / or, the high-gain readout unit also includes a high-gain memory connected to the output end of the high-gain counter; and / or, the low-gain readout unit also includes a low-gain memory connected to the output end of the low-gain counter.

[0028] Optionally, the high-gain readout unit further includes a fifth capacitor connected to the first input terminal of the high-gain comparator, and a sixth capacitor connected to the second input terminal of the high-gain comparator; and / or, the low-gain readout unit further includes a seventh capacitor connected to the first input terminal of the low-gain comparator; and an eighth capacitor connected to the second input terminal of the low-gain comparator; and / or, the high-gain readout unit further includes a first clearing switch and a second clearing switch, the first clearing switch being connected between the first input terminal of the high-gain comparator and the first-stage output terminal thereof, and the second clearing switch being connected between the second input terminal of the high-gain comparator and the second-stage output terminal thereof; and / or, the low-gain readout unit further includes a third clearing switch and a fourth clearing switch, the third clearing switch being connected between the first input terminal of the low-gain comparator and the first-stage output terminal thereof, and the fourth clearing switch being connected between the second input terminal of the low-gain comparator and the second-stage output terminal thereof.

[0029] Optionally, global exposure is implemented based on the image sensor, storage of high conversion gain signals in the global exposure mode is implemented based on the high gain storage control unit, and storage of low conversion gain signals in the global exposure mode is implemented based on the low gain storage control unit.

[0030] The present invention also provides a signal reading method of the image sensor as described in any one of the above items, comprising the steps of:

[0031] Based on the high gain storage control unit, the high gain reset voltage signal and the high gain image voltage signal in the high conversion gain mode are respectively stored;

[0032] The low gain reset voltage signal and the low gain image voltage signal in the low conversion gain mode are stored respectively based on the low gain storage control unit.

[0033] Optionally, when the high-gain reset voltage signal transmission branch, the high-gain image voltage signal transmission branch, the low-gain reset voltage signal transmission branch and the low-gain image voltage signal transmission branch exist, the following steps are performed in sequence:

[0034] A low gain reset voltage signal is collected based on the low gain reset voltage signal transmission branch, a high gain reset voltage signal is collected based on the high gain reset voltage signal transmission branch, a high gain image voltage signal is collected based on the high gain image voltage signal transmission branch, and a low gain image voltage signal is collected based on the low gain image voltage signal transmission branch.

[0035] Optionally, when the signal output mode of the high-gain storage control unit and the low-gain storage control unit is serial output, the high-gain readout unit and the low-gain readout unit perform readout operations successively;

[0036] When the signal output modes of the high-gain storage control unit and the low-gain storage control unit are parallel output, the high-gain readout unit and the low-gain readout unit perform readout operations simultaneously.

[0037] Optionally, the following steps are included:

[0038] Implementing global exposure based on the image sensor;

[0039] Simultaneously resetting the signals of the first capacitor and the second capacitor in the high-gain storage control unit and the third capacitor and the fourth capacitor in the low-gain storage control unit;

[0040] The third capacitor, the first capacitor, the second capacitor and the fourth capacitor are used to sequentially sample a low-gain reset voltage signal, a high-gain reset voltage signal, a high-gain image voltage signal and a low-gain image voltage signal;

[0041] The high-gain reset voltage signal and the high-gain image voltage signal are sequentially read out by the high-gain readout unit, and the low-gain reset voltage signal and the low-gain image voltage signal are sequentially read out by the low-gain readout unit.

[0042] Optionally, when the high-gain readout unit includes at least a high-gain comparator and a high-gain counter, the method for sequentially reading out the high-gain reset voltage signal and the high-gain image voltage signal includes: based on the high-gain readout unit, quantizing the high-gain reset voltage signal and outputting Vrst_hcg, and an average signal and outputting 1 / 2 (Vrst_hcg+Vsig_hcg), so that the high-gain readout unit quantizes and outputs 1 / 2 (Vrst_hcg-Vsig_hcg), wherein Vrst_hcg is the high-gain reset voltage signal, and Vsig_hcg is the high-gain image voltage signal;

[0043] When the low gain readout unit includes at least a low gain comparator and a low gain counter, the method for sequentially reading out the low gain reset voltage signal and the low gain image voltage signal includes: based on the low gain readout unit, quantizing the high gain reset voltage signal and outputting Vrst_lcg, and the average signal and outputting 1 / 2 (Vrst_lcg+Vsig_lcg), so that the low gain readout unit quantizes and outputs 1 / 2 (Vrst_lcg-Vsig_lcg), wherein Vrst_lcg is the low gain reset voltage signal, and Vsig_lcg is the low gain image voltage signal.

[0044] Optionally, the method further includes: a step of performing a clearing operation on the high-gain comparator and the low-gain comparator, and / or a step of performing a storage operation on the outputs of the high-gain readout unit and the low-gain readout unit.

[0045] As described above, an image sensor and a signal readout method thereof of the present invention effectively improve the dynamic range of the image sensor by combining dual conversion gain and global exposure, thereby achieving an increase in conversion gain with a smaller capacitor under low illumination conditions to improve sensitivity, and an increase in storage charge with a larger capacitor under high illumination conditions, thereby reducing the conversion gain to improve the dynamic range, thereby ensuring that the image sensor can capture images under extreme low light conditions without sacrificing performance under high illumination conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Shown is a schematic diagram of the pixel circuit with parallel output in the image sensor of the present invention.

[0047] Figure 2 Another schematic diagram of the pixel circuit with parallel output in the image sensor of the present invention is shown.

[0048] Figure 3 A schematic diagram of the pixel circuit with serial output in the image sensor of the present invention is shown.

[0049] Figure 4 Another schematic diagram of the pixel circuit with serial output in the image sensor of the present invention is shown.

[0050] Figure 5 Shown is a schematic diagram of the readout circuit in the image sensor of the present invention.

[0051] Figure 6 Shown by Figure 2 The pixel circuit and Figure 5 The timing diagram of each relevant signal in the image sensor formed by the readout circuit.

[0052] Component number description

[0053] 100 pixel circuit

[0054] 101 Photosensitive control unit

[0055] 102 Reset unit

[0056] 103 Gain Control Unit

[0057] 104 High gain storage control unit

[0058] 105 Low gain storage control unit

[0059] 200 Readout circuit

[0060] 201 High-gain readout unit

[0061] 201a High Gain Comparator

[0062] 201b High Gain Counter

[0063] 201c High Gain Memory

[0064] 202 Low gain readout unit

[0065] 202a Low Gain Comparator

[0066] 202b Low Gain Counter

[0067] 202c Low Gain Memory DETAILED DESCRIPTION

[0068] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0069] See also Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0070] like Figure 1-Figure 5 As shown, this embodiment provides an image sensor, which includes a pixel circuit 100 and a control circuit (not shown in the figure). Further, the image sensor also includes a readout circuit 200. It should be noted that the image sensor in this embodiment refers to a CMOS image sensor.

[0071] like Figure 1 As shown, the pixel circuit 100 at least includes a gain control unit 103, a high gain storage control unit 104 and a low gain storage control unit 105. Further, the pixel circuit 100 also includes a photosensitivity control unit 101 and a reset unit 102. In practical applications, the image sensor includes a plurality of pixel units arranged in rows and columns, and the pixel units correspond to the pixel circuit described in this embodiment.

[0072] The photosensitivity control unit 101 is connected between the floating diffusion point FD and the first reference potential and is controlled by a transmission control signal tx. It is used to generate exposure charges according to the photoelectric effect and transfer and output the exposure charges according to the transmission control signal tx.

[0073] As an example, the photosensitive control unit 101 includes a photoelectric conversion element and a transfer transistor M1; wherein the output end of the photoelectric conversion element is connected to the first connection end of the transfer transistor M1, and the other end is connected to the first reference potential; the gate end of the transfer transistor M1 is connected to the transmission control signal tx, and the second connection end is connected to the floating diffusion point FD. Optionally, the photoelectric conversion element is a photodiode PD, whose output end is the cathode of the photodiode PD, and the other end is the anode of the photodiode PD; the transfer transistor M1 is an NMOS tube, whose first connection end is the drain end, and the second connection end is the source end; the first reference potential is the ground potential.

[0074] In this embodiment, the photodiode PD generates exposure charges according to the photoelectric effect in response to incident light, and the transfer transistor M1 is turned on when the transfer control signal tx is at a high level, and transfers and outputs the exposure charges generated by the photodiode PD.

[0075] The reset unit 102 includes a reset transistor M2, the gate terminal of the reset transistor M2 is connected to the reset control signal rst, the first connection terminal is connected to the first power supply voltage VDD1, and the second connection terminal is connected to the floating diffusion point FD; it is used to reset the voltage of the floating diffusion point FD according to the reset control signal rst to complete the reset operation of the photoelectric conversion element (such as the photodiode PD). Optionally, the reset transistor M2 is an NMOS tube, the first connection terminal is the drain terminal, and the second connection terminal is the source terminal.

[0076] The gain control unit 103 receives a gain control signal dcg to enable the pixel circuit 100 to operate in different conversion gain modes, where the different conversion gain modes include a high conversion gain mode and a low conversion gain mode.

[0077] Specifically, the gain control unit 103 is connected between the second connection terminal of the reset transistor M2 and the floating diffusion point FD, and is controlled by a gain control signal dcg, and is used to adjust the equivalent charge storage capacity of the floating diffusion point FD according to the gain control signal dcg, so that the image sensor operates in the different conversion gain modes.

[0078] As an example, the gain control unit 103 includes a gain control transistor M3 and a gain adjustment capacitor Cdcg; wherein the gate terminal of the gain control transistor M3 is connected to the gain control signal dcg, the first connection terminal is connected to the second connection terminal of the reset transistor M2, and is connected to the second reference potential through the gain adjustment capacitor Cdcg, and the second connection terminal is connected to the floating diffusion point FD. Optionally, the gain control transistor M3 is an NMOS tube, the first connection terminal of which is the drain terminal, and the second connection terminal is the source terminal; the gain adjustment capacitor Cdcg can be a parasitic capacitance of the connection point between the reset transistor M2 and the gain control transistor M3 to the ground, or it can be a device capacitor (i.e., an external capacitor); the second reference potential is the ground potential.

[0079] In this embodiment, when the gain control signal dcg is at a high level, the gain control transistor M3 is turned on, and the equivalent charge storage capacity of the floating diffusion point FD is increased through the gain adjustment capacitor Cdcg, so that the final charge storage capacity is the sum of the charge storage capacity of the floating diffusion point FD itself and the charge storage capacity of the gain adjustment capacitor Cdcg. At this time, the image sensor in this embodiment operates in a low conversion gain mode (LCG); conversely, when the gain control signal dcg is at a low level, the gain control transistor M3 is turned off, so that the charge storage capacity of the floating diffusion point FD itself is the final charge storage capacity. At this time, the image sensor in this embodiment operates in a high conversion gain mode (HCG).

[0080] The high gain storage control unit 104 is connected to the floating diffusion point FD and is used to store the high gain reset voltage signal Vrst_hcg and the high gain image voltage signal Vsig_hcg in the high conversion gain mode respectively.

[0081] Specifically, the high gain storage control unit 104 includes a high gain reset voltage signal transmission branch and a high gain image voltage signal transmission branch. The high gain reset voltage signal transmission branch is used to transmit and store the high gain reset voltage signal Vrst_hcg, and the high gain image voltage signal transmission branch is used to transmit and store the high gain image voltage signal Vsig_hcg.

[0082] As an example, the high-gain reset voltage signal transmission branch includes a first high-gain control transistor M5 and a first capacitor C1, the high-gain image voltage signal transmission branch includes a second high-gain control transistor M6 and a second capacitor C2, and the high-gain storage control unit 104 also includes a third high-gain control transistor M7; wherein: the first connection end of the first high-gain control transistor M5 and the first connection end of the second high-gain control transistor M6 are coupled to the floating diffusion point FD; the gate end of the first high-gain control transistor M5 is connected to the first high-gain control signal rst_hcg, the second connection end is connected to the first connection end of the third high-gain control transistor M7, and is connected to the third reference potential through the first capacitor C1; the gate end of the second high-gain control transistor M6 is connected to the second high-gain control signal sig_hcg, and the second connection end is connected to the fourth reference potential through the second capacitor C2; the gate end of the third high-gain control transistor M7 is connected to the third high-gain control signal rs_hcg, and the second connection end is connected to the fourth reference potential through the second capacitor C2.

[0083] Furthermore, the high-gain storage control unit 104 also includes a first high-gain source follower transistor M4, a second high-gain source follower transistor M8 and a first row selection transistor M9; wherein: the gate terminal of the first high-gain source follower transistor M4 is connected to the floating diffusion point FD, the first connection terminal is connected to the first variable voltage Vrsf1, the second connection terminal is connected to the first connection terminal of the first high-gain control transistor M5 and the first connection terminal of the second high-gain control transistor M6; the gate terminal of the first high-gain control transistor M5 is connected to the first high-gain control signal rst_hcg, the second connection terminal is connected to the first connection terminal of the third high-gain control transistor M7, and is connected to the third reference potential through the first capacitor C1; the second high-gain control The gate terminal of the control transistor M6 is connected to the second high gain control signal sig_hcg, and the second connection terminal is connected to the fourth reference potential through the second capacitor C2; the gate terminal of the third high gain control transistor M7 is connected to the third high gain control signal rs_hcg, and the second connection terminal is connected to the fourth reference potential through the second capacitor C2; the gate terminal of the second high gain source follower transistor M8 is connected to the first connection terminal of the third high gain control transistor M7, the first connection terminal is connected to the second power supply voltage VDD2, and the second connection terminal is connected to the first connection terminal of the first row selection transistor M9; the gate terminal of the first row selection transistor M9 is connected to the high gain row selection signal sel_hcg, and the second connection terminal serves as the output terminal of the high gain storage control unit 104. Optionally, the first high gain source follower transistor M4, the first high gain control transistor M5, the second high gain control transistor M6, the third high gain control transistor M7, the second high gain source follower transistor M8 and the first row selection transistor M9 are all NMOS transistors, whose first connection end is a drain end, and the second connection end is a source end; the third reference potential and the fourth reference potential are both ground potentials; the second power supply voltage VDD2 is the same as the first power supply voltage VDD1, and both are operating voltages of the image sensor.

[0084] In this embodiment, when the first high gain control signal rst_hcg is at a high level and the second high gain control signal sig_hcg is at a low level, the first high gain control transistor M5 is turned on and the second high gain control transistor M6 is turned off. At this time, the high gain reset voltage signal Vrst_hcg stored in the floating diffusion point FD can be stored in the first capacitor C1 through the turned-on first high gain control transistor M5, and the high gain reset voltage signal Vrst_hcg may not be stored in the second capacitor C2, so that the second capacitor C2 does not need to be reset before the subsequent storage of the high gain image voltage signal Vsig_hcg, which can save time in terms of timing; when the second high gain control signal sig_hcg is at a high level and the first high gain control signal rst_hcg is at a low level, the second high gain control transistor M6 is turned on and the first high gain control transistor M5 is turned off. At this time, the high gain image voltage signal Vsig_hcg stored in the floating diffusion point FD can be stored in the second capacitor C2 through the turned-on second high gain control transistor M6. When the voltage signal is read out, the high gain reset voltage signal Vrst_hcg stored in the first capacitor C1 is read out first, and then the third high gain control signal rs_hcg is set to a high level, the third high gain control transistor M7 is turned on, and the high gain image voltage signal Vsig_hcg stored in the second capacitor C2 is read out; when the high gain image voltage signal Vsig_hcg is read out, since charge redistribution is required, the actually read voltage signal is 1 / 2 (Vrst_hcg+Vsig_hcg).

[0085] The low gain storage control unit 105 and the high gain storage control unit 104 are arranged in parallel and connected to the floating diffusion point FD, and are used to store the low gain reset voltage signal Vrst_lcg and the low gain image voltage signal Vsig_lcg in the low conversion gain mode respectively.

[0086] Specifically, the low gain storage control unit 105 includes a low gain reset voltage signal transmission branch and a low gain image voltage signal transmission branch. The low gain reset voltage signal transmission branch is used to transmit and store the low gain reset voltage signal Vrst_lcg, and the low gain image voltage signal transmission branch is used to transmit and store the low gain image voltage signal Vsig_lcg.

[0087] As an example, the low-gain reset voltage signal transmission branch includes a first low-gain control transistor M11 and a third capacitor C3, the low-gain image voltage signal transmission branch includes a second low-gain control transistor M12 and a fourth capacitor C4, and the low-gain storage control unit 105 also includes a third low-gain control transistor M13; wherein: the first connection end of the first low-gain control transistor M11 and the first connection end of the second low-gain control transistor M12 are coupled to the floating diffusion point FD; the gate end of the first low-gain control transistor M11 is connected to the first low-gain control signal rst_lcg, the second connection end is connected to the first connection end of the third low-gain control transistor M13, and is connected to the fifth reference potential through the third capacitor C3; the gate end of the second low-gain control transistor M12 is connected to the second low-gain control signal sig_lcg, and the second connection end is connected to the sixth reference potential through the fourth capacitor C4; the gate end of the third low-gain control transistor M13 is connected to the third low-gain control signal rs_lcg, and the second connection end is connected to the sixth reference potential through the fourth capacitor C4.

[0088] Furthermore, the low gain storage control unit 105 also includes a first low gain source follower transistor M10, a second low gain source follower transistor M14 and a second row selection transistor M15; wherein: the gate terminal of the first low gain source follower transistor M10 is connected to the floating diffusion point FD, the first connection terminal is connected to the second variable voltage Vrsf2, the second connection terminal is connected to the first connection terminal of the first low gain control transistor M11 and the first connection terminal of the second low gain control transistor M12; the gate terminal of the first low gain control transistor M11 is connected to the first low gain control signal rst_lcg, the second connection terminal is connected to the first connection terminal of the third low gain control transistor M13, and is connected to the fifth reference potential through the third capacitor C3; the second low gain The gate terminal of the gain control transistor M12 is connected to the second low gain control signal sig_lcg, and the second connection terminal is connected to the sixth reference potential through the fourth capacitor C4; the gate terminal of the third low gain control transistor M13 is connected to the third low gain control signal rs_lcg, and the second connection terminal is connected to the sixth reference potential through the fourth capacitor C4; the gate terminal of the second low gain source follower transistor M14 is connected to the first connection terminal of the third low gain control transistor M13, the first connection terminal is connected to the third power supply voltage VDD3, and the second connection terminal is connected to the first connection terminal of the second row selection transistor M15; the gate terminal of the second row selection transistor M15 is connected to the low gain row selection signal sel_lcg, and the second connection terminal serves as the output terminal of the low gain storage control unit 105. Optionally, the first low gain source follower transistor M10, the first low gain control transistor M11, the second low gain control transistor M12, the third low gain control transistor M13, the second low gain source follower transistor M14 and the second row selection transistor M15 are all NMOS transistors, whose first connection end is a drain end, and the second connection end is a source end; the second variable voltage Vrsf2 is the same as the first variable voltage Vrsf1; the fifth reference potential and the sixth reference potential are both ground potentials; the third power supply voltage VDD3 is the same as the first power supply voltage VDD1, and both are operating voltages of the image sensor.

[0089] In this embodiment, when the first low gain control signal rst_lcg is at a high level and the second low gain control signal sig_lcg is at a low level, the first low gain control transistor M11 is turned on and the second low gain control transistor M12 is turned off. At this time, the low gain reset voltage signal Vrst_lcg stored in the floating diffusion point FD can be stored in the third capacitor C3 through the turned-on first low gain control transistor M11, and the low gain reset voltage signal Vrst_lcg may not be stored in the fourth capacitor C4, so that it is not necessary to reset the fourth capacitor C4 before the subsequent storage of the low gain image voltage signal Vsig_lcg, which can save time in terms of timing; when the second low gain control signal sig_lcg is at a high level and the first low gain control signal rst_lcg is at a low level, the second low gain control transistor M12 is turned on and the first low gain control transistor M11 is turned off. At this time, the low gain image voltage signal Vsig_lcg stored in the floating diffusion point FD can be stored in the fourth capacitor C4 through the turned-on second low gain control transistor M12. When the voltage signal is read out, the low gain reset voltage signal Vrst_lcg stored in the third capacitor C3 is read out first, and then the third low gain control signal rs_lcg is set to a high level, the third low gain control transistor M13 is turned on, and the low gain image voltage signal Vsig_lcg stored in the fourth capacitor C4 is read out; when the low gain image voltage signal Vsig_lcg is read out, since charge redistribution is required, the actually read voltage signal is 1 / 2 (Vrst_lcg+Vsig_lcg).

[0090] In order to simplify the circuit, the first high-gain source follower transistor M4 and the first low-gain source follower transistor M10 are the same source follower transistor, the gate terminal of the shared source follower transistor is connected to the floating diffusion point FD, the first connection terminal is connected to the variable voltage Vrsf, and the second connection terminal is respectively connected to the first connection terminal of the first high-gain control transistor M5, the first connection terminal of the second high-gain control transistor M6, the first connection terminal of the first low-gain control transistor M11 and the first connection terminal of the second low-gain control transistor M12 (such as Figure 2 In addition, it should be noted that in this embodiment, the variable voltage Vrsf (in other embodiments, Vrsf1 and Vrsf2 may be used) can save the number of transistors, reduce the transistor area, and reduce the wiring settings.

[0091] In order to achieve flexible output, the high-gain storage control unit 104 and the low-gain storage control unit 105 correspond to the same or different column lines to respectively achieve serial output or parallel output of signals; if the high-gain storage control unit 104 and the low-gain storage control unit 105 correspond to different column lines, the parallel output of signals (such as Figure 1 and Figure 2 Alternatively, the high gain storage control unit 104 and the low gain storage control unit 105 correspond to the same column line to achieve serial output of the signal (as shown in Figure 3 and Figure 4 In practical applications, parallel output and serial output can be selected according to specific needs, which has no effect on this embodiment. It is only necessary to adjust the turn-on timing of the high-gain row selection signal sel_hcg and the low-gain row selection signal sel_lcg.

[0092] like Figure 5 As shown, the readout circuit 200 includes a high-gain readout unit 201 and a low-gain readout unit 202; wherein the high-gain readout unit 201 is connected to the output end of the high-gain storage control unit 104, and is used to sequentially read out the high-gain reset voltage signal Vrst_hcg and the high-gain image voltage signal Vsig_hcg; the low-gain readout unit 202 is connected to the output end of the low-gain storage control unit 105, and is used to sequentially read out the low-gain reset voltage signal Vrst_lcg and the low-gain image voltage signal Vsig_lcg.

[0093] As an example, the high-gain readout unit 201 at least includes a high-gain comparator 201a and a high-gain counter 201b, the first input terminal vinp of the high-gain comparator 201a is connected to the high-gain preset ramp voltage vramp_hcg, the second input terminal vinn is connected to the output terminal of the high-gain storage control unit 104, the output terminal vout is connected to the input terminal of the high-gain counter 201b, and the output terminal of the high-gain counter 201b serves as the output terminal of the high-gain readout unit 201; and / or, the low-gain readout unit 202 includes a low-gain comparator 202a and a low-gain counter 202b, the first input terminal vinp of the low gain comparator 202a is connected to the low gain preset ramp voltage vramp_lcg, the second input terminal vinn is connected to the output terminal of the low gain storage control unit 105, the output terminal vout is connected to the input terminal of the low gain counter 202b, and the output terminal of the low gain counter 202b serves as the output terminal of the low gain readout unit 202; wherein the high gain counter 201b is controlled by the high gain enable signal count_en_hcg, and the low gain counter 202b is controlled by the low gain enable signal count_en_lcg.

[0094] In this embodiment, when the high gain enable signal count_en_hcg is valid, the high gain counter 201b starts counting; the high gain comparator 201a is used to compare the output of the high gain storage control unit 104 with the high gain preset ramp voltage vramp_hcg, and when the output of the high gain storage control unit 104 is equal to the high gain preset ramp voltage vramp_hcg, its output is reversed, thereby triggering the high gain counter 201b to stop counting, thereby completing the quantization readout of the corresponding voltage signal. Similarly, when the low gain enable signal count_en_lcg is valid, the low gain counter 202b starts counting; the low gain comparator 202a is used to compare the output of the low gain storage control unit 105 with the low gain preset ramp voltage vramp_lcg, and when the output of the low gain storage control unit 105 is equal to the low gain preset ramp voltage vramp_lcg, its output is reversed, thereby triggering the low gain counter 202b to stop counting, thereby completing the quantization readout of the corresponding voltage signal. In practical applications, the corresponding counter can be made to count down first and then count up, so as to directly obtain the pixel signal; of course, the corresponding counter can also be made to count up or down at the same time, and then the back-end image processing circuit can be used to subtract the two counting results to obtain the pixel signal.

[0095] Further, the high-gain readout unit 201 also includes a first clearing switch S1 and a second clearing switch S2, the first clearing switch S1 is connected between the first input terminal vinp and the first-stage output terminal vop of the high-gain comparator 201a, and the second clearing switch S2 is connected between the second input terminal vinn and the second-stage output terminal von of the high-gain comparator 201a; and / or, the low-gain readout unit 202 also includes a third clearing switch S3 and a fourth clearing switch S4, the third clearing switch S3 is connected between the first input terminal vinp and the first-stage output terminal vop of the low-gain comparator 202a, and the fourth clearing switch S4 is connected between the second input terminal vinn and the second-stage output terminal von of the low-gain comparator 202a; wherein the first clearing switch S1 and the second clearing switch S2 are controlled by the high-gain clearing signal cmp_az_hcg, and the third clearing switch S3 and the fourth clearing switch S4 are controlled by the low-gain clearing signal cmp_az_lcg. Optionally, in this embodiment, the high-gain readout unit 201 includes a first clearing switch S1 and a second clearing switch S2, and the low-gain readout unit 202 includes a third clearing switch S3 and a fourth clearing switch S4.

[0096] In this embodiment, when the high-gain clearing signal cmp_az_hcg is valid, the first clearing switch S1 and the second clearing switch S2 are connected, and the first input terminal vinp and the first-stage output terminal vop, the second input terminal vinn and the second-stage output terminal von of the high-gain comparator 201a are short-circuited, so as to clear the high-gain comparator 201a; similarly, when the low-gain clearing signal cmp_az_lcg is valid, the third clearing switch S3 and the fourth clearing switch S4 are connected, and the first input terminal vinp and the first-stage output terminal vop, the second input terminal vinn and the second-stage output terminal von of the low-gain comparator 202a are short-circuited, so as to clear the low-gain comparator 202a.

[0097] Further, the high-gain readout unit 201 further includes a fifth capacitor C5 connected to the first input terminal vinp of the high-gain comparator 201a, and a sixth capacitor C6 connected to the second input terminal vinn of the high-gain comparator 201a; and / or, the low-gain readout unit 202 further includes a seventh capacitor C7 connected to the first input terminal vinp of the low-gain comparator 202a; and an eighth capacitor C8 connected to the second input terminal vinn of the low-gain comparator 202a. It should be noted that the high-gain readout unit 201 of this embodiment may include only one of the fifth capacitor C5 and the sixth capacitor C6, or may include both the fifth capacitor C5 and the sixth capacitor C6; similarly, the low-gain readout unit 202 may include only one of the seventh capacitor C7 and the eighth capacitor C8, or may include both the seventh capacitor C7 and the eighth capacitor C8; at the same time, the number and position of the capacitors in the high-gain readout unit 201 and the low-gain readout unit 202 may be the same or different. Optionally, in this embodiment, the high-gain readout unit 201 includes a fifth capacitor C5 and a sixth capacitor C6, and the low-gain readout unit 202 includes a seventh capacitor C7 and an eighth capacitor C8, which are used to buffer the voltage signal input to the corresponding comparator; wherein the fifth capacitor C5 and the seventh capacitor C7 are variable capacitors, and their specific capacitance values ​​can be set according to the corresponding high-gain preset ramp voltage vramp_hcg and the low-gain preset ramp voltage vramp_lcg.

[0098] Furthermore, the high-gain readout unit 201 also includes a high-gain memory 201c, which is connected to the output end of the high-gain counter 201b and is used to store the output of the high-gain counter 201b; and / or, the low-gain readout unit 202 also includes a low-gain memory 202c, which is connected to the output end of the low-gain counter 202b and is used to store the output of the low-gain counter 202b.

[0099] The control circuit (not shown in the figure) is at least used to provide a pixel circuit control signal to the pixel circuit 100, and the pixel circuit control signal includes the gain control signal dcg; the control circuit is also used to provide a readout circuit control signal to the readout circuit 200. In actual applications, the pixel circuit control signal also includes a transmission control signal tx, a reset control signal rst, a first high gain control signal rst_hcg, a second high gain control signal sig_hcg, a third high gain control signal rs_hcg, a high gain row selection signal sel_hcg, a first low gain control signal rst_lcg, a second low gain control signal sig_lcg, a third low gain control signal rs_lcg, and a low gain row selection signal sel_lcg; the readout circuit control signal includes a high gain clear signal cmp_az_hcg, a low gain clear signal cmp_az_lcg, a high gain enable signal count_en_hcg, and a low gain enable signal count_en_lcg; in this embodiment, the control circuit is used to sequentially store a low gain reset voltage signal Vrst_lcg, a high gain reset voltage signal Vrst_hcg, a high gain image voltage signal Vsig_hcg, and a low gain image voltage signal Vsig_lcg, and to control the quantized readout of the above voltage signals. Optionally, the control circuit is implemented using a controller.

[0100] This embodiment implements global exposure based on the image sensor, implements storage of high conversion gain signals in the global exposure mode based on the high gain storage control unit 104, and implements storage of low conversion gain signals in the global exposure mode based on the low gain storage control unit 105.

[0101] Accordingly, this embodiment further provides a signal reading method of the image sensor as described above, comprising the following steps:

[0102] 1) Based on the high gain storage control unit 104, the high gain reset voltage signal Vrst_hcg and the high gain image voltage signal Vsig_hcg in the high conversion gain mode are stored respectively;

[0103] 2) Based on the low gain storage control unit 105, the low gain reset voltage signal Vrst_lcg and the low gain image voltage signal Vsig_lcg in the low conversion gain mode are stored respectively.

[0104] Specifically, when the high-gain reset voltage signal transmission branch, the high-gain image voltage signal transmission branch, the low-gain reset voltage signal transmission branch and the low-gain image voltage signal transmission branch exist, the following steps are performed in sequence: based on the low-gain reset voltage signal transmission branch, a low-gain reset voltage signal Vrst_lcg is collected; based on the high-gain reset voltage signal transmission branch, a high-gain reset voltage signal Vrst_hcg is collected; based on the high-gain image voltage signal transmission branch, a high-gain image voltage signal Vsig_hcg is collected; and based on the low-gain image voltage signal transmission branch, a low-gain image voltage signal Vsig_lcg is collected.

[0105] More specifically, the specific steps of the signal readout method include:

[0106] S1 implements global exposure based on the image sensor.

[0107] S2 simultaneously resets the signals of the first capacitor C1 and the second capacitor C2 in the high-gain storage control unit 104 and the third capacitor C3 and the fourth capacitor C4 in the low-gain storage control unit 105 .

[0108] During specific operation, the variable voltage Vrsf is set to a low level, and the first high gain control signal rst_hcg, the second high gain control signal sig_hcg, the first low gain control signal rst_lcg, and the second low gain control signal sig_lcg are set to a high level, so that the first high gain control transistor M5, the second high gain control transistor M6, the first low gain control transistor M11, and the second low gain control transistor M12 are turned on, thereby pulling the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 to a low level, thereby realizing signal resetting of the four capacitors at the same time.

[0109] 3) The low gain reset voltage signal Vrst_lcg, the high gain reset voltage signal Vrst_hcg, the high gain image voltage signal Vsig_hcg and the low gain image voltage signal Vsig_lcg are sampled in sequence through the third capacitor C3, the first capacitor C1, the second capacitor C2 and the fourth capacitor C4.

[0110] During specific operation, the gain control signal dcg is set to a high level to turn on the gain control transistor M3, and then the reset control signal rst is set to a low level to turn off the reset transistor M2, and a low gain reset voltage signal Vrst_lcg is obtained at the floating diffusion point FD; the first low gain control signal rst_lcg is set to a high level to turn on the first low gain control transistor M11, so as to store the low gain reset voltage signal Vrst_lcg on the third capacitor C3.

[0111] The gain control signal dcg is set to a low level, so that the gain control transistor M3 is turned off, and a high gain reset voltage signal Vrst_hcg is obtained at the floating diffusion point FD; the first high gain control signal rst_hcg is set to a high level, so that the first high gain control transistor M5 is turned on, so that the high gain reset voltage signal Vrst_hcg is stored on the first capacitor C1.

[0112] The transmission control signal tx is set to a high level to turn on the transmission transistor M1, and a high-gain image voltage signal Vsig_hcg is obtained at the floating diffusion point FD; the second high-gain control signal sig_hcg is set to a high level to turn on the second high-gain control transistor M6, so that the high-gain image voltage signal Vsig_hcg is stored on the second capacitor C2.

[0113] The gain control signal dcg is set to a high level to turn on the gain control transistor M3 and switch the image sensor to a low conversion gain mode; the transmission control signal tx is set to a high level to turn on the transmission transistor M1 and obtain a low gain image voltage signal Vsig_lcg at the floating diffusion point FD; the second low gain control signal sig_lcg is set to a high level to turn on the second low gain control transistor M12 and store the low gain image voltage signal Vsig_lcg on the fourth capacitor C4.

[0114] 4) The high gain reset voltage signal Vrst_hcg and the high gain image voltage signal Vsig_hcg are sequentially read out through the high gain readout unit 201 , and the low gain reset voltage signal Vrst_lcg and the low gain image voltage signal Vsig_lcg are sequentially read out through the low gain readout unit 202 .

[0115] Specifically, the signal output mode of the high-gain storage control unit 104 and the low-gain storage control unit 105 includes serial output or parallel output. When the signal output mode of the high-gain storage control unit 104 and the low-gain storage control unit 105 is serial output, the high-gain readout unit 201 and the low-gain readout unit 202 perform readout operations successively; and when the signal output mode of the high-gain storage control unit 104 and the low-gain storage control unit 105 is parallel output, the high-gain readout unit 201 and the low-gain readout unit 202 perform readout operations simultaneously. It should be noted that the "high-gain readout unit 201 and the low-gain readout unit 202 perform readout operations successively" in this embodiment does not limit the order of the two, and the high-gain readout unit 201 may be in front and the low-gain readout unit 202 may be in the back, or the low-gain readout unit 202 may be in front and the high-gain readout unit 201 may be in the back, which has no effect on this embodiment. In practical applications, in order to shorten the pixel period, parallel output is usually used in combination with simultaneous readout operations.

[0116] Specifically, when the high-gain readout unit 201 includes at least a high-gain comparator 201a and a high-gain counter 201b, the method for sequentially reading out the high-gain reset voltage signal Vrst_hcg and the high-gain image voltage signal Vsig_hcg includes: based on the high-gain readout unit 201, quantizing the high-gain reset voltage signal and outputting Vrst_hcg, and the average signal and outputting 1 / 2 (Vrst_hcg+Vsig_hcg), so that the high-gain readout unit quantizes and outputs 1 / 2 (Vrst_hcg-Vsig_hcg), wherein Vrst_hcg is the high-gain reset voltage signal, and Vsig _hcg is the high gain image voltage signal; when the low gain readout unit includes at least a low gain comparator and a low gain counter, the method for sequentially reading out the low gain reset voltage signal and the low gain image voltage signal includes: based on the low gain readout unit, quantizing the high gain reset voltage signal and outputting Vrst_lcg, and the average signal and outputting 1 / 2 (Vrst_lcg+Vsig_lcg), so that the low gain readout unit quantizes and outputs 1 / 2 (Vrst_lcg-Vsig_lcg), wherein Vrst_lcg is the low gain reset voltage signal, and Vsig_lcg is the low gain image voltage signal.

[0117] More specifically, when the high-gain readout unit 201 includes at least a high-gain comparator 201a and a high-gain counter 201b, the method of sequentially reading out the high-gain reset voltage signal Vrst_hcg and the high-gain image voltage signal Vsig_hcg includes: the high-gain counter 201b counts down until the high-gain comparator 201a flips, and then the high-gain counter 201b counts up until the high-gain comparator 201a flips again, so that the high-gain readout unit 201 quantizes and outputs 1 / 2 (Vrst_hcg-Vsig_hcg), that is, directly obtaining the pixel voltage in the high conversion gain mode. signal; when the low gain readout unit 202 includes at least a low gain comparator 202a and a low gain counter 202b, the method of sequentially reading out the low gain reset voltage signal Vrst_lcg and the low gain image voltage signal Vsig_lcg includes: the low gain counter 202b counts down until the low gain comparator 202a flips, and then the low gain counter 202b counts up until the low gain comparator 202a flips again, so that the low gain readout unit 202 quantizes and outputs 1 / 2 (Vrst_lcg-Vsig_lcg), that is, directly obtaining the pixel signal in the low conversion gain mode. In the specific operation, the high-gain row selection signal sel_hcg and the low-gain row selection signal sel_lcg are first set to a high level, so that the first row selection transistor M9 and the second row selection transistor M15 are turned on, so that the high-gain readout unit 201 quantizes and reads the high-gain reset voltage signal Vrst_hcg, and the low-gain readout unit 202 quantizes and reads the low-gain reset voltage signal Vrst_lcg; then, the third high-gain control signal rs_hcg and the third low-gain control signal rs_lcg are set to a high level, so that the third high-gain control transistor M7 and the third low-gain control transistor M13 are turned on, and charge redistribution is performed, so that the high-gain readout unit 201 quantizes and reads 1 / 2 (Vrst_lcg). t_hcg+Vsig_hcg), the low gain readout unit 202 quantizes and reads out 1 / 2 (Vrst_lcg+Vsig_lcg); since the high gain counter 201b and the low gain counter 202b first count down and then count up, the final quantization output result of the high gain counter 201b is Vrst_hcg-1 / 2(Vrst_hcg+Vsig_hcg)=1 / 2(Vrst_hcg-Vsig_hcg), and the final quantization output result of the low gain counter 202b is Vrst_lcg-1 / 2(Vrst_lcg+Vsig_lcg)=1 / 2(Vrst_lcg-Vsig_lcg).

[0118] Furthermore, the method further includes: a step of performing a zeroing operation on the high gain comparator 201a and the low gain comparator 202a, and / or a step of performing a storage operation on the outputs of the high gain readout unit 201 and the low gain readout unit 202.

[0119] In specific operations, clearing can be achieved by setting clearing switches at the corresponding input and output ends of the comparator, and storage can be achieved by setting a memory at the back end of the corresponding counter.

[0120] Please combine the following Figure 2 , see Figure 5 , to describe in detail the working process of the image sensor described in this embodiment; wherein, the high gain storage control unit 104 and the low gain storage control unit 105 in the pixel circuit 100 adopt parallel output, the high gain readout unit 201 and the low gain readout unit 202 in the readout circuit 200 perform readout operations simultaneously, and the high gain counter 201b and the low gain counter 202b quantize the output by first counting down and then counting up.

[0121] At time t0, the variable voltage Vrsf becomes a low level; at time t1 to t2, the first high gain control signal rst_hcg, the second high gain control signal sig_hcg, the first low gain control signal rst_lcg, and the second low gain control signal sig_lcg are high levels, the first high gain control transistor M5, the second high gain control transistor M6, the first low gain control transistor M11, and the second low gain control transistor M12 are turned on, and the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are pulled to a low level; at time t3, the variable voltage Vrsf returns to a high level, completing global pre-charge;

[0122] At time t4, the gain control signal dcg is at a high level, the gain control transistor M3 is turned on, the reset control signal rst becomes a low level, the reset transistor M2 is turned off, and a low gain reset voltage signal Vrst_lcg in a low conversion gain mode is obtained;

[0123] From t5 to t6, the first low gain control signal rst_lcg is at a high level, the first low gain control transistor M11 is turned on, and the low gain reset voltage signal Vrst_lcg is stored on the third capacitor C3, completing the reset voltage signal sampling (sample LCG rst) in the low conversion gain mode;

[0124] At time t7, the gain control signal dcg becomes low level, the gain control transistor M3 is turned off, and a high gain reset voltage signal Vrst_hcg in a high conversion gain mode is obtained;

[0125] From t8 to t9, the first high gain control signal rst_hcg is at a high level, the first high gain control transistor M5 is turned on, and the high gain reset voltage signal Vrst_hcg is stored on the first capacitor C1, completing the reset voltage signal sampling (sample HCG rst) in the high conversion gain mode;

[0126] From t10 to t11, the transmission control signal tx is set to a high level, the transmission transistor M1 is turned on, and the high-gain image voltage signal Vsig_hcg in the high conversion gain mode begins to be transmitted;

[0127] From t12 to t13, the second high gain control signal sig_hcg is at a high level, the second high gain control transistor M6 is turned on, and the high gain image voltage signal Vsig_hcg is stored on the second capacitor C2, completing the image voltage signal sampling (sample HCG sig) in the high conversion gain mode;

[0128] At time t14, the gain control signal dcg becomes high level, the gain control transistor M3 is turned on, and the mode is switched to low conversion gain;

[0129] From time t15 to time t16, the transmission control signal tx is set to a high level, the transmission transistor M1 is turned on, and the low-gain image voltage signal Vsig_lcg in the low conversion gain mode begins to be transmitted;

[0130] From t17 to t18, the second low gain control signal sig_lcg is at a high level, the second low gain control transistor M12 is turned on, and the low gain image voltage signal Vsig_lcg is stored in the fourth capacitor C4, completing the image voltage signal sampling (sample LCG sig) in the low conversion gain mode;

[0131] From t20 to t29, the high-gain row selection signal sel_hcg and the low-gain row selection signal sel_lcg are at a high level, entering the voltage signal readout phase (read);

[0132] From t21 to t22, the high gain clearing signal cmp_az_hcg and the low gain clearing signal cmp_az_lcg are valid, the first clearing switch S1, the second clearing switch S2, the third clearing switch S3 and the fourth clearing switch S4 are connected, and the high gain comparator 201a and the low gain comparator 202a are cleared;

[0133] At time t23, the high gain enable signal count_en_hcg and the low gain enable signal count_en_lcg are valid, and the high gain counter 201b and the low gain counter 202b start counting down until the output of the corresponding comparator is flipped and stops counting, thereby obtaining the high gain reset voltage signal Vrst_hcg and the low gain reset voltage signal Vrst_lcg; at time t24, the quantization of the reset voltage signals in different conversion gain modes is completed;

[0134] From t25 to t26, the third high gain control signal rs_hcg and the third low gain control signal rs_lcg are at high level, the third high gain control transistor M7 and the third low gain control transistor M13 are turned on, and the voltage signals 1 / 2 (Vrst_hcg+Vsig_hcg) and 1 / 2 (Vrst_lcg+Vsig_lcg) are read out;

[0135] At time t27, the high gain enable signal count_en_hcg and the low gain enable signal count_en_lcg are valid, and the high gain counter 201b and the low gain counter 202b start counting up until the output of the corresponding comparator is flipped and stops counting. The high gain counter 201b finally outputs a high gain pixel signal 1 / 2 (Vrst_hcg-Vsig_hcg), and the low gain counter 202b finally outputs a low gain pixel signal 1 / 2 (Vrst_lcg-Vsig_lcg), that is, the pixel signal quantization value of the correlated double sampling is obtained; at time t28, the pixel signal quantization is completed.

[0136] It can be seen that this embodiment saves time by storing the high-gain reset voltage signal Vrst_hcg and the high-gain image voltage signal Vsig_hcg separately, and storing the low-gain reset voltage signal Vrst_lcg and the low-gain image voltage signal Vsig_lcg separately, thereby eliminating multiple charge clearing steps in the sampling stage and the readout stage.

[0137] In summary, an image sensor and a signal readout method thereof of the present invention effectively improve the dynamic range of the image sensor by combining dual conversion gain and global exposure, and realize that the conversion gain is increased with a smaller capacitor under low illumination conditions to improve sensitivity, and the storage charge is increased with a larger capacitor under high illumination conditions, and the conversion gain is reduced to improve the dynamic range, thereby ensuring that the image sensor can capture images under extreme low light conditions without sacrificing performance under high illumination conditions. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0138] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An image sensor, It is characterized in that It includes a pixel circuit and a control circuit; wherein, The pixel circuit at least includes a gain control unit, a high gain storage control unit and a low gain storage control unit: The gain control unit receives a gain control signal to enable the pixel circuit to operate in different conversion gain modes, wherein the different conversion gain modes include a high conversion gain mode and a low conversion gain mode; The high-gain storage control unit and the low-gain storage control unit are arranged in parallel and are both connected to the floating diffusion point; wherein the high-gain storage control unit is used to store the high-gain reset voltage signal and the high-gain image voltage signal in the high conversion gain mode respectively, and the low-gain storage control unit is used to store the low-gain reset voltage signal and the low-gain image voltage signal in the low conversion gain mode respectively, and the high-gain storage control unit and the low-gain storage control unit correspond to the same or different column lines to respectively realize serial output or parallel output of signals; The control circuit is at least used to provide a pixel circuit control signal to the pixel circuit, and the pixel circuit control signal includes the gain control signal; Wherein, the high-gain storage control unit comprises a first high-gain control transistor, a second high-gain control transistor, a third high-gain control transistor, a first capacitor and a second capacitor, the first connection terminals of the first high-gain control transistor and the second high-gain control transistor are coupled to the floating diffusion point, the gate terminal of the first high-gain control transistor is connected to a first high-gain control signal, the second connection terminal is connected to a first connection terminal of the third high-gain control transistor and connected to a third reference potential through the first capacitor, the gate terminal of the second high-gain control transistor is connected to a second high-gain control signal, the second connection terminal is connected to a fourth reference potential through the second capacitor, the gate terminal of the third high-gain control transistor is connected to the third high-gain control signal, and the second connection terminal is connected to the fourth reference potential through the second capacitor; And / or, the low gain storage control unit includes a first low gain control transistor, a second low gain control transistor, a third low gain control transistor, a third capacitor and a fourth capacitor, the first connection ends of the first low gain control transistor and the second low gain control transistor are coupled to the floating diffusion point, the gate end of the first low gain control transistor is connected to the first low gain control signal, the second connection end is connected to the first connection end of the third low gain control transistor and is connected to the fifth reference potential through the third capacitor, the gate end of the second low gain control transistor is connected to the second low gain control signal, the second connection end is connected to the sixth reference potential through the fourth capacitor, the gate end of the third low gain control transistor is connected to the third low gain control signal, and the second connection end is connected to the sixth reference potential through the fourth capacitor.

2. The image sensor according to claim 1, It is characterized in that The first high-gain control transistor and the first capacitor constitute a high-gain reset voltage signal transmission branch, and the second high-gain control transistor and the second capacitor constitute a high-gain image voltage signal transmission branch, wherein the high-gain reset voltage signal transmission branch is used to transmit and store the high-gain reset voltage signal, and the high-gain image voltage signal transmission branch is used to transmit and store the high-gain image voltage signal; and / or, The first low gain control transistor and the third capacitor constitute a low gain reset voltage signal transmission branch, and the second low gain control transistor and the fourth capacitor constitute a low gain image voltage signal transmission branch, wherein the low gain reset voltage signal transmission branch is used to transmit and store the low gain reset voltage signal, and the low gain image voltage signal transmission branch is used to transmit and store the low gain image voltage signal.

3. The image sensor according to claim 1, It is characterized in that The high-gain storage control unit further includes a first high-gain source follower transistor, a second high-gain source follower transistor and a first row selection transistor; wherein: The gate terminal of the first high-gain source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to the first variable voltage, and the second connection terminal is connected to the first connection terminal of the first high-gain control transistor and the first connection terminal of the second high-gain control transistor; the gate terminal of the first high-gain control transistor is connected to the first high-gain control signal, the second connection terminal is connected to the first connection terminal of the third high-gain control transistor, and is connected to the third reference potential through the first capacitor; the gate terminal of the second high-gain control transistor is connected to the second high-gain control signal, and the second connection terminal is connected to the fourth reference potential through the second capacitor; the gate terminal of the third high-gain control transistor is connected to the third high-gain control signal, and the second connection terminal is connected to the fourth reference potential through the second capacitor; the gate terminal of the second high-gain source follower transistor is connected to the first connection terminal of the third high-gain control transistor, the first connection terminal is connected to the second power supply voltage, and the second connection terminal is connected to the first connection terminal of the first row selection transistor; the gate terminal of the first row selection transistor is connected to the high-gain row selection signal, and the second connection terminal serves as the output terminal of the high-gain storage control unit; The low-gain storage control unit further includes a first low-gain source follower transistor, a second low-gain source follower transistor and a second row selection transistor; wherein: The gate terminal of the first low-gain source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to the second variable voltage, and the second connection terminal is connected to the first connection terminal of the first low-gain control transistor and the first connection terminal of the second low-gain control transistor; the gate terminal of the first low-gain control transistor is connected to the first low-gain control signal, the second connection terminal is connected to the first connection terminal of the third low-gain control transistor, and is connected to the fifth reference potential through the third capacitor; the gate terminal of the second low-gain control transistor is connected to the second low-gain control signal, and the second connection terminal is connected to the sixth reference potential through the fourth capacitor; the gate terminal of the third low-gain control transistor is connected to the third low-gain control signal, and the second connection terminal is connected to the sixth reference potential through the fourth capacitor; the gate terminal of the second low-gain source follower transistor is connected to the first connection terminal of the third low-gain control transistor, the first connection terminal is connected to the third power supply voltage, and the second connection terminal is connected to the first connection terminal of the second row selection transistor; the gate terminal of the second row selection transistor is connected to the low-gain row selection signal, and the second connection terminal serves as the output terminal of the low-gain storage control unit.

4. The image sensor according to claim 3, It is characterized in that The first high-gain source follower transistor and the first low-gain source follower transistor are the same source follower transistor, the gate terminal of the shared source follower transistor is connected to the floating diffusion point, the first connection terminal is connected to a variable voltage, and the second connection terminal is respectively connected to the first connection terminal of the first high-gain control transistor, the first connection terminal of the second high-gain control transistor, the first connection terminal of the first low-gain control transistor, and the first connection terminal of the second low-gain control transistor.

5. The image sensor according to claim 1, It is characterized in that The pixel circuit further includes: a photosensitivity control unit and a reset unit; wherein, The photosensitive control unit is connected between the floating diffusion point and the first reference potential and is controlled by a transmission control signal, and is used to generate exposure charges according to a photoelectric effect and transfer and output the exposure charges according to the transmission control signal; The reset unit comprises a reset transistor, a gate terminal of the reset transistor is connected to a reset control signal, a first connection terminal is connected to a first power supply voltage, and a second connection terminal is connected to the floating diffusion point; The gain control unit is connected between the second connection terminal of the reset transistor and the floating diffusion point, and is used to adjust the equivalent charge storage capacity of the floating diffusion point according to the gain control signal so that the image sensor works in the different conversion gain modes.

6. The image sensor according to claim 5, It is characterized in that The photosensitivity control unit includes a photoelectric conversion element and a transfer transistor; the output end of the photoelectric conversion element is connected to the first connection end of the transfer transistor, and the other end is connected to the first reference potential; the gate end of the transfer transistor is connected to the transmission control signal, and the second connection end is connected to the floating diffusion point; and / or, the gain control unit includes a gain control transistor and a gain adjustment capacitor; the gate end of the gain control transistor is connected to the gain control signal, the first connection end is connected to the second connection end of the reset transistor, and is connected to the second reference potential through the gain adjustment capacitor, and the second connection end is connected to the floating diffusion point.

7. The image sensor according to claim 1, It is characterized in that The image sensor further comprises: a readout circuit, wherein the readout circuit comprises a high-gain readout unit and a low-gain readout unit, wherein: The high-gain readout unit is connected to the output end of the high-gain storage control unit, and is used to sequentially read out the high-gain reset voltage signal and the high-gain image voltage signal; the low-gain readout unit is connected to the output end of the low-gain storage control unit, and is used to sequentially read out the low-gain reset voltage signal and the low-gain image voltage signal; The control circuit is further configured to provide a readout circuit control signal to the readout circuit.

8. The image sensor according to claim 7, It is characterized in that The high-gain readout unit at least includes a high-gain comparator and a high-gain counter; the first input end of the high-gain comparator is connected to the high-gain preset ramp voltage, the second input end is connected to the output end of the high-gain storage control unit, the output end is connected to the input end of the high-gain counter, and the output end of the high-gain counter serves as the output end of the high-gain readout unit; and / or, the low-gain readout unit includes a low-gain comparator and a low-gain counter; the first input end of the low-gain comparator is connected to the low-gain preset ramp voltage, the second input end is connected to the output end of the low-gain storage control unit, the output end is connected to the input end of the low-gain counter, and the output end of the low-gain counter serves as the output end of the low-gain readout unit; and / or, the high-gain readout unit also includes a high-gain memory connected to the output end of the high-gain counter; and / or, the low-gain readout unit also includes a low-gain memory connected to the output end of the low-gain counter.

9. The image sensor according to claim 8, It is characterized in that The high-gain readout unit further includes a fifth capacitor connected to the first input terminal of the high-gain comparator, and a sixth capacitor connected to the second input terminal of the high-gain comparator; and / or, the low-gain readout unit further includes a seventh capacitor connected to the first input terminal of the low-gain comparator; and an eighth capacitor connected to the second input terminal of the low-gain comparator; and / or, the high-gain readout unit further includes a first clearing switch and a second clearing switch, the first clearing switch is connected between the first input terminal of the high-gain comparator and the first-stage output terminal thereof, and the second clearing switch is connected between the second input terminal of the high-gain comparator and the second-stage output terminal thereof; and / or, the low-gain readout unit further includes a third clearing switch and a fourth clearing switch, the third clearing switch is connected between the first input terminal of the low-gain comparator and the first-stage output terminal thereof, and the fourth clearing switch is connected between the second input terminal of the low-gain comparator and the second-stage output terminal thereof.

10. The image sensor according to any one of claims 1 to 9, It is characterized in that Global exposure is achieved based on the image sensor, storage of high conversion gain signals in the global exposure mode is achieved based on the high gain storage control unit, and storage of low conversion gain signals in the global exposure mode is achieved based on the low gain storage control unit.

11. A signal reading method of an image sensor according to any one of claims 1 to 10, It is characterized in that Includes steps: Based on the high gain storage control unit, the high gain reset voltage signal and the high gain image voltage signal in the high conversion gain mode are respectively stored; The low gain reset voltage signal and the low gain image voltage signal in the low conversion gain mode are stored respectively based on the low gain storage control unit.

12. The signal reading method of the image sensor according to claim 11, It is characterized in that When the high-gain reset voltage signal transmission branch, the high-gain image voltage signal transmission branch, the low-gain reset voltage signal transmission branch and the low-gain image voltage signal transmission branch exist, the following steps are performed in sequence: A low gain reset voltage signal is collected based on the low gain reset voltage signal transmission branch, a high gain reset voltage signal is collected based on the high gain reset voltage signal transmission branch, a high gain image voltage signal is collected based on the high gain image voltage signal transmission branch, and a low gain image voltage signal is collected based on the low gain image voltage signal transmission branch.

13. The signal reading method of the image sensor according to claim 11, It is characterized in that When there is a readout circuit and the readout circuit includes a high gain readout unit and a low gain readout unit, When the signal output mode of the high-gain storage control unit and the low-gain storage control unit is serial output, the high-gain readout unit and the low-gain readout unit perform readout operations successively; When the signal output modes of the high-gain storage control unit and the low-gain storage control unit are parallel output, the high-gain readout unit and the low-gain readout unit perform readout operations simultaneously.

14. The signal reading method of the image sensor according to claim 11, It is characterized in that When there is a readout circuit and the readout circuit includes a high-gain readout unit and a low-gain readout unit, the method includes the following steps: Implementing global exposure based on the image sensor; Simultaneously resetting the signals of the first capacitor and the second capacitor in the high-gain storage control unit and the third capacitor and the fourth capacitor in the low-gain storage control unit; The third capacitor, the first capacitor, the second capacitor and the fourth capacitor are used to sequentially sample a low-gain reset voltage signal, a high-gain reset voltage signal, a high-gain image voltage signal and a low-gain image voltage signal; The high-gain reset voltage signal and the high-gain image voltage signal are sequentially read out by the high-gain readout unit, and the low-gain reset voltage signal and the low-gain image voltage signal are sequentially read out by the low-gain readout unit.

15. The signal reading method of an image sensor according to any one of claims 11 to 14, It is characterized in that When there is a readout circuit and the readout circuit includes a high gain readout unit and a low gain readout unit, When the high-gain readout unit includes at least a high-gain comparator and a high-gain counter, the method for sequentially reading out the high-gain reset voltage signal and the high-gain image voltage signal includes: quantizing the high-gain reset voltage signal and outputting Vrst_hcg, and an average signal and outputting 1 / 2 (Vrst_hcg+Vsig_hcg) based on the high-gain readout unit, so that the high-gain readout unit quantizes and outputs 1 / 2 (Vrst_hcg-Vsig_hcg), wherein Vrst_hcg is the high-gain reset voltage signal, and Vsig_hcg is the high-gain image voltage signal; When the low gain readout unit includes at least a low gain comparator and a low gain counter, the method for sequentially reading out the low gain reset voltage signal and the low gain image voltage signal includes: based on the low gain readout unit, quantizing the high gain reset voltage signal and outputting Vrst_lcg, and the average signal and outputting 1 / 2 (Vrst_lcg+Vsig_lcg), so that the low gain readout unit quantizes and outputs 1 / 2 (Vrst_lcg-Vsig_lcg), wherein Vrst_lcg is the low gain reset voltage signal, and Vsig_lcg is the low gain image voltage signal.

16. The signal reading method of the image sensor according to claim 15, It is characterized in that The method further includes: a step of performing a clearing operation on the high-gain comparator and the low-gain comparator, and / or a step of performing a storage operation on the outputs of the high-gain readout unit and the low-gain readout unit.

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