A system for logical rule induction in knowledge graphs for engineering systems

Abstract

A system and method for logical rule formula induction of a knowledge graph for engineering system design includes receiving multiple knowledge graphs for engineering systems. For disconnected knowledge graphs, an aggregated beam search is limited to the edges connecting the focus nodes, and candidate formulas representing corresponding edges found by the beam search engine are generated, each formula being constrained by the requirement of at least two independent variables of the defined formula chain length. Formula evaluation determines whether each candidate formula is valid. The highest ranked formula is selected from the candidate formulas according to the defined criteria. For well-connected graphs, a graph neural network is trained to predict the first class of the query graph and the second class of the interference graph. The counterfactual solver engine solves the minimum number of edits to the query graph towards the interference graph to convert the predicted first class of the query graph into the predicted second class.

Description

Technical Field

[0001] The present application relates to machine learning applied to engineering systems. More specifically, the present application relates to logical rule induction for knowledge graph analysis in the field of engineering design. Background Art

[0002] The problem of learning first-order logic rules from data has been a long-standing challenge in machine learning and plays an important role in many applications. For example, for systems such as gas turbines, power grids, or smart buildings, large amounts of data are recorded by sensors. For such systems, a knowledge graph can be constructed to represent the domain knowledge of the system. In the engineering design process, machine learning can be applied to accelerate the search for the optimal design among multiple candidate designs. In the case where the design consists of many interconnected parts, each with several alternatives to choose from, the arrangements of the available configurations can be interleaved.

[0003] Logical rules are human-interpretable representations of knowledge-based reasoning that can provide better insights into understanding the properties of data than black-box supervised learning models. In many cases, this interpretability leads to robustness in transfer learning. Moreover, logical rules are very useful for many downstream tasks (target tasks), such as question answering, extracting knowledge from human experience, and extracting knowledge from open domain text. Extracting rules from knowledge graphs is challenging due to the combinatorial search space. Performing a brute force search of all possible rules is computationally intractable. For practical applications, the number of candidate logical rule formulas can easily reach billions or even trillions.

[0004] Existing methods use templates of first-order logic formulas with various constraints to reduce the search space. Traditional inductive logic programming methods are not only inefficient but also cannot handle the noise in real-world data. Recent methods using deep learning techniques (e.g., neural logic programming) can handle the noise in the data, but require that the logic variables in the formula are linked and each predicate must have exactly two independent variables. Even with these restrictions, existing methods can only extract logic formulas with up to two or three predicates, which is very insufficient for the modeling requirements of many industrial applications. Summary of the invention

[0005] The system provides logical rule induction of the knowledge graph of the engineering system through a first framework for searching disconnected knowledge graphs and a second framework for searching well-connected knowledge graphs. In the first framework, when the formula construction process searches for longer formulas, the top-ranked candidates of the first-order logic rule formulas are generated to reduce the search space of the knowledge graph. The second framework applies a graph neural network (GNN) with a counterfactual solver engine to capture the local topological patterns of the knowledge graph and abstract the first-order logic rule formulas based on the atomic actions of the graph. The inducing first-order logic rules explain the optimal design of the engineering system. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like elements throughout the various figures unless otherwise specified.

[0007] Figure 1 An example of a system for first-order logic formula induction of a knowledge graph according to an embodiment of the present invention is shown.

[0008] Figure 2 An example of skeleton first-order logic formula induction from a disconnected knowledge graph according to an embodiment of the present invention is shown.

[0009] Figure 3 An example of an aggregated beam search order according to an embodiment of the present invention is shown.

[0010] Figure 4 An example of formula expansion from a candidate formula according to an embodiment of the present invention is shown.

[0011] Figure 5 An example of a counterfactual formula for training a graph neural network according to an embodiment of the present invention is shown, where the graph neural network is used to extract logical rule formulas from a well-connected knowledge graph.

[0012] Figure 6 An example of using atomic actions on well-connected knowledge to generate counterfactuals for logic rule induction according to an embodiment of the present invention is shown.

[0013] Figure 7 An example of a computing environment is shown in which embodiments of the invention may be implemented. DETAILED DESCRIPTION

[0014] A method and system for significantly improving the efficiency of searching for first-order logic formulas of knowledge graphs are disclosed. For disconnected knowledge graphs, an aggregated beam search method with dynamic formula generation and inversion indexing technology is used. For large-scale well-connected knowledge graphs, graph neural networks are incorporated to avoid intractable combinatorial search spaces. The technical problems solved by embodiments of the present invention include the need to define first-order logic formulas for extracting the best target design from multiple candidate designs, where the search space can be managed to reduce processing time and work to improve efficiency. In one aspect, the derived logic formula can be configured as an explanation of the best design, where the successful design is judged by the performance of individual elements and the relationship of interconnected elements executed according to the best criteria. Unlike traditional methods that rely on formula templates to reduce the search space, the disclosed framework can learn formulas from zero (no templates) and still quickly derive logic formulas. Although conventional methods constrain formulas to two or three predicates or a chain length of two to three elements, the disclosed framework does not have such constraints.

[0015] Figure 1 An example of a system for first-order logic formula induction of a knowledge graph according to an embodiment of the present invention is shown. In an embodiment, a design engineering project is performed for an industrial system 170 (e.g., an automation system) having machines and sensors that can provide feedback. The computing device 110 includes a processor 115 and a memory 111 (e.g., a non-transitory computer-readable medium) on which various computer applications, modules, or executable programs are stored. The engineering application 112 may include software for one or more of a modeling tool, a simulation engine, a computer-aided design (CAD) tool, and other engineering tools, and a user may access these tools through a graphical user interface (GUI) 116 and a user interface module 114, which drives the display feed of the GUI 116 and processes the user input returned to the processor 115, all of which can be used to perform system design, for example in the form of a 2D or 3D perspective view. A network 130 such as a local area network (UAN), a wide area network (WAN), or an Internet-based network connects the computing device 110 to a repository of a knowledge graph 150.

[0016] In an embodiment, the engineering data generated by the engineering application 112 is monitored and organized into a knowledge graph 150 as semantic data. The knowledge graph 150 is an accumulation of design data derived from the engineering application 112 and is generated by a knowledge graph algorithm that processes the ontology of the derived data. In some embodiments, the knowledge graph is obtained from a supplier, such as a supplier or manufacturer of similar systems, subsystems, or components related to the system under design. The ontology governs the types of elements of the system and the relationships between elements (e.g., motor control, logical function blocks, associated sensor signals). The ontology also describes the attributes and element relationships of the elements, and the element types can be organized into hierarchical structures, such as supertypes and subtypes. The knowledge graph 150 represents the ontology as nodes and edges of a set of elements corresponding to the ontology and element relationships, respectively. For example, the engineering system information contained in the ontology can include design parameters, sensor signal information, operating range parameters (e.g., voltage, current, temperature, stress, etc.). When measurement data is obtained from sensors in the industrial system 170, it can be added to the various nodes and edges in the knowledge graph 150. Therefore, the knowledge graph structure can contain structured and static domain knowledge about the system. The measurement data will contain implicit and explicit knowledge about the system, which can be very valuable for improving the operational performance of the system or the future design of such a system. Explicit knowledge can include, for example, trends, correlation patterns, data values ​​outside of desired limits, etc. Implicit knowledge can include rules that drive the performance of the system in a certain way, constraints and dependencies between certain sets of variables, non-linear relationships between variables, etc.

[0017] The AI ​​module 125 is configured to perform first-order logic formula induction on the knowledge graph 150 using multiple modules including a filter 121, a beam search engine 122, a dynamic formula generator 123, a formula evaluation engine 124, a counterfactual solver engine 127, and a graph neural network module 128. The AI ​​module 125 analyzes one or more knowledge graphs to introduce first-order logic rules representing optimal designs. In an embodiment, the induction of first-order logic rule formulas involves deriving formulas, which are chains of items representing component relationships of system designs. Using automobile design as an example, various knowledge graphs can be used for analysis, each graph representing a different set of component selections and combinations associated with different designs of the car. For example, five known designs have five knowledge graphs for analysis, thereby forming a new sixth design. The first-order logic formula to be derived consists of a chain of terms that may involve engineering system components, such as engines, chassis, shafts, and wheels extracted from a knowledge graph in the field of mechanical interconnection. Another formula chain may represent an electrical field, such as elements of an interconnected computer network for various sensors associated with engines, chassis, shafts, and wheels. An example of a simplified formula chain is a chain of four items, where A [involves] B, B [involves] C and D, C [involves] B and D, where "involves" can take the form of any relational syntax depending on the specific relationship (e.g., connected to, is a component of, is a sensor of, etc.) According to an embodiment, the constraint on the chain length can be to fit the formula within the available memory of the computer without other constraints.

[0018] In short, the filter 121 is used to determine a knowledge graph that is disconnected to perform formula induction according to the first process of the present invention. For example, the filter 121 can detect different clusters in the knowledge graph and allow such a knowledge graph to pass as a disconnected knowledge graph. The disconnected knowledge graph is explored by a beam search engine 122, which performs a step-by-step exploration of the knowledge graph with an increment of a beam (i.e., a knowledge graph edge). Here, the terms "beam" and "edge" are used interchangeably. The beam search starts at the node with the highest ranked formula, and at each cycle of the iterative process, the search is extended to all connected nodes, so a single beam incremental search is performed. The dynamic formula generator 123 defines a first-order logic formula for each search beam, such as P (t1, ..., tn), where the n-ary predicate P has at least two independent variables (i.e., n ≥ 2), such as items t1 and t2. In order to search for the generated formula, the formula evaluation engine 124 maps the formula according to the edge type, forms a set of subgraphs, and finds the set intersection to determine which subgraphs satisfy the candidate formula being evaluated. This serves to significantly speed up formula evaluation, since it avoids having to base every candidate formula on it.

[0019] Disconnected Knowledge Graph Analysis

[0020] Figure 2An example of a framework for first-order logic formula induction from a disconnected knowledge graph according to an embodiment of the present invention is shown. For a knowledge graph determined to be taxonomically disconnected by a filter 121, a framework 200 constructs a set of first-order logic rule formulas through an iterative process of knowledge graph data extraction that produces a set of top-ranked candidate logic rule formulas. In one aspect, a single iteration of the framework 200 includes a beam search 202, logic rule formula generation 203, and logic rule formula evaluation 204. Starting from a set of knowledge graphs 210, the filter 201 detects the first disconnected knowledge graph, and for an initial cycle of the framework 200, the beam search engine 122 receives k known short-length logic rule formulas 211 as input. The beam search 202 process starts at a cluster in the disconnected knowledge graph corresponding to the k short-length logic rule formulas. The beam search 202 is described below with reference to Figure 3 Proceed as described.

[0021] Figure 3 An example of an aggregated beam search sequence according to an embodiment of the present invention is shown. In an embodiment, the beam search engine 122 performs an aggregated beam search 202 such that the search domain is expanded one hop at a time (i.e., one edge of the knowledge graph for a given iteration of the framework 200) to search for longer logic rule formulas. Figure 3 As shown, the beam search sequence starts at step 301, where the initial k logic rule formulas 211 correspond to the initial clusters 311, 313 in the knowledge graph. In subsequent cycles, the k highest ranked logic rule formulas 212 feed the beam search 202. Although embodiments of the present invention are capable of searching and evaluating k>>1000 candidate formulas, for this simplified example, k=2. In an embodiment, the beam search 202 is applied to identify a search domain that is one cluster hop away from the initial clusters 311, 313. Therefore, the search domain includes all clusters connected to the focus nodes 312, 314 that are internal nodes of the clusters 311, 313. The beam search 202 defines a subgraph for each path of the set of search beams that are tracked to expand. The graph of this tracking is represented in Figure 3302 in the sequence, where a subgraph is formed by expanding a cluster of focus nodes 312, 314. For this first beam search, clusters 322, 323, 324, 325, 326 are identified as candidates for expanding the logic rule formula associated with cluster 311 in the logic rule induction, while clusters 327, 328, 329 are identified as candidates for formula expansion of cluster 313. Formula generation 203 and evaluation 204 are performed for the current cycle of the framework 200 using the knowledge graph object of each subgraph defined in step 302, which will be described in more detail below. The output of the evaluation 204 of the current cycle is the top k logic rule formulas 212, which then trigger the next beam search 303. In this example, clusters 324 and 327 correspond to the k formulas above (for k=2), so the focus nodes in step 303 are nodes 334, 335. From all the candidate bundles in step 302, only bundles 324 and 327 remain for logic rule induction for the second cycle in step 303. In a manner similar to that described for step 302, the beam search domain is expanded from the subgraph shown in step 303 to a single beam hop from each of nodes 334 and 335. The beam search 202 is repeated in a similar manner for subsequent cycles until the expanded subgraph exhausts the k top-ranked formulas, or until the desired length of the logic rule formula is reached. Other restrictions or constraints may also limit the number of cycles. For example, Figure 3 As seen in Figure 2, by limiting the iterative beam search to the top k candidates as the source of formula expansion, the number of candidate formulas to be generated and evaluated is significantly reduced. At practical scale, even for k>>1000, when knowledge graphs can have up to billions or trillions of edges, the computational savings are significant.

[0022] Figure 4 An example of constrained formula expansion from candidate formulas according to an embodiment of the present invention is shown. In an embodiment, the beam search algorithm tracks the top k ranked formulas according to a specified evaluation metric, where k is a constant that specifies how many formulas are needed as targets. In practice, setting k on the scale of thousands can be easily handled by the beam search algorithm 202. As a result, an exponentially increasing search space for longer formula sizes is avoided. As a simplified example for illustration purposes, a search is performed for k=2. Figure 4 Starting from two formula trees 401, 402, the elements of which correspond to Figure 34 and 5. In the next cycle of the framework 200, the two top ranked formulas are determined from the connected bundles in the beam search, as shown by elements 421 and 422 at tree level 452. The next top ranked formula is represented by elements 431, 432 at tree level 453 determined in the third cycle. In this way, formula evaluation is prevented from exponentially expanding with each iteration of the framework 200.

[0023] Back to Figure 2 Next, the dynamic logic rule formula generation 203 performed for each subgraph defined by the beam search 202 will be described. Although the beam search 202 is configured to reduce computation, generating candidate formulas for all subgraphs 213 is computationally expensive because each candidate formula must be checked to see if it satisfies its conditions, even with shortcut breaks for any predicates that do not satisfy the subgraph structure. In an embodiment, further reductions in computations for logic rule formula generation and evaluation 204 are achieved by generating an inversion index map 214 and a set intersection 215 as part of the logic rule formula generation 203. The formula generator 123 generates an inversion index for mapping each type of edge (bundle) associated with the candidate formula to a set of subgraphs in which it appears. In the set intersection operation, a logical AND operator is applied to the subgraph set of the inversion index map 214 to find multiple subgraphs that satisfy the currently generated candidate formula. In this way, formula generation does not consider eliminating duplicate subgraphs, avoids taking each candidate formula as a basis, and the formula evaluation phase 204 is significantly accelerated by having fewer candidate formulas to evaluate.

[0024] The number of candidate logic rule formulas generated is significantly reduced compared to the baseline method without inverted indexes. As an example, for logic rule formulas of length 2, 3, and 4 with 2, 3, and 4 predicates, respectively, the number of candidate rules generated is reduced by 7x, 22x, and 48x, respectively. For longer formulas, the baseline method is computationally prohibitive to generate all candidate rules, while the improved formula generation process 203 can easily generate candidate rules from a subset of the subgraph derived by the aggregated beam search 202.

[0025] Logical rule formula generation 203 generates a first-order logic rule formula formulated according to a logical rule grammar associated with subgraph connections. Because the framework 200 enables formulas to connect bundles based on beam search, each subgraph is inherently connected. This constraint corresponds to the focus of the framework 200 on entity groups rather than disconnected subgraphs in practical applications.

[0026] The base formula 216 is derived based on the constants that replace the variables of the logic rule formula. The formula used as the basis is dynamic because not all candidate formulas are used as the basis, but a subset is used as the basis as a result of the invert index and set intersection operation. As an example of deriving a base formula, consider the knowledge graph 210 related to the engineering system design of a vehicle with 15 available engine types, 11 chassis types, and 25 transaxle types. The subgraph of a particular knowledge graph is based by the following example: the engine 12 of 15 is connected to the chassis 5 of 11, which is connected to the transaxle 23 of 25. For a practical example, the dynamic basis of many (~100) subgraphs of multiple knowledge graphs can be a certainty of the specific probability of the formula. For example, if the engine 12 is rarely connected to the chassis 2, there is a strong certainty that the probability of such a connection is low.

[0027] The logic rule formula evaluation 204 ranks the base formulas 216. To rank the candidate formulas, a criterion is selected, such as coverage, accuracy, confidence score, or a combination thereof. A certain number k of the highest ranked formulas are retained for future searches for longer formulas.

[0028] As another advantage of the inverted index mapping 214 and the set intersection 215, the formula evaluation 204 is significantly more efficient than the baseline method. The test results of the framework 200 relative to the baseline method produce significant time savings. For candidate formulas with 2, 3, and 4 predicates, the framework 200 method can achieve faster formula evaluation processing times of factors of 22x, 660x, and 851x compared to the baseline method. For longer formulas, the baseline method is too slow to evaluate, while the framework 100 method can complete candidate formula generation very efficiently. For example, a formula with 12 predicates can be evaluated in about 30 minutes.

[0029] Once the top k ranked formulas are derived by formula evaluation 204, the process is repeated, starting with another beam search 202, searching for a subgraph with a chain length of x+1. The framework 200 performs an iterative process until the subgraph length reaches a predetermined maximum limit or a limit of the knowledge graph, or until a new candidate formula of length x+1 searched in the knowledge graph does not meet the formula criteria. The limit of the top k formulas can be predetermined as a constraint based on a trade-off between robustness and computation time and memory.

[0030] Well-connected knowledge graph analytics

[0031] Having covered the framework for inducing logical rule formulas from disconnected knowledge graphs as described above, the method for inducing logical rule formulas for large-scale well-connected knowledge graphs is described next. In an embodiment, according to the following description, the filter 121 determines that the received knowledge graph 150 meets the connectivity criteria and triggers the induction of logical rules on the knowledge graph to be a well-connected knowledge graph. The counterfactual solver 127 works with the GNN 128 to overcome the problem of rapid expansion when the logic formula is basicized. Counterfactuals are a method at the intersection of computational cognitive science and statistics that attempts to predict the outcome of an event, assuming that the event has not been observed by the model. To illustrate how counterfactuals are applied to well-connected knowledge graphs, recall the AI ​​concept of explanation of logical rules, which explains why the classification is as described. As an alternative, the counterfactual solver engine 127 finds one or more elements common to both the query knowledge graph and the interference knowledge graph, so that if the element is changed, the query knowledge graph will be classified as more likely to be an interference knowledge graph (or a "corresponding" version or replacement version of the query graph). The benefit of applying counterfactual analysis is that it can provide an understanding of which elements of the knowledge graph are necessary or critical to keep its classification intact. That is, by identifying the smallest atomic changes in the knowledge graph that trigger a different classification, a discriminative validation of the logic rules is established. In short, what situations produce knowledge graph classification X instead of Y.

[0032] More formally, given a certain classification of a subgraph or node of a knowledge graph, the explanation problem is formulated as the minimum amount of changes that need to be created to the knowledge graph that causes the misclassification of the subgraph or node using the combined operation of the GNN 128 and the counterfactual solver engine 127. An optimization problem can be formulated to attempt to identify the minimum number of edits to the knowledge graph that lead to the misclassification of a node. This translates directly into the formulation of counterfactuals, as the identification of graph structures is similar to the graph structure being classified, but different enough to cause the misclassification. The resulting graph structure is the resulting counterfactual.

[0033] Given a query knowledge graph G for which GNN 128 predicts class c, the goal is to generate counterfactual explanations that make minimal changes to graph G, looking for changes towards the perturbation graph G that GNN previously predicted as class c'. The solution is to perform a transformation from G to a counterfactual G*, such that G* appears to be an instance of class c' to the trained GNN model g. Here, the GNN can be represented as g c (f(G)) represents the log-probability of class c of graph G. Mathematically, the transformation from G to G* can be expressed as follows:

[0034]

[0035] Among them: 1 is a vector with all values ​​1;

[0036] a is a binary gating vector; and

[0037] ° is the Hadamard product between a vector and a matrix.

[0038] Figure 5 An example of applying counterfactuals to GNNs to derive logic rule formulas from large-scale well-connected knowledge graphs according to an embodiment of the present invention is shown. In an embodiment, the counterfactual solver 127 solves the optimization by minimizing the norm of the binary gating vector a, which represents the minimum number of edits from the graph G' to the query graph G to generate the counterfactual graph G*. This can be expressed as follows:

[0039]

[0040]

[0041]

[0042] in:

[0043] f(G) is the query graph feature vector

[0044] f(G*) is the counterfactual graph feature vector

[0045] f(G') is the interference graph feature vector

[0046] P is a permutation matrix that rearranges the elements of f(G') to be consistent with the elements of f(G),

[0047] Pf(G') is the rearranged interference eigenvector

[0048] P is the set of all permutation matrices

[0049] In an embodiment, a GNN is trained to learn a permutation matrix P, which enables the determination of the minimum number of edits directly from the knowledge graph. The method makes the processing algorithm faster, which enables the system to be trained in an end-to-end manner. The result of the method is a generated GNN that can interpret the learned parameters to discover human-readable logical formulas on large-scale knowledge graphs. Since GNNs can capture local topological patterns in the graph, the knowledge embedded in the learning model can be abstracted and generalized to logical formulas.

[0050] Figure 6 An example of generating counterfactuals for reducing search space logic rule induction on a well-connected knowledge graph according to an embodiment of the present invention is shown. In this example, a very simple graph is shown for illustrative purposes, as actual knowledge graphs may include millions or billions of nodes. As shown in the figure, starting from a query graph 601, various atomic edits include formula addition edit 602, formula subtraction edit 603, and term edit 604, such as Figure 6In each case, a single “atomic” edit is made to the graph 601 to analyze whether the graph class has changed when analyzed by the counterfactual solver engine 127 .

[0051] Figure 7 An example of a computing environment in which embodiments of the present invention may be implemented is shown. Computing environment 700 includes a computer system 710, which may include a communication mechanism such as a system bus 721 or other communication mechanism for transmitting information within the computer system 710. The computer system 710 also includes one or more processors 720 coupled to the system bus 721 for processing information. In an embodiment, the computing environment 700 corresponds to a system for logical rule induction of a knowledge graph, wherein the computer system 710 relates to a computer described in more detail below.

[0052] The processor 720 may include one or more central processing units (CPUs), graphics processing units (GPUs), or any other processors known in the art. More generally, the processor described herein is a device for executing machine-readable instructions stored on a computer-readable medium for performing tasks, and may include any one or a combination of hardware and firmware. The processor may also include a memory storing machine-readable instructions executable for performing tasks. The processor acts on information by manipulating, analyzing, modifying, converting, or transmitting information used by an executable program or information device and / or by routing the information to an output device. The processor may use or include the capabilities of, for example, a computer, a controller, or a microprocessor, and may be adjusted using executable instructions to perform special functions not performed by a general-purpose computer. The processor may include any type of appropriate processing unit, including but not limited to a central processing unit, a microprocessor, a reduced instruction set computer (RISC) microprocessor, a complex instruction set computer (CISC) microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a system on a chip (SoC), a digital signal processor (DSP), etc. In addition, the processor 720 may have any suitable micro-architecture design, which includes any number of components, such as registers, multiplexers, arithmetic logic units, a cache controller for controlling read / write operations to the cache memory, a branch predictor, etc. The micro-architecture design of the processor can support any of a variety of instruction sets. The processor can be connected (electrically connected and / or include executable components) to any other processor that can interact and / or communicate therebetween. The user interface processor or generator is a known element that includes electronic circuits or software or a combination of both for generating a display image or part thereof. The user interface includes one or more display images that enable a user to interact with the processor or other device.

[0053] The system bus 721 may include at least one of a system bus, a memory bus, an address bus, or a message bus, and may allow information (e.g., data (including computer executable code), signaling, etc.) to be exchanged between the various components of the computer system 710. The system bus 721 may include, but is not limited to, a memory bus or a memory controller, a peripheral bus, an accelerated graphics port, etc. The system bus 721 may be associated with any suitable bus architecture, including, but not limited to, an Industry Standard Architecture (ISA), a Micro Channel Architecture (MCA), an Enhanced ISA (EISA), a Video Electronics Standards Association (VESA) architecture, an Accelerated Graphics Port (AGP) architecture, a Peripheral Component Interconnect (PCI) architecture, a PCI-Express architecture, a Personal Computer Memory Card International Association (PCMCIA) architecture, a Universal Serial Bus (USB) architecture, etc.

[0054] Continue to refer Figure 7 , the computer system 710 may also include a system memory 730 coupled to the system bus 721 for storing information and instructions to be executed by the processor 720. The system memory 730 may include computer-readable storage media in the form of volatile and / or non-volatile memory, such as a read-only memory (ROM) 731 and / or a random access memory (RAM) 732. The RAM 732 may include other dynamic storage devices (e.g., dynamic RAM, static RAM, and synchronous DRAM). The ROM 731 may include other static storage devices (e.g., programmable ROM, erasable PROM, and electrically erasable PROM). In addition, the system memory 730 may be used to store temporary variables or other intermediate information during the execution of instructions by the processor 720. The basic input / output system 733 (BIOS) contains basic routines that help to transfer information between elements within the computer system 710, such as during startup, and may be stored in the ROM 731. The RAM 732 may contain data and / or program modules that are immediately accessible to and / or currently being operated by the processor 720. The system memory 730 may also include, for example, an operating system 734, an application module 735, and other program modules 736. The application module 735 may include the above-mentioned Figure 1 The modules described herein may also include a user portal for developing applications, allowing parameters to be entered and modified as needed.

[0055] An operating system 734 may be loaded into memory 730 and may provide an interface between other application software executing on computer system 710 and the hardware resources of computer system 710. More specifically, operating system 734 may include a set of computer executable instructions for managing the hardware resources of computer system 710 and providing common services to other applications (e.g., managing memory allocations between various applications). In certain example embodiments, operating system 734 may control the execution of one or more program modules depicted as being stored in data storage 740. Operating system 734 may include any operating system now known or that may be developed in the future, including but not limited to any server operating system, any host operating system, or any other proprietary or non-proprietary operating system.

[0056] The computer system 710 may also include a disk / media controller 743 coupled to the system bus 721 to control one or more storage devices for storing information and instructions, such as a magnetic hard disk 741 and / or a removable media drive 742 (e.g., a floppy disk drive, an optical drive, a tape drive, a flash drive, and / or a solid-state drive). The storage device 740 may be added to the computer system 710 using an appropriate device interface (e.g., a small computer system interface (SCSI), an integrated device electronics (IDE), a universal serial bus (USB), or FireWire). The storage devices 741, 742 may be external to the computer system 710.

[0057] The computer system 710 may include a user input / output interface 760 for communicating with one or more input devices 761, such as a keyboard, touch screen, input pad, and / or pointing device, and output devices 762, such as a display device, to enable interaction with a computer user and to provide information to the processor 720.

[0058] The computer system 710 may perform some or all of the processing steps of an embodiment of the present invention in response to the processor 720 executing one or more sequences of one or more instructions contained in a memory such as the system memory 730. Such instructions may be read into the system memory 730 from another computer-readable medium (such as a magnetic hard disk 741 or a removable media drive 742) storing 740. The hard disk 741 and / or the removable media drive 742 may contain one or more data stores and data files used by embodiments of the present invention. The data store 740 may include, but is not limited to, a database (e.g., relational, object-oriented, etc.), a file system, a flat file, a distributed data store in which data is stored on more than one node of a computer network, a peer-to-peer network data store, etc. The data store contents and data files may be encrypted to increase security. The processor 720 may also be used in a multi-processing configuration to execute one or more sequences of instructions contained in the system memory 730. In alternative embodiments, hard-wired circuits may be used in place of or in conjunction with software instructions. Therefore, the embodiments are not limited to any particular combination of hardware circuits and software.

[0059] As described above, the computer system 710 may include at least one computer-readable medium or memory for storing instructions programmed according to embodiments of the present invention and for containing data structures, tables, records, or other data described herein. The term "computer-readable medium" used herein refers to any medium that participates in providing instructions to the processor 720 for execution. Computer-readable media can take many forms, including but not limited to non-transient, non-volatile media, volatile media, and transmission media. Non-limiting examples of non-volatile media include optical disks, solid-state drives, magnetic disks, and magneto-optical disks, such as magnetic hard disks 741 or removable media drives 742. Non-limiting examples of volatile media include dynamic memory, such as system memory 730. Non-limiting examples of transmission media include coaxial cables, copper wires, and optical fibers, including wires that constitute the system bus 721. Transmission media can also take the form of sound waves or light waves, such as those generated during radio wave and infrared data communications.

[0060] The computer-readable medium instructions for performing the operation of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" programming language or similar programming languages. Computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits including, for example, programmable logic circuits, field programmable gate arrays (FPGAs) or programmable logic arrays (PLAs) may be executed by using the state information of computer-readable program instructions to personalize the electronic circuit to perform computer-readable program instructions so as to perform various aspects of the present invention.

[0061] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each block of the flowchart illustration and / or block diagram and the combination of blocks in the flowchart illustration and / or block diagram can be implemented by computer-readable medium instructions.

[0062] The computing environment 700 may also include a computer system 710 operating in a networked environment using logical connections to one or more remote computers, such as a remote computing device 773. The network interface 770 may enable communication with other remote devices 773 or systems and / or storage devices 741, 742, for example, via a network 771. The remote computing device 773 may be a personal computer (laptop or desktop), a mobile device, a server, a router, a network PC, a peer device, or a public network node, and typically includes many or all of the elements described above with respect to the computer system 710. When used in a networked environment, the computer system 710 may include a modem 772 for establishing communications over a network 771, such as the Internet. The modem 772 may be connected to the system bus 721 via the user network interface 770 or via another appropriate mechanism.

[0063] The network 771 can be any network or system generally known in the art, including the Internet, an intranet, a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), a direct connection or a series of connections, a cellular telephone network, or any other network or medium that can facilitate the communication between the computer system 710 and other computers (e.g., a remote computing device 773). The network 771 can be wired, wireless, or a combination thereof. The wired connection can be implemented using Ethernet, a universal serial bus (USB), RJ-6, or any other wired connection known in the art. The wireless connection can be implemented using Wi-Fi, WiMAX, and Bluetooth, infrared, a cellular network, a satellite, or any other wireless connection method known in the art. In addition, several networks can work alone or communicate with each other to facilitate the communication in the network 771.

[0064] It should be understood that Figure 7 The program modules, applications, computer executable instructions, codes, etc. stored in the system memory 730 described in the description are merely illustrative and not exhaustive, and the processing described as being supported by any particular module may be alternatively distributed across multiple modules or performed by different modules. In addition, various program modules, scripts, plug-ins, application programming interfaces (APIs), or any other suitable computer executable code hosted locally on the computer system 710, remote devices 773, and / or hosted on other computing devices accessible via one or more networks 771 may be provided to support the processing by Figure 7 The functions and / or additional or alternative functions provided by the program modules, applications or computer executable codes depicted in the embodiment of the present invention may be different modular functions such that the functions described as being provided by Figure 7 The processing collectively supported by the illustrated set of program modules may be performed by a fewer or greater number of modules, or the functionality described as supported by any particular module may be supported at least in part by another module. Furthermore, the program modules supporting the functionality described herein may form part of one or more applications that may be executed on any number of systems or devices according to any suitable computing model, such as a client-server model, a peer-to-peer model, or the like. In addition, the processing collectively supported by the illustrated set of program modules may be performed by a fewer or greater number of modules, or the functionality described as supported by any particular module may be supported at least in part by another module. Furthermore, the program modules supporting the functionality described herein may form part of one or more applications that may be executed on any number of systems or devices according to any suitable computing model, such as a client-server model, a peer-to-peer model, or the like. Figure 7 Any functionality supported by any program module depicted in the description may be implemented, at least in part, in hardware and / or firmware on any number of devices.

[0065] It should also be understood that the computer system 710 may include alternative and / or additional hardware, software or firmware components other than those described or depicted without departing from the scope of the present invention. More specifically, it should be understood that the software, firmware or hardware components depicted as forming part of the computer system 710 are merely illustrative, and in various embodiments, certain components may not be present or additional components may be provided. Although various illustrative program modules have been depicted and described as software modules stored in the system memory 730, it should be understood that the functionality described as supported by the program modules may be enabled by any combination of hardware, software and / or firmware. It should be further understood that in various embodiments, each of the above modules may represent a logical partition of the supported functions. The logical partition is depicted for ease of explanation of the functions and may not represent the structure of the software, hardware and / or firmware used to implement the functions. Therefore, it should be understood that in various embodiments, the functionality described as provided by a particular module may be provided at least in part by one or more other modules. In addition, in some embodiments, one or more of the depicted modules may not be present, while in other embodiments, additional modules that are not depicted may exist and may support at least a portion of the described functionality and / or additional functionality. Furthermore, while certain modules may be depicted and described as sub-modules of another module, in certain embodiments such modules may be provided as stand-alone modules or sub-modules of other modules.

[0066] Although specific embodiments of the present invention have been described, those of ordinary skill in the art will recognize that there are many other modifications and alternative embodiments within the scope of the present invention. For example, any function and / or processing capability described about a particular device or component can be performed by any other device or component. In addition, although various illustrative implementations and architectures have been described according to embodiments of the present invention, those of ordinary skill in the art will appreciate that many other modifications to the illustrative implementations and architectures described herein are also within the scope of the present invention. In addition, it should be understood that any operation, element, component, data, etc. described herein as being based on another operation, element, component, data, etc., can be based on one or more other operations, elements, components, data, etc. in addition. Therefore, the phrase "based on" or its variants should be interpreted as "based at least in part on".

[0067] The flow chart and block diagram in the figure show the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention.In this regard, each frame in the flow chart or block diagram can represent a module, segment or part of an instruction, which includes one or more executable instructions for realizing a specified logical function.In some replaceable embodiments, the function indicated in the square frame may not occur in the order indicated in the accompanying drawings.For example, according to the function involved, the two frames shown in succession can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order.It will also be noted that each frame in the block diagram and / or the flow chart illustration and the combination of the frames in the block diagram and / or the flow chart illustration can be realized by a system based on special hardware that performs a specified function or action or performs a combination of special hardware and computer instructions.

Claims

1. A system for summarizing first-order logic rule formulas of knowledge graphs for engineering system design, comprising: processor; as well as A memory storing a module executed by the processor, the module comprising: An artificial intelligence (AI) module is configured to receive a plurality of knowledge graphs for an engineering system, each knowledge graph representing a unique engineering system design used as a candidate, the AI ​​module comprising: a filtering module for determining whether each of the plurality of knowledge graphs is disconnected based on identifying a significant portion of disconnected nodes contributed by different node clusters, and in response to determining that the knowledge graph is disconnected, triggering first-order logic rule induction on the disconnected knowledge graph; A beam search engine configured to perform, for each disconnected knowledge graph, an aggregate search limited to edges connecting the focus nodes, and to define a subgraph for each path of the search; A formula generator configured to generate a plurality of candidate logic rule formulas, wherein for each candidate logic rule formula: (i) duplicate subgraphs are eliminated by mapping edge types to a set of subgraphs using a reverse index and finding intersections of the subgraphs that satisfy the candidate formula, and (ii) the formula is constrained by a requirement of at least two independent variables of a formula chain length L; A formula evaluator configured to perform formula evaluation on the basic candidate formulas and select top k ranked formulas from the candidate formulas according to the evaluation criteria; Therein, logical formula induction repeats the iterations of aggregate search, candidate formula generation, and formula evaluation by extending the candidate formula to a chain length of L+1 for each iteration, and repeats until a defined limit on the chain length is reached.

2. The system according to claim 1, wherein: The evaluation criteria include coverage, accuracy, confidence score, or a combination thereof.

3. The system according to claim 1, wherein: Aggregate beam search expands the search domain by one hop at each iteration.

4. The system according to claim 1, wherein: The formula has a dynamic basis by labeling or enumerating each node as a specific instance among all the different connection possibilities.

5. The system according to claim 1, wherein: The filtering module determines that the knowledge graph meets the connectivity criteria and triggers the logic rule formula induction as a connected knowledge graph. The system also includes: A graph neural network trained to predict the first class of a query graph and predict the second class of an interference graph; and A counterfactual solver engine is configured to solve a minimum number of edits to the query graph towards the interference graph to transform a predicted first class of the query graph into a predicted second class.

6. The system according to claim 5, wherein: The counterfactual solver engine is further configured to: rearrange features of the interference graph according to a permutation matrix; Applying the first Hadamard product of the gating vector and the matrix of rearranged features; and applying a second Hadamard product of the inverse of the gating vector and the matrix of query graph features; Wherein, a counterfactual matrix is ​​formed by the sum of the first Hadamard product and the second Hadamard product, and the minimum number of edits is represented by the gating vector.

7. The system according to claim 6, wherein: The graph neural network is trained to learn the permutation matrix.

8. A method for summarizing first-order logic rule formulas of a knowledge graph for engineering system design, comprising: Receiving, by an artificial intelligence (AI) module, a plurality of knowledge graphs for engineering systems, wherein each knowledge graph has a significant portion of disconnected nodes resulting from different node clusters, each knowledge graph representing a unique engineering system design used as a candidate; Determining whether each of the plurality of knowledge graphs is disconnected, and in response to determining that the knowledge graph is disconnected, triggering first-order logic rule induction of the disconnected knowledge graph, comprising: For each disconnected knowledge graph, perform an aggregate search limited to the edges connected by the focus nodes; Perform candidate formula generation, each candidate formula represents a corresponding edge found by the beam search engine, and each formula is constrained by the requirement of at least two independent variables of formula chain length L; Formula evaluation is performed to determine whether each candidate formula is valid, and the top k ranked formulas are selected from the candidate formulas according to defined criteria; wherein logical formula induction repeats the iterations of aggregate search, candidate formula generation, and formula evaluation by extending the candidate formulas to a chain length of L+1 for each iteration, and repeats until a defined limit on the chain length is reached.

9. The method according to claim 8, wherein: The defined criteria include coverage, accuracy, confidence score, or a combination thereof.

10. The method according to claim 8, wherein: Aggregate beam search expands the search domain by one hop at each iteration.

11. The method according to claim 8, wherein: The formula has a dynamic basis by labeling or enumerating each node as a specific instance among all the different connection possibilities.

12. The method according to claim 8, wherein: The filtering module determines that the knowledge graph meets the connectivity criteria and triggers the logic rule formula induction as a connected knowledge graph. The system also includes: A graph neural network, trained to predict the first class of the query graph and predict the second class of the interference graph; A counterfactual solver engine is configured to solve a minimum number of edits to the query graph towards the interference graph to transform a predicted first class of the query graph into a predicted second class.

13. The method according to claim 12, wherein: The counterfactual solver engine is further configured to: rearrange features of the interference graph according to a permutation matrix; Applying the first Hadamard product of the gating vector and the matrix of rearranged features; and applying a second Hadamard product of the inverse of the gating vector and the matrix of query graph features; Therein, a counterfactual matrix is ​​formed by the sum of the first Hadamard product and the second Hadamard product, and the minimum number of edits is represented by the gating vector.

14. The method according to claim 13, wherein: The graph neural network is trained to learn the permutation matrix.

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