Zero-delay prediction circuit for voltage sag monitoring

Abstract

This invention discloses a zero-delay prediction circuit for voltage sag monitoring, specifically addressing the problem of delayed output results caused by several cycles of response time in on-chip high-speed, high-precision voltage sag monitoring circuits. It belongs to the field of electronic circuit technology. This invention combines a short-cycle response voltage monitoring unit and a long-cycle response voltage monitoring unit, using a prediction factor calculation unit to obtain the slope information of the voltage sag. From the slope information, the voltage value several cycles later can be deduced, thus enabling the voltage monitoring unit's predicted output value to follow the actual on-chip voltage without delay. The voltage value at the moment of code value transition in the short-cycle response voltage monitoring unit is used as an anchor value, thereby improving monitoring accuracy. The adaptive prediction adjustment unit calculates the attenuation amplitude by recording the output code values ​​at two adjacent refresh times, thus adapting to slope changes during the voltage drop process.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and in particular relates to a zero-delay prediction circuit for voltage descent monitoring circuits. Background Technology

[0002] The rapid development of integrated circuits has required processors to handle more complex and variable tasks, and drastic load changes pose challenges to the stability of power supply networks. Load changes directly lead to changes in supply current, resulting in voltage sags. This means insufficient timing margin or even failure to meet minimum requirements, leading to calculation errors. Voltage sags can generally be divided into three stages, with the first-order voltage sag being the most difficult to monitor. Its frequency and amplitude depend on the package inductor and on-chip capacitor, ranging from tens to hundreds of megahertz in frequency and tens to hundreds of millivolts in amplitude. When a voltage sag occurs, various methods such as LDOs and DC-DC converters are needed to restore the voltage and prevent system errors.

[0003] To quickly and accurately monitor on-chip power supply voltage drops, monitoring circuits based on digital ring oscillators or inverter chains are typically used. These circuits often require multiple cycles for sampling, quantization, and calibration, leading to a mismatch between the current output code value and the actual voltage, and the output code value always lags behind the actual voltage. Directly using the current output code value to adjust the voltage can easily result in misjudgments and incorrect power management control. Therefore, a zero-delay predictive circuit for voltage drop monitoring is needed to quickly and accurately monitor voltage drop output values. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings and major design challenges of the aforementioned background technology by providing a zero-delay prediction circuit for voltage descent monitoring, thus solving the problem of delayed output results caused by several cycles of response time in on-chip high-speed, high-precision voltage descent monitoring circuits. This circuit primarily uses a high-speed, high-precision, long-cycle response voltage monitoring unit, supplemented by a short-cycle response voltage monitoring unit with a shorter response time to assist in the prediction function. A prediction factor calculation unit obtains the slope information of the voltage descent, from which the voltage value several cycles later can be deduced, thereby achieving zero-delay voltage detection. The voltage value at the moment of code value transition in the short-cycle response voltage monitoring unit is used as an anchor value to improve monitoring accuracy. An adaptive prediction adjustment unit calculates the attenuation amplitude by recording the output code values ​​at two adjacent refresh times, thus adapting to the slope changes during the voltage drop process.

[0005] The specific technical solution of the present invention is as follows:

[0006] The zero-delay prediction circuit for voltage sag monitoring includes a short-cycle response voltage monitoring unit, a long-cycle response voltage monitoring unit, a prediction factor calculation unit, an adaptive prediction adjustment unit, and a voltage prediction output unit. The short-cycle response voltage monitoring unit generates voltage code values ​​with fast response speeds, while the long-cycle response voltage monitoring unit generates voltage code values ​​with slow response speeds. The prediction factor calculation unit receives the outputs from the short-cycle and long-cycle response voltage monitoring units, calculates the slope of the voltage sag, and generates a prediction factor. The adaptive prediction adjustment unit receives the output from the prediction factor calculation unit and adaptively adjusts the prediction factor to adapt to the slope changes during the voltage sag process. The voltage prediction output unit receives the output from the adaptive prediction adjustment unit, uses the prediction factor calculation unit to obtain the slope information of the voltage sag, and can deduce the voltage value several cycles later from the slope information.

[0007] Preferably, the short-cycle response voltage monitoring unit consists of an inverter chain and is sampled using a flip-flop. The response time for voltage monitoring is a clock cycles, where a is a positive integer greater than or equal to 1. When the output code value changes, it is recorded as the anchor voltage.

[0008] Preferably, the long-cycle response voltage monitoring unit uses a ring oscillator to map voltage changes to device delay changes. The register samples the toggling position of the ring oscillator. Within one sampling period, the quantization logic combines the results of coarse and fine quantization to calculate the final voltage quantization result, and obtains the final voltage output code value through voltage calibration. The response time of the long-cycle response voltage monitoring unit for voltage monitoring is b clock cycles, where b is a positive integer greater than or equal to 2 and b is greater than a.

[0009] Preferably, the generation of predictor factors includes the following steps:

[0010] Step 101: Read the output code value of the short-cycle response voltage monitoring unit and record it as FF; if FF changes, proceed to step 102, otherwise proceed to step 101;

[0011] Step 102: Record FF as the anchor value FH, read the output code value of the long-cycle response voltage monitoring unit, record it as S, and proceed to step 103;

[0012] Step 103: Calculate the predictor PF = [(a + b) / b] × (S - FH).

[0013] The adaptive predictive adjustment unit records the output code values ​​of the long-cycle response voltage monitoring unit at adjacent refresh times to calculate the difference, which is recorded as the attenuation amplitude. Based on the proportion of the attenuation amplitude decrease, the prediction factor is adjusted proportionally to adapt to the slope change during the voltage drop process. If the prediction factor is not refreshed for a long time, its value will decay to 0 cycle by cycle. This situation only occurs when the system is already operating in normal voltage or low-power mode, and not during buck or voltage regulation.

[0014] The voltage prediction output unit outputs the final voltage code value V = S - PF.

[0015] The zero-delay prediction circuit for voltage descent monitoring proposed in this invention has the following advantages:

[0016] (1) The present invention combines a short-cycle response voltage monitoring unit and a long-cycle response voltage monitoring unit, and uses a prediction factor calculation unit to obtain the slope information of the voltage drop. The voltage value after several cycles can be deduced from the slope information, thereby realizing zero-delay voltage detection.

[0017] (2) The present invention uses the voltage value at the instant of the short-cycle response voltage monitoring unit code value jump as the anchor value, thereby improving the monitoring accuracy;

[0018] (3) The adaptive prediction adjustment unit of the present invention calculates the attenuation amplitude by recording the output code value at two adjacent refresh times, thereby adapting to the slope change during the voltage drop process and avoiding the over-prediction phenomenon of code value. Attached Figure Description

[0019] Figure 1 This is a flowchart of the zero-delay prediction circuit of the voltage descent monitoring circuit of the present invention;

[0020] Figure 2 This is a schematic diagram of the short-cycle response voltage monitoring unit of the present invention;

[0021] Figure 3 This is a schematic diagram of the long-period response voltage monitoring unit of the present invention;

[0022] Figure 4 This is a schematic diagram of the output of the short-cycle response voltage monitoring unit, the output of the long-cycle response voltage monitoring unit, and the current actual voltage of the present invention;

[0023] Figure 5 This is a schematic diagram of the predictor calculation unit of the present invention obtaining predictor factors;

[0024] Figure 6 This is a schematic diagram illustrating the calculation of attenuation amplitude by the adaptive predictive adjustment unit of the present invention;

[0025] Figure 7This is a schematic diagram illustrating the prediction effect of the zero-delay prediction circuit of the voltage descent monitoring circuit of the present invention. Detailed Implementation

[0026] To better understand the purpose, structure, and function of this invention, the zero-delay prediction circuit of the voltage descent monitoring circuit of this invention will be described in further detail below with reference to the accompanying drawings.

[0027] like Figure 1 As shown, the zero-delay prediction circuit of the voltage descent monitoring circuit includes a short-cycle response voltage monitoring unit, a long-cycle response voltage monitoring unit, a prediction factor calculation unit, an adaptive prediction adjustment unit, and a voltage prediction output unit. The short-cycle response voltage monitoring unit generates voltage code values ​​with fast response speed, and the long-cycle response voltage monitoring unit generates voltage code values ​​with slow response speed. The prediction factor calculation unit receives the outputs of the short-cycle response voltage monitoring unit and the long-cycle response voltage monitoring unit, calculates the slope of the voltage drop, and generates a prediction factor. The adaptive prediction adjustment unit receives the output of the prediction factor calculation unit and adaptively adjusts the prediction factor to adapt to the slope change during the voltage drop process. The voltage prediction output unit receives the output of the adaptive prediction adjustment unit and predicts the voltage of the next cycle based on the prediction factor.

[0028] like Figure 2 As shown, the short-cycle response voltage monitoring unit consists of an inverter chain and is sampled using a flip-flop. The response time for voltage monitoring is one clock cycle, where the select[4:0] signals are used to configure its detection range. Its output requires only one cycle, labeled P[7:0], which is processed into a 4-bit output code value FF. FF is used to divide the detection voltage range of the short-cycle response voltage monitoring unit from 700 mV to 900 mV into 16 levels, and when the output code value changes, it is recorded as the anchor voltage. For example, the output code value is 15 when the voltage is greater than 900 mV, 14 when the voltage is between 875 mV and 900 mV, 13 when the voltage is between 850 mV and 875 mV, and 12 when the voltage is between 825 mV and 850 mV. Therefore, the anchor voltage when the output code value is 14 is 900 mV, the anchor voltage when the output code value is 13 is 875 mV, and the anchor voltage when the output code value is 12 is 850 mV.

[0029] like Figure 3As shown, the long-cycle response voltage monitoring unit uses a ring oscillator to map voltage changes to device delay changes. The register samples the toggling position of the ring oscillator. Within one sampling period, the quantization logic combines the results of coarse and fine quantization to calculate the final voltage quantization result, and obtains the final voltage output code value through voltage calibration. The sampling period is 1 clock cycle, the quantization period is p clock cycles (p ≥ 1), and the calibration period is q clock cycles (q ≥ 1). Therefore, the response time of the long-cycle response voltage monitoring unit for voltage monitoring is (1 + p + qa) clock cycles. If p = q = 1, the response time is 2 clock cycles.

[0030] The output of the short-cycle response voltage monitoring unit, the output of the long-cycle response voltage monitoring unit, and a schematic diagram of the current actual voltage are shown below. Figure 4 As shown, the output of the long-cycle response voltage monitoring unit always lags behind the output of the short-cycle response voltage monitoring unit by one cycle.

[0031] The predictor calculation unit obtains predictors, such as... Figure 5 As shown, it includes the following steps:

[0032] Step 101: Read the output code value of the short-cycle response voltage monitoring unit and record it as FF. If FF changes, proceed to step 102; otherwise, proceed to step 101.

[0033] Step 102: Record FF as the anchor value FH, read the output code value of the long-cycle response voltage monitoring unit, record it as S, and proceed to step 103;

[0034] Step 103: Calculate the predictor PF = 1.5×(S - FH).

[0035] The adaptive predictive adjustment unit records the output code value of the long-cycle response voltage monitoring unit at adjacent refresh times to calculate the attenuation amplitude, which is used to adjust the prediction factor to adapt to the slope change during the voltage drop process, such as... Figure 6 As shown. If the predictor is not refreshed for a long time, its value will decay to 0 cycle by cycle. This only happens when the system is already running in normal voltage or low power mode, and not during buck or voltage regulation.

[0036] The voltage prediction output unit outputs the final voltage code value V = S - PF.

[0037] Figure 7This diagram illustrates the prediction effect of the zero-delay prediction circuit in the voltage sag monitoring circuit of the present invention. The output code value S of the long-cycle response voltage monitoring unit accurately reflects the voltage state three clock cycles prior (e.g., when S=900, the voltage state is 900mV), meaning there is a three-clock-cycle response time. Using the zero-delay prediction circuit of the voltage sag monitoring circuit of the present invention, the final output voltage code value V can accurately predict S and the current voltage state three clock cycles later during a voltage sag. Furthermore, at the bottom of the voltage sag phenomenon, the zero-delay prediction circuit of the voltage sag monitoring circuit of the present invention detects the slope change and adaptively adjusts the prediction factor PF, thereby minimizing the error between V and the current voltage state.

[0038] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A zero-delay prediction circuit for voltage sag monitoring, characterized in that, It includes a short-cycle response voltage monitoring unit, a long-cycle response voltage monitoring unit, a prediction factor calculation unit, an adaptive prediction adjustment unit, and a voltage prediction output unit; The short-cycle response voltage monitoring unit is used to generate voltage code values ​​with fast response speed; The long-period response voltage monitoring unit is used to generate voltage code values ​​with slow response speed; The predictor calculation unit is used to receive the outputs of the short-cycle response voltage monitoring unit and the long-cycle response voltage monitoring unit, calculate the slope of voltage drop, and generate a predictor. The adaptive prediction adjustment unit is used to receive the output of the prediction factor calculation unit and adaptively adjust the prediction factor to adapt to the slope change during the voltage drop process. The voltage prediction output unit is used to receive the output of the adaptive prediction adjustment unit, use the prediction factor calculation unit to obtain the slope information of the voltage drop, and derive the voltage value after several cycles from the slope information. The short-cycle response voltage monitoring unit has a response time of a clock cycles for voltage monitoring, where a is a positive integer greater than or equal to 1. The response time of the long-cycle response voltage monitoring unit to voltage monitoring is b clock cycles, where b is a positive integer greater than or equal to 2 and b is greater than a. The predictor calculation unit, in generating predictors, includes the following steps: Step 101: Read the output code value of the short-cycle response voltage monitoring unit and record it as FF; if FF changes, proceed to step 102, otherwise proceed to step 101; Step 102: Record FF as the anchor value FH, read the output code value of the long-cycle response voltage monitoring unit, record it as S, and proceed to step 103; Step 103: Calculate the predictor PF = [(a + b) / b] * (S - FH).

2. The zero-delay prediction circuit for the voltage descent monitoring circuit according to claim 1, characterized in that, The adaptive prediction adjustment unit records the output code value of the long-cycle response voltage monitoring unit at adjacent refresh times to calculate the difference, which is recorded as the attenuation amplitude. Based on the proportion of the decrease in attenuation amplitude, the prediction factor is adjusted proportionally to adapt to the slope change during the voltage drop process.

3. The zero-delay prediction circuit for the voltage descent monitoring circuit according to claim 1, characterized in that, The voltage prediction output unit is used to output the final voltage code value V = S - PF.

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