Time division multiplexing-based method for acquiring maximum continuous resource blocks of GPU

Abstract

The application relates to a GPU maximum continuous resource block acquisition method based on time division multiplexing, which comprises the following steps: step G1, setting the number C of time periods required in the acquisition of maximum continuous resource blocks in each round, and initializing c=1; step G2, acquiring a current resource state sequence corresponding to each resource type identifier in the cth time period, dividing shared hardware units into Rc groups, and storing each current resource state sequence into a corresponding shared hardware unit group; step G3, performing a maximum continuous resource block acquisition operation on Rc current resource state sequences in parallel based on the shared hardware units in the cth time period, and acquiring the maximum resource block quantity corresponding to each resource type identifier in the cth time period; and step G4, judging whether c is equal to C, if yes, ending, otherwise, setting c=c+1, and returning to step G2. The application reduces the area and power consumption of the GPU, and improves the resource utilization rate and computing performance of the GPU.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method for obtaining the largest contiguous resource block of a GPU based on time-division multiplexing. Background Technology

[0002] A Graphics Processing Unit (GPU), also known as a display core, visual processor, or display chip, is designed for computationally intensive, highly parallel computing. A GPU contains various resources, and an imbalance in the allocation of any of these resources during task execution can lead to wasted resources, reducing GPU resource utilization and computational performance. Therefore, during GPU operation, it is necessary to schedule each GPU resource as evenly as possible, ensuring that each resource is in a resource-balanced state, thereby improving the overall resource utilization and computational performance of the GPU.

[0003] However, GPUs possess a wide variety and large quantity of resources. In current technologies, achieving balanced GPU resource scheduling remains challenging, especially for complex computational tasks. It typically requires significant time to allocate resources, and the allocation results are unreliable and fail to guarantee resource balance. Therefore, providing an efficient and reliable GPU resource balancing scheduling technology to rationally allocate corresponding GPU resources to multi-tasking groups, thereby improving task processing efficiency, GPU resource utilization, and computational performance, has become a pressing technical problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a method for obtaining the largest contiguous resource block of a GPU based on time-division multiplexing, which reduces the area and power consumption of the GPU and improves the resource utilization and computing performance of the GPU.

[0005] According to the present invention, a method for obtaining the largest contiguous resource block of a GPU based on time-division multiplexing is provided, comprising the following steps:

[0006] Step G1: Set the number of time periods C required to acquire the largest contiguous resource block in each round, configure at least one resource type identifier for each time period, and initialize c = 1;

[0007] Step G2: Obtain the current resource status sequence corresponding to each type of resource identifier in the c-th time period, divide the shared hardware unit into Rc groups, where Rc is the number of resource type identifiers in the c-th time period, and store each current resource status sequence into the corresponding shared hardware unit group.

[0008] Step G3: In the c-th time period, the maximum contiguous resource block acquisition operation is performed in parallel on the Rc current resource state sequences based on the shared hardware unit to obtain the maximum number of resource blocks corresponding to each resource type identifier in the c-th time period.

[0009] Step G4: Determine if c is equal to C. If it is, end the acquisition operation of the largest contiguous resource block in this round. Otherwise, set c = c + 1 and return to step G2.

[0010] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the method for obtaining the largest contiguous resource block of a GPU based on time-division multiplexing provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It possesses at least the following advantages:

[0011] This invention enables time-division multiplexing of the hardware units in the execution module that acquire the largest contiguous resource block, and allows simultaneous acquisition of the largest contiguous resource from multiple resource groups within the same time period. This reduces the number of hardware units for acquiring the largest contiguous resource block in the execution module, thereby reducing the GPU's area and power consumption.

[0012] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0013] Figure 1 A schematic diagram illustrating the distribution of task groups to the GPU using the existing multitasking channel;

[0014] Figure 2 Here is a flowchart of the GPU resource scheduling method provided in Example 1;

[0015] Figure 3 Here is a flowchart of the GPU resource scheduling method provided in Example 2;

[0016] Figure 4 Flowchart of the GPU resource scheduling method provided in Example 3;

[0017] Figure 5 A flowchart of the method for obtaining the largest contiguous resource block of a GPU provided in Example 4;

[0018] Figure 6 A flowchart of the method for obtaining the largest contiguous resource block of a GPU provided in Example 5;

[0019] Figure 7A flowchart of the method for obtaining the largest contiguous resource block of a GPU provided in Example 6;

[0020] Figure 8 A flowchart of the method for obtaining the largest contiguous resource block of a GPU based on time-division multiplexing provided in Example 7;

[0021] Figure 9 Flowchart of the GPU resource scheduling method provided in Example 8;

[0022] Figure 10 Flowchart of the GPU resource scheduling method provided in Example 9;

[0023] Figure 11 The flowchart of the GPU resource scheduling method provided in Example 10. Detailed Implementation

[0024] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation and effects of a method for obtaining the maximum contiguous resource block of a GPU based on time-division multiplexing proposed in accordance with the present invention.

[0025] like Figure 1 In existing scenarios where upper-layer software connecting to the GPU distributes tasks to the GPU, multiple task channels W1-W are typically used. R Tasks are distributed to the GPU. Each task channel is independent and can send different task packages to the GPU. Each task package includes different work groups (WGs). The same task package corresponds to the same process, and the same task channel can receive task packages sent by different processes. Each task group includes m wave threads, where m ranges from 1 to M, and M is the maximum number of waves in the task group. Each wave contains the same number of threads.

[0026] Existing GPU architectures typically include P execution modules ( Figure 1 In this context, AP represents the execution module, which includes Q execution units (AP). Figure 1 (represented by PEU in Chinese) When multiple task groups are issued, they need to be distributed to the execution modules as evenly as possible. Specifically, each task group needs to be assigned to a corresponding execution module, and the waves in a task group should be evenly distributed to the Q execution units of the selected execution module to ensure the balance of GPU resources.

[0027] In existing GPU resource scheduling technologies, task groups are usually assigned priorities. When the GPU receives an R-path task group, it first looks for an execution module that can be allocated to the first priority task group, and then assigns the first priority task group to that execution module. Then it looks for an execution module that can be allocated to the second priority task group, and so on. The first priority is higher than the second priority.

[0028] However, existing GPU resource scheduling technologies suffer from at least the following problems: First, each task group in each task channel requires a resource lookup and matching process. Furthermore, for each resource requiring contiguous access, existing technologies employ hardware lookups based on multiple clock cycles or software lookups, resulting in very low efficiency and consuming significant GPU resources. Second, when a high-priority task cannot find a suitable execution module, it causes task group congestion across all task channels until the execution module releases resources to satisfy the high-priority task group, severely impacting task distribution and processing efficiency. To address these technical problems, this invention proposes the following multiple embodiments to provide solutions.

[0029] Example 1

[0030] A GPU resource scheduling method, such as Figure 2 As shown, including

[0031] Step A1: Obtain the task group to be distributed corresponding to each task channel and read the resource requirement information of each task group to be distributed.

[0032] It should be noted that each task group carries information on the required GPU resources for various types of tasks, including resource identifiers and corresponding resource quantities. This can be directly read using existing hardware technology, and will not be elaborated upon here.

[0033] Step A2: Obtain the current remaining resource information for each execution module in the current GPU;

[0034] This can be understood as the current remaining resource information of the execution module including the current remaining resource quantity for each resource in the execution module.

[0035] Step A3: Match the resource requirement information of each task group to be assigned with the current remaining resource information of all execution modules. If the current remaining resource information of at least one execution module matches the resource requirement information of the task group to be assigned, then add the task group to be assigned to the candidate task group set.

[0036] It should be noted that a match is indicated when the current remaining amount of each resource in the execution module is greater than or equal to the corresponding resource requirement of the task group to be distributed.

[0037] Step A4: Select the highest priority task group to be assigned from the candidate task group set as the target task group, and select a target execution module from the execution modules that match the target task group, and assign the target task group to the target execution module.

[0038] Each task group carries priority identification information. By reading the priority identification information of the task group, the corresponding priority can be obtained.

[0039] In this embodiment, by performing parallel synchronous matching of multiple task groups, all task groups that meet the requirements can be directly filtered out, and then the highest priority task group is selected for allocation from the candidate task groups. It is understood that even if a high-priority task group requires a large number of resources, and there is currently no execution module that can meet the high-priority resource requirements, a lower-priority task group that meets the resource requirements can be quickly allocated. This avoids the task blocking situation caused by the inability to match high-priority tasks, as is common in existing technologies, thus improving the efficiency of task allocation, saving GPU computation time, and conserving GPU power consumption.

[0040] As one embodiment, in step A2, the remaining resource information includes the maximum number of consecutive remaining resources corresponding to each type of first-class resource and the maximum number of remaining resources corresponding to each type of second-class resource. The first-class resources are resources in the execution module that have continuous allocation requirements, and the second-class resources are resources in the execution module that do not have continuous allocation requirements. It can be understood that GPU resources include multiple types of first-class resources and multiple types of second-class resources.

[0041] For example, GPU resources include Scalar General Purpose Registers (S-GPRs) and Vector General Purpose Registers (V-GPRs) distributed across execution units, allocable wave resources within execution units, and memory modules accessible to all execution units within the execution module. S-GPRs and V-GPRs are the first type of resources with contiguous allocation requirements. Allocable wave resources are fewer in number and only involve wave identifier mapping; therefore, they belong to the second type of resources without contiguous allocation requirements. Specifically, the maximum contiguous resource count for each type of resource can be calculated separately through GPU hardware implementation, or by using software querying to obtain the maximum contiguous resource count for each type of resource.

[0042] In this embodiment, instead of searching for and matching remaining resources for each task group separately, the resources in the execution module are divided into a first type of resource and a second type of resource. The maximum number of consecutive remaining resources corresponding to each type of first type of resource and the maximum number of remaining resources corresponding to each type of second type of resource are obtained. In this way, by calculating the remaining resource information in all execution modules at once, matching can be performed synchronously with each task group.

[0043] As one embodiment, each task channel is set up with a corresponding First In First Out (FIFO) queue. The task channel stores the received task groups one by one into the FIFO queue according to the order of receipt. The task group to be distributed is the first task group in the FIFO queue of the task group channel.

[0044] It should be noted that by setting up a first-in-first-out queue for each task channel, it can be ensured that the task groups of each task channel are always executed in the order issued by the upper-level software, and there will be no disorder.

[0045] As one embodiment, the GPU chip typically performs task distribution and processing on multi-channel task groups continuously. Specifically, after step A4, the following is also included:

[0046] Step A5: Determine whether the task group to be dispatched corresponding to each task channel is empty. If it is empty, end the process; otherwise, return to step A1.

[0047] As one embodiment, each execution module includes Q execution units, and step A3 includes:

[0048] Step A31: Divide the task group to be distributed into Q wave groups, obtain the resource requirement information corresponding to each wave group, and the shared resource requirement information of the task group to be distributed for the entire execution module.

[0049] Step A32: Match the resource requirement information corresponding to the Q wave groups with the remaining resource information of the Q execution units, and match the shared resource requirement information with the shared remaining resource information of the execution module. If all matches are successful, add the task group to be distributed to the candidate task group set.

[0050] It is understandable that when the resource requirement information corresponding to each wave group is less than or equal to the remaining resource information of the corresponding execution unit, and when the shared resource requirement information of Q wave groups is less than or equal to the shared remaining resource information of the execution module, the matching is successful.

[0051] There may be one highest priority task in the candidate task group set, or multiple highest priority tasks may appear at the same time. Therefore, a further processing mechanism is needed to ensure the balanced allocation of tasks across multiple task channels.

[0052] As one embodiment, step A4, selecting a target execution module from the execution modules matching the target task group, includes:

[0053] Step A41: If the candidate task group set includes only one highest priority task group to be assigned, then that task group to be assigned is determined as the target task group.

[0054] As one embodiment, in step A4, selecting a target execution module from the execution modules matching the target task group includes:

[0055] Step A42: If the candidate task group set includes multiple highest priority task groups to be assigned, then determine whether there are any task channels among the task channels corresponding to the multiple highest priority task groups to be assigned that do not have a selected flag marked for that priority:

[0056] If it exists, randomly select one from the unmarked channel's corresponding task group as the target task group, and mark the priority of that task group as selected in the task group channel.

[0057] If it does not exist, randomly select one from multiple highest priority task groups to be assigned as the target task group, retain the selected flag for that priority in the task group channel corresponding to that task group, and clear the selected flag for that priority in the task group channels corresponding to other task groups.

[0058] Step A42 ensures a balanced allocation of tasks across multiple task channels, especially when multiple task groups with the same priority simultaneously meet resource allocation requirements.

[0059] As one embodiment, step A4, assigning the target task group to the target execution module, includes:

[0060] Step A43: Obtain the starting allocation address of each first type of resource in the target execution module;

[0061] Step A44: Based on the initial allocation address and allocation quantity, allocate the corresponding first-type resources to the corresponding tasks in the target task group;

[0062] Step A45: Assign the corresponding second type of resource to the corresponding task in the target task group.

[0063] It should be noted that resources requiring continuous allocation can also be allocated non-contiguously. Existing technologies often employ this allocation method, but it requires multiple searches for the target location, resulting in low allocation efficiency. Furthermore, during task execution, multiple address searches are required, leading to a heavy information exchange burden and low execution efficiency. Embodiment 1, by obtaining the maximum number of consecutive remaining resources of the first type of resource, allocates the target task to a contiguous address space. This eliminates the need for separate address searches for each storage location; rapid allocation can be achieved simply by using the starting address and the target quantity, improving task allocation efficiency. Moreover, during task execution, rapid access and execution based on contiguous addresses improves information exchange efficiency, thereby enhancing task execution efficiency. It should be noted that the relevant technical details in subsequent embodiments are also applicable to the steps in this embodiment, and will not be repeated here.

[0064] Example 2

[0065] While Embodiment 1 can avoid the blocking problem caused by the remaining resources of the execution module not meeting the needs of the high-priority task group, there is another situation where, if the high-priority task group can consistently find an execution module that meets the conditions for a long period of time, then the low-priority task group will be unable to be allocated, and the task channel of the low-priority task group will be blocked for a long time. In order to solve this problem, the present invention further proposes Embodiment 2.

[0066] A GPU resource scheduling method, such as Figure 3 As shown, it includes:

[0067] Step B1: Obtain the priority of the task group received by the GPU, {P1, P2, ... P}. S}, P s Let s be the priority level, where s ranges from 1 to S, and S is the total number of priority levels in the task group.

[0068] It should be noted that each task group is assigned a priority identifier, which allows you to retrieve the priority information of the task group. This identifier can be set to P1, P2, ... P S The priority decreases in sequence. The range of values ​​for S is determined according to the specific application requirements. For example, the range of values ​​for S can be set from 2 to 8. Specifically, S can be 4.

[0069] Step B2: Divide the preset number of clock cycles into Y time windows {T1, T2, ... T...} Y}, T y Let y be the y-th time window;

[0070] Wherein, T1, T2, ... T can be set. YThe corresponding number of cycles decreases sequentially. The range of Y is determined according to specific application requirements; for example, the range of Y can be set to 2 to 8, specifically, Y can be 4. Preferably, the value of S is equal to the value of Y, and P... s With T s One-to-one correspondence.

[0071] Step B3: Set a clock cycle loop counter on the GPU, and loop the count within a preset number of clock cycles. When the value of the clock cycle loop counter is within T... y Within the time window, P s Adjust to highest priority;

[0072] Preferably, when P s When a priority is adjusted to the highest level, the remaining priorities are arranged in the original priority order.

[0073] Step B4: Allocate GPU resources to each task group based on the current priority sorting.

[0074] Using the above method, the priority order of task groups can be dynamically adjusted, and different time windows are allocated to different priorities. The time window for high priority is longer than that for low priority. Based on the current priority order obtained from this priority adjustment scheme, GPU resources are allocated to each task group.

[0075] As one embodiment, step B4 includes:

[0076] Step B41: Obtain the task group to be distributed corresponding to each task channel and read the resource requirement information of each task group to be distributed.

[0077] Step B42: Obtain the current remaining resource information for each execution module in the current GPU;

[0078] Step B43: Construct a candidate task group set based on the resource requirement information and current remaining resource information of each task group to be assigned;

[0079] Step B44: Read the current priority sorting, select the task group with the highest current priority from the candidate task group set as the target task group according to the current priority sorting, select a target execution module from the execution modules that match the target task group, and assign the target task group to the target execution module.

[0080] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.

[0081] Example 2 dynamically adjusts the priority order of task groups and allocates time windows of different lengths to different priorities. This avoids the situation where, under static priority, high-priority task groups can be matched with execution modules that meet the conditions for a long time, which would cause low-priority task groups to be unable to be assigned, and the task channels of low-priority groups to be blocked for a long time. This improves the task distribution efficiency and resource scheduling efficiency of the GPU.

[0082] Example 3

[0083] Typically, waves within a task group are interconnected and therefore need to be assigned to the same execution module for processing. However, in some cases, waves within a task group are independent and can be assigned to different execution modules. If a task group with independent waves requires a large amount of resources, and multiple execution modules are unable to meet the resource demands of the task group for an extended period, the task group will be unable to be distributed and will remain in a blocked state. Based on this scenario, the present invention further proposes Embodiment Three.

[0084] A GPU resource scheduling method, such as Figure 4 As shown, including

[0085] Step C1: Obtain the task group to be distributed corresponding to each task channel, read the resource requirement information of each task group to be distributed, and obtain the current remaining resource information of each execution module in the current GPU.

[0086] Step C2: Match the resource requirements of each task group to be distributed with the current remaining resource information of all execution modules. If all task groups to be distributed fail to match, set the value of the failure round counter G = G + 1, and determine whether G exceeds the preset number of times threshold. If it does, proceed to step C3; otherwise, return to step C1.

[0087] The preset number of times threshold is set according to specific application requirements; for example, the number of times threshold can be set to 256.

[0088] Step C3: Read the unique identifier information of each task group to be distributed. If there is a task group to be distributed marked with a unique identifier, then divide at least one task group to be distributed marked with a unique identifier into multiple sub-task groups.

[0089] In this context, if a task group to be assigned is marked with an independent identifier, it indicates that the waves within the task group are independent of each other. Task groups to be assigned without an independent identifier indicate that the waves within the task group are interconnected. Specifically, an independent identifier bit can also be set: an independent identifier of "1" indicates that the waves within the task group are independent, and an independent identifier of "0" indicates that the waves within the task group are interconnected.

[0090] Independent identifiers can be directly assigned to task groups by the upper-layer software when distributing task groups. It should be noted that in this embodiment, G exceeding the preset threshold number of times may occur in at least two situations: Situation 1: All task groups corresponding to all task channels fail to find an execution module that meets resource requirements for G consecutive times. Situation 2: Tasks on other task channels have been distributed, and at least one task channel's task group fails to find an execution module that meets resource requirements for G consecutive times. In these situations, if the release of execution unit resources is slow, or the resource requirements of the task group to be distributed are too high, it may cause multiple task channels to be blocked for a long time, seriously affecting task distribution efficiency and GPU resource scheduling efficiency. In Embodiment 3, for cases where waves are independent within the currently blocked task group to be processed, splitting such task groups to be distributed can quickly alleviate task congestion and improve task distribution efficiency and GPU resource scheduling efficiency.

[0091] As one embodiment, in step C3, if the current remaining resource information of at least one execution module matches the resource requirement information of the task group to be assigned, then the task group to be assigned is added to the candidate task group set, and step C4 is executed.

[0092] Step C4: Select the highest priority task group to be assigned from the candidate task group set as the target task group, and select a target execution module from the execution modules that match the target task group. Assign the target task group to the target execution module and return to step C1.

[0093] As one embodiment, step C0, setting the initial value of G, is included before step C1. Preferably, the initial value of G is set to 0 for easy counting.

[0094] As one embodiment, in step C3, dividing at least one task group to be distributed with an independent identifier into multiple sub-task groups includes: dividing each wave in at least one task group to be distributed with an independent identifier into a sub-task group.

[0095] It should be noted that dividing each wave in the task group to be distributed with an independent identifier into a sub-task group facilitates operation, simplifies the execution logic, eliminates the need for additional grouping, simplifies the processing flow, and improves processing efficiency. Furthermore, since at least one of the current task groups to be distributed contains only one wave after the division, the probability of successful resource matching is greatly increased, effectively alleviating task channel congestion.

[0096] As one embodiment, step C3 further includes setting the priority of each subtask group to the lowest priority.

[0097] It should be noted that by setting the priority of each subtask group to the lowest priority, it is possible to alleviate task channel congestion while still ensuring that, among the task groups that meet the resource requirements, those that can meet the overall resource requirements in the unsplit state are given priority allocation, thereby improving GPU resource utilization.

[0098] As one embodiment, after step C3 is completed, the method further includes: sequentially assigning each subtask group as a task group to be processed in the corresponding task channel, setting G to the initial value, and returning to step C1. It should be noted that the relevant technical details in the preceding embodiments and subsequent embodiments are also applicable to the relevant steps in this embodiment, and will not be repeated here.

[0099] In Example 3, for cases where waves are independent within the currently blocked task group, the task blocking is quickly alleviated by splitting such task groups, thereby improving task distribution efficiency and GPU resource scheduling efficiency.

[0100] Example 4

[0101] In existing technologies, the maximum consecutive resource count of each type of resource is typically read separately using GPU hardware, or obtained through software. However, software-based searches are time-intensive, requiring a bit-by-bit lookup. Each found usable resource needs to be recorded and matched, resulting in an uncontrollable number of clock cycles and extremely low search efficiency. Hardware implementations, on the other hand, merely implement the software approach with multiple clock cycles, also suffering from the uncontrollable and potentially large number of clock cycles inherent in software methods. Therefore, Embodiment 4 proposes a method for obtaining the maximum consecutive resource block of a GPU, comprising the following steps:

[0102] Step D1: Read the current resource status sequence S0 = {d1, d2, ... d} of the resource to be queried. N},d n The status identifier n for the nth resource block of the resource to be queried ranges from 1 to N, where N is the total number of resource blocks of the resource to be queried.

[0103] Step D2: Obtain the state sequence S1, S2, ... S1, S2, ... S1, S2, S3, S4, S5, S6, S7, S8, S9, S1, S2, ... S1, S2, S3, S4 ... N-1 , among which, S i The sequence obtained by moving S0 i positions in a preset direction and setting the last i positions of the moved S0 along the preset direction as occupied identifiers, where i ranges from 0 to N-1; wherein, moving i positions in the preset direction includes shifting i positions to the left or to the right.

[0104] Step D3: Parallel acquisition of S0 to S i The result of a bitwise AND or bitwise OR operation is SA i ;

[0105] Step D4: Place each SA i Perform an OR operation or a AND operation followed by a NOT operation to determine the current maximum number of contiguous resource blocks of the resource to be queried.

[0106] The current resource status sequence can be directly read from the hardware using existing technology. The status identifier includes an occupied identifier and an unoccupied identifier, where the occupied identifier is 0 and the unoccupied identifier is 1. Step D3 performs a bitwise AND operation, and step D4 performs a self-OR operation. Alternatively, the occupied identifier is 1, the unoccupied identifier is 0, step D3 performs a bitwise OR operation, and step D4 performs a self-AND followed by a NOT operation.

[0107] It should be noted that S0 to S i Perform a bitwise AND or bitwise OR operation, that is, first perform a bitwise AND or bitwise OR operation between S0 and S1 to obtain S. 0-1 Then S 0-1 Performing a bitwise AND or bitwise OR operation with S2 yields S. 0-2 S 0-2 Then perform a bitwise AND or bitwise OR operation with S3 to obtain S. 0-3 Execute sequentially until S is reached. 0-(i-1) With S i Perform a bitwise AND or bitwise OR operation to obtain S. 0-i That is, the SA mentioned above i For example, performing a bitwise AND operation on two sequences involves performing a bitwise AND operation on the values ​​at the same positions in both sequences, using the result as the value at that position, and finally obtaining a new sequence. For example, performing a bitwise AND operation on the sequences 0 0 1 0 0 1 and 1 0 1 1 0 1 yields the result 00 1 0 0 1. Those skilled in the art will know that other bitwise OR operations and bitwise AND followed by NOT operations follow similar logic, and will not be listed here. As one embodiment, step D4 includes:

[0108] Step D41, each SA i Perform an OR operation or a AND operation followed by an inverse operation to obtain the SAR. i ;

[0109] Step D42, based on all SARs i Generate the first test sequence {SAR0, SAR1, ... SAR} N-1};

[0110] Step D43: Based on {SAR0, SAR1, ... SAR N-1 Determine the current maximum number of contiguous resource blocks for the resource to be queried.

[0111] It is understandable that each SA i Perform an OR operation or a AND operation followed by an inverse operation to obtain the SAR. i The value is 0 or 1.

[0112] As one embodiment, steps D2, D3, and D4 are executed within the same clock cycle. A corresponding set of hardware units is set up to execute steps D2, D3, and D4 respectively. This improves task distribution and resource scheduling efficiency within a single cycle. When the GPU chip's operating frequency requirement is not high, it helps reduce the GPU chip area and power consumption. In this embodiment, since steps D2, D3, and D4 are executed within the same clock cycle, meaning they transmit information within the same clock cycle, the hardware units can be implemented using combinational logic. The specific implementation method of combinational logic technology is an existing method and will not be described further here.

[0113] As one embodiment, steps D2, D3, and D4 can each be executed serially within a preset clock cycle. Each of steps D2, D3, and D4 is equipped with a separate hardware unit, which helps improve the GPU chip's operating frequency and execution performance. In this embodiment, steps D2, D3, and D4 can transmit information over three consecutive clock cycles. The information transmission can be implemented using registers; the technical details of this register implementation are existing technology and will not be described further here.

[0114] As one embodiment, the occupied flag is 0 and the unoccupied flag is 1. A bitwise AND operation is performed in step D3, and a self-OR operation is performed in step D4. Alternatively, the occupied flag is 1 and the unoccupied flag is 0. A bitwise OR operation is performed in step D3, and a self-AND followed by a NOT operation is performed in step D4. It is understood that once the preset direction, occupied flag, and unoccupied flag are determined, the subsequent first mapping table is also set based on this configuration.

[0115] As one embodiment, step D43 includes:

[0116] Step D431: Set {SAR0, SAR1, ... SAR... N-1 The value of the first sequence to be tested is compared with a pre-configured first mapping table, and the current maximum number of consecutive resource blocks of the resource to be tested is output. The first mapping table is used to store the mapping relationship between the first sequence to be tested and the maximum number of consecutive resource blocks.

[0117] As one embodiment, step D43 includes:

[0118] Step D432, in {SAR0, SAR1, ... SAR N-1 From SAR N-1 Start reading backwards to identify the first SAR value equal to 1. i The value of i is denoted as i';

[0119] Step D433: Determine i'+1 as the current maximum number of contiguous resource blocks of the resource to be queried.

[0120] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.

[0121] Example 4 uses the current resource status sequence of the resource to be queried to quickly and accurately obtain the current maximum number of consecutive resource blocks of the resource to be queried within one or a few clock cycles with a controllable clock, based on simple hardware operations and a pre-configured first mapping table, thereby improving the efficiency of resource scheduling.

[0122] Example 5

[0123] Example 4 is preferably applicable when the total number of resources to be checked is small, for example, only 8 bits or 16 bits. However, when the total number of resources to be checked is large, such as 128, a large amount of hardware needs to be arranged, such as a large number of registers or circuit lines, and a large number of AND gates and OR gates, which will increase the area and power consumption of the GPU chip. Based on this, Example 5 is further proposed based on Example 4.

[0124] A method for obtaining the largest contiguous resource block in a GPU includes the following steps:

[0125] Step E1: Read the current resource status sequence S0 = {d1, d2, ... d} of the resource to be queried. N},d n This is the status identifier of the nth resource block of the resource to be queried, where n ranges from 1 to N, and N is the total number of resource blocks of the resource to be queried.

[0126] Step E2: Divide S0 into Z groups of resource state sequences {U1, U2, ..., U...}. Z}, where U z Let U be the resource state sequence of the z-th group. z ={d N*(z-1) / Z+1 ,d N*(z-1) / Z+2 ,…d N*z / ZThe value of z ranges from 1 to Z, where Z is less than N and Z is divisible by N. Let {U1, U2, ..., U...} be the range of z. Z Each U in} z Perform bitwise AND or bitwise OR operations to generate the state sequence to be processed, F0 = {UA1, UA2, ... UA...} Z}, UA z For U z The result of the corresponding bitwise AND or bitwise OR operation;

[0127] It should be noted that by equally dividing S0 into Z groups, the sequence can be shortened, which greatly reduces the computational load of subsequent shift, AND operation, and OR operation or AND-NOT operation, thereby reducing the number of corresponding hardware layouts and thus reducing the area and power consumption of the GPU.

[0128] Preferably, N is a multiple of 4 and Z is N / 4.

[0129] Step E3: Determine the current maximum number of contiguous resource blocks of the resource to be queried based on F0.

[0130] As one embodiment, step E3 includes:

[0131] Step E31: Obtain the state sequence F1, F2, ... S in parallel as F0 moves j positions in a preset direction. Z-1 , of which F j F0 is shifted j positions in a preset direction, and the last j positions in the preset direction are set as occupied identifiers to obtain the sequence. The value of j ranges from 0 to Z-1.

[0132] The movement of j positions in the preset direction includes either shifting j positions to the left or shifting j positions to the right.

[0133] Step E32: Obtain F0 to F in parallel j The result of a bitwise AND or bitwise OR operation is FA. j ;

[0134] Step E33, each FA j Perform an OR operation or a AND operation followed by a NOT operation to determine the current maximum number of contiguous resource blocks of the resource to be queried.

[0135] As one embodiment, steps E31, E32, and E33 are executed within the same clock cycle. A corresponding set of hardware units is set up to execute steps E31, E32, and E33, which improves task distribution and resource scheduling efficiency within a single cycle. When the GPU chip's operating frequency requirement is not high, this helps reduce the GPU chip area and power consumption. In this embodiment, since steps E31, E32, and E33 are executed within the same clock cycle, meaning that steps E31, E32, and E33 transmit information within the same clock cycle, the hardware unit can be implemented using combinational logic. The specific implementation method of combinational logic technology is an existing implementation method and will not be described in detail here.

[0136] As an example, the occupied flag is 0, and the unoccupied flag is 1. In step E2, {U1, U2, ... U Z Each U in} z Perform a bitwise AND operation; in step E32, the bitwise AND operation is performed, and in step E33, an OR operation is performed; or, if the occupied flag is 1 and the unoccupied flag is 0, in step E2, {U1, U2, ... U... Z Each U in} z A bitwise OR operation is performed. In step E32, the bitwise OR operation is performed, and in step E33, the bitwise AND operation is performed followed by the NOT operation.

[0137] As one embodiment, steps E31, E32, and E33 are executed serially each occupying a preset clock cycle. Steps E31, E32, and E33 reuse a set of hardware units, which helps to reduce the GPU chip area and power consumption.

[0138] As one embodiment, steps E31, E32, and E33 can each be executed serially within a preset clock cycle. Each of steps E31, E32, and E33 uses a separate hardware unit, which helps improve the GPU chip's operating frequency and execution performance. In this embodiment, steps E31, E32, and E33 can specifically transmit information over three consecutive clock cycles. The information transmission can be implemented using registers; the technical details of using registers are existing technology and will not be described further here. As one embodiment, step E33 includes:

[0139] Step E331, each FA j Perform an OR operation or a AND operation followed by a NOT operation to obtain FAR. j ;

[0140] Step E332, based on all FARs jGenerate the first test sequence {FAR0, FAR1, ... FAR} Z-1};

[0141] Step E333, based on {FAR0, FAR1, ... FAR... Z-1 Determine the current maximum number of contiguous resource blocks for the resource to be queried.

[0142] As one embodiment, step E333 includes:

[0143] Step E3333: Set {FAR0, FAR1, ... FAR} Z-1 The value of the query resource is compared with a pre-configured second mapping table, and the current maximum number of contiguous resource blocks is output. The second mapping table is used to store the mapping relationship between the auto-OR sequence and the maximum number of contiguous resource blocks.

[0144] Understandably, once the preset direction, occupied flag, and unoccupied flag are determined, the second mapping table is also set based on this configuration.

[0145] As one embodiment, step E333 includes:

[0146] Step E3331, in {FAR0, FAR1, ... FAR... Z-1 From FAR Z-1 Starting from the first bit, read backwards to determine the first FAR value equal to 1. j Given the value of j, set j' = j + 1;

[0147] Step E3332: Determine the current maximum number of contiguous resource blocks X of the resource to be queried based on j':

[0148] X = j'*(N / Z).

[0149] Example 5 divides the current resource state sequence of the resource to be queried into Z groups, shortening the state sequence from N bits to Z bits, greatly reducing the subsequent computational load and the area and power consumption of the GPU chip. The specific value of Z is determined according to the specific application scenario. Although Example 5 cannot cover all possible consecutive maximum resource block values, it is understandable that when the resource requirement is between (j-1)*(N / Z) and j*(N / Z), a successful match is considered if the maximum resource block satisfies a value greater than or equal to j*(N / Z). Although there may be some omissions, the probability is low, especially since GPUs typically contain multiple execution modules, each equipped with the same hardware resources. Therefore, when matching with multiple identical resources, the impact of grouping on the matching result is almost negligible. The following example illustrates this:

[0150] Taking a resource block count of 128 as an example, the blocks are divided into groups of 4, for a total of 32 groups. Each resource block is marked as occupied (0) and unoccupied (1). After dividing into 32 groups, the 4 status flag bits of each group are ANDed to form 1 bit. If the result is 1, it indicates that the current group is available; if it is 0, it indicates that the current group is unavailable. Assume that the resource availability is completely randomized, with a probability of 1 / 2 for both 1 and 0.

[0151] When the task group to be distributed has a large resource requirement, regardless of whether it is grouped or not, it needs multiple consecutive resource blocks or all blocks in the group to be 1. The disadvantage of grouping is not obvious. However, when the task group to be distributed has a small resource requirement, such as 4 resource blocks, without grouping, it is enough to find a number of consecutive 1s greater than or equal to 4 to meet the requirement. It is not necessary to satisfy that the starting position of the 4 1s is divisible by 4. However, with grouping, it is required that there are at least 4 1s and the starting position is divisible by 4. Intuitively, the effect of meeting the resource requirement will be worse. However, since the same resource on the GPU is usually multiple, the final matching effect is basically unchanged. The following is a specific analysis with a resource requirement of 4. In this example, it is assumed that there are 16 execution modules, each of which includes 4 execution units. The task group to be distributed needs to allocate the wave to the four execution units of one of the execution modules.

[0152] For one execution unit within an execution module, the probability that each group does not satisfy the condition is 1 - 1 / 16 = 15 / 16. Therefore, the probability that none of the 32 groups satisfy the condition is (15 / 16). 32 =0.127. In the worst case, assuming the current task group to be distributed exceeds 4 waves, if any one of the 4 execution units of an execution module does not have sufficient resources, it cannot adapt to the task group to be distributed, and the probability is 1-(1-0.127). 4 =0.418.

[0153] Thus, it is evident that when there is only one execution module, the grouping approach in Example 5 has a significant impact on finding resources for the task group to be distributed. However, as the number of execution modules increases, this impact weakens significantly. For example, in the commonly used scenario with 16 execution modules, the probability that none of the execution modules can adapt to the task group to be distributed is 0.418. 16 =9e-7=0, meaning the probability that none of the 16 execution modules can find resources is close to 0, which means that the impact of this grouping approach on the resource requirement of 4 can be ignored.

[0154] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.

[0155] Example 6

[0156] Example 4 increases the area and power consumption of the GPU chip when the total number of resources to be checked is large. Example 5, based on the examples, reduces the amount of hardware required and decreases the area and power consumption of the GPU chip, but the maximum number of resources determined can only be a multiple of N / Z, which has certain limitations. Based on this, Example 6 is proposed.

[0157] A method for obtaining the largest contiguous resource block in a GPU includes the following steps:

[0158] Step F1: Read the current resource status sequence S0 = {d1, d2, ... d} of the resource to be queried. N},d n This is the status identifier of the nth resource block of the resource to be queried, where n ranges from 1 to N, and N is the total number of resource blocks of the resource to be queried.

[0159] Step F2: Obtain the state sequence S1, S2, ... S1, S2, ... S1, S2, S3, S4, S5, S6, S7, S8, S9, S1, S2, ... S1, S2, S3, S4 ... N-1 , among which, S i Move S0 i positions in a preset direction and set the last i positions of the moved S0 along the preset direction as the occupied identifier to obtain the sequence. The value of i ranges from 0 to N-1.

[0160] The step of moving i positions in the preset direction includes shifting i positions to the left or shifting i positions to the right.

[0161] Step F3: Sample from 0 to N-1 to obtain W k values ​​{k0, k1, ..., k(W-1)}, and obtain S0 to S... in parallel. k The result of a bitwise AND or bitwise OR operation is SA k ;

[0162] Step F4, based on SA k Determine the current maximum number of contiguous resource blocks for the resource to be searched.

[0163] As one embodiment, step F4 includes:

[0164] Step F41, transfer each SA k Perform an OR operation or a AND operation followed by an inverse operation to obtain the SAR. k ;

[0165] Step F42, based on all SARs k Generate the SAR sampling sequence to be tested k0 SAR k1 , ...SAR k(w-1)};

[0166] Step F43, based on {SAR k0 SAR k1 , ...SARk(w-1) Determine the current maximum number of contiguous resource blocks for the resource to be queried.

[0167] As an example, the status identifier includes an occupied identifier and an unoccupied identifier. If the occupied identifier is 0 and the unoccupied identifier is 1, a bitwise AND operation is performed in step F3, and a self-OR operation is performed in step F41; or, if the occupied identifier is 1 and the unoccupied identifier is 0, a bitwise OR operation is performed in step F3, and a self-AND followed by NOT operation is performed in step F41.

[0168] As one embodiment, k(w+1)-kw≥kw-k(w-1), where kw is the (w+1)th k value in {k0,k1,…k(W-1)}, and the value of w ranges from 0 to W-1. Preferably, k(w+1)-kw is an integer power of 2.

[0169] It should be noted that k(w+1)-kw≥kw-k(w-1) allows the sampling step size to be gradually increased, making the values ​​with smaller k values ​​denser, which can hit more of the maximum consecutive resource blocks with smaller possible values; the values ​​with larger k values ​​are sparser, which can reduce the amount of computation of AND operations to a greater extent, reduce the number of AND gates and other hardware, and still ensure the accuracy of the calculation results.

[0170] In one embodiment, steps F2, F3, and F4 are executed within the same clock cycle. A corresponding set of hardware units is set up to execute steps F2, F3, and F4 respectively. This improves task distribution and resource scheduling efficiency within a single cycle. When the GPU chip's operating frequency requirements are not high, it helps reduce the GPU chip area and power consumption. In this embodiment, since steps F2, F3, and F4 are executed within the same clock cycle, meaning they transmit information within the same clock cycle, the hardware units can be implemented using combinational logic. The specific implementation method of combinational logic technology is an existing method and will not be described further here.

[0171] As one embodiment, steps F2, F3, and F4 can each be executed serially within a preset clock cycle. Each of steps F2, F3, and F4 is equipped with a separate hardware unit, which helps improve the GPU chip's operating frequency and execution performance. In this embodiment, steps F2, F3, and F4 can specifically transmit information over three consecutive clock cycles. The information transmission can be implemented using registers; the technical details of using registers are existing technology and will not be described further here.

[0172] As one embodiment, in step F3, the sampling from 0 to N-1 includes:

[0173] Step F31: First, exclude the preset exclusion values ​​from 0 to N-1, and then sample W k values. The preset exclusion values ​​include values ​​where the probability of hitting the number of consecutive resources required by the task group is less than or equal to a preset probability threshold.

[0174] Specifically, the preset exclusion value may include prime numbers from 0 to N-1.

[0175] As one embodiment, step F43 includes:

[0176] Step F431, {SAR k0 SAR k1 , ...SAR k(w-1) The sampled sequence is compared with a pre-configured third mapping table, and the current maximum number of consecutive resource blocks of the resource to be queried is output. The third mapping table is used to store the mapping relationship between the sampled sequence and the maximum number of consecutive resource blocks.

[0177] Understandably, once the preset direction, occupied flag, and unoccupied flag are determined, the third mapping table is also set based on this configuration.

[0178] As one embodiment, step F43 includes:

[0179] Step F432, in {SAR k0 SAR k1 , ...SAR k(w-1) From SAR k(w-1) Start reading backwards to identify the first SAR value equal to 1. k The value of k is denoted as k';

[0180] Step F433: Determine k'+1 as the current maximum number of contiguous resource blocks of the resource to be checked.

[0181] Compared to Example 4, Example 6 reduces the number of AND operations through k-value sampling, further reducing the number of subsequent OR operations, thereby reducing the amount of hardware required and decreasing the area and power consumption of the GPU chip. Compared to Example 5, the final maximum number of resources is not limited to multiples of N / Z; sampling can be performed according to specific application requirements, providing flexibility.

[0182] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.

[0183] Example 7

[0184] A GPU execution module typically includes various types of resources, each with contiguous allocation requirements, and the number of resource blocks may vary. On one hand, setting up a separate hardware unit for each type of resource to acquire the largest contiguous resource block would result in complex GPU hardware units and a large footprint. On the other hand, after distributing a group of tasks, the GPU needs time to execute the distributed tasks. Therefore, Embodiment Seven proposes a time-sharing approach where each execution unit can share a single hardware unit for acquiring the largest contiguous resource block. This satisfies the computational requirements for the largest contiguous resource block while reducing the number of hardware units required on the GPU, thereby reducing GPU area and power consumption.

[0185] A method for obtaining the largest contiguous resource block in a GPU based on time-division multiplexing includes the following steps:

[0186] Step G1: Set the number of time periods C required to acquire the largest contiguous resource block in each round, configure at least one resource type identifier for each time period, and initialize c = 1;

[0187] In each period, the total number of resource blocks of all resource types is less than or equal to A, and A is greater than or equal to the maximum number of resource blocks of all resource types.

[0188] Step G2: Obtain the current resource status sequence corresponding to each type of resource identifier in the c-th time period, divide the shared hardware unit into Rc groups, where Rc is the number of resource type identifiers in the c-th time period, and store each current resource status sequence into the corresponding shared hardware unit group.

[0189] Step G3: In the c-th time period, the maximum contiguous resource block acquisition operation is performed in parallel on the Rc current resource state sequences based on the shared hardware unit to obtain the maximum number of resource blocks corresponding to each resource type identifier in the c-th time period.

[0190] Step G4: Determine if c is equal to C. If it is, end the acquisition operation of the largest contiguous resource block in this round. Otherwise, set c = c + 1 and return to step G2.

[0191] As one embodiment, if Rc equals 1, in step G3, there is only one corresponding current resource state sequence in the shared hardware unit. The current resource state sequence in the shared hardware unit is used as S0 in any of Embodiments 4, 5, or 6 to perform the corresponding maximum contiguous resource block acquisition operation. That is, when there is only one corresponding current resource state sequence in the shared hardware unit, the maximum number of contiguous resource blocks is acquired for only one resource type within a time period. When there are multiple corresponding current resource state sequences in the shared hardware unit, the maximum number of contiguous resource blocks is acquired simultaneously for multiple resource types within the same time period. The time period may include one or more clock cycles.

[0192] As one embodiment, if Rc is greater than or equal to 2, step G3 includes:

[0193] Step G31: Divide the shared hardware unit into Rc groups, and store each current resource state sequence into the corresponding shared hardware unit group to obtain the sequence D0 = {Q1, Q2, ... Q}. Rc}, where Q r Let r be the current resource state sequence corresponding to the r-th group, where r ranges from 1 to Rc.

[0194] Step G32: Obtain D1, D2, ... D in parallel. E Among them, D e To shift D0 by e positions in a preset direction, and simultaneously move each Q... r The tail of e consecutive bits along the preset direction is set as the state sequence generated by the occupied identifier. The value of e ranges from 0 to E-1, where E is the maximum number of bits in the shared hardware unit.

[0195] The step of moving e positions in the preset direction includes moving e positions to the left or to the right in the preset direction.

[0196] Step G33: Parallel acquisition of D0 to D e The result of performing a bitwise AND or bitwise OR operation is DA. e DA e ={DQ e1 DQ e2 ...DQ eRc}, where DQ er The result of the bitwise AND or bitwise OR operation corresponding to the r-th group;

[0197] Step G34, transfer each DQ er Perform an OR operation or a AND operation followed by a NOT operation to determine the current maximum number of contiguous resource blocks for the resource type corresponding to the r-th group.

[0198] As one embodiment, step G34 includes:

[0199] Step G341, transfer each DQ er Perform an OR operation or a AND operation followed by a NOT operation to obtain the DQR. er ;

[0200] Step G342, based on all DQRs er Generate the first test sequence {DQR} corresponding to the r-th group. 0r DQR 1r ...DQR (E-1)r};

[0201] Step G343, based on {DQR 0r DQR 1r ...DQR (E-1)r Determine the current maximum number of contiguous resource blocks for the resource type corresponding to the r-th group.

[0202] Step G343 includes:

[0203] Step G3431, in {DQR 0r DQR 1r ...DQR (E-1)r From DQR (E-1)r Start reading backwards to determine the first DQR that equals 1. er The value of e is denoted as e';

[0204] In step G3432, e'+1 is determined as the current maximum number of consecutive resource blocks of the resource type corresponding to the r-th group.

[0205] As an example, the status identifier includes an occupied identifier and an unoccupied identifier. The occupied identifier is 0, and the unoccupied identifier is 1. In step G33, a bitwise AND operation is performed, and in steps G34 and G341, a self-OR operation is performed; or, the occupied identifier is 1, and the unoccupied identifier is 0. In step G33, a bitwise OR operation is performed, and in steps G34 and G341, a self-AND followed by a NOT operation is performed.

[0206] As one embodiment, step G343 includes:

[0207] Step G3433, determine {DQR} 0r DQR 1r ...DQR (E-1)r} Check if the number of bits is less than E. If it is less, then check in DQR. (E-1)r Insert the occupied flag, so that the padded {DQR} 0r DQR 1r ...DQR (E-1)rThe total number of bits in the sequence is E, which serves as the second sequence to be tested.

[0208] Step G3434: Compare the second test sequence with the pre-configured fourth mapping table, and output the current maximum number of consecutive resource blocks for the resource type corresponding to the r-th group. The fourth mapping table is used to store the mapping relationship between the second test sequence and the maximum number of consecutive resource blocks. The number of bits for the second test sequence is E.

[0209] Embodiment 7 enables time-division multiplexing of the hardware unit in the execution module that acquires the largest contiguous resource block, and allows simultaneous acquisition of the corresponding largest contiguous resource from multiple groups of resources within the same time period. This reduces the number of hardware units for acquiring the largest contiguous resource block in the execution module, thereby reducing the GPU's area and power consumption.

[0210] The following is a specific example to further illustrate this:

[0211] For ease of explanation, we will use the reuse of hardware units for the largest contiguous resource block as an example, considering three types of resources. In this embodiment, the first resource has a total of 128 resource blocks, the second resource has a total of 64 resource blocks, and the third resource has a total of 48 resource blocks. To meet the sharing requirements, the maximum number of bits in the shared hardware unit is 128 (1 indicates an unoccupied flag, and 0 indicates an occupied flag). I0 represents the current resource status sequence corresponding to the current time period, which is stored in the corresponding shared hardware unit group, divided into high and low parts I0. H and I L Each part occupies half, or 64 bits.

[0212] In this embodiment, the first time period of the shared hardware unit is the maximum number of consecutive resource blocks to be searched for the first resource. The search steps are shown in the following block diagram; Figure 1 This represents 128 possible right shifts from 0 bits to 127 bits. (Box) Figure 2 For the current sequence, perform a logical AND operation with the sequence shifted right by 1 bit, then perform a logical AND operation with the sequence shifted right by 2 bits, and so on, until the result of the logical AND operation with the sequence shifted right by 127 bits is obtained. Then, perform a self-OR operation on the result of each logical AND operation, and then search for the sequence number corresponding to the first sequence with a result of 1 from the last self-ORed sequence. Adding 1 to this sequence number yields the maximum number of resource blocks for the first resource. To facilitate the explanation of the multiplexing of shared hardware units for the second and third resources within the same time period, the following method can also be used to find the first resource: [framework omitted]. Figure 3 and frame Figure 4 In the statistics box respectively Figure 2 The logical result in the OR logic case is statistically analyzed in two parts: the high 64 bits and the low 64 bits. The result is denoted by S. The final result is assumed to be S. Li |SHi =1 (that is, S) Li and S Hi If any one of them is 1, then the maximum contiguous free space size is not less than (i+1), according to S. L127 |S H127 Start the calculation and find the first (i+1) with a result of 1, which corresponds to the maximum contiguous free space size.

[0213] The shared hardware unit searches for the maximum contiguous free space size for both Type II and Type III resources during the second time period. The search steps are shown in the following flowchart. Figure 5 There are 128 possible right shifts from 0 bits to 127 bits. M can be prepared in advance according to the previous definition. M(i) represents a 128-bit sequence where all bits except the i-th bit are 1. For example, M(0) means all bits except the lowest bit are 1, i.e., M(0) = 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_fffe; another example is M(0,1) = 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_fffc. Then, a box is used... Figure 2 ,box Figure 3 ,box Figure 4 Perform the response calculations using the exact same method as in the first cycle; the final results are then viewed in S. Li and S Hi, S Li If the value is 1, then the size of the second type of maximum contiguous free space is not less than (i+1), according to S. L63 The calculation begins by finding the first (i+1) element with a result of 1, which corresponds to the second type of maximum contiguous free space size; S Hi If the value is 1, then the maximum contiguous free space size of the third type is not less than (i+1), according to S. H63 Start the calculation and find the first (i+1) with a result of 1, which corresponds to the maximum contiguous free space size of the third type.

[0214] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.

[0215] Example 8

[0216] The fundamental principles and characteristics of GPUs lie in GPU resource balancing and synchronized resource allocation. Completion is largely synchronous. For execution modules, multiple task groups are processed continuously. Ensuring that each task group is allocated as evenly as possible across multiple execution units, and ensuring overall resource balance across multiple execution modules processing multiple task groups, is key to achieving balanced GPU resource allocation, improving GPU resource utilization, and reducing power consumption. Example 8 proposes a GPU resource scheduling method to address this problem.

[0217] A GPU resource scheduling method, comprising:

[0218] Step H1: Obtain the task group to be assigned and read the number of tasks to be assigned. The tasks to be assigned are the tasks that need to be balanced and distributed to the execution units of the execution module. The execution module includes Q execution units.

[0219] Step H2: Determine the initial allocation combination sequence corresponding to the number of tasks to be allocated based on the task number partitioning table. The task number partitioning table is used to store the mapping relationship between the number of allocated tasks and the initial allocation combination sequence.

[0220] The initial allocation combination is a balanced allocation combination when the execution module has not been assigned any tasks.

[0221] Step H3: Obtain the preset pointer information in the execution module, determine the cyclic shift number Su based on the pointer information, and cyclically shift the initial allocation combination sequence Su positions in a preset direction to obtain the target allocation combination information;

[0222] Step H4: Match the GPU resources of the execution module based on the target allocation combination information corresponding to the task group to be distributed.

[0223] It should be noted that if tasks are always assigned to each execution module according to the initial allocation combination, it will inevitably lead to some execution modules having a larger assigned task load than others, thus hindering the balance of task allocation and resource scheduling. This application addresses this by setting pointer information to record the task allocation information of each execution module in the previous round. Based on this, the target allocation combination information for the current round is adjusted, thereby ensuring that each execution module achieves a balance between task allocation and resource scheduling as much as possible in multiple rounds of task allocation execution.

[0224] As one embodiment, the method further includes step H10, constructing a task number partitioning table, including:

[0225] Step H101: Set the sequence number identifiers corresponding to Q execution units from 0 to Q-1 along the preset direction, initialize the number of tasks WX = 1, and initialize the initial allocation combination as {qx0, qx1, ... qx}. Q-1Each bit in} is 0, qx t is the number of tasks assigned to the t-th execution unit, where t ranges from 0 to Q - 1;

[0226] Step H102, obtain the quotient Wy and the remainder Wz of WX divided by Q. If t < Wz, then set qx t = Wy + 1. If t ≥ Wz, then set qx t = Wy. Based on all qx t generate the corresponding initial allocation combination {qx0, qx1, … qx Q-1};

[0227] Step H103, determine whether WX is equal to Q * L, where L is the maximum number of tasks that each execution unit can execute. If so, generate the task number segmentation table based on the mapping relationship between all WX and the corresponding initial allocation combinations. Otherwise, set WX = WX + 1, and return to execute Step H102.

[0228] By Steps H101 - H103, the task number segmentation table can be constructed, and the initial allocation combination corresponding to each execution module can be obtained. Subsequently, it can be adjusted in combination with pointer information to obtain the target allocation combination. It should be noted that the hardware resource layout of each execution module is the same. Therefore, multiple execution modules can share the same task number segmentation table. To ensure parallel execution of multiple task channels, a task number segmentation table can be set for each task channel, and the pointer information of each execution module is stored in the execution module.

[0229] As an embodiment,

[0230] The cyclic shift number Su is determined based on the execution unit identifier t1' pointed to by the pointer in the previous round and the task number WX2' in this round.

[0231] The preset pointer is the tail pointer. The target of the preset pointer in this round points to the t-th execution unit, where t is the remainder of (t1' + WX2') divided by Q. When the remainder is 0, t = t1'. The tail pointer initially points to the 0-th execution unit. Then in Step H3, Su = t + 1.

[0232] As an embodiment, the preset pointer is the head pointer. The target of the preset pointer in this round points to the t-th execution unit, where t is the remainder of (t1' + 1 + WX2') divided by Q. When the remainder is 0, t = t1'. The head pointer initially points to the 0-th execution unit. Then in Step H3, Su = t.

[0233] As one embodiment, the method further includes H5: if the remaining resources in the execution module match the target allocation combination information of the task group to be distributed, and the execution module is selected as the target execution module, then the preset pointer is updated to point to the t-th execution unit. That is, after obtaining the target allocation combination information, resource matching judgment and execution module selection operations are still required. Only the execution module that is ultimately selected as the target execution module to execute this round of task distribution and task execution needs to update the corresponding pointer information.

[0234] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.

[0235] Example 8 can ensure that each task group is distributed to multiple execution units as evenly as possible, and ensure that multiple execution modules continuously process multiple task groups with overall resource balance, thereby achieving GPU resource allocation balance, improving GPU resource utilization and reducing power consumption.

[0236] Example 9

[0237] In a GPU architecture, there are typically P execution modules. For the same group of tasks to be distributed, there may be multiple target execution modules with remaining resources matching their resource requirements. Existing technologies typically use round-robin scheduling algorithms to select the target execution module from multiple eligible execution units. However, this method does not consider the remaining resources in each execution unit, and therefore cannot guarantee a balanced allocation of GPU resources. Based on this, the present invention proposes Embodiment Nine.

[0238] A GPU resource scheduling method, comprising:

[0239] Step I1: Obtain the list of candidate execution modules {AP1, AP2, ... AP1} F},AP f Let f be the f-th candidate execution module, where f ranges from 1 to F, and F is the total number of candidate execution modules. A candidate execution module is the execution module whose current remaining resource information matches the resource requirement information of the target task group.

[0240] The candidate execution module is the execution module whose current remaining resource information matches the resource requirement information of the target task group. The GPU resources include a first category of resources with continuous allocation requirements and a second category of resources without continuous allocation requirements. The current remaining resource information includes the maximum number of consecutive remaining resources corresponding to each type of first-category resource and the maximum number of remaining resources corresponding to each type of second-category resource.

[0241] Step I2: Obtain AP f The current remaining resource quantity R of the h-th resource. h and the weight a of the pre-stored h-th resource h The value of h ranges from 1 to H, where H is the total number of resource types in the execution module;

[0242] Step I3, based on R h and a h Get AP f The current total weight of remaining resources Ta f :

[0243]

[0244] Step I4: Obtain the largest value, Ta. f The corresponding f value is taken as fx, the fx-th candidate execution module is determined as the target execution module, and the target task group is distributed to the target execution module.

[0245] It should be noted that the larger the total weight of the remaining resources, the more resources the execution module has. Therefore, identifying this module as the target execution module can balance the resource utilization of each execution unit of the GPU and reduce power consumption.

[0246] As one embodiment, the method further includes: step I10, obtaining the weight 'a' corresponding to each type of resource in the execution module. h Specifically, it includes:

[0247] Step I101: Send MA test tasks that only require the h-th resource to the execution module under test, execute the test tasks, and obtain the power consumption value ax corresponding to the h-th resource. h ;

[0248] It should be noted that by setting up the corresponding upper-level test program, the test task that only requires the h-th resource can be sent to the GPU. This can be achieved directly using existing technology and will not be elaborated on here.

[0249] Step I102: Set the weight value of each resource based on its power consumption value, and calculate the weight of all resources using the ax-value. h The proportional relationship with a h The proportional relationship is the same for all a. h Stored in each execution module.

[0250] As one embodiment, the GPU includes P execution modules, and step I10 further includes:

[0251] Step I100: Randomly select one of the P execution modules as the execution module to be tested, and shut down the other execution modules.

[0252] It should be noted that since each execution module has the same hardware resource configuration, the weight 'a' can be determined by testing using only one execution module. h .

[0253] As one embodiment, step I2, obtaining AP f The current remaining resource quantity R of the h-th resource. h include:

[0254] Step I21: Read the current remaining resource quantity R from the preset counting unit corresponding to each h-th resource. h .

[0255] As one embodiment, a preset counting unit for each h-th resource is set in the execution module, and the preset counting unit is used to store the current remaining resource quantity R. h R h Initialize to the total number of resources at the h-th level. For each resource at the h-th level allocated, then R... h Subtract 1, and for each h-th resource released, R will be... h Add 1.

[0256] As one embodiment, step I2, obtaining AP f The current remaining resource quantity R of the h-th resource. h If the h-th resource is a first-type resource for which the largest contiguous resource block needs to be acquired, the number of the largest contiguous resource blocks can also be obtained through any one of the methods in Embodiments 4, 5, and 6, and used as the corresponding R. h The value will not be elaborated upon here.

[0257] Example 9 can select the target execution module based on the current remaining resources of each candidate execution module, which is real-time, so that all execution modules are in a stable state and the power consumption is relatively uniform, so that all GPU resources are balanced as much as possible and resource waste is avoided.

[0258] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.

[0259] Example 10

[0260] Once the target task is assigned to the corresponding execution unit in the target execution module, the execution unit will retrieve the corresponding execution instructions for execution. Embodiment 10 proposes a method for selecting the target execution module based on the execution status of the execution instructions. Compared with Embodiment 9, it can obtain the current resource utilization status of each execution module in a more granular manner, thereby further improving the balance of GPU resource scheduling.

[0261] A GPU resource scheduling method, comprising:

[0262] Step J1: Obtain the candidate execution module list {AP1, AP2, ... AP... F},AP f Let f be the f-th candidate execution module, where f ranges from 1 to F, and F is the total number of candidate execution modules;

[0263] Among them, the candidate execution module is the execution module whose current remaining resource information matches the resource requirement information of the target task group.

[0264] Step J2: Obtain the AP data within the current preset NX historical clock cycles. f The number of instructions C executed s Obtain the weight B of the pre-stored instruction s. s ;

[0265] Step J3, based on C s and B s Get AP f Total power consumption Tb over the current preset NX historical clock cycles f :

[0266]

[0267] Step J4: Obtain the smallest value of Tb f The corresponding f value is taken as fx, the fx-th candidate execution module is determined as the target execution module, and the target task group is distributed to the target execution module.

[0268] It should be noted that the total power consumption Tb of the execution module over the past NX historical clock cycles is... f The smaller the value, the more remaining resources the execution module has. Therefore, Tb... f The minimum execution module is determined as the target execution module, thereby improving GPU resource utilization and reducing power consumption.

[0269] As an example, the instructions include instruction categories such as data transfer instructions, read storage instructions, write storage instructions, matrix operation instructions, comparison instructions, and jump instructions. Among them, matrix operation instructions can be further classified according to the matrix size. Each instruction category can include multiple different execution instructions. In step J2, the number of executions of each instruction within NX historical clock cycles is counted, which improves the accuracy of resource prediction and thus improves the balance of GPU resource allocation.

[0270] As one embodiment, in step J1, obtaining the candidate execution module list includes:

[0271] Step J11: Obtain the resource requirements information of the task group to be distributed;

[0272] Step J12: Obtain the current remaining resource information for each execution module in the current GPU;

[0273] Step J13: Match the resource requirement information of the task group to be distributed with the current remaining resource information of all execution modules, and add the successfully matched execution modules to the execution module list.

[0274] As one embodiment, the method further includes: step J10, obtaining the weight B corresponding to each type of instruction in the execution module. s Specifically, it includes:

[0275] Step J101: Send a test task to the execution module under test that only requires calling NA s-th instructions, execute the test task, and obtain the power consumption value BX for executing NA s-th instructions. s ;

[0276] It should be noted that the test task can be issued to the GPU with NA s instructions by setting up the corresponding upper-level test program. This can be achieved directly using existing technology and will not be elaborated on here.

[0277] Step J102: Set the weight value for each type of instruction based on the power consumption value of each type of instruction, and set the weight value for all instructions' BX. s The proportional relationship with B s The proportional relationship is the same, so all B s Stored in each execution module.

[0278] As one example, NX is an integer power of 2. NX is directly proportional to statistical balance and inversely proportional to prediction accuracy. That is, the larger the NX value, the better the balance of the statistical results. The larger the NX value, the longer the time between the longest statistical point and the current time point, and the lower the prediction accuracy. Therefore, the NX value can be set according to the specific application requirements. As an example, the value of NX can be set to 1024.

[0279] As one embodiment, step J10 further includes:

[0280] Step J100: Randomly select one of the P execution modules as the execution module to be tested, and shut down the other execution modules;

[0281] It should be noted that since each execution module has the same hardware resource configuration, the weight B can be determined by testing using only one execution module. s .

[0282] Example 10 selects the target execution module based on the historical resource usage of each candidate execution module, providing more granular statistical analysis than Example 9. This ensures all execution modules remain in a stable state with even heat distribution, balancing GPU resources as much as possible and avoiding resource waste. However, it is understood that Examples 10 and 9 can be combined and assigned corresponding weights for a comprehensive selection of the target execution module, which will not be elaborated upon here.

[0283] It should be noted that the relevant technical details in the preceding embodiments and other subsequent embodiments can also be applied to the relevant steps in this embodiment, and will not be repeated here.

[0284] It should be noted that in the embodiments of the present invention, some exemplary embodiments are described as processes or methods depicted as flowcharts. The numbering of the steps does not imply a limitation on the order of execution of the steps. Unless specifically specified, those skilled in the art will understand that although the embodiments of the present invention describe the steps as sequential processes, some steps may be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. The process may be terminated when its operation is complete, but may also have additional steps not included in the figures. A process may correspond to a method, function, procedure, subroutine, subroutine, etc.

[0285] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for obtaining the largest contiguous resource block in a GPU based on time-division multiplexing. Its features are, Includes the following steps: Step G1: Set the number of time periods C required to acquire the largest contiguous resource block in each round, configure at least one resource type identifier for each time period, and initialize c=1. Step G2: Obtain the current resource status sequence corresponding to each type of resource identifier in the c-th time period, divide the shared hardware unit into Rc groups, where Rc is the number of resource type identifiers in the c-th time period, and store each current resource status sequence into the corresponding shared hardware unit group. Step G3: In the c-th time period, the maximum contiguous resource block acquisition operation is performed in parallel on the Rc current resource state sequences based on the shared hardware unit to obtain the maximum number of resource blocks corresponding to each resource type identifier in the c-th time period. Step G4: Determine if c is equal to C. If they are equal, end the acquisition of the largest contiguous resource block in this round. Otherwise, set c = c + 1 and return to step G2.

2. The method according to claim 1, characterized in that, The total number of resource blocks of all resource types corresponding to each time period is less than or equal to A, and A is greater than or equal to the maximum number of resource blocks of all resource types.

3. The method according to claim 1, characterized in that, If Rc is greater than or equal to 2, step G3 includes: Step G31: Divide the shared hardware unit into Rc groups, and store each current resource state sequence into the corresponding shared hardware unit group to obtain the sequence D0={Q1, Q2, ..., Q...} r Q Rc }, where Q r Let r be the current resource state sequence corresponding to the r-th group, where r ranges from 1 to Rc. Step G32: Obtain D1, D2, ..., D in parallel. e D E Among them, D e To shift D0 in the preset direction by e positions, and simultaneously move each Q... r The tail of e consecutive bits along the preset direction is set as the state sequence generated by the occupied identifier. The value of e ranges from 0 to E-1, where E is the maximum number of bits in the shared hardware unit. Step G33: Parallel acquisition of D0 to D e The result of performing a bitwise AND or bitwise OR operation is DA. e DA e ={DQ e1 DQ e2 DQ er DQ eRc }, where DQ er The result of the bitwise AND or bitwise OR operation corresponding to the r-th group; Step G34, transfer each DQ er Perform an OR operation or a AND operation followed by a NOT operation to determine the current maximum number of contiguous resource blocks for the resource type corresponding to the r-th group.

4. The method according to claim 3, characterized in that... The movement of e positions in the preset direction includes moving e positions to the left or to the right in the preset direction.

5. The method according to claim 3, characterized in that, Step G34 includes: Step G341, transfer each DQ er Perform an OR operation or a AND operation followed by a NOT operation to obtain the DQR. er ; Step G342, based on all DQRs er Generate the first test sequence {DQR} corresponding to the r-th group. 0r DQR 1r ...DQR （E-1）r }; Step G343, based on {DQR 0r DQR 1r ...DQR （E-1）r Determine the current maximum number of contiguous resource blocks for the resource type corresponding to the r-th group.

6. The method according to claim 5, characterized in that, Step G343 includes: Step G3431, in {DQR 0r DQR 1r ...DQR （E-1）r From DQR （E-1）r Start reading backwards to determine the first DQR that equals 1. er The value of e is denoted as e ， ; Step G3432, e ， +1 is determined as the current maximum number of contiguous resource blocks for the resource type corresponding to the r-th group.

7. The method according to claim 5, characterized in that, Step G343 includes: Step G3433, determine {DQR} 0r DQR 1r ...DQR （E-1）r } Check if the number of bits is less than E. If it is less, then check in DQR. （E-1）r Insert the occupied flag, so that the padded {DQR} 0r DQR 1r ...DQR （E-1）r The total number of bits in the sequence is E, which serves as the second sequence to be tested. Step G3434: Compare the second test sequence with the pre-configured fourth mapping table, and output the current maximum number of consecutive resource blocks for the resource type corresponding to the r-th group. The fourth mapping table is used to store the mapping relationship between the second test sequence and the maximum number of consecutive resource blocks. The number of bits for the second test sequence is E.

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