Gate driving circuit and control method thereof, display panel and electronic device
By dividing the display panel into refresh areas and adjusting the refresh rate, the power consumption and heat generation problems caused by the increased number of timing signal pulses in the gate drive circuit are solved, thereby reducing power consumption and heat generation while maintaining display quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HKC CORP LTD
- Filing Date
- 2023-03-31
- Publication Date
- 2026-05-01
AI Technical Summary
As the resolution and refresh rate of display panels increase, the number of timing signal pulses required by the gate drive circuit increases, leading to power consumption and heat generation issues, which affect the lifespan of electronic components and display performance.
The display panel is divided into a first refresh area and a second refresh area along the line-by-line scanning direction of the gate drive circuit, and different refresh rates are controlled. The scanning signal is generated through the GOA unit to reduce the number of timing signal pulses, thereby reducing power consumption and heat generation.
By adjusting the refresh rate and area division, the number of timing signal pulses in the gate drive circuit is reduced, thereby lowering power consumption and heat generation while maintaining display quality.
Smart Images
Figure CN116453483B_ABST
Abstract
Description
Gate driving circuit and its control method, display panel and electronic equipment Technical Field
[0001] This application relates to the field of display technology, and in particular to a gate driving circuit and its control method, a display panel, and an electronic device. Background Technology
[0002] Display technology has always been one of the important research directions in electronic devices. The current mainstream display technologies are Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED). Both LCD and OLED technologies use Gate Driver Less (GDL) circuits to provide scanning signals and realize the line-by-line scanning function of the pixel circuits in the display panel.
[0003] Since GDL is a scanning signal generated based on timing signal pulses, as the resolution and refresh rate of the display panel increase, the number of timing signal pulses required by GDL also increases. Each timing signal pulse generates a certain current pulse, thus increasing the power consumption and heat generation, which affects the lifespan of electronic components and the display effect of the display panel. Summary of the Invention
[0004] This application discloses a gate drive circuit that can solve the technical problem of increasing power consumption and heat generation due to the increasing number of timing signal pulses required by GDL.
[0005] In a first aspect, this application provides a gate driving circuit applied to a display panel, the display panel including a plurality of pixel circuits arranged in an array, the gate driving circuit including n cascaded GOA units, wherein each GOA unit is used to generate a corresponding scan signal to drive the pixel circuit of a corresponding row to turn on, the display panel having a first refresh area and a second refresh area along the line-by-line scanning direction of the gate driving circuit, the pixel circuit disposed in the first refresh area being turned on at a first refresh rate under the drive of the GOA unit, the pixel circuit disposed in the second refresh area being turned on at a second refresh rate under the drive of the GOA unit, wherein the first refresh rate and the second refresh rate are different;
[0006] During the time when the display panel displays X frames, the pixel circuit located in the first refresh area is used to enable frame A time ta under the drive of the GOA unit, and the pixel circuit located in the second refresh area is used to enable frame B time tb under the drive of the GOA unit, wherein the starting frames of frame A and frame B are the same, and tb is less than ta.
[0007] By dividing the display panel into a first refresh area and a second refresh area along the line-by-line scanning direction of the gate driving circuit, and controlling the first refresh rate and the second refresh rate to be different, the number of timing signal pulses required by a portion of the GOA units to generate the scan signal is reduced, thereby reducing the corresponding power consumption and heat generation.
[0008] Optionally, when n is greater than 5, all GOA units from the 5th level to the nth level are used to receive the start signal and the reset signal. The GOA unit is used to generate the scan signal with a first level under the control of the start signal, and to generate the scan signal with a second level under the control of the reset signal.
[0009] Optionally, each of the first to fourth level GOA units includes a first transistor, a second transistor, a third transistor, a fourth transistor, a pull-down unit, and a capacitor. The gate of the first transistor is electrically connected to the first electrode of the first transistor and is used to receive the start signal. The second electrode of the first transistor is electrically connected to one end of the capacitor, the gate of the second transistor, and the first electrode of the third transistor. The first electrode of the second transistor is electrically connected to the other end of the capacitor and is used to receive the timing signal CLK(N). The second electrode of the second transistor is electrically connected to the first electrode of the fourth transistor and is used to output the scan signal G(N). The gate of the third transistor is electrically connected to the pull-down unit and the gate of the fourth transistor and is used to receive the scan signal G(N+4). The second electrode of the third transistor is electrically connected to the second electrode of the fourth transistor and is used to receive a first voltage signal. The pull-down unit is used to receive a second voltage signal and generate a pull-down signal according to the second voltage signal.
[0010] Optionally, when n is greater than 9, each of the 5th to N-4th level GOA units includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a pull-down unit, and a capacitor. The gate of the first transistor is electrically connected to the first electrode of the first transistor and is used to receive the scan signal G(N-4). The second electrode of the first transistor is electrically connected to the second electrode of the fifth transistor, one end of the capacitor, the gate of the second transistor, and the first electrode of the third transistor. The first electrode of the second transistor is electrically connected to the other end of the capacitor and is used to receive the timing signal CLK(N). The second electrode of the second transistor is electrically connected to the first electrode of the fourth transistor and is used to output the scan signal G(N). The gate of the third transistor is electrically connected to the pull-down unit and the gate of the fourth transistor and is used to receive the reset signal and the scan signal G(N+4). The second electrode of the third transistor is electrically connected to the second electrode of the fourth transistor and is used to receive a first voltage signal. The pull-down unit is used to receive a second voltage signal and generate a pull-down signal according to the second voltage signal.
[0011] Optionally, when n is greater than 9, each of the (N-3)th to Nth level GOA units includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a pull-down unit, and a capacitor. The gate of the first transistor is electrically connected to the first electrode of the first transistor and is used to receive the scan signal G(N-4). The second electrode of the first transistor is electrically connected to the second electrode of the fifth transistor, one end of the capacitor, the gate of the second transistor, and the first electrode of the third transistor. The first electrode of the second transistor is electrically connected to the other end of the capacitor and is used to receive the timing signal CLK(N). The second electrode of the second transistor is electrically connected to the first electrode of the fourth transistor and is used to output the scan signal G(N). The gate of the third transistor is electrically connected to the pull-down unit and the gate of the fourth transistor and is used to receive the reset signal. The second electrode of the third transistor is electrically connected to the second electrode of the fourth transistor and is used to receive a first voltage signal. The pull-down unit is used to receive a second voltage signal and generate a pull-down signal according to the second voltage signal.
[0012] Optionally, the first refresh area and the second refresh area are connected, and the number of GOA units used to drive the pixel circuit of the first refresh area is less than the number of GOA units used to drive the pixel circuit of the second refresh area.
[0013] Secondly, this application also provides a control method for a gate driving circuit, applied to the gate driving circuit as described in the first aspect, the control method for the gate driving circuit comprising:
[0014] Obtain the X-frame display of the display panel;
[0015] The pixel circuit located in the first refresh area is driven to start A-frame time ta;
[0016] The pixel circuit in the second refresh area is driven to start A-frame time tb;
[0017] In this case, frames A and B have the same starting frame, and tb is less than ta.
[0018] Thirdly, this application also provides a display panel, the display panel including pixel circuits, data driving circuits and gate driving circuits as described in the first aspect, the pixel circuits being distributed in an array, the pixel circuits being turned on under the control of the scan signal generated by the gate driving circuit, the data driving circuits being used to generate data signals and to charge the pixel circuits turned on under the control of the scan signal generated by the gate driving circuit, so as to realize the display function of the display panel.
[0019] Optionally, during the time ta when the display panel displays frame A, the data signal generated by the data driving circuit is used to charge the pixel circuit disposed in the first refresh area, and during the time tb when the display panel displays frame B, the data signal generated by the data driving circuit is used to charge the pixel circuit disposed in the first refresh area and the second refresh area.
[0020] Fourthly, this application also provides an electronic device, the electronic device including a housing and a display panel as described in the second aspect, the housing being used to support the display panel. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0022] Figure 1 is a schematic diagram of the gate drive circuit framework provided in one embodiment of this application.
[0023] Figure 2 is a schematic diagram of a possible timing signal waveform provided in one embodiment of this application.
[0024] Figure 3 is a schematic diagram of the refresh area of the display panel provided in one embodiment of this application.
[0025] Figure 4 is a schematic diagram of the timing signal waveform of the first refresh area provided in an embodiment of this application.
[0026] Figure 5 is a schematic diagram of the GOA unit circuit provided in one embodiment of this application.
[0027] Figure 6 is a schematic diagram of the GOA unit circuit provided in another embodiment of this application.
[0028] Figure 7 is a schematic diagram of the GOA unit circuit provided in another embodiment of this application.
[0029] Figure 8 is a schematic flowchart of the control method for the gate drive circuit provided in one embodiment of this application.
[0030] Figure 9 is a schematic diagram of a display panel frame provided in one embodiment of this application.
[0031] Figure 10 is a top view schematic diagram of an electronic device provided in one embodiment of this application.
[0032] Explanation of reference numerals: Scan signal - G(N), Start signal - STV, Reset signal - RST, Timing signal - CLK(N), First voltage signal - VSS, Second voltage signal - VDD, Gate - g, First electrode - s, Second electrode - d, Gate drive circuit - 1, GOA unit - 11, First transistor - T1, Second transistor - T2, Third transistor - T3, Fourth transistor - T4, Fifth transistor - T5, Pull-down unit - 111, Capacitor - C(N), Display panel - 2, Pixel circuit - 21, First refresh area - 22, Second refresh area - 23, Data drive circuit - 24, Electronic device - 3, Housing - 31. Detailed Implementation
[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0034] This application provides a gate driving circuit 1 applied to a display panel 2. Please refer to Figure 1, which is a schematic diagram of the gate driving circuit framework provided in one embodiment of this application. The display panel 2 includes a plurality of pixel circuits 21 arranged in an array. The gate driving circuit 1 includes n-level cascaded array substrate row driving (GOA) units 11, wherein each level of the GOA unit 11 is used to generate a corresponding scan signal G(N) to drive the pixel circuit 21 of the corresponding row to turn on. Along the row-by-row scanning direction of the gate driving circuit 1, the display panel 2 has a first refresh area 22 and a second refresh area 23. The pixel circuits 21 disposed in the first refresh area 22 are used to turn on at a first refresh rate under the drive of the GOA unit 11, and the pixel circuits 21 disposed in the second refresh area 23 are used to turn on at a second refresh rate under the drive of the GOA unit 11, wherein the first refresh rate and the second refresh rate are different.
[0035] During the time when the display panel 2 displays X frames, the pixel circuit 21 located in the first refresh area 22 is used to enable the A frame time ta under the drive of the GOA unit 11, and the pixel circuit 21 located in the second refresh area 23 is used to enable the B frame time tb under the drive of the GOA unit 11, wherein the starting frames of the A frame and the B frame are the same, and tb is less than ta.
[0036] It should be noted that the pixel circuit 21 typically includes transistors and pixel units electrically connected to the transistors. A certain level of the GOA unit 11 is electrically connected to the transistors in a certain row of the pixel circuit 21. The GOA unit 11 driving the pixel circuit 21 to turn on means that the transistors are turned on under the control of the scan signal G(N), thereby transmitting the data signal to the pixel unit through the transistor to charge the pixel unit.
[0037] Specifically, the GOA unit 11 is typically used to generate the scan signal G(N) based on the pulse of the timing signal CLK(N), the start signal STV, the reset signal RST, the first voltage signal VSS, and the second voltage signal VDD. In this embodiment, the pulse of the timing signal CLK(N) refers to a rising edge in the waveform of the timing signal CLK(N), the start signal STV refers to the signal that starts refreshing the display of a new frame, and the reset signal RST refers to the signal that interrupts the signal transmission between different levels of the GOA unit 11. Please also refer to Figure 2, which is a schematic diagram of a possible timing signal waveform provided in one embodiment of this application. For example, when the value of n is 2160, that is, the display panel 2 includes 2160 rows of pixel circuits 21, the gate driving circuit 1 generates the scan signal G(N) required for a row of pixel circuits 21 under the control of 8 timing signals CLK(N). As shown in FIG2, the first-stage GOA unit 11 is used to generate the scan signal G(N) required for the first row of pixel circuits 21 according to the first pulse in the timing signal CLK1, and the second-stage GOA unit 11 is used to generate the scan signal G(N) required for the first row of pixel circuits 21 according to the timing signal CLK1. The first pulse in K2 generates the scan signal G(N) required for the second row of pixel circuit 21. The third-level GOA unit 11 is used to generate the scan signal G(N) required for the third row of pixel circuit 21 according to the first pulse in the timing signal CLK3... and so on. It can be seen that when the gate driving circuit 1 generates the scan signal G(N) under the control of the eight timing signals CLK(N), it takes 2160 / 8 = 270 pulses to drive the 2160 rows of pixel circuit 21 to display one frame of display image.
[0038] Specifically, please refer to Figure 3, which is a schematic diagram of the refresh area of a display panel provided in one embodiment of this application. The progressive scan direction of the gate driving circuit 1 is shown by the arrow in Figure 3. In the daily display of the display panel 2, it is highly likely that some display areas require a higher refresh rate, while others require a lower refresh rate. For example, the first refresh area 22 is used to display content requiring a higher refresh rate, such as video, while the second refresh area 23 is used to display content requiring a lower refresh rate, such as text. Therefore, in this embodiment, the first refresh rate is greater than the second refresh rate. By having the pixel circuit 21 disposed in the first refresh area 22 activated at the first refresh rate under the drive of the GOA unit 11, and the pixel circuit 21 disposed in the second refresh area 23 activated at the second refresh rate under the drive of the GOA unit 11, the number of pulses of the timing signal CLK(N) required by the GOA unit 11 can be reduced compared to the latter method where all pixel circuits 21 are activated at the first refresh rate under the drive of the GOA unit 11.
[0039] It is understood that by reducing the generation of pulses in the timing signal CLK(N), or by controlling the signal waveforms of the start signal STV and the reset signal RST, the pixel circuit 21 located in the first refresh area 22 can be turned on at the first refresh rate under the drive of the GOA unit 11, and the pixel circuit 21 located in the second refresh area 23 can be turned on at the second refresh rate under the drive of the GOA unit 11. This application does not limit this.
[0040] It is understood that in this embodiment, by dividing the display panel 2 into the first refresh region 22 and the second refresh region 23 along the line-by-line scanning direction of the gate driving circuit 1, and controlling the first refresh rate and the second refresh rate to be different, the number of pulses of the timing signal CLK(N) required by a portion of the GOA units 11 to generate the scan signal G(N) is reduced, thereby reducing the corresponding power consumption and heat generation.
[0041] In this embodiment, for example, when the first refresh rate is 180Hz, the second refresh rate is 60Hz, and the value of X is 3, that is, the display time of the display panel 2 is approximately 16.67 milliseconds (1 / 60Hz) per frame. During the time when the display panel 2 displays 3 frames, the GOA unit 11 drives the pixel circuit 21 set in the first refresh area 22 and the second refresh area 23 to activate for 1 frame time, approximately 5.56 milliseconds (1 / 180Hz), at the first refresh rate; the GOA unit 11 then activates the pixel circuit 21 at the first refresh rate. The pixel circuit 21 located in the first refresh area 22 is activated for 2 frames, approximately 11.12 milliseconds (2 / 180Hz), so that the pixel circuit 21 located in the first refresh area 22 is activated for 3 frames under the drive of the GOA unit 11. That is, the time for the display panel 2 to display 3 frames at the first refresh rate is equal to ta, i.e., ta is approximately 16.67 milliseconds. The pixel circuit 21 located in the second refresh area 23 is activated for 1 frame under the drive of the GOA unit 11, i.e., tb is approximately 5.56 milliseconds. The so-called A frame and B frame starting frame being the same means that the start time of A frame and the start time of B frame are the same. In other words, the GOA unit 11 simultaneously drives the pixel circuit 21 located in the first refresh area 22 and the second refresh area 23 to be activated, but since tb is less than ta, the GOA unit 11 will first drive the pixel circuit 21 located in the second refresh area 23 to be deactivated.
[0042] It is understood that in this embodiment, the actual refresh rate of the pixel circuit 21 located in the first refresh area 22 is the first refresh rate, i.e., 180Hz, while the pixel circuit 21 located in the second refresh area 23 is only activated for 1 frame during the time when the display panel 2 displays 3 frames, so its actual refresh rate is the second refresh rate, i.e., 180Hz / 3 = 60Hz. This achieves the purpose that the pixel circuit 21 located in the first refresh area 22 is activated at the first refresh rate under the drive of the GOA unit 11, and the pixel circuit 21 located in the second refresh area 23 is activated at the second refresh rate under the drive of the GOA unit 11.
[0043] It should be noted that, in this embodiment, please refer to Figure 4 as well. Figure 4 is a schematic diagram of the timing signal waveform of the first refresh area provided in an embodiment of this application. The number of rows of the pixel circuit 21 disposed in the first refresh area 22 can be 720 rows, then the number of rows of the pixel circuit 21 disposed in the second refresh area 23 can be 2160-720=1440 rows. Figure 4 shows the waveform of the timing signal CLK(N) required by the first-level GOA unit 11 to the 720th-level GOA unit 11 to drive the first row of pixel circuits 21 to the 720th row of pixel circuits 21 disposed in the first refresh area 22. As shown in Figure 4, when the gate driving circuit 1 generates the scan signal G(N) under the control of the 8 timing signals CLK(N), it takes 720 pulses to drive the 720 rows of pixel circuits 21 to display one frame of display screen. Therefore, when the gate driving circuit 1 is used to drive the display panel 2 to display 3 frames, the number of pulses of the timing signal CLK(N) required by the gate driving circuit 1 is reduced from the original 2160*3=6480 to 2160+720+720=3600. In other words, during the time when the display panel 2 displays X frames, the pixel circuit 21 located in the first refresh area 22 is used to enable 3 frames under the drive of the GOA unit 11, and the pixel circuit 21 located in the second refresh area 23 is used to enable 1 frame under the drive of the GOA unit 11. Compared with the original driving method of the gate driving circuit 1, the gate driving circuit 1 in this embodiment reduces power consumption and heat generation by nearly 2 times, and does not affect or has little effect on the effect of the gate driving circuit 1 driving the display panel 2 to display images.
[0044] It is understood that in other possible implementations, the values of X, A, B, ta, and tb can be changed according to the actual situation, thereby changing the numerical relationship between the first refresh rate and the second refresh rate. This application does not limit this.
[0045] In one possible implementation, when n is greater than 5, the 5th level GOA unit 11 to the nth level GOA unit 11 are all used to receive the start signal STV and the reset signal RST. The GOA unit 11 is used to generate the scan signal G(N) with a first level under the control of the start signal STV, and to generate the scan signal G(N) with a second level under the control of the reset signal RST.
[0046] It is understandable that, since the start signal STV is the signal that starts refreshing the display of a new frame, and the reset signal RST is the signal that interrupts the signal transmission between the GOA units 11 at different levels, compared with the conventional gate drive circuit 1, the GOA unit 11 located at the beginning generates a start signal according to the start signal STV, and performs cascading transmission between the GOA units 11 in the middle part, so that the GOA unit 11 generates the scan signal G(N) with a first level, thereby driving the pixel circuit 21 of the corresponding row to turn on; the GOA unit 11 at the end generates the scan signal G(N) with a second level according to the reset signal RST, thereby driving the pixel circuit 21 of the corresponding row to turn off.
[0047] It is understood that in this embodiment, each level of the GOA unit 11 is used to receive the start signal STV and the reset signal RST, realizing the start and stop of any level of the GOA unit 11. Thus, the refresh rate of any area of the display panel 2 can be realized by dynamically adjusting the start signal STV and the reset signal RST, thereby reducing the number of pulses of the timing signal CLK(N) required by the gate drive circuit 1, and reducing the corresponding power consumption and heat.
[0048] In one possible implementation, please refer to Figure 5, which is a schematic diagram of a GOA unit circuit provided in one embodiment of this application. The first-level GOA unit 11 to the fourth-level GOA unit 11 each include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a pull-down unit 111, and a capacitor C(N). The gate g of the first transistor T1 is electrically connected to the first electrode s of the first transistor T1 and is used to receive the start signal STV. The second electrode d of the first transistor T1 is electrically connected to one end of the capacitor C(N), the gate g of the second transistor T2, and the first electrode s of the third transistor T3. The first electrode s of the second transistor T2 is electrically connected to the other end of the capacitor C(N) and is used to receive the start signal STV. When receiving the timing signal CLK(N), the second electrode d of the second transistor T2 is electrically connected to the first electrode s of the fourth transistor T4 and is used to output the scan signal G(N); the gate g of the third transistor T3 is electrically connected to the pull-down unit 111 and the gate g of the fourth transistor T4 and is used to receive the scan signal G(N+4); the second electrode d of the third transistor T3 is electrically connected to the second electrode d of the fourth transistor T4 and is used to receive the first voltage signal VSS; the pull-down unit 111 is used to receive the second voltage signal VDD and generate a pull-down signal according to the second voltage signal VDD.
[0049] It should be noted that a transistor typically has a gate (g), a source, and a drain. When a voltage is applied to the gate (g), a source-drain channel is formed between the source and drain, thus connecting the source and drain of the transistor. Therefore, the electrical connection points of the source and drain of a transistor can usually be interchanged. In this embodiment, the first electrode (s) is used as the source and the second electrode (d) as the drain for illustrative purposes. It is understood that in other possible embodiments, the first electrode (s) can also be used as the drain and the second electrode (d) can also be used as the source; this application does not limit this.
[0050] In this embodiment, the start signal STV is used to control the turn-on of the first transistor T1, so that the start signal STV is transmitted to the gate g of the second transistor T2 through the first transistor T1. The second transistor T2 is turned on under the control of the start signal STV, so that the timing signal CLK(N) is output as the scan signal G(N) with a first level through the second transistor T2. When the N+4th stage GOA unit 11 generates the scan signal G(N+4) with a first level, the third transistor T3 is turned on under the control of the scan signal G(N+4), so that the first voltage signal VSS is transmitted to the gate g of the second transistor T2 through the third transistor T3. The second transistor T2 is turned off under the control of the first voltage signal VSS. The fourth transistor T4 is turned on under the control of the scan signal G(N+4), so that the first voltage signal VSS is output as the scan signal G(N) with a second level through the fourth transistor T4. The pull-down unit 111 is used to generate the pull-down signal according to the second voltage signal VDD when the scan signal G(N+4) is at the second level, so that the potential of the gate g of the second transistor T2 and the timing signal CLK(N) is maintained at the second level, and the capacitor C(N) plays a filtering role.
[0051] In one possible implementation, please refer to Figure 6, which is a schematic diagram of a GOA unit circuit provided in another embodiment of this application. When n is greater than 9, the 5th level GOA unit 11 to the (N-4)th level GOA unit 11 each includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a pull-down unit 111, and a capacitor C(N). The gate g of the first transistor T1 is electrically connected to the first electrode s of the first transistor T1 and is used to receive the scan signal G(N-4). The second electrode d of the first transistor T1 is electrically connected to the second electrode d of the fifth transistor T5, one end of the capacitor C(N), the gate g of the second transistor T2, and the first electrode s of the third transistor T3. The first electrode s of the second transistor T2 is electrically connected to the pull-down unit 111. The other end of capacitor C(N) is used to receive timing signal CLK(N). The second electrode d of the second transistor T2 is electrically connected to the first electrode s of the fourth transistor T4 and is used to output scan signal G(N). The gate g of the third transistor T3 is electrically connected to the pull-down unit 111 and the gate g of the fourth transistor T4 and is used to receive the reset signal RST and scan signal G(N+4). The second electrode d of the third transistor T3 is electrically connected to the second electrode d of the fourth transistor T4 and is used to receive the first voltage signal VSS. The pull-down unit 111 is used to receive the second voltage signal VDD and generate a pull-down signal according to the second voltage signal VDD.
[0052] It is understood that the difference between this embodiment and the previous embodiment is that the start signal STV and the reset signal RST are added to the 5th level GOA unit 11 to the N-4th level GOA unit 11 for control, so that any level of the 5th level GOA unit 11 to the N-4th level GOA unit 11 can be turned on or off.
[0053] Specifically, the fifth transistor T5 is turned on under the loading of the start signal STV, so as to transmit the start signal STV to the gate g of the second transistor T2 through the fifth transistor T5. The second transistor T2 is turned on under the control of the start signal STV, so as to output the timing signal CLK(N) as the scan signal G(N) with the first level through the second transistor T2. The third transistor T3 is turned on under the control of the reset signal RST, so as to transmit the first voltage signal VSS to the gate g of the second transistor T2 through the third transistor T3. The second transistor T2 is turned off under the control of the first voltage signal VSS. The fourth transistor T4 is turned on under the control of the reset signal RST, so as to output the first voltage signal VSS as the scan signal G(N) with the second level through the fourth transistor T4.
[0054] In one possible implementation, please refer to Figure 7, which is a schematic diagram of a GOA unit circuit provided in another embodiment of this application. When n is greater than 9, the (N-3)th level GOA unit 11 to the Nth level GOA unit 11 each include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a pull-down unit 111, and a capacitor C(N). The gate g of the first transistor T1 is electrically connected to the first electrode s of the first transistor T1 and is used to receive the scan signal G(N-4). The second electrode d of the first transistor T1 is electrically connected to the second electrode d of the fifth transistor T5, one end of the capacitor C(N), the gate g of the second transistor T2, and the first electrode s of the third transistor T3; the first electrode s of the second transistor T2... The second electrode d of the second transistor T2 is electrically connected to the other end of the capacitor C(N) and is used to receive the timing signal CLK(N). The second electrode d of the second transistor T2 is electrically connected to the first electrode s of the fourth transistor T4 and is used to output the scan signal G(N). The gate g of the third transistor T3 is electrically connected to the pull-down unit 111 and the gate g of the fourth transistor T4 and is used to receive the reset signal RST. The second electrode d of the third transistor T3 is electrically connected to the second electrode d of the fourth transistor T4 and is used to receive the first voltage signal VSS. The pull-down unit 111 is used to receive the second voltage signal VDD and generate a pull-down signal according to the second voltage signal VDD.
[0055] It should be noted that since this application uses eight timing signals CLK(N) to control the GOA unit 11 to generate the scan signal G(N), when N is greater than 8, the N in the timing signal CLK(N) needs to be modulo 8. For example, when the value of N is 9, since 9%8 = 1, the timing signal CLK(1) is used to control the 9th level GOA unit 11; when the value of N is 10, since 10%8 = 2, the timing signal CLK(2) is used to control the 10th level GOA unit 11, and so on. It is understood that in other possible embodiments, different numbers of the timing signals CLK(N) can be used to control the GOA unit 11 to generate the scan signal G(N), and this application does not limit this.
[0056] It is understood that this application uses the value of n as 2160 as an example for illustration only, and does not limit the value of n. In other possible implementations, the value of n can also be other values, as long as it does not affect the control of the opening or closing of the GOA unit 11 at any level through the start signal STV and the reset signal RST. This application does not limit the circuit structure of the GOA unit 11 or the value of n.
[0057] In one possible implementation, referring again to FIG3, the first refresh area 22 and the second refresh area 23 are connected, and the number of GOA units 11 of the pixel circuit 21 used to drive the first refresh area 22 is less than the number of GOA units 11 of the pixel circuit 21 used to drive the second refresh area 23.
[0058] It is understandable that, under normal circumstances, when there is a need for different refresh rates in the display panel 2, the portion of the display panel 2 with a higher refresh rate is usually less than the portion with a lower refresh rate. That is, the number of GOA units 11 used to drive the pixel circuit 21 of the first refresh area 22 is less than the number of GOA units 11 used to drive the pixel circuit 21 of the second refresh area 23.
[0059] In this embodiment, as shown in FIG3, the first refresh area 22 and the second refresh area 23 are connected. In other possible embodiments, the first refresh area 22 and the second refresh area 23 may also be set at intervals to accommodate more possible display screens of the display panel 2. This application does not limit this.
[0060] This application also provides a control method for a gate driving circuit, applied to the gate driving circuit described above. Please refer to Figure 8, which is a schematic flowchart of the control method for a gate driving circuit provided in one embodiment of this application. The control method for the gate driving circuit includes steps S801, S802, and S803, wherein the detailed descriptions of steps S801, S802, and S803 are as follows.
[0061] S801, Obtain the X-frame display image of display panel 2;
[0062] S802, drive the pixel circuit 21 located in the first refresh area 22 to start the A-frame time ta;
[0063] S803, drive the pixel circuit 21 located in the second refresh area 23 to enable B-frame time tb;
[0064] In this case, frames A and B have the same starting frame, and tb is less than ta.
[0065] It should be noted that the gate driving circuit 1, the display panel 2, the first refresh area 22, the second refresh area 23, the pixel circuit 21, the X frame, the A frame, the B frame, ta, and tb are described above and will not be repeated here.
[0066] It is understood that in this embodiment, by dividing the display panel 2 into the first refresh region 22 and the second refresh region 23 along the line-by-line scanning direction of the gate driving circuit 1, and controlling the first refresh rate and the second refresh rate to be different, the number of pulses of the timing signal CLK(N) required by a portion of the GOA units 11 to generate the scan signal G(N) is reduced, thereby reducing the corresponding power consumption and heat generation.
[0067] This application also provides a display panel 2, please refer to Figure 9, which is a schematic diagram of the display panel frame provided in one embodiment of this application. The display panel 2 includes pixel circuits 21, data driving circuits 24, and gate driving circuits 1 as described above. The pixel circuits 21 are arranged in an array. The pixel circuits 21 are turned on under the control of the scan signal G(N) generated by the gate driving circuit 1. The data driving circuit 24 is used to generate data signals and charge the pixel circuits 21 that are turned on under the control of the scan signal G(N) generated by the gate driving circuit 1, so as to realize the display function of the display panel 2. Specifically, please refer to the description of the gate driving circuit 1 and the pixel circuits 21 above, and this application will not repeat them here.
[0068] It is understood that in this embodiment, by dividing the display panel 2 into the first refresh region 22 and the second refresh region 23 along the line-by-line scanning direction of the gate driving circuit 1, and controlling the first refresh rate and the second refresh rate to be different, the number of pulses of the timing signal CLK(N) required by a portion of the GOA units 11 to generate the scan signal G(N) is reduced, thereby reducing the overall power consumption and heat generation of the display panel 2.
[0069] In one possible implementation, during the time ta when the display panel 2 displays frame A, the data signal generated by the data driving circuit 24 is used to charge the pixel circuit 21 disposed in the first refresh area 22, and during the time tb when the display panel displays frame B, the data signal generated by the data driving circuit 24 is used to charge the pixel circuit 21 disposed in the first refresh area 22 and the second refresh area 23.
[0070] Specifically, the A-frame time ta and B-frame time tb are described above and will not be repeated here. It should be noted that the data driving circuit 24 typically generates the data signals required for an entire column of pixel circuits 21. In this embodiment, during the A-frame time ta displayed on the display panel 2, the data driving circuit 24 can generate only the data signals for charging the pixel circuits 21 located in the first refresh area 22, based on the start signal STV and the reset signal RST, without needing to generate the data signals for charging the pixel circuits 21 located in the second refresh area 23; during the B-frame time tb displayed on the display panel 2, the data driving circuit 24 then generates the data signals for charging the pixel circuits 21 located in both the first refresh area 22 and the second refresh area 23, thereby reducing the power consumption and heat generated by the data driving circuit 24.
[0071] This application also provides an electronic device 3, please refer to FIG10, which is a top view schematic diagram of an embodiment of the electronic device provided in this application. The electronic device 3 includes a housing 31 and a display panel 2 as described above, the housing 31 being used to support the display panel 2.
[0072] It should be noted that the electronic device 3 in the embodiments of this application can be a television, mobile phone, smartphone, tablet computer, e-reader, wearable portable device, laptop computer, or other electronic device 3. It can communicate with a data transfer server via the Internet. The data transfer server can be an instant messaging server, an SNS (Social Networking Services) server, etc. The embodiments of this application do not limit this.
[0073] It is understood that in this embodiment, by dividing the display panel 2 into the first refresh region 22 and the second refresh region 23 along the line-by-line scanning direction of the gate driving circuit 1, and controlling the first refresh rate and the second refresh rate to be different, the number of pulses of the timing signal CLK(N) required by a portion of the GOA units 11 to generate the scan signal G(N) is reduced, thereby reducing the overall power consumption and heat generation of the electronic device 3.
[0074] This document uses specific examples to illustrate the principles and implementation methods of this application. The above description of the implementation methods is only for the purpose of helping to understand the core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A gate driving circuit applied to a display panel, the display panel including a plurality of pixel circuits arranged in an array, the gate driving circuit including n-stage cascaded GOA units, wherein, Each level of the GOA unit is used to generate a corresponding scan signal to drive the pixel circuit of the corresponding row to turn on. The display panel has a first refresh area and a second refresh area along the row-by-row scanning direction of the gate driving circuit. The first refresh area and the second refresh area are spaced apart along the row-by-row scanning direction. The pixel circuit disposed in the first refresh area is turned on at a first refresh rate under the drive of the GOA unit, and the pixel circuit disposed in the second refresh area is turned on at a second refresh rate under the drive of the GOA unit. The first refresh rate and the second refresh rate are different. When n is greater than 5, the 5th level GOA unit to the nth level GOA unit are all used to receive a start signal and a reset signal. Each level of the GOA unit is used to receive the start signal and reset signal. Under the control of the signal, a scanning signal with a first level is generated to drive the pixel circuit of the corresponding row to turn on, and under the control of the reset signal, a scanning signal with a second level is generated to drive the pixel circuit of the corresponding row to turn off, where n is a positive integer; during the time when the display panel displays X frames, the pixel circuit set in the first refresh area is used to turn on frame A for time ta under the drive of the GOA unit, and the pixel circuit set in the second refresh area is used to turn on frame B for time tb under the drive of the GOA unit. The GOA unit simultaneously drives the pixel circuits set in the first refresh area and the second refresh area to turn on, wherein the starting frames of frames A and B are the same, and tb is less than ta, the number of frames A is less than or equal to the number of frames X, and the number of frames B is less than the number of frames A.
2. The gate driving circuit as described in claim 1, characterized in that, Each of the four GOA units (Level 1 to Level 4) includes a first transistor, a second transistor, a third transistor, a fourth transistor, a pull-down unit, and a capacitor. The gate of the first transistor is electrically connected to its first electrode and is used to receive the start signal. The second electrode of the first transistor is electrically connected to one end of the capacitor, the gate of the second transistor, and the first electrode of the third transistor. The first electrode of the second transistor is electrically connected to the other end of the capacitor and is used to receive the timing signal CLK(N). The second electrode of the second transistor is electrically connected to the first electrode of the fourth transistor and is used to output the scan signal G(N). The gate of the third transistor is electrically connected to the pull-down unit and the gate of the fourth transistor and is used to receive the scan signal G(N+4). The second electrode of the third transistor is electrically connected to the second electrode of the fourth transistor and is used to receive a first voltage signal. The pull-down unit receives a second voltage signal and generates a pull-down signal based on the second voltage signal. The value of N is greater than or equal to 1 and less than or equal to n.
3. The gate driving circuit as described in claim 1, characterized in that, When n is greater than 9, each of the GOA units from level 5 to level N-4 includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a pull-down unit, and a capacitor. The gate of the first transistor is electrically connected to the first electrode of the first transistor and is used to receive the scan signal G(N-4). The second electrode of the first transistor is electrically connected to the second electrode of the fifth transistor, one end of the capacitor, the gate of the second transistor, and the first electrode of the third transistor. The first electrode of the second transistor is electrically connected to the other end of the capacitor and is used to receive the timing signal CLK(N). The second electrode of the second transistor is electrically connected to the first electrode of the fourth transistor and is used to output the scan signal G(N). The gate of the third transistor is electrically connected to the pull-down unit and the gate of the fourth transistor and is used to receive the reset signal and the scan signal G(N+4). The second electrode of the third transistor is electrically connected to the second electrode of the fourth transistor and is used to receive a first voltage signal. The pull-down unit is used to receive a second voltage signal and generate a pull-down signal based on the second voltage signal.
4. The gate driving circuit as described in claim 1, characterized in that, When n is greater than 9, each of the N-3 level GOA units to the Nth level GOA unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a pull-down unit, and a capacitor. The gate of the first transistor is electrically connected to the first electrode of the first transistor and is used to receive the scan signal G(N-4). The second electrode of the first transistor is electrically connected to the second electrode of the fifth transistor, one end of the capacitor, the gate of the second transistor, and the first electrode of the third transistor. The first electrode of the second transistor is electrically connected to the other end of the capacitor and is used to receive the timing signal CLK(N). The second electrode of the second transistor is electrically connected to the first electrode of the fourth transistor and is used to output the scan signal G(N). The gate of the third transistor is electrically connected to the pull-down unit and the gate of the fourth transistor and is used to receive the reset signal. The second electrode of the third transistor is electrically connected to the second electrode of the fourth transistor and is used to receive a first voltage signal. The pull-down unit is used to receive a second voltage signal and generate a pull-down signal according to the second voltage signal.
5. The gate driving circuit as described in claim 1, characterized in that, The first refresh area and the second refresh area are connected, and the number of GOA units used to drive the pixel circuit of the first refresh area is less than the number of GOA units used to drive the pixel circuit of the second refresh area.
6. A control method for a gate driving circuit, applied to the gate driving circuit as described in any one of claims 1-5, characterized in that, The control method of the gate driving circuit includes: acquiring X frames of display images from the display panel; driving the pixel circuit located in the first refresh area to enable A frame time ta; driving the pixel circuit located in the second refresh area to enable B frame time tb; wherein, the starting frames of A frame and B frame are the same, and tb is less than ta.
7. A display panel, characterized in that, The display panel includes pixel circuits, a data driving circuit, and a gate driving circuit as described in any one of claims 1-5. The pixel circuits are distributed in an array. The pixel circuits are turned on under the control of the scan signal generated by the gate driving circuit. The data driving circuit is used to generate data signals and charge the pixel circuits that are turned on under the control of the scan signal generated by the gate driving circuit, so as to realize the display function of the display panel.
8. The display panel as described in claim 7, characterized in that, During the time ta when frame A is displayed on the display panel, the data signal generated by the data driving circuit is used to charge the pixel circuit disposed in the first refresh area. During the time tb when frame B is displayed on the display panel, the data signal generated by the data driving circuit is used to charge the pixel circuit disposed in the first refresh area and the second refresh area.
9. An electronic device, characterized in that, The electronic device includes a housing and a display panel as described in claim 7 or 8, wherein the housing is used to support the display panel.