Flat panel detector control method, control device and flat panel detector device

Abstract

The control method, control device, and flat panel detector provided in this disclosure divide the shift register into cascaded groups, and couple different cascaded groups to different frame start signal lines and different clock signal lines. This allows each cascaded group to achieve different operating states in different reading modes. Furthermore, in the first reading mode, line-by-line scanning and reading can be achieved. In the second reading mode, multiple lines can be scanned and read simultaneously, thereby reducing reading time and increasing the acquisition frame rate.

Description

Technical Field

[0001] This disclosure relates to the field of detection technology, and in particular to control methods, control devices, and flat panel detectors. Background Technology

[0002] X-ray imaging utilizes the short wavelength and penetrating properties of X-rays, as well as the different absorption characteristics of X-rays by different tissues, to create images by detecting the intensity of X-rays that pass through an object. The flat panel detector (FPD), as the core component of an X-ray imaging system, is responsible for converting X-rays into electrical signals and recording them into images. These signals can be displayed on a monitor or stored for later retrieval. Summary of the Invention

[0003] The control method, control device, and flat panel detector provided in this disclosure can reduce reading time.

[0004] The control method for a flat panel detector provided in this disclosure includes: multiple gate lines, multiple data lines intersecting and insulated from the gate lines, a detection unit defined by the multiple gate lines and the multiple data lines, a gate driving circuit coupled to each of the gate lines, and multiple frame start signal lines and multiple clock signal lines coupled to the gate driving circuit; the gate driving circuit includes multiple shift registers, each shift register is coupled to one gate line, the multiple shift registers are divided into multiple cascaded groups, the shift registers in the same cascaded group are cascaded, and different cascaded groups are coupled to different frame start signal lines and different clock signal lines;

[0005] The control method includes:

[0006] When using the first read mode, within one frame scan time, different frame start signals are loaded onto each frame start signal line, and different clock signals are loaded onto each clock signal line to control the sequential operation of each cascaded group. The multiple gate lines are scanned line by line, and during the gate line scan, the detection signals on each data line are collected to determine the target detection signal corresponding to each detection unit. Among them, each shift register in the same cascaded group scans the coupled gate lines line by line.

[0007] When using the second read mode, within one frame scan time, the same frame start signal is loaded onto at least some of the frame start signal lines coupled to the cascaded groups, and the same clock signal is loaded onto the clock signal lines coupled to the at least some of the cascaded groups, controlling the at least some of the cascaded groups to work simultaneously, scanning multiple adjacent gate lines among the multiple gate lines simultaneously, and acquiring the detection signal on the data line during the gate line scanning to determine the target detection signal corresponding to each detection unit group; wherein, the detection unit group includes detection units coupled to the simultaneously scanned gate lines and coupled to at least one of the data lines, and each shift register in the same cascaded group scans the coupled gate lines line by line.

[0008] In some possible implementations, the plurality of shift registers are divided into N cascaded groups, and each shift register in the same cascaded group is coupled to a gate line spaced N-1 rows apart; N is an integer greater than 1.

[0009] The step of loading the same frame start signal onto at least some of the cascaded group coupled frame start signal lines, and loading the same clock signal onto at least some of the cascaded group coupled clock signal lines, to control the at least some of the cascaded groups to operate simultaneously, and to simultaneously scan multiple adjacent gate lines among the multiple gate lines, includes:

[0010] A gate line group is formed by taking at least two adjacent gate lines. For a gate line group, the same frame start signal is applied to the frame start signal line corresponding to the cascade group coupled to the gate line group, and the same clock signal is applied to the clock signal line corresponding to the cascade group coupled to the gate line group. The cascade group coupled to the gate line group is controlled to work simultaneously, and the gate lines in the gate line group are scanned simultaneously.

[0011] In some possible implementations, the cascaded groups coupled to two adjacent gate line groups are different. For the first and second gate line groups in the two adjacent gate line groups, different frame start signals are loaded onto the frame start signal lines corresponding to the cascaded groups coupled to the first and second gate line groups, and different clock signals are loaded onto the clock signal lines corresponding to the cascaded groups coupled to the first and second gate line groups, thereby controlling the cascaded groups coupled to the first and second gate line groups to work sequentially and scanning the first and second gate line groups in turn.

[0012] In some possible implementations, two adjacent gate line groups are coupled to the same cascade group, the same frame start signal is loaded onto the frame start signal line corresponding to all the cascade groups, and the same clock signal is loaded onto the clock signal line corresponding to all the cascade groups, controlling all the cascade groups to work simultaneously, and scanning all the gate lines in the same gate line group simultaneously.

[0013] In some possible implementations, N=4, the plurality of clock signal lines include clock signal lines 1 to 8, and the plurality of frame start signal lines include frame start signal lines 1 to 4.

[0014] The plurality of cascade groups include cascade groups 1 to 4; wherein, cascade group 1 is coupled to gate line 4k-3, cascade group 2 is coupled to gate line 4k-2, cascade group 3 is coupled to gate line 4k-1, and cascade group 4 is coupled to gate line 4k, where k is an integer greater than 0; and, cascade group 1 is coupled to clock line 1, clock line 5, and start signal line 1, respectively; cascade group 2 is coupled to clock line 2, clock line 6, and start signal line 2, respectively; cascade group 3 is coupled to clock line 3, clock line 7, and start signal line 3, respectively; and cascade group 4 is coupled to clock line 4, clock line 8, and start signal line 4.

[0015] When two adjacent gate line groups are coupled to different cascade groups, the first gate line group is coupled to the first cascade group and the second cascade group, the second gate line group is coupled to the third cascade group and the fourth cascade group, and the same frame start signal is loaded onto the first frame start signal line and the second frame start signal line, the same clock signal is loaded onto the first clock signal line and the second clock signal line, the same clock signal is loaded onto the fifth clock signal line and the sixth clock signal line; the same frame start signal is loaded onto the third frame start signal line and the fourth frame start signal line, the same clock signal is loaded onto the third clock signal line and the fourth clock signal line, and the same clock signal is loaded onto the seventh clock signal line and the eighth clock signal line.

[0016] When two adjacent gate line groups are coupled to the same cascade group, each gate line group is coupled to the first cascade group to the fourth cascade group, and the same frame start signal is loaded onto the first frame start signal line to the fourth frame start signal line, the same clock signal is loaded onto the first clock signal line to the fourth clock signal line, and the same clock signal is loaded onto the fifth clock signal line to the eighth clock signal line.

[0017] In some possible implementations, the effective level of the frame start signal loaded on the frame start signal line corresponding to the cascaded group coupled to the first gate line group is 1 / 4 clock cycle ahead of the effective level of the frame start signal loaded on the frame start signal line corresponding to the cascaded group coupled to the second gate line group.

[0018] The clock signal loaded on the clock signal line corresponding to the cascaded group coupled to the first gate line group has the same clock period as the clock signal loaded on the clock signal line corresponding to the cascaded group coupled to the second gate line group, and the duty cycle of the clock signal loaded on the clock signal line corresponding to the cascaded group coupled to the first gate line group is 25%.

[0019] In some possible implementations, when the second reading mode is used, a target detection signal is determined based on the rule that a target detection signal is obtained by simultaneously acquiring detection signals on adjacent m data lines; where 2≤m≤M; M is the number of simultaneously scanned grid lines; the detection unit group includes detection units coupled to the simultaneously scanned grid lines and coupled to the m data lines.

[0020] In some possible implementations, the cascade group coupled to the odd-numbered gate line is disposed at the first end of the plurality of gate lines, and the cascade group coupled to the even-numbered gate line is disposed at the second end of the plurality of gate lines.

[0021] The control device for a flat panel detector provided in this embodiment includes: multiple gate lines, multiple data lines intersecting and insulated from the gate lines, a detection unit defined by the multiple gate lines and the multiple data lines, a gate driving circuit coupled to each of the gate lines, and multiple frame start signal lines and multiple clock signal lines coupled to the gate driving circuit; the gate driving circuit includes multiple shift registers, each shift register is coupled to one gate line, the multiple shift registers are divided into multiple cascaded groups, the shift registers in the same cascaded group are cascaded, and each cascaded group is coupled to different frame start signal lines and different clock signal lines;

[0022] The control device includes:

[0023] The driving circuit is configured to, in a first read mode, load different frame start signals onto each of the frame start signal lines and different clock signals onto each of the clock signal lines within a frame scan time, controlling each of the cascaded groups to operate sequentially and scan the multiple gate lines line by line; and in a second read mode, load the same frame start signal onto the frame start signal lines coupled to at least a portion of the cascaded groups and the same clock signal onto the clock signal lines coupled to the at least a portion of the cascaded groups within a frame scan time, controlling the at least a portion of the cascaded groups to operate simultaneously and scan adjacent gate lines of the multiple gate lines simultaneously; wherein, each shift register in the same cascaded group scans the coupled gate lines line by line.

[0024] The acquisition circuit is configured to, when using the first read mode, acquire detection signals on each of the data lines during the gate line scanning to determine a target detection signal corresponding to each of the detection units; and when using the second read mode, acquire detection signals on the data lines during the gate line scanning to determine a target detection signal corresponding to the detection unit group; wherein the detection unit group includes detection units coupled to the simultaneously scanned gate lines and coupled to at least one of the data lines.

[0025] In some possible implementations, the plurality of shift registers are divided into N cascaded groups, and the shift registers in the same cascaded group are respectively coupled to gate lines spaced N-1 rows apart; N is an integer greater than 1;

[0026] The driving circuit is further configured to: use at least two adjacent gate lines as a gate line group; for a gate line group, load the same frame start signal on the frame start signal line corresponding to the cascade group coupled to the gate line group, and load the same clock signal on the clock signal line corresponding to the cascade group coupled to the gate line group, control the cascade group coupled to the gate line group to work simultaneously, and scan the gate lines in the gate line group simultaneously.

[0027] The flat panel detection device provided in this embodiment includes a flat panel detector and a control device for the flat panel detector. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of the flat panel detection device in the embodiments of this disclosure;

[0029] Figure 2 This is a schematic diagram of the structure of the flat panel detector in an embodiment of this disclosure;

[0030] Figure 3 This is a schematic diagram of the shift register structure in an embodiment of this disclosure;

[0031] Figure 4a These are some signal timing diagrams from embodiments of this disclosure;

[0032] Figure 4b Here are some other signal timing diagrams in the embodiments of this disclosure;

[0033] Figure 4c These are some more signal timing diagrams in the embodiments of this disclosure;

[0034] Figure 5 These are some structural schematic diagrams of the gate drive circuit in the embodiments of this disclosure;

[0035] Figure 6 These are some other structural schematic diagrams of the gate drive circuit in the embodiments of this disclosure;

[0036] Figure 7a These are further schematic diagrams of the gate drive circuit in the embodiments of this disclosure;

[0037] Figure 7b These are further schematic diagrams of the gate drive circuit in the embodiments of this disclosure;

[0038] Figure 7c These are further schematic diagrams of the gate drive circuit in the embodiments of this disclosure;

[0039] Figure 7d These are further schematic diagrams of the gate drive circuit in the embodiments of this disclosure;

[0040] Figure 8 Here are some flowcharts of the control methods in the embodiments of this disclosure;

[0041] Figure 9 These are some more signal timing diagrams in the embodiments of this disclosure;

[0042] Figure 10 These are some more signal timing diagrams in the embodiments of this disclosure;

[0043] Figure 11a These are further structural schematic diagrams of the flat panel detector in the embodiments of this disclosure;

[0044] Figure 11b These are further structural schematic diagrams of the flat panel detector in the embodiments of this disclosure;

[0045] Figure 12 These are some more signal timing diagrams in the embodiments of this disclosure;

[0046] Figure 13a These are further structural schematic diagrams of the flat panel detector in the embodiments of this disclosure;

[0047] Figure 13b These are further structural schematic diagrams of the flat panel detector in the embodiments of this disclosure. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0049] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “coupled” or “connected” are not limited to physical or mechanical coupling, but can include electrical coupling, whether direct or indirect.

[0050] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0051] See Figure 1 and Figure 2 The flat panel detection device may include a flat panel detector 100 and a control device 200 for the flat panel detector. The flat panel detector 100 may include: multiple gate lines GA (e.g., GA1, GA2, GA3, GA4), multiple data lines DA (e.g., DA1, DA2, DA3) intersecting and insulated from the gate lines GA (e.g., GA1, GA2, GA3, GA4), a detection unit SPX arranged in an array defined by the multiple gate lines GA (e.g., GA1, GA2, GA3, GA4) and the multiple data lines DA (e.g., DA1, DA2, DA3), and a gate drive circuit 110 coupled to each gate line GA1, GA2, GA3, GA4. The control device 200 may include: a drive circuit 210 and a data acquisition circuit 220. The drive circuit 210 is coupled to the gate drive circuit 110, and the data acquisition circuit 220 is coupled to the data lines DA1, DA2, DA3.

[0052] See Figure 2As shown, each detection unit SPX includes a transistor 11 and a photodetector 12. One row of detection units SPX corresponds to one gate line, and one column of detection units SPX corresponds to one data line. The gate of transistor 11 is coupled to the corresponding gate line, the source of transistor 11 is coupled to the corresponding data line, and the drain of transistor 11 is coupled to the photodetector 12. It should be noted that the specific arrangement of detection units and data lines / scan lines is not limited in this disclosure. For example, the flat panel detector in this embodiment can be an X-ray flat panel detector. In practical applications, the photodetector 12 may include a scintillator and a photodiode. The scintillator absorbs X-rays and converts them into visible light, while the photodiode converts the visible light generated by the scintillator into an electrical signal. When the driving circuit 210 controls the gate driving circuit 110 to scan the gate line, the transistor 11 coupled to the gate line is turned on, so that the electrical signal converted by the photodiode can be input to the data line through the turned-on transistor 11. The acquisition circuit 220 can acquire the signal on the data line and generate a target detection signal, thereby enabling imaging based on the generated target detection signal.

[0053] In some embodiments of this disclosure, the gate drive circuit may include multiple shift registers, each shift register coupled to a gate line. For example, as shown... Figure 3 As shown, the shift register may include switching transistors M1~M15 and a storage capacitor CST. Furthermore, the shift register is coupled to the input signal terminal IP, the reset signal terminal RE, the clock signal terminal CLK, the reference voltage terminal VREF, the first scan control terminal VDS, the second scan control terminal VSD, the first conversion control terminal VDD1, the second conversion control terminal VDD2, the noise reduction control terminal GCL, the drive output terminal GOUT, the first node N1, the second node N2, and the third node N3. Figure 3 The timing diagram showing the shift register operating in frame n, Fn, can be presented in various ways. In some examples, Figure 3 The timing diagram of the shift register operating in frame n, Fn, shown below, can be seen as follows: Figure 4a As shown, its specific working process is basically the same as that in the prior art, and will not be described in detail here. In some other examples, Figure 3 The timing diagram of the shift register operating in frame n, Fn, shown below, can also be represented as follows: Figure 4b As shown, its specific working process is basically the same as that in the prior art, and will not be described in detail here. In some other examples, Figure 3 The timing diagram of the shift register operating in frame n, Fn, shown below, can also be represented as follows: Figure 4c As shown, its specific working process is basically the same as that in the prior art, and will not be described in detail here. It should be noted that this disclosure is only based on... Figure 3The shift register structure shown is used as an example for illustration. In practical applications, shift registers can also adopt other structures, which are not limited here.

[0054] It should be noted that, as Figures 4a to 4c As shown, TS represents the scan phase, and BT represents the blanking time phase. ip represents the input signal IP, ck_1~ck_3 represent the clock signals CLK, ga_1~ga_3 represent the gate scan signals GOUT, re represents the reset signal RE, vds represents the first scan control signal VDS, vsd represents the second scan control signal VSD, vdd1 represents the first conversion control signal VDD1, vdd2 represents the second conversion control signal VDD2, gcl represents the noise reduction control signal GCL, and vref represents the reference voltage signal VREF. Figures 4a to 4c In this example, the clock periods of clock signals ck_1 to ck_3 are different. Taking the clock period of clock signal ck_3 as T, the clock period of clock signal ck_2 can be 2T, and the clock period of clock signal ck_1 can be 4T. Of course, in practical applications, the clock periods of clock signals ck_2 and ck_3 can be set to other values, which are not limited here.

[0055] For example, the drive output terminal GOUT of each shift register is coupled to a gate line one-to-one. The effective level of the gate scan signals ga_1~ga_3 can control the transistor in the corresponding gate-coupled detection unit to turn on, and the ineffective level can control the transistor in the corresponding gate-coupled detection unit to turn off. For example, the switching transistors M1~M15 are N-type transistors, the effective level of the gate scan signals ga_1~ga_3 can be high, the ineffective level is low, and the signal vref is a fixed low voltage. Alternatively, the switching transistors M1~M15 are P-type transistors, the effective level of the gate scan signals ga_1~ga_3 can also be low, the ineffective level is high, and the signal vref is a fixed high voltage. No limitation is made here.

[0056] It should be noted that in the shift register provided in this embodiment, the switching transistors M1 and M2 are symmetrically designed, and the switching transistors M5 and M6 are symmetrically designed, allowing for functional interchangeability. Therefore, the shift register provided in this embodiment can achieve bidirectional scanning. During forward scanning, switching transistors M1 and M5 are used as input transistors, and switching transistors M2 and M6 are used as reset transistors. Furthermore, taking the effective level of the gate scan signals ga_1~ga_3 as high and the invalid level as low as an example, the signal vds of the first scan control terminal VDS is a fixed high voltage, and the signal vsd of the second scan control terminal VSD is a fixed low voltage. During reverse scanning, switching transistors M2 and M6 are used as input transistors, and switching transistors M1 and M5 are used as reset transistors. Furthermore, taking the effective level of the gate scan signals ga_1~ga_3 as high and the invalid level as low as an example, the signal vds of the first scan control terminal VDS is a fixed low voltage, and the signal vsd of the second scan control terminal VSD is a fixed low voltage.

[0057] In specific implementation, the signals vdd1 of the first conversion control terminal VDD1 and vdd2 of the second conversion control terminal VDD2 can be pulse signals switching between high and low levels, respectively, and the levels of the signals vdd1 and vdd2 of the first conversion control terminal VDD1 and the second conversion control terminal VDD2 are opposite. Alternatively, the signals vdd1 of the first conversion control terminal VDD1 and vdd2 of the second conversion control terminal VDD2 can also be DC signals. Furthermore, when the first conversion control terminal VDD1 is loaded with a high-level DC signal, the second conversion control terminal VDD2 is not loaded with a signal or is loaded with a low-level DC signal. When the second conversion control terminal VDD2 is loaded with a high-level DC signal, the first conversion control terminal VDD1 is not loaded with a signal or is loaded with a low-level DC signal. For example, in the first stage, the signal vdd1 of the first conversion control terminal VDD1 is a high-level signal, and the signal vdd2 of the second conversion control terminal VDD2 is a low-level signal. In the second stage, the signal vdd1 of the first conversion control terminal VDD1 is a low-level signal, and the signal vdd2 of the second conversion control terminal VDD2 is a high-level signal. For example, the duration of the first stage can be the same as the duration of the second stage. For instance, the duration of the first stage and the duration of the second stage can be set to the length of one frame, multiple frames, 2 seconds, 1 hour, or 24 hours, etc., without limitation. Furthermore, the order of the first and second stages can be determined according to the actual application. For example, the work process in the first stage can be executed first, followed by the work process in the second stage. Alternatively, the work process in the second stage can be executed first, followed by the work process in the first stage.

[0058] In some embodiments of this disclosure, the flat panel detector may further include multiple clock signal lines and multiple frame start signal lines, and these multiple clock signal lines and multiple frame start signal lines are respectively coupled to a gate driving circuit. This allows a corresponding clock signal to be input to the gate driving circuit via the clock signal lines. This clock signal is input to the clock signal terminal of the shift register, thereby causing the shift register to output a gate scan signal to the coupled gate lines. For example, as... Figure 5 As shown, the flat panel detector may include eight clock signal lines CK1~CK8 and four frame start signal lines STV1~STV4. These eight clock signal lines CK1~CK8 and four frame start signal lines STV1~STV4 are coupled to the gate drive circuit 110. Furthermore, CK1 serves as the first clock signal line, CK2 as the second clock signal line, CK3 as the third clock signal line, CK4 as the fourth clock signal line, CK5 as the fifth clock signal line, CK6 as the sixth clock signal line, CK7 as the seventh clock signal line, and CK8 as the eighth clock signal line. STV1 serves as the first frame start signal line, STV2 as the second frame start signal line, STV3 as the third frame start signal line, and STV4 as the fourth frame start signal line. It should be noted that... Figure 5 This example uses 8 clock signal lines and 4 frame start signal lines. In practical applications, the specific number of clock signal lines and frame start signal lines can be determined according to the actual application requirements and is not limited here. For example, it can also be other numbers of clock signal lines and frame start signal lines that are multiples of 2, such as 2, 4, 6, 10, 12, etc.

[0059] In some embodiments of this disclosure, the shift registers in the gate drive circuit are divided into multiple cascaded groups. Shift registers within the same cascaded group are cascaded together. Furthermore, different cascaded groups are coupled to different frame start signal lines. The multiple shift registers are also divided into multiple register groups, with each register group coupled to the same clock signal line. At least one gate line between adjacent shift registers coupled within the same register group is coupled to another register group. For example, the multiple shift registers are divided into N cascaded groups, and each shift register in the same cascaded group is coupled to gate lines spaced N-1 rows apart; N is an integer greater than 1. Taking gate lines GA1~GA24, clock signal lines CK1~CK8, and frame start signal lines STV1~STV4 as examples, ... Figures 6 to 7dAs shown, the gate drive circuit 110 includes shift registers SR1 to SR24. The drive output terminal GOUT of shift register SR1 is coupled to the gate line GA1, the drive output terminal GOUT of shift register SR2 is coupled to the gate line GA2, the drive output terminal GOUT of shift register SR3 is coupled to the gate line GA3, ... the drive output terminal GOUT of shift register SR23 is coupled to the gate line GA23, and the drive output terminal GOUT of shift register SR24 is coupled to the gate line GA24. Taking N=4 as an example, shift registers SR1 to SR24 are divided into 4 cascaded groups: the first cascade group ZSR1 to the fourth cascade group ZSR4. Specifically, the first cascade group ZSR1 is coupled to the first frame start signal line STV1, the second cascade group ZSR2 is coupled to the second frame start signal line STV2, the third cascade group ZSR3 is coupled to the third frame start signal line STV3, and the fourth cascade group ZSR4 is coupled to the fourth frame start signal line STV4. Furthermore, the first cascade group ZSR1 is coupled to the first clock signal line CK1 and the fifth clock signal line CK5, the second cascade group ZSR2 is coupled to the second clock signal line CK2 and the sixth clock signal line CK6, the third cascade group ZSR3 is coupled to the third clock signal line CK3 and the seventh clock signal line CK7, and the fourth cascade group ZSR4 is coupled to the fourth clock signal line CK4 and the eighth clock signal line CK8. Furthermore, the first cascade group is coupled to the 4k-3 gate line, the second cascade group is coupled to the 4k-2 gate line, the third cascade group is coupled to the 4k-1 gate line, and the fourth cascade group is coupled to the 4k gate line. k is an integer greater than 0.

[0060] For example, such as Figure 6 and Figure 7a As shown, the first cascade group ZSR1 includes shift registers SR1, SR5, SR9, SR13, SR17, and SR21. The input signal terminal IP of shift register SR1 is coupled to the first frame start signal line STV1. The drive output terminal GOUT of shift register SR1 is coupled to the input signal terminal IP of shift register SR5. The drive output terminal GOUT of shift register SR5 is coupled to the reset signal terminal RE of shift register SR1. The drive output terminal GOUT of shift register SR5 is coupled to the input signal terminal IP of shift register SR9. The drive output terminal GOUT of shift register SR9 is coupled to the reset signal terminal RE of shift register SR5. The rest are similarly coupled and will not be elaborated further. Furthermore, the clock signal terminals of shift registers SR1, SR9, and SR17 are all coupled to the first clock signal line CK1. The clock signal terminals of shift registers SR5, SR13, and SR21 are all coupled to the fifth clock signal line CK5.

[0061] For example, such as Figure 6 and Figure 7bAs shown, the second cascade group ZSR2 includes shift registers SR2, SR6, SR10, SR14, SR18, and SR22. The input signal terminal IP of shift register SR2 is coupled to the second frame start signal line STV2. The drive output terminal GOUT of shift register SR2 is coupled to the input signal terminal IP of shift register SR6. The drive output terminal GOUT of shift register SR6 is coupled to the reset signal terminal RE of shift register SR2. The drive output terminal GOUT of shift register SR6 is coupled to the input signal terminal IP of shift register SR10. The drive output terminal GOUT of shift register SR10 is coupled to the reset signal terminal RE of shift register SR6. The rest are similarly coupled and will not be elaborated further. Furthermore, the clock signal terminals of shift registers SR2, SR10, and SR18 are all coupled to the second clock signal line CK2. The clock signal terminals of shift registers SR6, SR14, and SR22 are all coupled to the sixth clock signal line CK6.

[0062] For example, such as Figure 6 and Figure 7c As shown, the third cascade group ZSR3 includes shift registers SR3, SR7, SR11, SR15, SR19, and SR23. The input signal terminal IP of shift register SR3 is coupled to the third frame start signal line STV3. The drive output terminal GOUT of shift register SR3 is coupled to the input signal terminal IP of shift register SR7. The drive output terminal GOUT of shift register SR7 is coupled to the reset signal terminal RE of shift register SR3. The drive output terminal GOUT of shift register SR7 is coupled to the input signal terminal IP of shift register SR11. The drive output terminal GOUT of shift register SR11 is coupled to the reset signal terminal RE of shift register SR7. The rest are similarly coupled and will not be elaborated further. Furthermore, the clock signal terminals of shift registers SR3, SR11, and SR19 are all coupled to the third clock signal line CK3. The clock signal terminals of shift registers SR7, SR15, and SR23 are all coupled to the seventh clock signal line CK7.

[0063] For example, such as Figure 6 and Figure 7dAs shown, the fourth cascade group ZSR4 includes shift registers SR4, SR8, SR12, SR16, SR20, and SR24. The input signal terminal IP of shift register SR4 is coupled to the fourth frame start signal line STV4. The drive output terminal GOUT of shift register SR4 is coupled to the input signal terminal IP of shift register SR8. The drive output terminal GOUT of shift register SR8 is coupled to the reset signal terminal RE of shift register SR4. The drive output terminal GOUT of shift register SR8 is coupled to the input signal terminal IP of shift register SR12. The drive output terminal GOUT of shift register SR12 is coupled to the reset signal terminal RE of shift register SR8. The rest are similarly coupled and will not be elaborated further. Furthermore, the clock signal terminals of shift registers SR4, SR12, and SR20 are all coupled to the fourth clock signal line CK4. The clock signal terminals of shift registers SR8, SR16, and SR24 are all coupled to the eighth clock signal line CK8.

[0064] In some embodiments of this disclosure, cascade groups coupled to odd-numbered gate lines can be disposed at the first end of the plurality of gate lines, and cascade groups coupled to even-numbered gate lines can be disposed at the second end of the plurality of gate lines. For example, as... Figure 6 As shown, cascade groups coupled to odd-numbered gate lines can be placed on the left side of the multiple gate lines, and cascade groups coupled to even-numbered gate lines can be placed on the right side of the multiple gate lines. That is, the first cascade group ZSR1 and the third cascade group ZSR3 are placed on the left side of the multiple gate lines, and the second cascade group ZSR2 and the fourth cascade group ZSR4 are placed on the left side of the multiple gate lines.

[0065] In existing gate drive circuits, shift registers are typically cascaded row by row. This limits their ability to acquire target detection signals from detection units line by line. However, in FPXD (Flat Panel X-ray Detector) applications, especially in dynamic DR (Digital Radiation) or CBCT (Conebeam CT) applications, binning is used to increase the acquisition frame rate and quickly locate lesions. This involves merging multiple rows and columns to reduce resolution, thereby reducing read time and increasing the acquisition frame rate. The gate drive circuit provided in this disclosure divides shift registers into cascaded groups, with different cascaded groups coupled to different frame start signal lines and clock signal lines. This allows for control of each cascaded group to achieve different operating states in different read modes. Furthermore, in the first read mode, line-by-line scanning and reading are achieved. In the second read mode, simultaneous scanning and reading of multiple rows are achieved, further reducing read time and increasing the acquisition frame rate.

[0066] In some embodiments of this disclosure, the control method for the flat panel detector, such as Figure 8 As shown, it may include the following steps:

[0067] S10. In the first read mode, within one frame scan time, different frame start signals are loaded onto each frame start signal line, and different clock signals are loaded onto each clock signal line to control the sequential operation of each stage group, scanning multiple gate lines line by line. During gate line scanning, detection signals on each data line are collected to determine the target detection signal corresponding to each detection unit. Each shift register in the same cascade group scans the coupled gate lines line by line. For example, in the first read mode, each stage group outputs the first gate scan signal line by line to achieve line-by-line scanning of multiple gate lines. Optionally, the effective level of each first gate scan signal has the same duration. Optionally, the effective level of the clock signal loaded in the first read mode is used to output the effective level of the first gate scan signal. Optionally, the effective level of the clock signal loaded in the first read mode has the same duration. Optionally, the clock period of the clock signal loaded in the first read mode is the same.

[0068] For example, in the first read mode, Figure 6 The signal timing diagram corresponding to the gate drive circuit shown is as follows: Figure 9 As shown. In the first read mode, ck1_1 represents the clock signal input to the first clock signal line CK1, ck2_1 represents the clock signal input to the second clock signal line CK2, ck3_1 represents the clock signal input to the third clock signal line CK3, ck4_1 represents the clock signal input to the fourth clock signal line CK4, ck5_1 represents the clock signal input to the fifth clock signal line CK5, ck6_1 represents the clock signal input to the sixth clock signal line CK6, ck7_1 represents the clock signal input to the seventh clock signal line CK7, and ck8_1 represents the clock signal input to the eighth clock signal line CK8. stv1_1 represents the frame start signal input to the first frame start signal line STV1, stv2_1 represents the frame start signal input to the second frame start signal line STV2, stv3_1 represents the frame start signal input to the third frame start signal line STV3, and stv4_1 represents the frame start signal input to the fourth frame start signal line STV4.

[0069] Furthermore, signal ga1_1 represents the first gate scan signal output by gate drive circuit 110 to gate line GA1, signal ga2_1 represents the first gate scan signal output by gate drive circuit 110 to gate line GA2, ... signal ga22_1 represents the first gate scan signal output by gate drive circuit 110 to gate line GA22, signal ga23_1 represents the first gate scan signal output by gate drive circuit 110 to gate line GA23, and signal ga24_1 represents the first gate scan signal output by gate drive circuit 110 to gate line GA24. Taking a high level as the effective level of the first gate scan signal, shift register SR1 outputs the first high level of clock signal ck1_1 to gate line GA1 to generate the high level in the first gate scan signal ga1_1. Shift register SR2 outputs the first high level of clock signal ck2_1 to gate line GA2 to generate the high level in the first gate scan signal ga2_1. Shift register SR3 outputs the first high level of clock signal ck3_1 to gate line GA3 to generate the high level in the first gate scan signal ga3_1. Shift register SR4 outputs the first high level of clock signal ck4_1 to gate line GA4 to generate the high level in the first gate scan signal ga4_1. Shift register SR5 outputs the first high level of clock signal ck5_1 to gate line GA5 to generate the high level in the first gate scan signal ga5_1. Shift register SR6 outputs the first high level of clock signal ck6_1 to gate line GA6 to generate the high level in the first gate scan signal ga6_1. Shift register SR7 outputs the first high level of clock signal ck7_1 to gate line GA7 to generate the high level in the first gate scan signal ga7_1. Shift register SR8 outputs the first high level of clock signal ck8_1 to gate line GA8 to generate the high level in the first gate scan signal ga8_1. Shift register SR9 outputs the second high level of clock signal ck1_1 to gate line GA9 to generate the high level in the first gate scan signal ga9_1. Shift register SR10 outputs the second high level of clock signal ck2_1 to gate line GA10 to generate the high level in the first gate scan signal ga10_1. Shift register SR11 outputs the second high level of clock signal ck3_1 to gate line GA11 to generate the high level in the first gate scan signal ga11_1. Shift register SR12 outputs the second high level of clock signal ck4_1 to gate line GA12 to generate the high level in the first gate scan signal ga12_1. Shift register SR13 outputs the second high level of clock signal ck5_1 to gate line GA13 to generate the high level in the first gate scan signal ga13_1.Shift register SR14 outputs the second high level of clock signal ck6_1 to gate line GA14 to generate the high level in the first gate scan signal ga14_1. Shift register SR15 outputs the second high level of clock signal ck7_1 to gate line GA15 to generate the high level in the first gate scan signal ga15_1. Shift register SR16 outputs the second high level of clock signal ck8_1 to gate line GA16 to generate the high level in the first gate scan signal ga16_1. The rest follow the same logic and will not be elaborated further here.

[0070] In other words, the high-level duration of each clock signal ck1_1 to ck8_1 is the same, and the clock period of each clock signal ck1_1 to ck8_1 is the same. Furthermore, the high level of clock signals ck1_1 to ck8_1 can be considered their valid level, and the low level their invalid pulse. Of course, when the shift register outputs the low level of the clock signal to generate the low-level signal controlling the transistor's conduction in the first gate scan signal, the low level of the clock signal can be considered its valid level, and the high level its invalid pulse.

[0071] Combination Figure 2 and Figure 9 As shown, in practical applications, the scintillator absorbs X-rays and converts them into visible light. The photodiode converts the visible light generated by the scintillator into an electrical signal. When the first gate scan signal ga1_1~ga24_1 is high, i.e., when scanning gate lines GA1~GA24, the transistor 11 coupled to the gate lines GA1~GA24 is turned on. For example, when the first gate scan signal ga1_1 is high, i.e., when scanning gate line GA1, the transistor 11 in each detection unit coupled to the gate line GA1 is turned on, so that the electrical signal converted by the photodiode can be input to the data lines DA1~DA3 through the turned-on transistor 11. The acquisition circuit 220 can acquire the signals on the data lines DA1~DA3 and generate target detection signals corresponding to each detection unit in the first row. Subsequently, when the first gate scan signal ga2_1 is high, i.e., when scanning the gate line GA2, the transistors 11 in each detection unit coupled to the gate line GA2 are turned on, allowing the electrical signal converted by the photodiode to be input to the data lines DA1~DA3 through the turned-on transistors 11. The acquisition circuit 220 can acquire the signals on the data lines DA1~DA3 to generate target detection signals corresponding to each detection unit in the second row. The rest are similar, and so on, and will not be elaborated here. In this way, a target detection signal corresponding to each detection unit can be obtained, and imaging can be performed based on the target detection signal corresponding to each detection unit.

[0072] S20. When the second reading mode is adopted, within one frame scanning time, the same frame start signal is loaded onto at least some of the frame start signal lines coupled to the cascade groups, and the same clock signal is loaded onto at least some of the clock signal lines coupled to the cascade groups, to control at least some of the cascade groups to work simultaneously, scan multiple adjacent gate lines among the multiple gate lines simultaneously, and when the gate lines are scanned, collect the detection signals on the data lines to determine the target detection signals corresponding to each detection unit group one by one; wherein, the detection unit group includes detection units coupled to the simultaneously scanned gate lines and coupled to at least one data line, and each shift register pair in the same cascade group scans the coupled gate lines row by row. Exemplarily, when in the second reading mode, each cascade group outputs a second gate scan signal to multiple gate lines to achieve simultaneous scanning of multiple adjacent gate lines among the multiple gate lines. Optionally, the duration of maintaining the valid level of each second gate scan signal is the same. Optionally, the valid level of the clock signal loaded in the second reading mode is used to output the valid level of the second gate scan signal. Optionally, the duration of maintaining the valid level of the clock signal loaded in the second reading mode is the same. Optionally, the clock cycles of the clock signals loaded in the second reading mode are the same.

[0073] In some embodiments of the present disclosure, loading the same frame start signal onto at least some of the frame start signal lines coupled to the cascade groups, and loading the same clock signal onto at least some of the clock signal lines coupled to the cascade groups, to control at least some of the cascade groups to work simultaneously and scan multiple adjacent gate lines among the multiple gate lines simultaneously, includes: taking at least two adjacent gate lines as a gate line group, for a gate line group, loading the same frame start signal onto the frame start signal line corresponding to the cascade group coupled to the gate line group, and loading the same clock signal onto the clock signal line corresponding to the cascade group coupled to the gate line group, to control the cascade group coupled to the gate line group to work simultaneously and scan the gate lines in the gate line group simultaneously. Exemplarily, the number of gate lines in the same gate line group can be N / A. A is an integer, and 1 ≤ A < N, and N / A is an integer. For example, when N = 4, A = 2 or A = 1. When A = 2, the number of gate lines in the same gate line group can be 2, and the second gate scan signals loaded on these 2 gate lines are the same, so that these 2 gate lines can be driven simultaneously. When A = 1, the number of gate lines in the same gate line group can be 4, and the second gate scan signals loaded on these 4 gate lines are the same, so that these 4 gate lines can be driven simultaneously. Of course, in practical applications, it can be determined according to the actual application requirements, and is not limited herein.

[0074] In some embodiments of this disclosure, the cascaded groups coupled to adjacent gate line groups are different. For the first and second gate line groups in the two adjacent gate line groups, different frame start signals are loaded onto the frame start signal lines corresponding to the cascaded groups coupled to the first and second gate line groups, and different clock signals are loaded onto the clock signal lines corresponding to the cascaded groups coupled to the first and second gate line groups, controlling the cascaded groups coupled to the first and second gate line groups to operate sequentially, scanning the first and second gate line groups sequentially. For example, the sum of the number of gate lines in the first gate line group and the number of gate lines in the second gate line group can be equal to the number of cascaded groups. For example, when the number of gate lines in the first gate line group and the number of gate lines in the second gate line group are both 2, the first gate line group is coupled to the first cascade group ZSR1 and the second cascade group ZSR2, and the second gate line group is coupled to the third cascade group ZSR3 and the fourth cascade group ZSR4. Furthermore, the same frame start signal is applied to the first and second frame start signal lines, the same frame start signal is applied to the third and fourth frame start signal lines, and the frame start signal applied to the first and third frame start signal lines is different. Also, the same clock signal is applied to the first and second clock signal lines, the same clock signal is applied to the fifth and sixth clock signal lines, the same clock signal is applied to the third and fourth clock signal lines, and the same clock signal is applied to the seventh and eighth clock signal lines. The clock signals applied to the 1st, 3rd, 5th, and 7th clock signal lines are different.

[0075] In some embodiments of this disclosure, the clock signal loaded on the clock signal line corresponding to the cascaded group coupled to the first gate line group has the same clock period as the clock signal loaded on the clock signal line corresponding to the cascaded group coupled to the second gate line group, and the duty cycle of the clock signal loaded on the clock signal line corresponding to the cascaded group coupled to the first gate line group is 25%. For example, as... Figure 10As shown, in the second read mode, ck1_2 represents the clock signal input to the first clock signal line CK1, ck2_2 represents the clock signal input to the second clock signal line CK2, ck3_2 represents the clock signal input to the third clock signal line CK3, ck4_2 represents the clock signal input to the fourth clock signal line CK4, ck5_2 represents the clock signal input to the fifth clock signal line CK5, ck6_2 represents the clock signal input to the sixth clock signal line CK6, ck7_2 represents the clock signal input to the seventh clock signal line CK7, and ck8_2 represents the clock signal input to the eighth clock signal line CK8. The clock signals ck1_2 to ck8_2 have the same clock period and a duty cycle of 25%. Furthermore, clock signals ck1_2 and ck2_2 are the same, clock signals ck3_2 and ck4_2 are the same, clock signals ck5_2 and ck6_2 are the same, and clock signals ck7_2 and ck8_2 are the same. Furthermore, the clock signals ck1_2, ck3_2, ck5_2, and ck7_2 are different.

[0076] In some embodiments of this disclosure, the effective level of the frame start signal loaded on the frame start signal line corresponding to the cascaded group coupled to the first gate line group is 1 / 4 clock cycle ahead of the effective level of the frame start signal loaded on the frame start signal line corresponding to the cascaded group coupled to the second gate line group. For example, as... Figure 10 As shown, in the second read mode, stv1_2 represents the frame start signal input to the first frame start signal line STV1, stv2_2 represents the frame start signal input to the second frame start signal line STV2, stv3_2 represents the frame start signal input to the third frame start signal line STV3, and stv4_2 represents the frame start signal input to the fourth frame start signal line STV4. Specifically, stv1_2 and stv2_2 are the same, and stv3_2 and stv4_2 are the same. Furthermore, the effective level (e.g., high level) of the frame start signal stv1_2 is 1 / 4 clock cycle earlier than the effective level (e.g., high level) of the frame start signal stv3_2 (this clock cycle is the clock cycle of the clock signal ck1_2).

[0077] Furthermore, signal ga1_2 represents the second gate scan signal output by gate drive circuit 110 to gate line GA1, signal ga2_2 represents the second gate scan signal output by gate drive circuit 110 to gate line GA2, ... signal ga22_2 represents the second gate scan signal output by gate drive circuit 110 to gate line GA22, signal ga23_2 represents the second gate scan signal output by gate drive circuit 110 to gate line GA23, and signal ga24_2 represents the second gate scan signal output by gate drive circuit 110 to gate line GA24. Taking a high level as the effective level of the second gate scan signal, shift register SR1 outputs the first high level of clock signal ck1_2 to gate line GA1 to generate the high level in the second gate scan signal ga1_2. Shift register SR2 outputs the first high level of clock signal ck2_2 to gate line GA2 to generate the high level in the second gate scan signal ga2_2. Shift register SR3 outputs the first high level of clock signal ck3_2 to gate line GA3 to generate the high level in the second gate scan signal ga3_2. Shift register SR4 outputs the first high level of clock signal ck4_2 to gate line GA4 to generate the high level in the second gate scan signal ga4_2. Shift register SR5 outputs the first high level of clock signal ck5_2 to gate line GA5 to generate the high level in the second gate scan signal ga5_2. Shift register SR6 outputs the first high level of clock signal ck6_2 to gate line GA6 to generate the high level in the second gate scan signal ga6_2. Shift register SR7 outputs the first high level of clock signal ck7_2 to gate line GA7 to generate the high level in the second gate scan signal ga7_2. Shift register SR8 outputs the first high level of clock signal ck8_2 to gate line GA8 to generate the high level in the second gate scan signal ga8_2. Shift register SR9 outputs the second high level of clock signal ck1_2 to gate line GA9 to generate the high level in the second gate scan signal ga9_2. Shift register SR10 outputs the second high level of clock signal ck2_2 to gate line GA10 to generate the high level in the second gate scan signal ga10_2. Shift register SR11 outputs the second high level of clock signal ck3_2 to gate line GA11 to generate the high level in the second gate scan signal ga11_2. Shift register SR12 outputs the second high level of clock signal ck4_2 to gate line GA12 to generate the high level in the second gate scan signal ga12_2. Shift register SR13 outputs the second high level of clock signal ck5_2 to gate line GA13 to generate the high level in the second gate scan signal ga13_2.Shift register SR14 outputs the second high level of clock signal ck6_2 to gate line GA14 to generate the high level in the second gate scan signal ga14_2. Shift register SR15 outputs the second high level of clock signal ck7_2 to gate line GA15 to generate the high level in the second gate scan signal ga15_2. Shift register SR16 outputs the second high level of clock signal ck8_2 to gate line GA16 to generate the high level in the second gate scan signal ga16_2. The rest follow the same logic and will not be elaborated further here.

[0078] In other words, the high-level duration of each clock signal ck1_2 to ck8_2 is the same, and the clock period of each clock signal ck1_2 to ck8_2 is the same. Furthermore, the high level of clock signals ck1_2 to ck8_2 can be considered their valid level, and the low level their invalid pulse. Of course, when the shift register outputs the low level of the clock signal to generate the low-level signal controlling the transistor's conduction in the second gate scan signal, the low level of the clock signal can be considered its valid level, and the high level its invalid pulse.

[0079] In some examples, when using the second readout mode, the target detection signal corresponding to each detection unit group can be determined based on the rule that a target detection signal is obtained by acquiring a target detection signal for each data line separately. The detection unit group includes detection units coupled to simultaneously scanned grid lines and coupled to a single data line. For example, in combination with... Figure 2 , Figure 10 as well as Figure 11aAs shown, in practical applications, the scintillator absorbs X-rays and converts them into visible light. The photodiode converts the visible light generated by the scintillator into an electrical signal. When the second gate scan signals ga1_2~ga24_2 are high, i.e., when scanning gate lines GA1~GA24, the transistors 11 coupled to gate lines GA1~GA24 are turned on. For example, when the second gate scan signals ga1_2 and ga2_2 are both high, i.e., when scanning gate lines GA1 and GA2 simultaneously, the transistors 11 in each detection unit coupled to gate lines GA1 and GA2 are turned on simultaneously. This means that the transistors 11 in the first and second row detection units in the same column are turned on simultaneously. This allows the detection signals in the first and second row detection units in the same column to be input to the coupled data lines, thereby merging the detection signals in these two detection units into a single target detection signal. That is, the first and second row detection units in the same column are treated as a detection unit group ZSPX. Furthermore, when the second gate scan signals ga3_2 and ga4_2 are simultaneously high, i.e., when the gate lines GA3 and GA4 are scanned simultaneously, the transistors 11 in each detection unit coupled to the gate lines GA3 and GA4 are simultaneously turned on. This means that the transistors 11 in the third and fourth rows of detection units in the same column are simultaneously turned on. This allows the detection signals in the third and fourth rows of detection units in the same column to be input to the coupled data lines, thus merging the detection signals in these two detection units into a single target detection signal. In other words, the third and fourth rows of detection units in the same column are treated as a single detection unit group ZSPX. The rest follows the same principle and will not be elaborated further. This allows for simultaneous signal acquisition of two adjacent detection units in each column, obtaining a target detection signal corresponding to each detection unit group ZSPX. This enables imaging based on the target detection signal corresponding to each detection unit group ZSPX. Consequently, the resolution in the column direction is reduced to half of its original value, increasing the acquisition frame rate and reducing the readout time, which is beneficial for quickly locating lesions.

[0080] In some examples, when using the second readout mode, the target detection signal corresponding to each detection unit group can be determined based on the rule that a target detection signal is simultaneously acquired from the detection signals on adjacent m data lines; where 2≤m≤M; M is the number of simultaneously scanned gate lines; the detection unit group includes detection units coupled to the simultaneously scanned gate lines and coupled to the m data lines. For example, combined with... Figure 2 , Figure 10 as well as Figure 11bAs shown, when m=2, in practical applications, the scintillator absorbs X-rays and converts them into visible light. The photodiode converts the visible light generated by the scintillator into an electrical signal. When the second gate scan signals ga1_2~ga24_2 are high, that is, when scanning the gate lines GA1~GA24, the transistors 11 coupled to the gate lines GA1~GA24 are turned on. For example, when the second gate scan signals ga1_2 and ga2_2 are both high, that is, when scanning the gate lines GA1 and GA2 simultaneously, the transistors 11 in each detection unit coupled to the gate lines GA1 and GA2 are turned on simultaneously. Then, the transistors 11 in the first row and second row detection units in the same column are turned on simultaneously. This allows the detection signals in the first row and second row detection units in the first column and the first row and second row detection units in the second column to be input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the first row and second row detection units in the first column and the first row and second row detection units in the second column are combined into a detection unit group ZSPX. Furthermore, the detection signals from the first and second rows of detection units in the third column and the first and second rows of detection units in the fourth column are all input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the first and second rows of detection units in the third column and the first and second rows of detection units in the fourth column constitute a detection unit group ZSPX. Similarly, the detection signals from the first and second rows of detection units in the fifth column and the first and second rows of detection units in the sixth column are all input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the first and second rows of detection units in the fifth column and the first and second rows of detection units in the sixth column constitute a single detection unit group ZSPX. Finally, the detection signals from the first and second rows of detection units in the seventh column and the first and second rows of detection units in the eighth column are all input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the first and second rows of detection units in the seventh column and the first and second rows of detection units in the eighth column constitute a single detection unit group ZSPX.

[0081] Furthermore, when the second gate scan signals ga3_2 and ga4_2 are simultaneously high, i.e., when gate lines GA3 and GA4 are scanned simultaneously, the transistors 11 in each detection unit coupled to gate lines GA3 and GA4 are simultaneously turned on. This means that the transistors 11 in the first and second rows of detection units in the same column are simultaneously turned on. This allows the detection signals from the third and fourth rows of detection units in the first column and the third and fourth rows of detection units in the second column to be input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the third and fourth rows of detection units in the first column and the third and fourth rows of detection units in the second column are treated as a single detection unit group ZSPX. Similarly, the detection signals from the third and fourth rows of detection units in the third column and the third and fourth rows of detection units in the fourth column are input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the third and fourth rows of detection units in the third column and the third and fourth rows of detection units in the fourth column are treated as a single detection unit group ZSPX. Furthermore, the detection signals from the detection units in the third and fourth rows of the fifth column and the third and fourth rows of the sixth column are all input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the detection units in the third and fourth rows of the fifth column and the third and fourth rows of the sixth column are treated as a single detection unit group ZSPX. Similarly, the detection signals from the detection units in the third and fourth rows of the seventh column and the third and fourth rows of the eighth column are all input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the detection units in the third and fourth rows of the seventh column and the third and fourth rows of the eighth column are treated as a single detection unit group ZSPX. The rest are handled similarly, and will not be elaborated further here. This allows for simultaneous signal acquisition from two adjacent detection units in two adjacent columns (i.e., two rows and two columns of detection units), obtaining a target detection signal corresponding to each detection unit group ZSPX, thus achieving the goal of detecting M rows of... M columns of detection units form a scanning area, obtaining the target detection signal corresponding to each scanning area. This allows for imaging based on the target detection signal corresponding to each detection unit group ZSPX. Consequently, the resolution in both the column and row directions is reduced to half of the original, increasing the acquisition frame rate, reducing readout time, and facilitating rapid lesion location.

[0082] This disclosure provides other control methods for flat panel detectors, which are variations of the implementation methods in the above embodiments. The differences between this embodiment and the above embodiments are described below; similarities are not repeated here.

[0083] In some embodiments of this disclosure, adjacent gate line groups are coupled to the same cascade group. The same frame start signal is loaded onto the frame start signal lines corresponding to all cascade groups, and the same clock signal is loaded onto the clock signal lines corresponding to all cascade groups, controlling all cascade groups to operate simultaneously and scanning all gate lines in the same gate line group simultaneously. Exemplarily, the number of gate lines in the same gate line group is equal to the number of cascade groups. For example, when adjacent gate line groups are coupled to the same cascade group, the number of gate lines in the gate line group is 4, and each gate line group is coupled to the first cascade group ZSR1 to the fourth cascade group ZSR4. Furthermore, the same frame start signal is loaded onto the first to fourth frame start signal lines. Also, the same clock signal is loaded onto the first to fourth clock signal lines, and the same clock signal is loaded onto the fifth to eighth clock signal lines. The clock signals loaded onto the first and fifth clock signal lines are different.

[0084] In some embodiments of this disclosure, when two adjacent gate line groups are coupled in the same cascaded group, the clock signal loaded on the first clock signal line and the clock signal loaded on the fifth clock signal line have the same clock period but opposite levels, and the duty cycle of the clock signal loaded on the first clock signal line is 50%. For example, as... Figure 12 As shown, in the second read mode, ck1_3 represents the clock signal input to the first clock signal line CK1, ck2_3 represents the clock signal input to the second clock signal line CK2, ck3_3 represents the clock signal input to the third clock signal line CK3, ck4_3 represents the clock signal input to the fourth clock signal line CK4, ck5_3 represents the clock signal input to the fifth clock signal line CK5, ck6_3 represents the clock signal input to the sixth clock signal line CK6, ck7_3 represents the clock signal input to the seventh clock signal line CK7, and ck8_3 represents the clock signal input to the eighth clock signal line CK8. The clock signals ck1_3 to ck8_3 have the same clock period and a duty cycle of 50%. Furthermore, clock signals ck1_3 to ck4_3 are identical, clock signals ck5_3 and ck8_3 are identical, and the voltage levels of clock signals ck1_3 and ck8_3 are opposite.

[0085] For example, such as Figure 12 As shown, in the second read mode, stv1_3 represents the frame start signal input to the first frame start signal line STV1, stv2_3 represents the frame start signal input to the second frame start signal line STV2, stv3_3 represents the frame start signal input to the third frame start signal line STV3, and stv4_3 represents the frame start signal input to the fourth frame start signal line STV4. The frame start signals stv1_3 to stv4_3 are the same.

[0086] Furthermore, signal ga1_3 represents the second gate scan signal output by gate drive circuit 110 to gate line GA1, signal ga2_3 represents the second gate scan signal output by gate drive circuit 110 to gate line GA2, ... signal ga22_3 represents the second gate scan signal output by gate drive circuit 110 to gate line GA22, signal ga23_3 represents the second gate scan signal output by gate drive circuit 110 to gate line GA23, and signal ga24_3 represents the second gate scan signal output by gate drive circuit 110 to gate line GA24. Taking a high level as the effective level of the second gate scan signal, shift register SR1 outputs the first high level of clock signal ck1_3 to gate line GA1 to generate the high level in the second gate scan signal ga1_3. Shift register SR2 outputs the first high level of clock signal ck2_3 to gate line GA2 to generate the high level in the second gate scan signal ga2_3. Shift register SR3 outputs the first high level of clock signal ck3_3 to gate line GA3 to generate the high level in the second gate scan signal ga3_3. Shift register SR4 outputs the first high level of clock signal ck4_3 to gate line GA4 to generate the high level in the second gate scan signal ga4_3. Shift register SR5 outputs the first high level of clock signal ck5_3 to gate line GA5 to generate the high level in the second gate scan signal ga5_3. Shift register SR6 outputs the first high level of clock signal ck6_3 to gate line GA6 to generate the high level in the second gate scan signal ga6_3. Shift register SR7 outputs the first high level of clock signal ck7_3 to gate line GA7 to generate the high level in the second gate scan signal ga7_3. Shift register SR8 outputs the first high level of clock signal ck8_3 to gate line GA8 to generate the high level in the second gate scan signal ga8_3. Shift register SR9 outputs the second high level of clock signal ck1_3 to gate line GA9 to generate the high level in the second gate scan signal ga9_3. Shift register SR10 outputs the second high level of clock signal ck2_3 to gate line GA10 to generate the high level in the second gate scan signal ga10_3. Shift register SR11 outputs the second high level of clock signal ck3_3 to gate line GA11 to generate the high level in the second gate scan signal ga11_3. Shift register SR12 outputs the second high level of clock signal ck4_3 to gate line GA12 to generate the high level in the second gate scan signal ga12_3. Shift register SR13 outputs the second high level of clock signal ck5_3 to gate line GA13 to generate the high level in the second gate scan signal ga13_3.Shift register SR14 outputs the second high level of clock signal ck6_3 to gate line GA14 to generate the high level in the second gate scan signal ga14_3. Shift register SR15 outputs the second high level of clock signal ck7_3 to gate line GA15 to generate the high level in the second gate scan signal ga15_3. Shift register SR16 outputs the second high level of clock signal ck8_3 to gate line GA16 to generate the high level in the second gate scan signal ga16_3. The rest follow the same logic and will not be elaborated further here.

[0087] In other words, the high-level duration of each clock signal ck1_3 to ck8_3 is the same, and the clock period of each clock signal ck1_3 to ck8_3 is the same. Furthermore, the high level of clock signals ck1_3 to ck8_3 can be considered their valid level, and the low level their invalid pulse. Of course, when the shift register outputs the low level of the clock signal to generate the low-level signal controlling the transistor's conduction in the second gate scan signal, the low level of the clock signal can be considered its valid level, and the high level its invalid pulse.

[0088] In some examples, when using the second readout mode, the target detection signal corresponding to each detection unit group can be determined based on the rule that a target detection signal is simultaneously acquired from the detection signals on adjacent m data lines; where 2≤m≤M; M is the number of simultaneously scanned gate lines; the detection unit group includes detection units coupled to the simultaneously scanned gate lines and coupled to the m data lines. For example, combined with... Figure 2 , Figure 12 as well as Figure 13aAs shown, when m=2, in practical applications, the scintillator absorbs X-rays and converts them into visible light. The photodiode converts the visible light generated by the scintillator into an electrical signal. When the second gate scan signal ga1_3~ga24_3 is high, that is, when scanning the gate lines GA1~GA24, the transistor 11 coupled to the gate lines GA1~GA24 is turned on. For example, when the second gate scan signal ga1_3~ga4_3 is high at the same time, that is, when scanning the gate lines GA1~GA4 simultaneously, the transistor 11 in each detection unit coupled to the gate lines GA1~GA4 is turned on simultaneously. Then, the transistors 11 in the first to fourth rows of detection units in the same column are turned on simultaneously. This allows the detection signals in the first to fourth rows of detection units in the first column and the first to fourth rows of detection units in the second column to be input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the first to fourth rows of detection units in the first column and the first and second rows of detection units in the second column are combined into a detection unit group ZSPX. Furthermore, the detection signals from the detection units in rows 1 to 4 of the third column and the first to fourth of the fourth column are both input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the detection units in rows 1 to 4 of the third column and the first to fourth of the fourth column are treated as a single detection unit group ZSPX. Similarly, the detection signals from the detection units in rows 1 to 4 of the fifth column and the first to fourth of the sixth column are both input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the detection units in rows 1 to 4 of the fifth column and the first to fourth of the sixth column are treated as a single detection unit group ZSPX. Furthermore, the detection signals from the first to fourth rows of the seventh column and the first to fourth rows of the eighth column are all input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal, i.e., the first to fourth rows of the seventh column and the first to fourth rows of the eighth column are combined into a detection unit group ZSPX.

[0089] Furthermore, when the second gate scan signals ga5_3 and ga8_3 are simultaneously high, i.e., when the gate lines GA5~GA8 are scanned simultaneously, the transistors 11 in each detection unit coupled to the gate lines GA5~GA8 are simultaneously turned on. This means that the transistors 11 in the fifth to eighth rows of the same column are simultaneously turned on. This allows the detection signals from the fifth to eighth rows of the first column and the fifth to eighth rows of the second column to be input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the fifth to eighth rows of the first column and the fifth to eighth rows of the second column are treated as a single detection unit group ZSPX. Similarly, the detection signals from the fifth to eighth rows of the third column and the fifth to eighth rows of the fourth column are input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the fifth to eighth rows of the third column and the fifth to eighth rows of the fourth column are treated as a single detection unit group ZSPX. Furthermore, the detection signals from the detection units in rows 5 to 8 of the fifth column and the fifth to 8 of the sixth column are all input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the detection units in rows 5 to 8 of the fifth column and the fifth to 8 of the sixth column are treated as a single detection unit group ZSPX. Similarly, the detection signals from the detection units in rows 5 to 8 of the seventh column and the fifth to 8 of the eighth column are all input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the detection units in rows 5 to 8 of the seventh column and the fifth to 8 of the eighth column are treated as a single detection unit group ZSPX. The rest are handled similarly, and will not be elaborated further here. This allows for simultaneous signal acquisition from adjacent detection units in adjacent columns, obtaining a target detection signal corresponding to each detection unit group ZSPX, thus enabling imaging based on the target detection signal corresponding to each detection unit group ZSPX. This reduces the resolution in the column direction to 1 / 4 of the original, increases the acquisition frame rate, reduces the reading time, and facilitates rapid location of lesions.

[0090] For example, combined Figure 2 , Figure 12 as well as Figure 13bAs shown, when m=4, in practical applications, the scintillator absorbs X-rays and converts them into visible light. The photodiode converts the visible light generated by the scintillator into an electrical signal. When the second gate scan signal ga1_3~ga24_3 is high, that is, when scanning the gate lines GA1~GA24, the transistor 11 coupled to the gate lines GA1~GA24 is turned on. For example, when the second gate scan signal ga1_3~ga4_3 is high at the same time, that is, when scanning the gate lines GA1~GA4 simultaneously, the transistor 11 in each detection unit coupled to the gate lines GA1~GA4 is turned on simultaneously. Then, the transistors 11 in the first to fourth rows of the same column are turned on simultaneously. This allows the detection signals in the first to fourth rows of the first column to the fourth row of the fourth column to be input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the first to fourth rows of the first column to the fourth row of the fourth column are treated as a detection unit group ZSPX. In addition, the detection signals from the first to fourth rows of the fifth column to the first to fourth rows of the eighth column are all input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal, that is, the first to fourth rows of the fifth column to the first to fourth rows of the eighth column are treated as a detection unit group ZSPX.

[0091] Furthermore, when the second gate scan signals ga5_3 and ga8_3 are simultaneously high, i.e., when the gate lines GA5~GA8 are scanned simultaneously, the transistors 11 in each detection unit coupled to the gate lines GA5~GA8 are simultaneously turned on. This means that the transistors 11 in the fifth to eighth rows of the same column are simultaneously turned on. This allows the detection signals from the fifth to eighth rows of the first column to the fifth to eighth rows of the fourth column to be input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the fifth to eighth rows of the first column to the fifth to eighth rows of the fourth column are treated as a single detection unit group ZSPX. Similarly, the detection signals from the fifth to eighth rows of the fifth column are input to the coupled data lines, thereby merging the detection signals on these two data lines into a single target detection signal. That is, the fifth to eighth rows of the fifth column are treated as a single detection unit group ZSPX. The rest follow the same principle and will not be elaborated further here. This allows for simultaneous signal acquisition of four adjacent detection units in four adjacent columns (i.e., four rows and four columns of detection units), obtaining the target detection signal corresponding to each detection unit group ZSPX, thus achieving the goal of detecting M rows... M columns of detection units form a scanning area, obtaining the target detection signal corresponding to each scanning area. This allows for imaging based on the target detection signal corresponding to each detection unit group ZSPX. Consequently, the resolution in both the column and row directions is reduced to 1 / 4 of the original, increasing the acquisition frame rate and reducing readout time, which is beneficial for quickly locating lesions.

[0092] In some embodiments of this disclosure, the clock period of the clock signal loaded on the clock signal line in the first acquisition mode is greater than the clock period of the clock signal loaded on the clock signal line in the second acquisition mode. For example, in the first acquisition mode, the clock period of the clock signals ck1_1~ck8_1 loaded on the clock signal line is 4T. In the second acquisition mode, the clock period of the clock signals ck1_2~ck8_2 loaded on the clock signal line is 2T, and the clock period of the clock signals ck1_3~ck8_3 is T.

[0093] This disclosure also provides a control device for the flat panel detector, such as... Figure 1 As shown, it includes a driving circuit 210 and a data acquisition circuit 220. The driving circuit 210 is configured to, in a first read mode, load different frame start signals onto each frame start signal line and different clock signals onto each clock signal line within one frame scan time, controlling each cascaded group to operate sequentially and scan the multiple gate lines line by line; in a second read mode, within one frame scan time, load the same frame start signal onto at least some of the frame start signal lines coupled to the cascaded groups and the same clock signal onto the clock signal lines coupled to the at least some of the cascaded groups, controlling the at least some cascaded groups to operate simultaneously and scan adjacent gate lines simultaneously; wherein, each shift register in the same cascaded group scans the coupled gate lines line by line. The acquisition circuit 220 is configured to, when using the first read mode, acquire detection signals on each of the data lines during the gate line scanning to determine a target detection signal corresponding to each of the detection units; and when using the second read mode, acquire detection signals on the data lines during the gate line scanning to determine a target detection signal corresponding to each group of detection units; wherein the group of detection units includes detection units coupled to the simultaneously scanned gate lines and coupled to at least one of the data lines.

[0094] In some embodiments of this disclosure, the plurality of shift registers are divided into N cascaded groups, and the shift registers in the same cascaded group are respectively coupled to gate lines spaced N-1 rows apart; N is an integer greater than 1. The driving circuit is further configured to: take at least two adjacent gate lines as a gate line group, and for a gate line group, load the same frame start signal on the frame start signal line corresponding to the cascaded group coupled to the gate line group, and load the same clock signal on the clock signal line corresponding to the cascaded group coupled to the gate line group, thereby controlling the cascaded group coupled to the gate line group to work simultaneously and scanning the gate lines in the gate line group simultaneously.

[0095] It should be noted that the working principle and specific implementation method of this control device are the same as those of the control method in the above embodiments. Therefore, the working process of this control device can be implemented by referring to the specific implementation method of the control method in the above embodiments, and will not be repeated here.

[0096] This disclosure also provides a flat panel detection device, including a flat panel detector and a control device for the aforementioned flat panel detector. The principle by which this flat panel detection device solves the problem is similar to that of the aforementioned control device for the flat panel detector; therefore, the implementation of this flat panel detection device can refer to the implementation of the aforementioned control device for the flat panel detector, and the repetitions will not be repeated here. It should be noted that other essential components of this flat panel detection device are all understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure.

[0097] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0098] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1A device that provides the functions specified in one or more boxes.

[0099] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0100] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0101] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0102] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A control method for a flat panel detector, characterized in that, The flat panel detector includes: multiple grid lines, multiple data lines intersecting and insulated from the grid lines, a detection unit defined by the multiple grid lines and the multiple data lines, a gate driving circuit coupled to each of the grid lines, and multiple frame start signal lines and multiple clock signal lines coupled to the gate driving circuit; the gate driving circuit includes multiple shift registers, each shift register is coupled to one grid line, the multiple shift registers are divided into multiple cascaded groups, the shift registers in the same cascaded group are cascaded, and different cascaded groups are coupled to different frame start signal lines and different clock signal lines; The control method includes: When using the first read mode, within one frame scan time, different frame start signals are loaded onto each frame start signal line, and different clock signals are loaded onto each clock signal line to control the sequential operation of each cascaded group. The multiple gate lines are scanned line by line, and during the gate line scan, the detection signals on each data line are collected to determine the target detection signal corresponding to each detection unit. Among them, each shift register in the same cascaded group scans the coupled gate lines line by line. When using the second read mode, within one frame scan time, the same frame start signal is loaded onto at least some of the frame start signal lines coupled to the cascaded groups, and the same clock signal is loaded onto the clock signal lines coupled to the at least some of the cascaded groups, controlling the at least some of the cascaded groups to work simultaneously, scanning multiple adjacent gate lines among the multiple gate lines simultaneously, and acquiring the detection signal on the data line during the gate line scanning to determine the target detection signal corresponding to each detection unit group; wherein, the detection unit group includes detection units coupled to the simultaneously scanned gate lines and coupled to at least one of the data lines, and each shift register in the same cascaded group scans the coupled gate lines line by line.

2. The control method for a flat panel detector as described in claim 1, characterized in that, The multiple shift registers are divided into N cascaded groups, and each shift register in the same cascaded group is coupled to a gate line spaced N-1 rows apart; N is an integer greater than 1. The step of loading the same frame start signal onto at least some of the cascaded group coupled frame start signal lines, and loading the same clock signal onto at least some of the cascaded group coupled clock signal lines, to control the at least some of the cascaded groups to operate simultaneously, and to simultaneously scan multiple adjacent gate lines among the multiple gate lines, includes: A gate line group is formed by taking at least two adjacent gate lines. For a gate line group, the same frame start signal is applied to the frame start signal line corresponding to the cascade group coupled to the gate line group, and the same clock signal is applied to the clock signal line corresponding to the cascade group coupled to the gate line group. The cascade group coupled to the gate line group is controlled to work simultaneously, and the gate lines in the gate line group are scanned simultaneously.

3. The control method for a flat panel detector as described in claim 2, characterized in that, The cascaded groups coupled to two adjacent gate line groups are different. For the first gate line group and the second gate line group in the two adjacent gate line groups, different frame start signals are loaded onto the frame start signal lines corresponding to the cascaded groups coupled to the first gate line group and the cascaded groups coupled to the second gate line group. Different clock signals are loaded onto the clock signal lines corresponding to the cascaded groups coupled to the first gate line group and the cascaded groups coupled to the second gate line group. This controls the cascaded groups coupled to the first gate line group and the cascaded groups coupled to the second gate line group to work sequentially, and the first gate line group and the second gate line group are scanned sequentially.

4. The control method for a flat panel detector as described in claim 2, characterized in that, The cascaded groups of two adjacent gate line groups are identical. The same frame start signal is loaded onto the frame start signal line corresponding to all the cascaded groups, and the same clock signal is loaded onto the clock signal line corresponding to all the cascaded groups, so that all the cascaded groups can work simultaneously and all the gate lines in the same gate line group can be scanned simultaneously.

5. The control method for a flat panel detector as described in claim 3 or 4, characterized in that, N=4, the multiple clock signal lines include clock signal lines 1 to 8, and the multiple frame start signal lines include frame start signal lines 1 to 4. The plurality of cascade groups include cascade groups 1 to 4; wherein, cascade group 1 is coupled to gate line 4k-3, cascade group 2 is coupled to gate line 4k-2, cascade group 3 is coupled to gate line 4k-1, and cascade group 4 is coupled to gate line 4k, where k is an integer greater than 0; and, cascade group 1 is coupled to clock line 1, clock line 5, and start signal line 1, respectively; cascade group 2 is coupled to clock line 2, clock line 6, and start signal line 2, respectively; cascade group 3 is coupled to clock line 3, clock line 7, and start signal line 3, respectively; and cascade group 4 is coupled to clock line 4, clock line 8, and start signal line 4. When two adjacent gate line groups are coupled to different cascade groups, the first gate line group is coupled to the first cascade group and the second cascade group, the second gate line group is coupled to the third cascade group and the fourth cascade group, and the same frame start signal is loaded onto the first frame start signal line and the second frame start signal line, the same clock signal is loaded onto the first clock signal line and the second clock signal line, the same clock signal is loaded onto the fifth clock signal line and the sixth clock signal line; the same frame start signal is loaded onto the third frame start signal line and the fourth frame start signal line, the same clock signal is loaded onto the third clock signal line and the fourth clock signal line, and the same clock signal is loaded onto the seventh clock signal line and the eighth clock signal line. When two adjacent gate line groups are coupled to the same cascade group, each gate line group is coupled to the first cascade group to the fourth cascade group, and the same frame start signal is loaded onto the first frame start signal line to the fourth frame start signal line, the same clock signal is loaded onto the first clock signal line to the fourth clock signal line, and the same clock signal is loaded onto the fifth clock signal line to the eighth clock signal line.

6. The control method for a flat panel detector as described in claim 5, characterized in that, The effective level of the frame start signal loaded on the frame start signal line corresponding to the cascaded group coupled to the first gate line group is 1 / 4 clock cycle ahead of the effective level of the frame start signal loaded on the frame start signal line corresponding to the cascaded group coupled to the second gate line group. The clock signal loaded on the clock signal line corresponding to the cascaded group coupled to the first gate line group has the same clock period as the clock signal loaded on the clock signal line corresponding to the cascaded group coupled to the second gate line group, and the duty cycle of the clock signal loaded on the clock signal line corresponding to the cascaded group coupled to the first gate line group is 25%.

7. The control method for a flat panel detector as described in any one of claims 1-4, characterized in that, When the second reading mode is adopted, the target detection signal corresponding to the detection unit group is determined based on the rule that a target detection signal is obtained by simultaneously acquiring the detection signals on the adjacent m data lines; where 2≤m≤M; M is the number of grid lines scanned at the same time; the detection unit group includes detection units coupled to the grid lines scanned at the same time and coupled to the m data lines.

8. The control method for a flat panel detector as described in any one of claims 1-4, characterized in that, A cascade group coupled to the odd-numbered gate line is disposed at the first end of the plurality of gate lines, and a cascade group coupled to the even-numbered gate line is disposed at the second end of the plurality of gate lines.

9. A control device for a flat panel detector, characterized in that, The flat panel detector includes: multiple grid lines, multiple data lines intersecting and insulated from the grid lines, a detection unit defined by the multiple grid lines and the multiple data lines, a gate driving circuit coupled to each of the grid lines, and multiple frame start signal lines and multiple clock signal lines coupled to the gate driving circuit; the gate driving circuit includes multiple shift registers, each shift register is coupled to one grid line, the multiple shift registers are divided into multiple cascaded groups, the shift registers in the same cascaded group are cascaded, and each cascaded group is coupled to different frame start signal lines and different clock signal lines; The control device includes: The driving circuit is configured to, in a first read mode, load different frame start signals onto each of the frame start signal lines and different clock signals onto each of the clock signal lines within a frame scan time, controlling each of the cascaded groups to operate sequentially and scan the multiple gate lines line by line; and in a second read mode, load the same frame start signal onto the frame start signal lines coupled to at least a portion of the cascaded groups and the same clock signal onto the clock signal lines coupled to the at least a portion of the cascaded groups within a frame scan time, controlling the at least a portion of the cascaded groups to operate simultaneously and scan adjacent gate lines of the multiple gate lines simultaneously; wherein, each shift register in the same cascaded group scans the coupled gate lines line by line. The acquisition circuit is configured to, when using the first read mode, acquire detection signals on each of the data lines during the gate line scanning to determine a target detection signal corresponding to each of the detection units; and when using the second read mode, acquire detection signals on the data lines during the gate line scanning to determine a target detection signal corresponding to the detection unit group; wherein the detection unit group includes detection units coupled to the simultaneously scanned gate lines and coupled to at least one of the data lines.

10. The control device for the flat panel detector as described in claim 9, characterized in that, The multiple shift registers are divided into N cascaded groups, and the shift registers in the same cascaded group are coupled to gate lines spaced N-1 rows apart; N is an integer greater than 1. The driving circuit is further configured to: use at least two adjacent gate lines as a gate line group; for a gate line group, load the same frame start signal on the frame start signal line corresponding to the cascade group coupled to the gate line group, and load the same clock signal on the clock signal line corresponding to the cascade group coupled to the gate line group, control the cascade group coupled to the gate line group to work simultaneously, and scan the gate lines in the gate line group simultaneously.

11. A flat panel detection device, characterized in that, It includes a flat panel detector and a control device for the flat panel detector as described in claim 9 or 10.

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