Data extraction circuit
By designing a data extraction circuit in DDR5 and adjusting the timing relationship using the latch clock signal, the problem of mismatched data processing speed in DDR5 was solved, and accurate data extraction and processing were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-07
- Publication Date
- 2026-05-26
Smart Images
Figure CN116453557B_ABST
Abstract
Description
Technical Field
[0001] This application relates to, but is not limited to, a data extraction circuit. Background Technology
[0002] Currently, DRAM (Dynamic Random Access Memory) technology is developing rapidly, and the main types used include Synchronous Dynamic Random Access Memory (SDRAM), 2nd generation Double Data Rate (DDR2) SDRAM, 3rd generation Double Data Rate (DDR3) SDRAM, 4th generation Double Data Rate (DDR4) SDRAM and 5th generation Double Data Rate (DDR5) SDRAM.
[0003] However, there is a problem that the data processing speed cannot match the processor's data transmission speed, which causes DRAM to be unable to accurately distinguish the transmitted data in high-speed data transmission. Summary of the Invention
[0004] This application provides a data extraction circuit, characterized in that it includes:
[0005] The first input circuit has an input terminal that establishes first input data under the trigger of a first data clock signal, and its input terminal that establishes second input data under the trigger of a second data clock signal. It is used to latch the first input data and the second input data under the trigger of a latch clock signal.
[0006] The second input circuit has an input terminal that establishes first identifier data under the trigger of the first data clock signal, and its input terminal that also establishes second identifier data under the trigger of the second data clock signal, for latching the first identifier data and the second identifier data under the trigger of the latch clock signal.
[0007] The output circuit has a first output terminal and a second output terminal, which are connected to the first input circuit and the second input circuit. Under the control of the first identification data and the second identification data, the first input data is output at the first output terminal, and the second input data is output synchronously at the second output terminal.
[0008] The data extraction circuit provided in this application includes a first input circuit that latches first input data and second input data received within two clock cycles, and a second input circuit that latches first identification data and second identification data received within two clock cycles. This enables the output circuit to output first input data via its first output terminal and second input data via its second output terminal under the control of the first identification data and the second identification data, thereby realizing the extraction of input data received within two clock cycles. Attached Figure Description
[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0010] Figure 1 This is a schematic diagram of the structure of a data acquisition circuit provided in an embodiment of this application;
[0011] Figure 2 This is a schematic diagram of the structure of a data acquisition circuit provided in another embodiment of this application;
[0012] Figure 3 This is a schematic diagram of the structure of a data acquisition circuit provided in another embodiment of this application;
[0013] Figure 4A and Figure 4B The relationship between the data clock signal and the latch clock signal provided in this application;
[0014] Figure 5 This is a schematic diagram of the structure of a data acquisition circuit provided in another embodiment of this application;
[0015] Figure 6A and Figure 6B This is a data timing diagram of a data acquisition circuit provided in another embodiment of the present application.
[0016] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0017] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0018] For high-speed input signals, the data receiving and processing end with a slower internal processing speed will first receive and buffer the data, and then process the data according to the internal processing clock. However, for high-speed data sent in multiple batches, it is impossible to determine the order of receiving data according to the internal clock, which leads to data processing errors.
[0019] According to the JEDEC specification for DDR4, the input pins of DDR4 include command pins and address pins. The CPU sends command and address data (CMD / ADD) based on one clock cycle.
[0020] That is, in DDR4, such as Figure 1 As shown, the data acquisition circuit includes a data receiver 201, a data buffer 202, a flip-flop 203, and an instruction decoder 204. The data acquisition circuit also includes a clock receiver 205 and a clock buffer 206. The output of the data receiver 201 is connected to the input of the data buffer 202, and the output of the data buffer 202 is connected to the data input of the flip-flop 203. The clock receiver 205 is connected to the clock input of the flip-flop 203 through the clock buffer 206. The CPU sends instruction data and address data in one clock cycle. The data receiver 201 receives the instruction data and address data, the buffer 202 buffers the instruction data and address data, and the flip-flop 203, under the control of the clock signal, samples the input instruction data and address data and outputs the sampled data to the instruction decoder 204. The data processed by the instruction decoder 204 is within the same clock cycle, eliminating interference from processing data from multiple cycles simultaneously.
[0021] However, for DDR5, for an activation instruction, the CPU sends instruction data and address data (CMD / ADD) over two clock cycles. When the flag data (CS) is low (L), the first data clock (CK) of the operation instruction sent by the CPU contains instruction data, such as Command and BA / BG information. When the flag data (CS) is high (H), the second data clock (CK) of the operation instruction sent by the CPU contains address data, such as row address and column address data. The instruction data and address data are transmitted to the instruction decoder via the input / output interface. The instruction decoder needs to process the instruction data and address data received for an activation instruction, but it does not receive the flag data processing signal. This results in an inability to effectively distinguish between the received instruction data and address data, leading to decoding errors.
[0022] In DDR5, designing a data extraction circuit to distinguish information from the two clock cycles in the CPU's instruction transmission is particularly important. Furthermore, due to the high interface input speed in DDR5, limitations imposed by manufacturing processes and design necessitate a transformation of the data clock (CK) to suit the internal data processing speed of DDR5. Because the instruction decoder's internal processing clock differs from the interface data transmission clock, it becomes impossible to distinguish the information received within a single interface data transmission cycle based on the internal processing clock frequency. This further complicates the design of the data extraction circuit.
[0023] like Figure 2 As shown, one embodiment of this application provides a data extraction circuit. The data extraction circuit includes a first input circuit 110, a second input circuit 120, and an output circuit 130.
[0024] The data to be extracted includes first input data C0 and second input data C1. The data to be extracted is transmitted via two clock signal cycles, labeled as first data clock signal CK0 and second data clock signal CK1. First data clock signal CK0 and second data clock signal CK1 have the same clock period, and the phase of first data clock signal CK0 is 360° earlier than the phase of second data clock signal CK1.
[0025] The first identification data S1 is used to identify the type of the first input data C0, and the second identification data S2 is used to identify the type of the second input data C1. For example, the first identification data S1 indicates that the first input data C0 is instruction data, and the second identification data S2 indicates that the second input data C1 is address data.
[0026] The first input circuit 110 has an input terminal. Triggered by the first data clock signal CK0, a first input data C0 is established at the input terminal of the first input circuit 110. Triggered by the second data clock signal CK1, a second input data C1 is established at the input terminal of the first input circuit 110. That is, the input terminal of the first input circuit 110 receives the first input data C0 and the second input data C1 within two data clock cycles.
[0027] After establishing the first input data C0 and the second input data C1 at the input terminal of the first input circuit 110, the first input circuit 110 is also used to latch the first input data C0 and the second input data C1 under the trigger of the latch clock signal.
[0028] The second input circuit 120 also has an input terminal. Triggered by the first data clock signal CK0, a first identification data S1 is established at the input terminal of the second input circuit 120. Triggered by the second data clock signal CK1, a second identification data S2 is established at the input terminal of the second input circuit 120. That is, the second input circuit 120 receives the first identification data S1 and the second identification data S2 based on two data clock cycles.
[0029] After the first identification data S1 and the second identification data S2 are established at the input terminal of the second input circuit 120, the second input circuit 120 is also used to latch the first identification data S1 and the second identification data S2 under the trigger of the latch clock signal.
[0030] The output circuit 130 has an input terminal and two output terminals, labeled as the first output terminal CA1st and the second output terminal CA2nd, respectively. The input terminal of the output circuit 130 is connected to the output terminal of the first input circuit 110, and the input terminal of the output circuit 130 is also connected to the output terminal of the second input circuit 120.
[0031] The output circuit 130 is used to output the first input data C0 at the first output terminal CA1st and synchronously output the second input data C1 at the second output terminal CA2nd under the control of the first identification data S1 and the second identification data S2.
[0032] The first data clock signal CK0 and the second data clock signal CK1 are used to control the timing of establishing the first input data C0 and the second input data C1 at the input terminal of the first input circuit 110, and also to control the timing of establishing the first identification data S1 and the second identification data S2 at the input terminal of the second input circuit 120.
[0033] The latch clock signal is used to control the timing of the output of the first input data C0 and the second input data C1 at the output terminal of the first input circuit 110. Since the first input data C0 and the second input data C1 are established at different times at the input terminal of the first input circuit 110, the first input data C0 and the second input data C1 with different timings can be output at the output terminal of the first input circuit 110.
[0034] The latching clock signal is also used to control the timing of the output of the first identification data S1 and the second identification data S2 at the output terminal of the second input circuit 120. Since the first identification data S1 and the second identification data S2 are established at different times at the input terminal of the second input circuit 120, the first identification data S1 and the second identification data S2 with different timings can be output at the output terminal of the second input circuit 120.
[0035] By setting the timing relationship between the latch clock signal and the first data clock signal CK0 and the second data clock signal CK1, the timing relationship between the first input data C0, the second input data C1, the first identifier data S1 and the second identifier data S2 are adjusted so that the first input data C0 is output through the first output terminal CA1st of the output circuit 130 and the second input data C1 is output through the second output terminal CA2nd of the output circuit 130, controlled by the first identifier data S1 and the second identifier data S2.
[0036] In the above technical solution, the first input circuit 110 latches the first input data C0 and the second input data C1 received within two clock cycles, and the second input circuit 120 latches the first identification data S1 and the second identification data S2 received within two clock cycles, so that the output circuit 130, under the control of the first identification data S1 and the second identification data S2, outputs the first input data C0 through its first output terminal CA1st and the second input data C1 through its second output terminal CA2nd, so as to distinguish the input data received within the two clock cycles.
[0037] In one embodiment, reference Figure 3 The data extraction circuit also includes a clock circuit 140, which is connected to the clock terminal of the first input circuit 110 and the clock terminal of the second input circuit 120, for generating a first latch clock signal CKT and a second latch clock signal CKTB based on the first data clock signal CK0.
[0038] The first latch clock signal CKT and the second latch clock signal CKTB have the same clock period, the phase of the first latch clock signal CKT and the phase of the second latch clock signal CKTB are 180° apart, and the signal period of the first latch clock signal CKT is twice the signal period of the first data clock signal CK0.
[0039] In the above technical solution, the period of the two latched clock signals output by the output terminal of the clock circuit is twice that of the data clock signal. This can extend the clock period inside the data extraction circuit, thereby reducing the data processing rate inside the data extraction circuit, improving the data processing accuracy, and meeting the subsequent data processing requirements.
[0040] In one embodiment, reference Figure 3The first input circuit 110 includes a first latch circuit 111 and a second latch circuit 112. The first latch circuit 111 has one input terminal and two output terminals, labeled as first output terminal CA1 and second output terminal CA2, respectively. The two output terminals of the first latch circuit 111 are connected to the input terminals of the output circuit 130. The input terminal of the first latch circuit 111 is used to establish first input data C0 under the trigger of the first data clock signal CK0, and to establish second input data C1 under the trigger of the second data clock signal CK1.
[0041] The second latch circuit 112 is similar to the first latch circuit 111. It also has one input terminal and two output terminals, labeled as the first output terminal CA3 and the second output terminal CA4, respectively. The two output terminals of the second latch circuit 112 are connected to the input terminals of the output circuit 130. The input terminal of the second latch circuit 112 is used to establish the first input data C0 under the trigger of the first data clock signal CK0, and to establish the second input data C1 under the trigger of the second data clock signal CK1.
[0042] The second input circuit 120 includes a third latch circuit 121 and a fourth latch circuit 122. The third latch circuit 121 has an input terminal and an output terminal CS1. The output terminal CS1 of the third latch circuit 121 is connected to the control terminal of the output circuit 130. The input terminal of the third latch circuit 121 is used to establish first identifier data S1 under the trigger of the first data clock signal CK0, and to establish second identifier data S2 under the trigger of the second data clock signal CK1.
[0043] The fourth latch circuit 122 also has an input terminal and an output terminal CS2. The output terminal CS2 of the fourth latch circuit 122 is connected to the control terminal of the output circuit 130. The input terminal of the fourth latch circuit 122 is used to establish the first identification data S1 under the trigger of the first data clock signal CK0, and to establish the second identification data S2 under the trigger of the second data clock signal CK1.
[0044] The first latch circuit 111 and the second latch circuit 112 are used to output corresponding input data under the triggering of the first latch clock signal CKT and the second latch clock signal CKTB. The third latch circuit 121 and the fourth latch circuit 122 are used to output corresponding identification data under the triggering of the first latch clock signal CKT and the second latch clock signal CKTB.
[0045] When the phase relationship between the two latch clock signals and the two data clock signals is different, the data output from the two output terminals of the first latch circuit 111 and the data output from the two output terminals of the second latch circuit 112 will also change. The data output from the output terminal of the third latch circuit 121 and the data output from the output terminal of the fourth latch circuit 122 will also change.
[0046] When designing the latching sequence of the four latch circuits, the data output by the first latch circuit 111 corresponds to the data output by the third latch circuit 121, and the data output by the second latch circuit 112 corresponds to the data output by the fourth latch circuit 122. That is, when the first latch circuit 111 outputs the first input data C0, the third latch circuit 121 outputs the first identifier data S1. When the second latch circuit 112 outputs the second input data C1, the fourth latch circuit 122 outputs the second identifier data S2. This arrangement facilitates the design of the corresponding output circuit 130, ensuring that the first output terminal CA1st of the output circuit 130 outputs the first input data C0, and the second output terminal CA2nd outputs the second input data C1.
[0047] refer to Figure 4A If the rising edge of the first latch clock signal CKT corresponds to the rising edge of the first data clock signal CK0, and the rising edge of the second latch clock signal CKTB corresponds to the falling edge of the first latch clock signal CKT, then the first latch circuit 111 is used to sequentially establish the first input data C0 at the first output terminal CA1 and the second output terminal CA2 under the triggering of the first latch clock signal CKT and the second latch clock signal CKTB. That is, the first input data C0 is established first at the first output terminal CA1 of the first latch circuit 111, and then at the second output terminal CA2 of the first latch circuit 111. The second latch circuit 112 is used to sequentially establish the second input data C1 at the first output terminal CA3 and the second output terminal CA4 under the triggering of the first latch clock signal CKT and the second latch clock signal CKTB. That is, the second input data C1 is established first at the first output terminal CA3 of the second latch circuit 112, and then at the second output terminal CA4 of the second latch circuit 112.
[0048] Accordingly, the third latch circuit 121 establishes the first identification data S1 at its output terminal CS1 under the triggering of the first latch clock signal CKT and the second latch clock signal CKTB, and the fourth latch circuit 122 establishes the second identification data S2 at its output terminal CS2 under the triggering of the first latch clock signal CKT and the second latch clock signal CKTB.
[0049] refer to Figure 4BIf the rising edge of the second latch clock signal CKTB corresponds to the rising edge of the first data clock signal CK0, and the rising edge of the first latch clock signal CKT corresponds to the falling edge of the second latch clock signal CKTB, then the first latch circuit 111 is used to sequentially establish the second input data C1 at the first output terminal CA1 and the second output terminal CA2 under the triggering of the first latch clock signal CKT and the second latch clock signal CKTB. The second latch circuit 112 is used to sequentially establish the first input data C0 at the first output terminal CA3 and the second output terminal CA4 under the triggering of the first latch clock signal CKT and the second latch clock signal CKTB.
[0050] Accordingly, the third latch circuit 121 establishes the second identification data S2 at its output terminal CS1 under the triggering of the first latch clock signal CKT and the second latch clock signal CKTB, and the fourth latch circuit 122 establishes the first identification data S1 at its output terminal CS2 under the triggering of the first latch clock signal CKT and the second latch clock signal CKTB.
[0051] In the above technical solution, the input data and timing of the output terminals of the first latch circuit 111 and the second latch circuit 112 are controlled by two latch signals with a phase difference of 180° and the same period. These two latch signals are also used to control the identification data output by the output terminals of the third latch circuit 121 and the fourth latch circuit 122. Therefore, the output circuit 130 can be controlled to output the first input data C0 via its first output terminal CA1st and the second input data C1 via its second output terminal CA2nd, based on the identification data. Furthermore, when the rising edge of the first latch clock signal CKT corresponds to the rising edge of the first data clock signal CK0, or when the rising edge of the second latch clock signal CKTB corresponds to the rising edge of the first data clock signal CK0, the first output terminal CA1st can output the first input data, and the second output terminal CA2nd can output the second input data.
[0052] In one embodiment, reference continues Figure 3 The output circuit 130 includes a first selection circuit 131 and a second selection circuit 132. The first selection circuit 131 has two input terminals, two control terminals, and one output terminal, with the output terminal serving as the first output terminal CA1st. The two input terminals are labeled as the first input terminal and the second input terminal, respectively, and the two control terminals are labeled as the first control terminal and the second control terminal, respectively.
[0053] The first input terminal of the first selection circuit 131 is connected to the second output terminal CA2 of the first latch circuit 111, and the second input terminal of the first selection circuit 131 is connected to the second output terminal CA4 of the second latch circuit 112. The first control terminal of the first selection circuit 131 is connected to the output terminal CS1 of the third latch circuit 121, and the second control terminal of the first selection circuit 131 is connected to the output terminal CS2 of the fourth latch circuit 122. The first selection circuit 131 is used to establish the first input data C0 at its output terminal under the control of the first identification data S1 and the second identification data S2.
[0054] With this configuration, if the rising edge of the first latch clock signal CKT corresponds to the rising edge of the first data clock signal CK0, the first input terminal of the first selection circuit 131 receives the first input data C0, and the second input terminal of the first selection circuit 131 receives the second input data C1. If the rising edge of the second latch clock signal CKTB corresponds to the rising edge of the first data clock signal CK0, the first input terminal of the first selection circuit 131 receives the second input data C1, and the second input terminal of the first selection circuit 131 receives the first input data C0. That is, when the timing of the latch clock signal and the data clock signal is different, the first selection circuit 131 will receive both the first input data C0 and the second input data C1. Then, based on the first identifier data S1 and the second identifier data S2, it selects the first input data C0 from the first input data C0 and the second input data C1 for output, ensuring that the first output terminal CA1st of the output circuit 130 outputs the first input data C0 when the timing of the latch clock signal and the data clock signal is different.
[0055] The second selection circuit 132 has two input terminals, two control terminals, and one output terminal, with the output terminal serving as the second output terminal CA2nd of the output circuit. The two input terminals are labeled as the first input terminal and the second input terminal, respectively, and the two control terminals are labeled as the first control terminal and the second control terminal, respectively.
[0056] The first input terminal of the second selection circuit 132 is connected to the first output terminal CA3 of the second latch circuit 112, and the second input terminal of the second selection circuit 132 is connected to the first output terminal CA1 of the first latch circuit 111. The first control terminal of the second selection circuit 132 is connected to the output terminal CS1 of the third latch circuit 121, and the second control terminal of the second selection circuit 132 is connected to the output terminal CS2 of the fourth latch circuit 122. The second selection circuit 132 is used to establish the second input data C1 at its output terminal under the control of the first identification data S1 and the second identification data S2.
[0057] With this configuration, if the rising edge of the first latch clock signal CKT corresponds to the rising edge of the first data clock signal CK0, the first input terminal of the second selection circuit 132 receives the second input data C1, and the second input terminal of the second selection circuit 132 receives the first input data C0. If the rising edge of the second latch clock signal CKTB corresponds to the rising edge of the first data clock signal CK0, the first input terminal of the second selection circuit 132 receives the first input data C0, and the second input terminal of the second selection circuit 132 receives the second input data C1. In other words, the second selection circuit 132 receives the first input data C0 and the second input data C1, and then selects the second input data C1 from the first input data C0 and the second input data C1 based on the first identifier data S1 and the second identifier data S2, to ensure that the second output terminal CA2nd of the output circuit 130 outputs the second input data C1 when the timing of the latch clock signal and the data clock signal is different.
[0058] In one embodiment, the first input circuit 110 further includes a first receiving circuit 113. The output terminal of the first receiving circuit 113 is connected to the input terminal of the first latch circuit 111, and the output terminal of the first receiving circuit 113 is also connected to the input terminal of the second latch circuit 112. The first receiving circuit 113 is used to amplify the first input data C0 and the second input data C1 to enhance the signal of the two input data.
[0059] In one embodiment, the second input circuit 120 further includes a second receiving circuit 123. The output terminal of the second receiving circuit 123 is connected to the input terminal of the third latch circuit 121, and the output terminal of the second receiving circuit 123 is also connected to the input terminal of the fourth latch circuit 122. The second receiving circuit 123 is used to amplify the first identification data S1 and the second identification data S2 to enhance the signal of the two identification data.
[0060] In one embodiment, the clock circuit 140 includes a third receiving circuit 141 and a frequency divider circuit 142. The input terminal of the frequency divider circuit 142 is connected to the third receiving circuit 141, and the output terminal of the frequency divider circuit 142 is connected to the clock terminal of the first input circuit 110. The output terminal of the frequency divider circuit 142 is also connected to the clock terminal of the second input circuit 120. The third receiving circuit 141 is used to receive a first data clock signal CK0, and the frequency divider circuit 142 is used to perform frequency division processing on the first data clock signal CK0 to output a first latch clock signal CKT and a second latch clock signal CKTB. By performing frequency division processing on the data clock signal, the data processing speed inside the data extraction circuit can be reduced. The first data clock signal CK0 can be a single clock signal or a differential clock signal.
[0061] In one embodiment, the first input circuit 110 further includes a first buffer circuit 114. The input terminal of the first buffer circuit 114 is connected to the first receiving circuit 113, the output terminal of the first buffer circuit 114 is connected to the input terminal of the first latch circuit 111, and the output terminal of the first buffer circuit 114 is also connected to the input terminal of the second latch circuit 112. The first buffer circuit 114 is used to buffer the first input data C0 and the second input data C1 that are amplified by the signal.
[0062] The second input circuit 120 also includes a second buffer circuit 124. The input terminal of the second buffer circuit 124 is connected to the second receiving circuit 123, the output terminal of the second buffer circuit 124 is connected to the input terminal of the third latch circuit 121, and the output terminal of the second buffer circuit 124 is also connected to the input terminal of the fourth latch circuit 122. The second buffer circuit 124 is used to buffer the first identification data S1 and the second identification data S2 that are amplified by the signal.
[0063] The clock circuit 140 also includes a third buffer circuit 143, which is connected to the output of the frequency divider circuit 142. The third buffer circuit 143 is used to buffer the first latched clock signal CKT and the second latched clock signal CKTB.
[0064] In the above technical solution, by setting a buffer circuit inside the first input circuit, the second input circuit and the clock circuit, data loss caused by the difference between the external clock and the internal clock of the data extraction circuit can be avoided, and the synchronization of the two input data, the two identification data and the latch clock signal can also be guaranteed.
[0065] In one embodiment, reference Figure 5 The first latch circuit 111 includes a first flip-flop F1 and a second flip-flop F2. The input terminal of the first flip-flop F1 receives the first input data C0 and the second input data C1, the clock terminal of the first flip-flop F1 receives the first latch clock signal CKT, and the output terminal of the first flip-flop F1 is the first output terminal CA1 of the first latch circuit 111.
[0066] The input of the second flip-flop F2 is connected to the output of the first flip-flop F1. The clock terminal of the second flip-flop F2 receives the second latch clock signal CKTB. The output of the second flip-flop F2 is the second output terminal CA2 of the first latch circuit 111.
[0067] Continue to refer to Figure 5The second latch circuit 112 includes a third flip-flop F3 and a fourth flip-flop F4. The input terminal of the third flip-flop F3 receives the first input data C0 and the second input data C1. The clock terminal of the third flip-flop F3 receives the second latch clock signal CKTB. The output terminal of the third flip-flop F3 is the first output terminal CA3 of the second latch circuit 112.
[0068] The input of the fourth flip-flop F4 is connected to the output of the third flip-flop F3. The clock terminal of the fourth flip-flop F4 is used to receive the first latch clock signal CKT. The output of the fourth flip-flop F4 is the second output terminal CA4 of the second latch circuit 112.
[0069] refer to Figure 6A If the rising edge of the first latch clock signal CKT and the rising edge of the first data clock signal CK0 are at the same time, the first latch clock signal CKT and the second latch clock signal CKTB are 180° out of phase.
[0070] Between time t0 and time t1, that is, at the rising edge of the first input clock cycle CK0 of the two input data clocks, the first input circuit 110 receives the first input data C0, that is, the first data clock cycle establishes the first input data C0 at the input terminal of the first flip-flop F1.
[0071] At time t1, the rising edge of the first latch clock signal CKT arrives, and the output of the first flip-flop F1 outputs the first input data C0, that is, the first output CA1 of the first latch circuit 111 outputs the first input data C0, and the first input data C0 is established at the input of the second flip-flop F2.
[0072] At time t2, the rising edge of the second latch clock signal CKTB arrives, and the second flip-flop F2 outputs the first input data C0 under the control of the second latch clock signal CKTB. That is, the first input data C0 is output at the second output terminal CA2 of the first latch circuit 111, and the phase of the first input data C0 output by the second output terminal CA2 is 180° later than the phase of the first input data C0 output by the first output terminal CA1.
[0073] Between time t1 and time t2, at the rising edge of the second data clock cycle CK1 of the two input data clocks, the first input circuit 110 receives the second input data C1, that is, the second input data C1 is established at the input terminal of the third flip-flop F3.
[0074] At time t2, the rising edge of the second latch clock signal CKTB arrives. Under the control of the second latch clock signal CKTB, the third flip-flop F3 outputs the second input data C1, that is, the second input data C1 is output at the first output terminal CA3 of the second latch circuit 112, and the second input data C1 is established at the input terminal of the fourth flip-flop F4.
[0075] At time t3, the rising edge of the first latch clock signal CKT arrives again. Under the control of the first latch clock signal CKT, the fourth flip-flop F4 outputs the second input data C1, that is, the second output terminal CA4 of the second latch circuit 112 outputs the second input data C1. The phase of the second input data C1 output by the second output terminal CA4 is 180° later than the phase of the second input data C1 output by the first output terminal CA3.
[0076] Continue to refer to Figure 6A If the rising edge of the first latch clock signal CKT corresponds to the rising edge of the first data clock signal CK0 at the same time, the time t2 at which the second output terminal CA2 of the first latch circuit 111 outputs the first input data C0 is the same as the time t2 at which the first output terminal CA3 of the second latch circuit 112 outputs the second input data C1. In other words, the time at which the first input terminal of the first selection circuit 131 establishes the first input data C0 is the same as the time at which the first input terminal of the second selection circuit 132 establishes the second input data C1. Thus, under the control of the first identification data S1 and the second identification data S2, the data at the first input terminal of the first selection circuit 131 is output through its output terminal, and the data at the first input terminal of the second selection circuit 132 is output through its output terminal, so as to realize that the first input data C0 is output at the output terminal of the first selection circuit 131 and the second input data C1 is output synchronously at the output terminal of the second selection circuit 132.
[0077] refer to Figure 6B If the rising edge of the second latch clock signal CKTB is at the same time as the rising edge of the first data clock signal CK0, the first latch clock signal CKT and the second latch clock signal CKTB are 180° out of phase.
[0078] Between time t4 and time t5, that is, at the rising edge of the first input clock cycle CK0 of the two input data clocks, the first input circuit 110 receives the first input data C0, that is, the first input data C0 is established at the input terminal of the third flip-flop F3.
[0079] At time t5, the rising edge of the second latch clock signal CKTB arrives, and the output of the third flip-flop F3 outputs the first input data C0, that is, the first output CA3 of the second latch circuit 112 outputs the first input data C0, and the first input data C0 is established at the input of the fourth flip-flop F4.
[0080] At time t6, the rising edge of the first latch clock signal CKT arrives, and the fourth flip-flop F4 outputs the first input data C0 under the control of the first latch clock signal CKT. That is, the second output terminal CA4 of the second latch circuit 112 outputs the first input data C0, and the phase of the first input data C0 output by the second output terminal CA4 is 180° later than the phase of the first input data C0 output by the first output terminal CA3.
[0081] Between time t5 and time t6, that is, at the rising edge of the second input clock cycle CK1 of the two input data clocks, the first input circuit 110 receives the second input data C1, that is, the input terminal of the first flip-flop F1 establishes the second input data C1.
[0082] At time t6, the rising edge of the first latch clock signal CKT arrives, and the output of the first flip-flop F1 outputs the second input data C1. That is, the first output CA1 of the first latch circuit 111 outputs the second input data C1, and the second input data C1 is established at the input of the second flip-flop F2.
[0083] At time t7, the rising edge of the second latch clock signal CKTB arrives again, and the output of the second flip-flop F2 outputs the second input data C1, that is, the second output terminal CA2 of the first latch circuit 111 outputs the second input data C1, and the phase of the second input data C1 output by the second output terminal CA2 is 180° later than the phase of the second input data C1 output by the first output terminal CA1.
[0084] If the rising edge of the second latch clock signal CKTB corresponds to the rising edge of the first data clock signal CK0 at the same time, the time t6 at which the first input data C0 is output at the second output terminal CA4 of the second latch circuit 112 and the time t6 at which the second input data C1 is output at the first output terminal CA1 of the first latch circuit 111 are the same. The time at which the second input terminal of the first selection circuit 131 establishes the first input data C0 is the same as the time at which the second input terminal of the second selection circuit 132 establishes the second input data C1. Thus, under the control of the first identification data S1 and the second identification data S2, the data at the second input terminal of the first selection circuit 131 can be output through its output terminal, and the data at the second input terminal of the second selection circuit 132 can be output through its output terminal, so as to realize that the first input data C0 is output at the output terminal of the first selection circuit 131 and the second input data C1 is output synchronously at the output terminal of the second selection circuit 132.
[0085] Continue to refer to Figure 5 The third latch circuit 121 includes a fifth flip-flop F5 and a sixth flip-flop F6. The input of the fifth flip-flop F5 receives the first identification data S1 and the second identification data S2, and the clock input of the fifth flip-flop F5 receives the first latch clock signal CKT. The input of the sixth flip-flop F6 is connected to the output of the fifth flip-flop F5, the clock input of the sixth flip-flop F6 receives the second latch clock signal CKTB, and the output of the sixth flip-flop F6 is the output CS1 of the third latch circuit 121.
[0086] The fourth latch circuit 122 includes a seventh flip-flop F7 and an eighth flip-flop F8. The input of the seventh flip-flop F7 receives the first identification data S1 and the second identification data S2. The clock terminal of the seventh flip-flop F7 receives the second latch clock signal CKTB. The input of the eighth flip-flop F8 is connected to the output of the seventh flip-flop F7. The clock terminal of the eighth flip-flop F8 receives the first latch clock signal CKT. The output of the eighth flip-flop F8 is the output terminal CS2 of the fourth latch circuit 122.
[0087] refer to Figure 6A If the rising edge of the first latch clock signal CKT and the rising edge of the first data clock signal CK0 are at the same time, the first latch clock signal CKT and the second latch clock signal CKTB are 180° out of phase.
[0088] Between time t0 and time t1, that is, at the rising edge of the first input clock cycle CK0 of the two input data clocks, the second input circuit 120 receives the first identification data S1, that is, the first identification data S1 is established at the input of the fifth flip-flop F5.
[0089] At time t1, the rising edge of the first latch clock signal CKT arrives, and the output of the fifth flip-flop F5 outputs the first identifier data S1, which is also established at the input of the sixth flip-flop F6. At time t2, the second latch clock signal CKTB arrives, and the sixth flip-flop F6 outputs the first identifier data S1 under the control of the second latch clock signal CKTB, which means that the first identifier data S1 is output at the output terminal CS1 of the third latch circuit 121.
[0090] Between time t1 and time t2, that is, at the rising edge of the second input clock cycle CK1 of the two input data clocks, the second input circuit 120 receives the second identification data S2 and establishes the second identification data S2 at the input of the seventh flip-flop F7.
[0091] At time t2, the rising edge of the second latch clock signal CKTB arrives, and the seventh flip-flop F7 outputs the second identifier data S2 under the control of the second latch clock signal CKTB. At time t3, the rising edge of the first latch clock signal CKT arrives again, and the eighth flip-flop F8 outputs the second identifier data S2 under the control of the first latch clock signal CKT, that is, the second identifier data S2 is output at the output terminal CS2 of the fourth latch circuit 122.
[0092] refer to Figure 6B If the rising edge of the second latch clock signal CKTB is at the same time as the rising edge of the first data clock signal CK0, the first latch clock signal CKT and the second latch clock signal CKTB are 180° out of phase.
[0093] Between time t4 and time t5, that is, at the rising edge of the first input clock cycle CK0 of the two input data clocks, the second input circuit 120 receives the first identification data S1, and the input terminal of the seventh flip-flop F7 establishes the first identification data S1.
[0094] At time t5, the rising edge of the second latch clock signal CKTB arrives, and the output of the seventh flip-flop F7 outputs the first identifier data S1. At time t6, the rising edge of the first latch clock signal CKT arrives again, and the eighth flip-flop F8 outputs the first identifier data S1 under the control of the first latch clock signal CKT, that is, the first identifier data S1 is output at the output terminal CS2 of the fourth latch circuit 122.
[0095] Between time t5 and time t6, which is the rising edge of the second input clock cycle CK1 of the two input data clocks, the second input circuit 120 receives the second identification data S2, that is, the input terminal of the fifth flip-flop F5 establishes the second identification data S2.
[0096] At time t6, the rising edge of the first latch clock signal CKT arrives, and the output of the fifth flip-flop F5 outputs the second identifier data S2, which is also established at the input of the sixth flip-flop F6. At time t7, the rising edge of the second latch clock signal CKTB arrives again, and the output of the sixth flip-flop F6 outputs the second identifier data S2, which is also the output of the third latch circuit 121 at its output terminal CS1.
[0097] Continue to refer to Figure 5 The first selection circuit 131 includes a first transmission gate G1 and a second transmission gate G2. The input terminal of the first transmission gate G1 is the first input terminal of the first selection circuit 131, and is used to connect to the second output terminal CA2 of the first latch circuit 111. The control terminal of the first transmission gate G1 is the first control terminal of the first selection circuit 131, and the output terminal of the first transmission gate G1 is the output terminal of the first selection circuit 131, serving as the first output terminal CA1st of the output circuit.
[0098] The input terminal of the second transmission gate G2 is the second input terminal of the first selection circuit 131, and is used to connect to the second output terminal CA4 of the second latch circuit 112. The control terminal of the second transmission gate G2 is the second control terminal of the first selection circuit 131, and the output terminal of the second transmission gate G2 is connected to the output terminal of the first transmission gate G1.
[0099] The second selection circuit 132 includes a third transmission gate G3 and a fourth transmission gate G4. The input terminal of the third transmission gate G3 is the first input terminal of the second selection circuit 132, and is used to connect to the first output terminal CA3 of the second latch circuit 112. The control terminal of the third transmission gate G3 is the first control terminal of the second selection circuit 132, and the output terminal of the third transmission gate G3 is the output terminal of the second selection circuit 132, serving as the second output terminal CA2nd of the output circuit.
[0100] The input terminal of the fourth transmission gate G4 is the second input terminal of the second selection circuit 132, and is used to connect to the first output terminal CA1 of the first latch circuit 111. The control terminal of the fourth transmission gate G4 is the second control terminal of the second selection circuit 132, and the output terminal of the fourth transmission gate G4 is connected to the output terminal of the first transmission gate G1.
[0101] Continue to refer to Figure 6A The first identification data S1 is used to control the control terminal of the first transmission gate G1 and the control terminal of the third transmission gate G3. The second identification data S2 is used to control the control terminal of the second transmission gate G2 and the control terminal of the fourth transmission gate G4. The first identification data S1 is output at time t2. The first identification data S1 is low level, the first transmission gate G1 and the third transmission gate G3 are turned on. The first transmission gate G1 outputs the first input data C0 at time t2, and the third transmission gate G3 outputs the second input data C1 at time t2.
[0102] Continue to refer to Figure 6B The second identification data S2 is used to control the control terminal of the first transmission gate G1 and the control terminal of the third transmission gate G3. The first identification data S1 is used to control the control terminal of the second transmission gate G2 and the control terminal of the fourth transmission gate G4. The first identification data S1 is output at time t6. When the first identification data S1 is low, the second transmission gate G2 and the fourth transmission gate G4 are turned on. The second transmission gate G2 outputs the first input data C0 at time t6, and the fourth transmission gate G4 outputs the second input data C1 at time t6.
[0103] In the first input circuit 110, the structures of the first latch circuit and the second latch circuit are symmetrically configured to allow the first input circuit to output first input data and second input data with two different timing sequences. The first selection circuit is connected to both latch circuits to ensure that the first selection circuit can still receive the first input data even when the timing of the latch clock signal and the data clock signal is different. This ensures that the first selection circuit can output the first input data under the control of the first and second identifier data. The same principle ensures that the second selection circuit can output the second input data. By fixing the transmission channels for the first and second input data, the subsequent instruction decoder can accurately distinguish between the first and second input data based on the fixed data transmission channels, unaffected by the data input frequency and internal data processing frequency.
[0104] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0105] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A data extraction circuit, characterized by, include: The first input circuit (110) establishes first input data under the trigger of the first data clock signal and establishes second input data under the trigger of the second data clock signal. It is used to latch the first input data and the second input data under the trigger of the latch clock signal. The second input circuit (120) establishes first identification data at its input terminal under the trigger of the first data clock signal, and also establishes second identification data at its input terminal under the trigger of the second data clock signal, for latching the first identification data and the second identification data under the trigger of the latch clock signal. The output circuit (130) is provided with a first output terminal and a second output terminal. It is connected to the first input circuit (110) and also to the second input circuit (120). It is used to output the first input data at the first output terminal and synchronously output the second input data at the second output terminal under the control of the first identification data and the second identification data.
2. The data extraction circuit of claim 1, wherein, The first data clock signal and the second data clock signal have the same clock period, and the phase of the first data clock signal is 360° earlier than the phase of the second data clock signal; The latch clock signal includes a first latch clock signal and a second latch clock signal with the same clock period; the phase of the first latch clock signal and the phase of the second latch clock signal are 180° apart.
3. The data extraction circuit of claim 2, wherein, The first input circuit (110) includes: The first latch circuit (111) is provided with a first output terminal and a second output terminal, and is used to sequentially establish the first input data at the first output terminal and the second output terminal under the triggering of the first latch clock signal and the second latch clock signal; The second latch circuit (112) is provided with a first output terminal and a second output terminal, and is used to establish the second input data sequentially at the first output terminal and the second output terminal under the triggering of the first latch clock signal and the second latch clock signal; Wherein, the rising edge of the first latch clock signal corresponds to the same time as the rising edge of the first data clock signal.
4. The data extraction circuit of claim 2, wherein, The first input circuit (110) includes: The first latch circuit (111) has a first output terminal and a second output terminal, which are used to establish the second input data sequentially at the first output terminal and the second output terminal under the triggering of the first latch clock signal and the second latch clock signal; The second latch circuit (112) is provided with a first output terminal and a second output terminal, and is used to sequentially establish the first input data at the first output terminal and the second output terminal under the triggering of the first latch clock signal and the second latch clock signal; The rising edge of the second latch clock signal corresponds to the same time as the rising edge of the first data clock signal.
5. The data extraction circuit of claim 3 or 4, characterized in that ； The first latch circuit (111) includes: The first flip-flop (F1) receives the first input data and the second input data at its input terminal, receives the first latch clock signal at its clock terminal, and its output terminal is the first output terminal of the first latch circuit (111). The second flip-flop (F2) has its input connected to the output of the first flip-flop (F1), its clock terminal receives the second latch clock signal, and its output terminal is the second output terminal of the first latch circuit (111). The second latch circuit (112) includes: The third flip-flop (F3) receives the first input data and the second input data at its input terminal, receives the second latch clock signal at its clock terminal, and its output terminal is the first output terminal of the second latch circuit (112); The fourth flip-flop (F4) has its input connected to the output of the third flip-flop (F3), its clock terminal is used to receive the first latch clock signal, and its output terminal is the second output terminal of the second latch circuit (112).
6. The data extraction circuit according to claim 2, characterized in that, The second input circuit (120) includes: The third latch circuit (121) has an output terminal for establishing the first identification data at its output terminal under the triggering of the first latch clock signal and the second latch clock signal. The fourth latch circuit (122) has an output terminal, which is used to establish the second identification data at its output terminal when triggered by the second latch clock signal; The rising edge of the first latch clock signal corresponds to the same time as the rising edge of the second data clock signal.
7. The data extraction circuit according to claim 2, characterized in that, The second input circuit (120) includes: The third latch circuit (121) has an output terminal for establishing the second identification data at its output terminal under the triggering of the first latch clock signal and the second latch clock signal; The fourth latch circuit (122) has an output terminal, which is used to establish the first identification data at its output terminal when triggered by the second latch clock signal; The rising edge of the second latch clock signal corresponds to the same time as the rising edge of the second data clock signal.
8. The data extraction circuit according to claim 6 or 7, characterized in that; The third latch circuit (121) includes: The fifth flip-flop (F5) receives the first identification data and the second identification data at its input terminal, and receives the first latch clock signal at its clock terminal; The sixth flip-flop (F6) has its input connected to the output of the fifth flip-flop (F5), its clock terminal receives the second latch clock signal, and its output is the output of the third latch circuit (121). The fourth latch circuit (122) includes: The seventh flip-flop (F7) receives the first identification data and the second identification data at its input terminal, and receives the second latch clock signal at its clock terminal; The eighth flip-flop (F8) has its input connected to the output of the seventh flip-flop (F7), its clock terminal receives the first latch clock signal, and its output terminal is the output of the fourth latch circuit (122).
9. The data extraction circuit according to claim 3 or 4, characterized in that, The output circuit (130) includes: The first selection circuit (131) has its first input terminal connected to the second output terminal of the first latch circuit (111), its second input terminal connected to the second output terminal of the second latch circuit (112), its first control terminal connected to the output terminal of the third latch circuit (121), and its second control terminal connected to the output terminal of the fourth latch circuit (122), and is used to establish the first input data at its output terminal under the control of the first identification data and the second identification data; The second selection circuit (132) has its first input terminal connected to the first output terminal of the second latch circuit (112), its second input terminal connected to the first output terminal of the first latch circuit (111), its first control terminal connected to the output terminal of the third latch circuit (121), and its second control terminal connected to the output terminal of the fourth latch circuit (122). It is used to establish second input data at its output terminal under the control of the first identification data and the second identification data.
10. The data extraction circuit according to claim 9, Its characteristics are: The first selection circuit (131) includes: The first transmission gate (G1) has its input terminal as the first input terminal of the first selection circuit (131), its control terminal as the first control terminal of the first selection circuit (131), and its output terminal as the output terminal of the first selection circuit (131). The second transmission gate (G2) has its input terminal as the second input terminal of the first selection circuit (131), its control terminal as the second control terminal of the first selection circuit (131), and its output terminal connected to the output terminal of the first transmission gate (G1). The second selection circuit (132) includes: The third transmission gate (G3) has its input terminal as the first input terminal of the second selection circuit (132), its control terminal as the first control terminal of the second selection circuit (132), and its output terminal as the output terminal of the second selection circuit (132). The fourth transmission gate (G4) has its input terminal as the second input terminal of the second selection circuit (132), its control terminal as the second control terminal of the second selection circuit (132), and its output terminal connected to the output terminal of the first transmission gate (G1).
11. The data extraction circuit according to claim 3 or 4, characterized in that... ； The first input circuit (110) further includes: The first receiving circuit (113) has its output terminal connected to the input terminal of the first latch circuit (111) and its output terminal also connected to the input terminal of the second latch circuit (112), and is used to amplify the first input data and the second input data. The second input circuit (120) further includes: The second receiving circuit (123) has its output terminal connected to the input terminal of the third latch circuit (121) and its output terminal also connected to the input terminal of the fourth latch circuit (122), and is used to amplify the first identification data and the second identification data.
12. The data extraction circuit according to any one of claims 1 to 4, characterized in that, The data extraction circuit also includes: A clock circuit (140) is connected to the clock terminal of the first input circuit (110) and also to the clock terminal of the second input circuit (120), for generating a first latch clock signal and a second latch clock signal based on the first data clock signal.
13. The data extraction circuit according to claim 12, characterized in that, The clock circuit (140) specifically includes: The third receiving circuit (141) is used to receive the first data clock signal; The frequency divider circuit (142) is connected to the third receiving circuit (141). Its output terminal is connected to the clock terminal of the first input circuit (110), and its output terminal is also connected to the clock terminal of the second input circuit (120). It is used to perform frequency division processing on the first data clock signal to output the first latch clock signal and the second latch clock signal.
14. The data extraction circuit according to claim 13, characterized in that, The signal period of the first latch clock signal is twice the signal period of the first data clock signal.
15. The data extraction circuit according to claim 11, characterized in that... ； The first input circuit (110) further includes: The first buffer circuit (114) has its input terminal connected to the first receiving circuit (113), its output terminal connected to the input terminal of the first latch circuit (111), and its output terminal also connected to the input terminal of the second latch circuit (112), and is used to buffer the first input data and the second input data that are amplified by the signal. The second input circuit (120) further includes: The second buffer circuit (124) has its input connected to the second receiving circuit (123), its output connected to the input of the third latch circuit (121), and its output also connected to the input of the fourth latch circuit (122), and is used to buffer the first identification data and the second identification data that are amplified by the signal.
16. The data extraction circuit according to any one of claims 1 to 4, characterized in that, The first input data is instruction data, and the second input data is address data.