Semiconductor device and method of manufacturing the same
By controlling the etching rate of the protective layer during the semiconductor device fabrication process to form alignment grooves with a shallow depth, the problem of alignment failure in lithography machines has been solved, thereby improving the alignment accuracy and production efficiency of lithography machines.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-07
- Publication Date
- 2026-05-19
AI Technical Summary
In the prior art, during the rewiring process of semiconductor devices, the large depth of the alignment grooves leads to the problem of alignment failure in the lithography machine.
By forming a protective layer on top of the isolation material layer group and controlling the etching rate of the protective layer to be lower than that of the isolation material layer group, a shallow alignment groove is formed, which reduces the number of times the lithography laser is reflected in the groove and improves the alignment accuracy.
It improves the alignment accuracy of lithography machines, reduces the risk of alignment failure, increases production efficiency, and reduces production costs.
Smart Images
Figure CN116453944B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the semiconductor device. Background Technology
[0002] Redistribution layer (RDL) of semiconductor chips is the process of changing the contact positions (I / O pads) of the original IC circuit through wafer-level metal wiring and bumping processes, so that the IC can be adapted to different package forms.
[0003] However, during the current rewiring process, due to process limitations, the depth of the alignment grooves is relatively large, resulting in a large aspect ratio. This causes significant noise to the alignment of the lithography machine, which may lead to alignment failure.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art, which has a large depth of alignment groove, and to provide a semiconductor device with a smaller depth of alignment groove and a method for fabricating the semiconductor device.
[0006] According to one aspect of this disclosure, a method for fabricating a semiconductor device is provided, comprising:
[0007] A substrate is provided, including an alignment region and a connection region;
[0008] A first conductive layer is formed on the substrate;
[0009] An isolation material layer group is formed on the first conductive layer;
[0010] A protective layer is formed on top of the isolation material layer group, and the protective layer is located on the alignment region;
[0011] The isolation material layer group and the protective layer are etched, with the etching rate of the protective layer being less than the etching rate of the isolation material layer group, to remove the isolation material layer group on the connection area to form an isolation layer group, and an alignment groove is formed on the isolation layer group in the alignment area, the depth of the alignment groove being less than the thickness of the isolation layer group;
[0012] A second conductive layer group is formed on top of the isolation layer group and the first conductive layer, the second conductive layer group covering the alignment groove.
[0013] In one exemplary embodiment of this disclosure, the gases used to etch the isolation layer group and the protective layer include C4F6 and O2.
[0014] In one exemplary embodiment of this disclosure, an insulating material layer group is formed on the first conductive layer, including:
[0015] A first insulating material layer is formed on top of the first conductive layer;
[0016] A second isolation material layer is formed on top of the first isolation material layer;
[0017] A third isolation material layer is formed on top of the second isolation material layer, the thickness of the third isolation material layer being greater than the thickness of the first isolation material layer.
[0018] In one exemplary embodiment of this disclosure, the step of forming the alignment groove includes:
[0019] Remove the protective layer and part of the third isolation material layer to form the alignment groove on the third isolation material layer.
[0020] In one exemplary embodiment of this disclosure, the protective layer is removed before the second conductive layer group is formed.
[0021] In one exemplary embodiment of this disclosure, forming the second conductive layer group includes forming a multilayer conductive layer.
[0022] In one exemplary embodiment of this disclosure, forming a second conductive layer group over the isolation layer group and the first conductive layer includes:
[0023] A titanium metal layer is formed on the isolation layer group and the first conductive layer;
[0024] An aluminum metal layer is formed on top of the titanium metal layer;
[0025] A titanium nitride layer is formed on top of the aluminum metal layer.
[0026] In one exemplary embodiment of this disclosure, the connecting region is located on both sides of the aligning region.
[0027] According to another aspect of this disclosure, a semiconductor device is provided, comprising:
[0028] The substrate includes alignment regions and connection regions;
[0029] A first conductive layer is disposed on the substrate;
[0030] An isolation layer group is disposed on the first conductive layer and located on the alignment region. The isolation layer group is provided with an alignment groove, the depth of which is less than the thickness of the isolation layer group.
[0031] A second conductive layer group is disposed above the isolation layer group and the first conductive layer, and the second conductive layer group covers the alignment groove.
[0032] In one exemplary embodiment of this disclosure, the isolation layer group includes:
[0033] A first isolation layer is disposed on top of the first conductive layer;
[0034] The second isolation layer is disposed on top of the first isolation layer;
[0035] A third isolation layer is disposed on top of the second isolation layer, and the thickness of the third isolation layer is greater than the thickness of the first isolation layer.
[0036] In one exemplary embodiment of this disclosure, the depth of the alignment groove is less than the thickness of the third isolation layer.
[0037] In one exemplary embodiment of this disclosure, the depth of the alignment groove is between 0.4 and 0.6 micrometers.
[0038] In one exemplary embodiment of this disclosure, the second conductive layer group includes multiple conductive layers.
[0039] In one exemplary embodiment of this disclosure, the second conductive layer group includes:
[0040] A titanium metal layer is disposed on the isolation layer group and the first conductive layer;
[0041] An aluminum metal layer is disposed on top of the titanium metal layer;
[0042] A titanium nitride layer is disposed on the aluminum metal layer.
[0043] In one exemplary embodiment of this disclosure, the thickness of the titanium metal layer is between 0.1 and 0.15 micrometers, the thickness of the aluminum metal layer is between 4.2 and 4.7 micrometers, and the thickness of the titanium nitride layer is between 0.04 and 0.06 micrometers.
[0044] The semiconductor device fabrication method disclosed herein involves forming a protective layer on top of an isolation material layer group, with the protective layer located on an alignment region. During etching of the isolation material layer group and the protective layer, since the etching rate of the protective layer is lower than that of the isolation layer group, alignment grooves can be formed on the isolation material layer group in the alignment region while removing the isolation material layer group on the connection region. The depth of the alignment grooves is less than the thickness of the isolation material layer group, resulting in shallower grooves with a smaller depth-to-width ratio. When the lithography machine performs alignment, the laser emitted by the lithography machine reflects less within the alignment groove, reducing laser error and improving laser alignment accuracy. This allows the lithography machine to align well through the alignment grooves, mitigating alignment failures. Furthermore, the shallower alignment grooves are less prone to forming tilted structures at the bottom, which also facilitates alignment by the lithography machine.
[0045] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0047] Figure 1 This is a schematic flowchart illustrating an example embodiment of the method for fabricating a semiconductor device disclosed herein.
[0048] Figure 2 This is a schematic diagram of the substrate structure provided in the method for fabricating the semiconductor device disclosed herein.
[0049] Figure 3 In order to be in Figure 2 This is a schematic diagram of the structure after the first conductive layer is formed.
[0050] Figure 4 In order to be in Figure 3 This is a schematic diagram of the structure after the isolation layer group is formed based on the above.
[0051] Figure 5 In order to be in Figure 4 This is a schematic diagram of the structure after the protective layer is formed.
[0052] Figure 6 In order to be in Figure 5 The structural diagram is formed based on the preset pattern.
[0053] Figure 7 In order to be in Figure 6 The diagram shows the structure after etching.
[0054] Figure 8 In order to be in Figure 7 The structural diagram after removing the preset pattern is based on the above.
[0055] Figure 9 In order to be in Figure 8 This is a schematic diagram of the structure after the second conductive layer group is formed on the basis of the above.
[0056] Explanation of reference numerals in the attached figures:
[0057] 1. Substrate; 2. First conductive layer;
[0058] 3. Insulation material layer group; 31. First insulation material layer; 32. Second insulation material layer; 33. Third insulation material layer;
[0059] 4. Isolation layer group; 41. First isolation layer; 42. Second isolation layer; 43. Third isolation layer;
[0060] 7. Protective layer; 8. Alignment groove; 9. Preset pattern;
[0061] 10. Second conductive layer group; 101. Titanium metal layer; 102. Aluminum metal layer; 103. Titanium nitride layer;
[0062] A. Alignment region; B. Connecting region. Detailed Implementation
[0063] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.
[0064] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.
[0065] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.
[0066] This disclosure provides an example embodiment of a method for fabricating a semiconductor device, such as... Figure 1 As shown, the method for fabricating this semiconductor device may include the following steps:
[0067] Step S10: Provide a substrate 1, including an alignment region A and a connection region B.
[0068] Step S20: A first conductive layer 2 is formed on the substrate 1.
[0069] Step S30: An isolation material layer group 3 is formed on the first conductive layer 2.
[0070] Step S40: A protective layer 7 is formed on the isolation material layer group 3, and the protective layer 7 is located on the alignment region A.
[0071] Step S50: Etch the isolation material layer group 3 and the protective layer 7. The etching rate of the protective layer 7 is less than the etching rate of the isolation material layer group 3 to remove the isolation material layer group 3 on the connection area B to form an isolation layer group 4. And form an alignment groove 8 on the isolation layer group 4 in the alignment area A. The depth of the alignment groove 8 is less than the thickness of the isolation layer group 4.
[0072] In step S60, a second conductive layer group 10 is formed on the isolation layer group 4 and the first conductive layer 2, and the second conductive layer group 10 covers the alignment groove 8.
[0073] The semiconductor device fabrication method disclosed herein involves forming a protective layer 7 on an isolation material layer group 3, with the protective layer 7 located on an alignment region A. During etching of the isolation material layer group 3 and the protective layer 7, since the etching rate of the protective layer 7 is lower than the etching rate of the isolation layer group 4, an alignment groove 8 can be formed on the isolation material layer group 3 in the alignment region A while removing the isolation material layer group 3 on the connection region B. The depth of the alignment groove 8 is less than the thickness of the isolation material layer group 3, resulting in a shallower depth and smaller depth-to-width ratio. When the lithography machine is aligning, the laser emitted by the lithography machine reflects less within the alignment groove 8, reducing laser error and improving laser alignment accuracy. This allows the lithography machine to align well through the alignment groove 8, improving the problem of alignment failure. Furthermore, the shallower alignment groove 8 is less prone to forming a tilted structure at its bottom, which also facilitates alignment by the lithography machine. If the depth and width of the alignment groove 8 are relatively large, the laser emitted by the lithography machine will be reflected more times after hitting the alignment groove 8. The accuracy of the laser after multiple reflections will be reduced, which will affect the alignment of the lithography machine and lead to alignment failure.
[0074] The fabrication method of this semiconductor device will be described in detail below.
[0075] Step S10: Provide a substrate 1, including an alignment region A and a connection region B.
[0076] In this example embodiment, substrate 1 can be a semiconductor die that has already been fabricated. The semiconductor die can be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or simply a MOS transistor. The MOS transistor can be a PMOS (positive channel Metal-Oxide-Semiconductor) transistor or an NMOS (negative channel Metal-Oxide-Semiconductor) transistor. The MOS transistor can include storage capacitors, bit lines, word lines, gate, source, and drain, etc.
[0077] Reference Figure 2 As shown, substrate 1 may include alignment region A and connection region B. Specifically, there may be two connection regions B, which are located on both sides of alignment region A.
[0078] Of course, in other exemplary embodiments of this disclosure, the number of connected regions B can be set to multiple, and the specific location of connected regions B can be set as needed; the number of aligned regions A can also be set to multiple, and the specific location of aligned regions A can also be set as needed.
[0079] Step S20: A first conductive layer 2 is formed on the substrate 1.
[0080] In this example embodiment, a first conductive material layer is formed on a substrate 1 by methods such as deposition, sputtering, or evaporation, and then the first conductive material layer is etched to form a patterned first conductive layer 2. (Refer to...) Figure 3 As shown, the first conductive layer 2 is formed not only in the alignment region A but also in the connection region B. The first conductive layer 2 can be connected to the gate, source, or drain in the substrate 1. Signals can be input to the gate, source, or drain in the substrate 1 through the first conductive layer 2, or signals stored in the substrate 1 can be output through the first conductive layer 2. The material of the first conductive layer 2 is, for example, aluminum. The thickness of the first conductive layer 2 is, for example, between 0.6 and 1.0 micrometers, such as 0.6, 0.8, or 1.0 micrometers.
[0081] Of course, in other exemplary embodiments of this disclosure, the material of the first conductive layer 2 may include metals such as copper and silver.
[0082] Step S30: An isolation material layer group 3 is formed on the first conductive layer 2.
[0083] In this example implementation, refer to Figure 4 As shown, a first insulating material layer 31 is formed on the first conductive layer 2 by methods such as deposition, sputtering, or evaporation. The first insulating material layer 31 is formed not only in the alignment region A but also in the connection region B; that is, the orthogonal projection of the first insulating material layer 31 onto the substrate 1 lies within both the alignment region A and the connection region B. The material of the first insulating material layer 31 includes, for example, silicon oxide, and the thickness of the first insulating material layer 31 is, for example, between 0.6 and 1.0 micrometers; for example, the thickness of the first insulating material layer 31 can be 0.6, 0.8, or 1.0 micrometers.
[0084] A second isolation material layer 32 is formed on the first isolation material layer 31 by methods such as deposition, sputtering, or evaporation. The second isolation material layer 32 is formed not only in the alignment region A but also in the connection region B, that is, the orthogonal projection of the second isolation material layer 32 on the substrate 1 lies within the alignment region A and the connection region B. The material of the second isolation material layer 32 includes, for example, silicon nitride, and the thickness of the second isolation material layer 32 is, for example, between 0.5 and 0.7 micrometers, for example, 0.5, 0.6, or 0.7 micrometers.
[0085] A third isolation material layer 33 is formed on the second isolation material layer 32 by methods such as deposition, sputtering, or evaporation. The third isolation material layer 33 is formed not only in the alignment region A but also in the connection region B; that is, the orthogonal projection of the third isolation material layer 33 onto the substrate 1 lies within both the alignment region A and the connection region B. The material of the third isolation material layer 33 includes, for example, silicon oxide. The thickness of the third isolation material layer 33 is greater than the thickness of the first isolation material layer 31. The thickness of the third isolation material layer 33 is, for example, between 4.0 and 5.0 micrometers; for example, the thickness of the third isolation material layer 33 can be 4.0, 4.5, or 5.0 micrometers.
[0086] The isolation material layer 3 protects the substrate 1 and the first conductive layer 2. The relatively thick third isolation material layer 33 provides planarization, creating a better substrate for the subsequent formation of the second conductive layer 10. This facilitates the formation of a more uniform thickness of the second conductive layer 10, improving the conductivity uniformity of the semiconductor device. Furthermore, the thickness of the third isolation material layer 33 prevents erosion to the second isolation material layer 32 during the formation of the alignment groove 8, protecting the second isolation material layer 32 and preventing it from being exposed by the alignment groove 8, thus improving the performance of the semiconductor device.
[0087] Step S40: A protective layer 7 is formed on the isolation material layer group 3, and the protective layer 7 is located on the alignment region A.
[0088] In this example implementation, refer to Figure 5 As shown, a protective material layer is formed on the isolation material layer group 3 by methods such as deposition, sputtering, or evaporation. The protective material layer is then etched using a mixed gas of CHF3 and O2 to form a protective layer 7. The protective layer 7 is formed only in the alignment region A, and not in the connection region B. That is, the orthogonal projection of the protective layer 7 onto the substrate 1 is only located within the alignment region A. The material of the protective layer 7 includes, for example, silicon oxide, and the thickness of the protective layer 7 is between 0.4 and 0.6 micrometers. For example, the thickness of the protective layer 7 can be 0.4, 0.5, or 0.6 micrometers.
[0089] Step S50: Etch the isolation material layer group 3 and the protective layer 7. The etching rate of the protective layer 7 is less than the etching rate of the isolation material layer group 3 to remove the isolation material layer group 3 on the connection area B to form an isolation layer group 4. And form an alignment groove 8 on the isolation layer group 4 in the alignment area A. The depth of the alignment groove 8 is less than the thickness of the isolation layer group 4.
[0090] In this example implementation, refer to Figure 6As shown, photoresist is coated on the protective layer 7, and then the photoresist is exposed and developed to form a preset pattern 9, which is formed only in the alignment region A.
[0091] Reference Figure 6 As shown, in some embodiments, the third isolation material layer 33 can also be made of amorphous carbon, and the protective layer 7 can also be made of silicon oxide. Since the light absorption rate of the protective layer 7 is lower than that of the third isolation material layer 33, the protective layer 7 absorbs less light when photoresist is formed on it. Therefore, the protective layer 7 can reduce the degree of light absorption, thereby improving the accuracy of patterning. Simultaneously, since amorphous carbon is easier to etch than silicon oxide, it is beneficial for subsequent pattern transfer. Figure 6 As can be seen, since the thickness of the third isolation material layer 33 is greater than the thickness of the protective layer 7, if photoresist is formed directly on the third isolation material layer 33, the absorption rate of light by the third isolation material layer 33 is large, and the thickness of the third isolation material layer 33 is also large, which will reduce the accuracy of patterning.
[0092] Reference Figure 7 As shown, the isolation material layer group 3 and the protective layer 7 are etched. The isolation material layer group and the protective layer 7 located below the preset pattern 9 will not be etched because they are protected by the preset pattern 9; the isolation material layer group 3 and the protective layer 7 that are not protected by the preset pattern 9 will be etched.
[0093] However, because the etching rate of the etching gas on the protective layer 7 is lower than that on the isolation material layer group 3, after the same etching time, the etching depth of the isolation material layer group 3 is shallower in the alignment region A due to the obstruction of the protective layer 7; while in the connection region B, the etching depth of the isolation material layer group 3 is deeper due to the absence of the protective layer 7. Ultimately, after etching, the isolation material layer group 3 in the connection region B is completely etched away, forming the isolation layer group 4, which in turn forms a bump. The isolation layer group 4 in the alignment region A, which is not protected by the preset pattern 9, is not completely etched away; instead, an alignment groove 8 is formed on the third isolation material layer 33. The depth of the alignment groove 8 is not only less than the thickness of the isolation layer group 4, but also less than the thickness of the third isolation layer 43. The depth of the alignment groove 8 is, for example, between 0.4 and 0.6 micrometers; for example, the depth of the alignment groove 8 can be 0.4, 0.5, or 0.6 micrometers.
[0094] The gas used to etch the isolation material layer 3 and the protective layer 7 may include C4F6 and O2. The ratio of C4F6 to O2 may be (40-60):(20-40), for example, 50:30. Since the composition ratio of the etching gas can be adjusted, the isolation material layer 3 and the protective layer 7 can be etched better.
[0095] Because the protective layer 7 blocks the process, a thicker isolation layer group 4 can be formed in the same etching process, and a shallower alignment groove 8 can be formed on the isolation layer group 4. This saves one etching process, improves production efficiency, and reduces production costs.
[0096] Then, refer to Figure 8 As shown, the preset pattern 9 is removed. The material of the preset pattern 9 is photoresist, which can be removed by exposure and development. That is, the preset pattern 9 is exposed to light, and then the exposed preset pattern 9 is removed by developing solution. Of course, in some other example embodiments of this disclosure, the preset pattern 9 can also be removed by an ashing process.
[0097] Finally, the protective layer 7 is removed by etching with a mixed gas including CHF3, O2 and CF4.
[0098] It should be noted that in some embodiments, when the etching gas etches the isolation material layer group 3, the etching gas can also etch the preset pattern 9 and the protective layer 7. That is, while forming the groove 8, the preset pattern 9 and the protective layer 7 can be removed at the same time, thereby reducing the etching steps.
[0099] In step S60, a second conductive layer group 10 is formed on the isolation layer group 4 and the first conductive layer 2, and the second conductive layer group 10 covers the alignment groove 8.
[0100] In this example implementation, refer to Figure 9 As shown, a second conductive layer group 10 is formed on the isolation layer group 4 and the exposed first conductive layer 2 by methods such as deposition, sputtering, or evaporation. The second conductive layer group 10 covers the alignment groove 8. The orthographic projection of the second conductive layer group 10 on the substrate 1 is located in the alignment region A and the connection region B. The second conductive layer group 10 is connected to the first conductive layer 2 in the connection region B, thereby realizing the connection between the first conductive layer 2 and the external circuit. The second conductive layer group 10 can also be patterned to form new connection lines, achieving the purpose of line redistribution. The material of the second conductive layer group 10 includes, for example, aluminum.
[0101] Specifically, firstly, a titanium metal layer 101 is formed on the isolation layer group and the first conductive layer by methods such as deposition, sputtering, or evaporation; the thickness of the titanium metal layer 101 is, for example, between 0.1 and 0.15 micrometers, such as 0.12 micrometers. Then, an aluminum metal layer 102 is formed on the titanium metal layer 101 by methods such as deposition, sputtering, or evaporation; the thickness of the aluminum metal layer 102 is, for example, between 4.2 and 4.7 micrometers, such as 4.2, 4.5, or 4.7 micrometers. Then, a titanium nitride layer 103 is formed on the aluminum metal layer 102 by methods such as deposition, sputtering, or evaporation; the thickness of the titanium nitride layer 103 is, for example, between 0.04 and 0.06 micrometers, such as 0.05 micrometers. The titanium metal layer 101, the aluminum metal layer 102, and the titanium nitride layer 103 form the second conductive layer group 10.
[0102] As a redistribution layer, the aluminum metal layer 102 is not easily formed on the third isolation material layer 33, which makes it prone to open circuits. By placing the titanium metal layer 101 between the aluminum metal layer 102 and the third isolation material layer 33, on the one hand, the aluminum metal layer 102 is easily deposited on the titanium metal layer 101, that is, the titanium metal layer 101 can improve the adhesion of the aluminum metal layer 102 deposition, thereby reducing the occurrence of open circuits in the aluminum metal layer 102 due to insufficient deposition. On the other hand, even if there are open circuits in the aluminum metal layer 102, the titanium metal layer 101 can connect the open circuits in the aluminum metal layer 102, further preventing the occurrence of open circuits in the aluminum metal layer 102 and improving product yield.
[0103] In addition, since the aluminum metal layer 102 is relatively thick, it generates greater stress and is prone to warping, which affects the conductivity. Since titanium nitride has a higher density, placing the titanium nitride layer 103 on top of the aluminum metal layer 102 can improve the warping of the aluminum metal layer 102 and enhance the conductivity through the gravity of the titanium nitride.
[0104] Moreover, the second conductive layer group 10 of the three-layer structure has a low impedance, which improves the conductivity of the semiconductor device.
[0105] It should be noted that, since the depth-to-width ratio of the groove 8 is small, when the second conductive layer group 10 is formed on the groove 8, since part of the second conductive layer 10 is located inside the groove 8, the depth-to-width ratio of the groove 8 will be further reduced. Therefore, when the lithography machine is aligned, the alignment accuracy can be further improved.
[0106] Of course, in other exemplary embodiments of this disclosure, the material of the second conductive layer group 10 may also include copper, and nickel-gold or nickel-palladium-gold plating may be applied to the copper lines as needed. Thick copper structures are a preferred choice for high-current and high-power devices due to their advantages of low resistance, high heat dissipation, and low cost.
[0107] The second conductive layer group 10 can also increase the spacing between interfaces, provide a larger bump (isolation layer group 4) area, reduce the stress between the substrate and the component, and increase the reliability of the component; replace part of the circuit design and accelerate the development time of IC chip (Integrated Circuit Chip).
[0108] It should be noted that although the steps of the semiconductor device fabrication method of this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0109] Based on the same inventive concept, this disclosure also provides a semiconductor device prepared by the above-described preparation method, with reference to... Figure 9 As shown, the semiconductor device may include a substrate 1, a first conductive layer 2, an isolation layer group 4, and a second conductive layer group 10; the substrate 1 may include an alignment region A and a connection region B; the first conductive layer 2 is disposed on the substrate 1; the isolation layer group 4 is disposed on the first conductive layer 2 and located on the alignment region A, and the isolation layer group 4 is provided with an alignment groove 8, the depth of the alignment groove 8 being less than the thickness of the isolation layer group 4; the second conductive layer group 10 is disposed on the isolation layer group 4 and the first conductive layer 2, and the second conductive layer group 10 covers the alignment groove 8.
[0110] In this example embodiment, substrate 1 can be a semiconductor die that has already been fabricated. The semiconductor die can be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or simply a MOS transistor. The MOS transistor can be a PMOS (positive channel Metal-Oxide-Semiconductor) transistor or an NMOS (negative channel Metal-Oxide-Semiconductor) transistor. The MOS transistor can include storage capacitors, bit lines, word lines, gate, source, and drain, etc.
[0111] Reference Figure 2 As shown, substrate 1 may include alignment region A and connection region B. Specifically, there may be two connection regions B, which are located on both sides of alignment region A.
[0112] Of course, in other exemplary embodiments of this disclosure, the number of connected regions B can be set to multiple, and the specific location of connected regions B can be set as needed; the number of aligned regions A can also be set to multiple, and the specific location of aligned regions A can also be set as needed.
[0113] In this example embodiment, the first conductive layer 2 is formed not only in the alignment region A but also in the connection region B. The first conductive layer 2 can be connected to the gate, source, or drain within the substrate 1. Signals can be input to the gate, source, or drain within the substrate 1 through the first conductive layer 2, or signals stored in the substrate 1 can be output through the first conductive layer 2. The material of the first conductive layer 2 is, for example, aluminum. The thickness of the first conductive layer 2 is, for example, between 0.6 and 1.0 micrometers; for example, the thickness of the first conductive layer 2 can be 0.8 micrometers. The material of the first conductive layer 2 can be a metal such as copper or silver.
[0114] In this example embodiment, the isolation layer group 4 may include a first isolation layer 41, a second isolation layer 42 and a third isolation layer 43; the first isolation layer 41 is disposed on the first conductive layer 2; the second isolation layer 42 is disposed on the first isolation layer 41; the third isolation layer 43 is disposed on the second isolation layer 42, and the thickness of the third isolation layer 43 is greater than the thickness of the first isolation layer 41.
[0115] The material of the first isolation layer 41 includes, for example, silicon oxide, and the thickness of the first isolation layer 41 is, for example, between 0.6 and 1.0 micrometers, such as 0.8 micrometers.
[0116] The material of the second isolation layer 42 includes, for example, silicon nitride, and the thickness of the second isolation layer 42 is, for example, between 0.5 and 0.7 micrometers, such as 0.6 micrometers.
[0117] The material of the third isolation layer 43 includes, for example, silicon oxide, and the thickness of the third isolation layer 43 is, for example, between 4.0 and 5.0 micrometers, such as 4.5 micrometers.
[0118] The isolation layer group 4 is formed only in the alignment region A, that is, the orthogonal projection of the isolation layer group 4 on the substrate 1 is only located in the alignment region A.
[0119] The isolation material group 4 protects the substrate 1 and the first conductive layer 2. Furthermore, the relatively thick third isolation layer 43 provides planarization, offering a better substrate for the subsequent formation of the second conductive layer group 10. This facilitates the formation of a more uniform thickness of the second conductive layer group 10, improving the conductivity uniformity of the semiconductor device. Moreover, the thickness of the third isolation layer 43 prevents erosion to the second isolation layer 42 during the formation of the alignment groove 8, protecting the second isolation layer 42 and preventing it from being exposed by the alignment groove 8, thereby improving the performance of the semiconductor device.
[0120] In this example embodiment, the alignment groove 8 is disposed on the third isolation layer 43, but not on the second isolation layer 42 or the first isolation layer 41. The depth of the alignment groove 8 is less than the thickness of the third isolation layer 43. Therefore, the alignment groove 8 is shallow and has a small depth-to-width ratio. When the lithography machine is aligning, the laser emitted by the lithography machine reflects less within the alignment groove 8, thus reducing laser error and improving laser alignment accuracy. This allows the lithography machine to align well through the alignment groove 8, improving the problem of alignment failure. Moreover, the shallow depth of the alignment groove 8 makes it less likely to form a tilted structure at the bottom, which is also beneficial for the lithography machine to align and expose through the alignment groove 8. The depth of the alignment groove 8 is greater than or equal to 0.4 micrometers and less than or equal to 0.6 micrometers; for example, the depth of the alignment groove 8 can be 0.5 micrometers.
[0121] In this example embodiment, two alignment grooves 8 are provided, with a partition wall between two adjacent alignment grooves 8, and a partition wall is also provided on the outermost side of the alignment groove 8. Of course, the number and structure of the alignment grooves 8 can be set to multiple as needed, and the multiple alignment grooves 8 can be arranged in parallel or intersecting to form the required alignment pattern.
[0122] In this example embodiment, the second conductive layer group 10 is disposed above the isolation layer group 4 and the first conductive layer 2, and the second conductive layer group 10 covers the alignment groove 8. That is, the orthographic projection of the second conductive layer group 10 on the substrate 1 is located at the alignment region A and the connection region B. The second conductive layer group 10 is connected to the first conductive layer 2 in the connection region B. The second conductive layer group 10 can also be patterned to form new connection lines, thereby achieving the purpose of line redistribution.
[0123] Specifically, the second conductive layer group 10 may include a titanium metal layer 101, an aluminum metal layer 102, and a titanium nitride layer 103; the titanium metal layer 101 is disposed above the isolation layer group and the first conductive layer; the aluminum metal layer 102 is disposed above the titanium metal layer 101; and the titanium nitride layer 103 is disposed above the aluminum metal layer 102. The thickness of the titanium metal layer 101 is, for example, 0.1 micrometers. The thickness of the aluminum metal layer 102 is, for example, between 4.2 and 4.7 micrometers, such as 4.5 micrometers. The thickness of the titanium nitride layer 103 is, for example, between 0.04 and 0.06 micrometers, such as 0.05 micrometers. The titanium metal layer 101, the aluminum metal layer 102, and the titanium nitride layer 103 form the second conductive layer group 10.
[0124] As a redistribution layer, the aluminum metal layer 102 is not easily formed on the third isolation material layer 33, which makes it prone to open circuits. By placing the titanium metal layer 101 between the aluminum metal layer 102 and the third isolation material layer 33, on the one hand, the aluminum metal layer 102 is easily deposited on the titanium metal layer 101, that is, the titanium metal layer 101 can improve the adhesion of the aluminum metal layer 102 deposition, thereby reducing the occurrence of open circuits in the aluminum metal layer 102 due to insufficient deposition. On the other hand, even if there are open circuits in the aluminum metal layer 102, the titanium metal layer 101 can connect the open circuits in the aluminum metal layer 102, further preventing the occurrence of open circuits in the aluminum metal layer 102 and improving product yield.
[0125] In addition, since the aluminum metal layer 102 is relatively thick, it generates greater stress and is prone to warping, which affects the conductivity. Since titanium nitride has a higher density, placing the titanium nitride layer 103 on top of the aluminum metal layer 102 can improve the warping of the aluminum metal layer 102 and enhance the conductivity through the gravity of the titanium nitride.
[0126] Moreover, the second conductive layer group 10 of the three-layer structure has a low impedance, which improves the conductivity of the semiconductor device.
[0127] Of course, in other exemplary embodiments of this disclosure, the material of the second conductive layer group 10 can also be copper, and nickel-gold or nickel-palladium-gold plating can be applied to the copper lines as needed. Thick copper structures are the best choice for high-current and high-power devices due to their advantages of low resistance, high heat dissipation, and low cost.
[0128] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, including an alignment region and a connection region; A first conductive layer is formed on the substrate; An isolation material layer group is formed on the first conductive layer; A protective layer is formed on top of the isolation material layer group, and the protective layer is located on the alignment region; The isolation material layer group and the protective layer are etched, with the etching rate of the protective layer being less than the etching rate of the isolation material layer group, to remove the isolation material layer group on the connection area to form an isolation layer group, and an alignment groove is formed on the isolation layer group in the alignment area, the depth of the alignment groove being less than the thickness of the isolation layer group; A second conductive layer group is formed on top of the isolation layer group and the first conductive layer, the second conductive layer group covering the alignment groove.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The gases used to etch the isolation layer group and the protective layer include C4F6 and O2.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, An isolation material layer group is formed on the first conductive layer, including: A first insulating material layer is formed on top of the first conductive layer; A second isolation material layer is formed on top of the first isolation material layer; A third isolation material layer is formed on top of the second isolation material layer, the thickness of the third isolation material layer being greater than the thickness of the first isolation material layer.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming the alignment groove includes: Remove the protective layer and part of the third isolation material layer to form the alignment groove on the third isolation material layer.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, Before forming the second conductive layer group, the protective layer is also removed.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, Forming the second conductive layer group includes forming multiple conductive layers.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The step of forming a second conductive layer group on the isolation layer group and the first conductive layer includes: A titanium metal layer is formed on the isolation layer group and the first conductive layer; An aluminum metal layer is formed on top of the titanium metal layer; A titanium nitride layer is formed on top of the aluminum metal layer.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The connecting region is located on both sides of the aligning region.