Display device

Abstract

A display device is provided that includes a first pixel region including a plurality of first pixels and a plurality of first gate control lines coupled to the first pixels, and a second pixel region separate from the first pixel region. The second pixel region includes a plurality of second pixels and a plurality of second gate control lines coupled to the second pixels. The display device further includes a first non-pixel region disposed between the first pixel region and the second pixel region, and a plurality of first coupling lines disposed in the first non-pixel region. A first coupling line of the plurality of first coupling lines commonly couples at least two first gate control lines disposed in the first pixel region and at least two second gate control lines disposed in the second pixel region.

Description

[0001] This application is a divisional application of the invention patent application filed on November 8, 2018, with application number 201811323874.5 and the invention title "Display Device".

[0002] Cross-references to related applications

[0003] This application claims priority to Korean Patent Application No. 10-2017-0178356, filed on December 22, 2017, the entire disclosure of which is incorporated herein by reference. Technical Field

[0004] Exemplary embodiments of this disclosure relate to a display device. Background Technology

[0005] In addition to typical shapes such as a single quadrilateral shape, display devices may also include multiple pixel regions separated from each other, or may have a display area in which one part is partially recessed. Summary of the Invention

[0006] An exemplary embodiment of this disclosure provides a display device including a first pixel region and a second pixel region separated from each other, with at least one non-pixel region interposed between the first pixel region and the second pixel region. This display device reduces the area of ​​the non-pixel region included in the display device.

[0007] According to an exemplary embodiment of this disclosure, a display device includes: a first pixel region, the first pixel region including a plurality of first pixels and a plurality of first gate control lines coupled to the plurality of first pixels; and a second pixel region separated from the first pixel region. The second pixel region includes a plurality of second pixels and a plurality of second gate control lines coupled to the plurality of second pixels. The display device further includes: a first non-pixel region disposed between the first pixel region and the second pixel region; and a plurality of first coupling lines disposed in the first non-pixel region. One of the plurality of first coupling lines couples at least two first gate control lines disposed in the first pixel region and at least two second gate control lines disposed in the second pixel region.

[0008] In one exemplary embodiment, the first gate control line includes at least some of a plurality of first scan lines, a plurality of first initialization control lines, and a plurality of first emission control lines that control the driving of the plurality of first pixels. Furthermore, the second gate control line includes at least some of a plurality of second scan lines, a plurality of second initialization control lines, and a plurality of second emission control lines that control the driving of the plurality of second pixels.

[0009] In one exemplary embodiment, the first coupling line is coupled together with the i-th first emission control line and the (i+1)-th first emission control line respectively disposed on the i-th horizontal row and the (i+1)-th horizontal row of the first pixel region, and the i-th second emission control line and the (i+1)-th second emission control line respectively disposed on the i-th horizontal row and the (i+1)-th horizontal row of the second pixel region, where i is a natural number.

[0010] In one exemplary embodiment, the display device further includes a second coupling wire disposed on one side of the first pixel region or the second pixel region. The second coupling wire couples the i-th first emission control line and the (i+1)-th first emission control line, or the i-th second emission control line and the (i+1)-th second emission control line.

[0011] In one exemplary embodiment, the display device further includes: a transmission control driver, the transmission control driver including a k-th transmission control stage, the k-th transmission control stage providing transmission control signals for the i-th first transmission control line and the (i+1)-th first transmission control line, and the i-th second transmission control line and the (i+1)-th second transmission control line, where k is a natural number.

[0012] In one exemplary embodiment, the emission control driver includes a plurality of emission control stages sequentially disposed on one side of the first pixel region or the second pixel region. The plurality of emission control stages includes the k-th emission control stage.

[0013] In one exemplary embodiment, the emission control driver includes a plurality of emission control stages alternately disposed on one side of the first pixel region and one side of the second pixel region. The plurality of emission control stages includes the k-th emission control stage.

[0014] In one exemplary embodiment, the first coupling line is coupled together with the i-th first scan line and the i-th second scan line respectively disposed on the i-th horizontal row of the first pixel region and the i-th horizontal row of the second pixel region, and the (i+1)-th first initialization control line and the (i+1)-th second initialization control line respectively disposed on the (i+1)-th horizontal row of the first pixel region and the (i+1)-th horizontal row of the second pixel region, where i is a natural number.

[0015] In one exemplary embodiment, the display device further includes a second coupling wire disposed on one side of the first pixel region or the second pixel region. The second coupling wire couples the i-th first scan line and the (i+1)-th first initialization control line, or the i-th second scan line and the (i+1)-th second initialization control line.

[0016] In one exemplary embodiment, the display device further includes: a scan driver, the scan driver including an i-th scan level, the i-th scan level providing scan signals for the i-th first scan line, the i-th second scan line, the (i+1)-th first initialization control line and the (i+1)-th second initialization control line.

[0017] In one exemplary embodiment, the scan driver includes: a plurality of scan levels sequentially disposed on one side of the first pixel region or the second pixel region, wherein the plurality of scan levels includes the i-th scan level.

[0018] In one exemplary embodiment, the scan driver includes a plurality of scan levels alternately disposed on one side of the first pixel region and one side of the second pixel region. The plurality of scan levels includes the i-th scan level.

[0019] In one exemplary embodiment, the display device further includes: a third pixel region disposed on one side of the first pixel region and the second pixel region and in contact with the first pixel region and the second pixel region. The third pixel region includes a plurality of third pixels.

[0020] In one exemplary embodiment, the display device further includes a fourth pixel region disposed opposite to the third pixel region. The first pixel region, the second pixel region, and the first non-pixel region are interposed between the third pixel region and the fourth pixel region.

[0021] In one exemplary embodiment, the display device further includes an opening disposed in the first non-pixel region.

[0022] In one exemplary embodiment, the display device further includes: a plurality of first coupling wires including the first coupling wire. The plurality of first coupling wires are disposed in the first non-pixel region, and the plurality of first coupling wires are disposed at the upper end and the lower end of the opening in the first non-pixel region.

[0023] In one exemplary embodiment, the display device further includes: a substrate, wherein the plurality of first pixels and the plurality of second pixels are disposed on a surface of the substrate. The substrate includes a plurality of protrusions corresponding to the first pixel regions and the second pixel regions, and a recess corresponding to the first non-pixel regions.

[0024] According to an exemplary embodiment of this disclosure, a display device includes: a first pixel region, the first pixel region including a plurality of first pixels and a plurality of first gate control lines coupled to the plurality of first pixels; and a second pixel region separated from the first pixel region. The second pixel region includes a plurality of second pixels and a plurality of second gate control lines coupled to the plurality of second pixels. The display device further includes: a first non-pixel region disposed between the first pixel region and the second pixel region, the first non-pixel region including a recess. The display device further includes: a first coupling wire disposed in the first non-pixel region, the first coupling wire jointly coupling at least two of the first gate control lines and at least two of the second gate control lines.

[0025] In one exemplary embodiment, the first gate control line includes at least some of a plurality of first scan lines, a plurality of first initialization control lines, and a plurality of first emission control lines that control the driving of the plurality of first pixels. Furthermore, the second gate control line includes at least some of a plurality of second scan lines, a plurality of second initialization control lines, and a plurality of second emission control lines that control the driving of the plurality of second pixels.

[0026] In one exemplary embodiment, the first coupling line couples together the i-th first emission control line and the (i+1)-th first emission control line disposed on the i-th horizontal row and the (i+1)-th horizontal row of the first pixel region, and the i-th second emission control line and the (i+1)-th second emission control line disposed on the i-th horizontal row and the (i+1)-th horizontal row of the second pixel region, where i is a natural number.

[0027] In one exemplary embodiment, the display device further includes a second coupling wire disposed in a second non-pixel region on one side of the first pixel region or the second pixel region. The second coupling wire couples the i-th first emission control line and the (i+1)-th first emission control line, or the i-th second emission control line and the (i+1)-th second emission control line.

[0028] In one exemplary embodiment, the first coupling line is coupled together with the i-th first scan line and the i-th second scan line respectively disposed on the i-th horizontal row of the first pixel region and the i-th horizontal row of the second pixel region, and the (i+1)-th first initialization control line and the (i+1)-th second initialization control line respectively disposed on the (i+1)-th horizontal row of the first pixel region and the (i+1)-th horizontal row of the second pixel region, where i is a natural number.

[0029] In one exemplary embodiment, the display device further includes a second coupling wire disposed in a second non-pixel region on one side of the first pixel region or the second pixel region. The second coupling wire couples the i-th first scan line and the (i+1)-th first initialization control line, or the i-th second scan line and the (i+1)-th second initialization control line.

[0030] According to an exemplary embodiment of this disclosure, a display device includes: a substrate, the substrate including a first protrusion, a second protrusion, and a cutout region disposed between the first protrusion and the second protrusion. The display device further includes: a first pixel region disposed on the first protrusion, wherein the first pixel region includes a first row of first pixels and a first gate control line coupled to the first row of first pixels, and a second row of first pixels and a second gate control line coupled to the second row of first pixels. The display device further includes: a second pixel region disposed on the second protrusion, wherein the second pixel region includes a first row of second pixels and a third gate control line coupled to the first row of second pixels, and a second row of second pixels and a fourth gate control line coupled to the second row of second pixels. The display device further includes: a first non-pixel region disposed in the cutout region, and a first coupling line disposed in the first non-pixel region, wherein the first coupling line is coupled to the first gate control line, the second gate control line, the third gate control line, and the fourth gate control line. Attached Figure Description

[0031] The above and other features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0032] Figures 1 to 12 Each illustrates a display area according to an exemplary embodiment of the present disclosure and a substrate on which the display area is formed.

[0033] Figure 13 A pixel is shown according to an exemplary embodiment of the present disclosure.

[0034] Figure 14 and Figure 15 An exemplary embodiment according to this disclosure is shown. Figure 13 The timing diagram corresponding to the driving method of the pixel shown.

[0035] Figure 16 A display panel is shown according to an exemplary embodiment of the present disclosure.

[0036] Figure 17 and Figure 18 Exemplary embodiments according to this disclosure are shown respectively. Figure 16 The first scan driver and the second scan driver are shown in the figure.

[0037] Figure 19 and Figure 20 Exemplary embodiments according to this disclosure are shown respectively. Figure 16 The first and second transmit control drivers are shown in the figure.

[0038] Figure 21 and Figure 22 Each shows a display panel according to an exemplary embodiment of the present disclosure.

[0039] Figures 23 to 26 Each shows a region of a display panel according to an exemplary embodiment of the present disclosure.

[0040] Figure 27 and Figure 28 Each shows a region of a display panel according to an exemplary embodiment of the present disclosure.

[0041] Figure 29 and Figure 30 Each shows a region of a display panel according to an exemplary embodiment of the present disclosure.

[0042] Figure 31 An area of ​​a display panel according to an exemplary embodiment of the present disclosure is shown. Detailed Implementation

[0043] Exemplary embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. Similar reference numerals may refer to similar elements throughout the drawings.

[0044] It will be understood that when a component is referred to as being "on" another component, "connected to", "coupled to", or "adjacent to" another component, the component may be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or there may be intermediate components. It will also be understood that when a component is referred to as being "between" two components, the component may be the only component between the two components, or there may be one or more intermediate components.

[0045] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and these elements are not limited by these terms. Thus, an “first” element in one exemplary embodiment may be described as a “second” element in another exemplary embodiment.

[0046] Figures 1 to 12 Each illustrates a display area according to an exemplary embodiment of the present disclosure and a substrate on which the display area is formed. For example, Figures 1 to 12 An exemplary embodiment is shown relating to the shape of a display area that can be disposed in a display device according to an exemplary embodiment of the present disclosure, and the shape of a substrate on which the display area is formed.

[0047] Reference Figure 1 In one exemplary embodiment, substrate 101 is a display substrate constituting a base substrate of a display panel. A display area DA for displaying an image, a first non-pixel area NA1 disposed on one side of the display area DA, and a second non-pixel area NA2 disposed around the display area DA and the first non-pixel area NA1 are defined on substrate 101. In this exemplary embodiment, a specific region within the non-pixel area where no pixels are disposed (e.g., the non-pixel area between the first pixel area AA1 and the second pixel area AA2 at the upper end of the display area DA) is referred to as the first non-pixel area NA1, and the remaining non-pixel areas other than the first non-pixel area NA1 are referred to as the second non-pixel area NA2.

[0048] The substrate 101 may be made of glass or plastic material. However, exemplary embodiments of this disclosure are not limited thereto. For example, the substrate 101 may be a flexible substrate including at least one of polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyaryl ester (PAR), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), and cellulose acetate propionate (CAP). Furthermore, the substrate 101 may be a rigid substrate including one of glass and tempered glass. Additionally, the substrate 101 may be made of a transparent material, such as a light-transmitting substrate. However, exemplary embodiments of this disclosure are not limited thereto. Furthermore, the substrate 101 may be configured to have different materials and / or different structures depending on the region, such that different characteristics are exhibited for each region. Furthermore, the substrate 101 may have a single-layer or multi-layer structure. However, the structure of the substrate 101 is not limited thereto.

[0049] The display area DA includes a first pixel area AA1 and a second pixel area AA2 separated from each other, with a first non-pixel area NA1 interposed between the first pixel area AA1 and the second pixel area AA2. In an exemplary embodiment, the display area DA may further include a third pixel area AA3 disposed on one side of the first pixel area AA1 and the second pixel area AA2. For example, the third pixel area AA3 may be disposed on one side of the first pixel area AA1 and the second pixel area AA2 to contact the first pixel area AA1 and the second pixel area AA2. As an example, the first pixel area AA1 may be disposed at the upper left end of the third pixel area AA3, and the second pixel area AA2 may be disposed at the upper right end of the third pixel area AA3 to separate it from the first pixel area AA1. In this case, the first non-pixel area NA1 may be disposed at the upper center of the third pixel area AA3.

[0050] At least two of the first pixel region AA1, the second pixel region AA2, and the third pixel region AA3 may have different widths and / or different areas. For example, the third pixel region AA3 may occupy the largest area in the display area DA while having the widest width, and each of the first pixel region AA1 and the second pixel region AA2 may have a width narrower than the width of the third pixel region AA3 while having a smaller area than the area of ​​the third pixel region AA3. Furthermore, the first pixel region AA1 and the second pixel region AA2 may have the same width and / or the same area, or they may have different widths and / or different areas.

[0051] Multiple first pixels PXL1, multiple second pixels PXL2, and multiple third pixels PXL3 can be respectively disposed in the first pixel region AA1, the second pixel region AA2, and the third pixel region AA3. The first pixels PXL1, the second pixels PXL2, and the third pixels PXL3 can have the same structure, or at least some of the first pixels PXL1, the second pixels PXL2, and the third pixels PXL3 can have different structures. That is, in the exemplary embodiments of this disclosure, the structure of the first pixels PXL1, the second pixels PXL2, and the third pixels PXL3 is not specifically limited. Each of the first pixels PXL1, the second pixels PXL2, and the third pixels PXL3 can be a self-emissive pixel including an organic light-emitting diode. However, the exemplary embodiments of this disclosure are not limited thereto.

[0052] First pixel PXL1, second pixel PXL2, and third pixel PXL3 are disposed on a substrate 101 on which first pixel region AA1, second pixel region AA2, and third pixel region AA3 are defined. For example, first pixel PXL1, second pixel PXL2, and third pixel PXL3 may be formed on the same surface of substrate 101.

[0053] No pixels are provided in the first non-pixel region NA1 and the second non-pixel region NA2. For example, the first non-pixel region NA1 and the second non-pixel region NA2 constitute a non-display region that does not include pixels. Lines for driving pixels PXL1, PXL2, and PXL3 in the display region DA may be provided in the first non-pixel region NA1 and / or the second non-pixel region NA2. For example, lines for providing various drive signals and / or various drive power supplies for pixels PXL1, PXL2, and PXL3 may be provided in the first non-pixel region NA1 and / or the second non-pixel region NA2. Furthermore, in an exemplary embodiment, at least one drive circuit unit for driving pixels PXL1, PXL2, and PXL3 may be provided in the first non-pixel region NA1 and / or the second non-pixel region NA2. As an example, at least one of a scan driver, a transmit controller, and a data driver may be provided in the second non-pixel region NA2. Here, the scan driver may also be referred to as a scan driver circuit, the transmit controller may also be referred to as a transmit controller circuit, and the data driver may also be referred to as a data driver circuit.

[0054] The shapes of the display area DA and the first non-pixel area NA1 can be modified in various ways. For example, the display area DA and / or the first non-pixel area NA1 can have a polygonal shape, a circular shape, an elliptical shape, or a combination thereof.

[0055] In an exemplary embodiment, substrate 101 may include a recess (also referred to as a partial opening or notch) disposed between the first pixel region AA1 and the second pixel region AA2. As an example, substrate 101 may include a protrusion 101a corresponding to each of the first pixel region AA1 and the second pixel region AA2, and a recess 101b (also referred to as a cutout region) corresponding to the first non-pixel region NA1. For example, in an exemplary embodiment, a region of the first non-pixel region NA1 may be recessed. When substrate 101 includes recess 101b, the internal space of the display device can be utilized more effectively. For example, components such as cameras, speakers, etc., may be disposed at the recess 101b.

[0056] It will be understood that the shape of the substrate 101 is not limited to the shape described above. For example, in an exemplary embodiment, the substrate 101 does not include the recess between the first pixel region AA1 and the second pixel region AA2, such as... Figure 2 As shown in the figure. As an example, substrate 101 may be a rectangular or square substrate including display area DA, first non-pixel area NA1 and second non-pixel area NA2. However, the shape of substrate 101 is not limited to this. For example, at least one corner of substrate 101 may have a diagonal shape, a stepped shape, a curved shape, etc.

[0057] The shapes of each of the first pixel region AA1, the second pixel region AA2, the third pixel region AA3, and the first non-pixel region NA1 can also be modified in various ways. For example, as Figures 3 to 5 As shown, in an exemplary embodiment, at least one of the first pixel region AA1, the second pixel region AA2, the third pixel region AA3, and the first non-pixel region NA1 may have a diagonal shape, which has a sloping portion with a predetermined slope. As an example, the first pixel region AA1, the second pixel region AA2, the third pixel region AA3, and / or the first non-pixel region NA1 may have a diagonal shape at at least one corner. In this case, the width of each of the first pixel region AA1, the second pixel region AA2, the third pixel region AA3, and the first non-pixel region NA1 may gradually vary in at least one of its regions.

[0058] For example, refer to Figure 3 In one exemplary embodiment, the edges of the connecting protrusions 101a and recesses 101b of the substrate 101 are inclined. Furthermore, the boundary between the first pixel region AA1 and the first non-pixel region NA1 is inclined, and the boundary between the second pixel region AA2 and the first non-pixel region NA1 is inclined.

[0059] Reference Figure 4 In one exemplary embodiment, the edge defining the outer boundary of the protrusion 101a at the top of the substrate 101 is inclined. Furthermore, the opposing edges defining the outer boundary of the substrate 101 at the bottom of the substrate 101 are inclined. Additionally, the boundaries between the first pixel region AA1 and the second non-pixel region NA2 at the top of the substrate 101, the boundaries between the second pixel region AA2 and the second non-pixel region NA2, and the boundaries between the third pixel region AA3 and the second non-pixel region NA2 at the bottom of the substrate 101 are inclined.

[0060] Reference Figure 5 In one exemplary embodiment, the edges connecting the protrusion 101a and the recess 101b of the substrate 101 are inclined. Furthermore, the boundary between the first pixel region AA1 and the first non-pixel region NA1 is inclined, and the boundary between the second pixel region AA2 and the first non-pixel region NA1 is inclined. Additionally, the boundary between the first pixel region AA1 and the second non-pixel region NA2 is inclined, and the boundary between the second pixel region AA2 and the second non-pixel region NA2 is inclined. Furthermore, the edge of the substrate 101 that defines the outer boundary of the protrusion 101a at the top of the substrate 101 is inclined.

[0061] In addition, such as Figure 6 and Figure 7 As shown, in an exemplary embodiment, at least one of the first pixel region AA1, the second pixel region AA2, the third pixel region AA3, and the first non-pixel region NA1 may have a stepped shape, the stepped shape having at least one step difference.

[0062] For example, refer to Figure 6 In one exemplary embodiment, the boundary between the first pixel region AA1 and the first non-pixel region NA1 has a stepped shape, the boundary between the second pixel region AA2 and the first non-pixel region NA1 has a stepped shape, and the edges of the connecting protrusion 101a and the recess 101b of the substrate 101 have a stepped shape.

[0063] Reference Figure 7 In one exemplary embodiment, the edge defining the outer boundary of the protrusion 101a at the top of the substrate 101 has a stepped shape. Furthermore, the opposing edges defining the outer boundary of the substrate 101 at the bottom of the substrate 101 have stepped shapes. Additionally, the boundaries between the first pixel region AA1 and the second non-pixel region NA2 at the top of the substrate 101, the boundaries between the second pixel region AA2 and the second non-pixel region NA2, and the boundaries between the third pixel region AA3 and the second non-pixel region NA2 at the bottom of the substrate 101 have stepped shapes.

[0064] In addition, such as Figures 8 to 10 As shown, at least one of the first pixel region AA1, the second pixel region AA2, the third pixel region AA3, and the first non-pixel region NA1 may have a curved shape.

[0065] For example, refer to Figure 8 In one exemplary embodiment, the edge defining the outer boundary of the protrusion 101a at the top of the substrate 101 has a curved shape. Furthermore, the opposing edges defining the outer boundary of the substrate 101 at the bottom of the substrate 101 have curved shapes. Additionally, the boundaries between the first pixel region AA1 and the second non-pixel region NA2 at the top of the substrate 101, the boundaries between the second pixel region AA2 and the second non-pixel region NA2, and the boundaries between the third pixel region AA3 and the second non-pixel region NA2 at the bottom of the substrate 101 have curved shapes. Furthermore, the boundaries between the first pixel region AA1 and the first non-pixel region NA1, and between the second pixel region AA2 and the first non-pixel region NA1, have curved shapes.

[0066] Reference Figure 9In one exemplary embodiment, the edges of the connecting protrusion 101a and recess 101b of the substrate 101 have a curved shape. Furthermore, the boundary between the first pixel region AA1 and the first non-pixel region NA1 has a curved shape, and the boundary between the second pixel region AA2 and the first non-pixel region NA1 has a curved shape. Additionally, the boundary between the first pixel region AA1 and the second non-pixel region NA2 has a curved shape, and the boundary between the second pixel region AA2 and the second non-pixel region NA2 has a curved shape. Furthermore, the edge of the substrate 101 that defines the outer boundary of the protrusion 101a at the top of the substrate 101 has a curved shape.

[0067] Reference Figure 10 In one exemplary embodiment, the edges connecting the protrusion 101a and the recess 101b of the substrate 101 have a curved shape. Furthermore, the boundary between the first pixel region AA1 and the first non-pixel region NA1 has a curved shape, and the boundary between the second pixel region AA2 and the first non-pixel region NA1 has a curved shape. Similarly, the boundary between the first pixel region AA1 and the second non-pixel region NA2 has a curved shape, and the boundary between the second pixel region AA2 and the second non-pixel region NA2 has a curved shape. Additionally, the edge of the substrate 101 defining the outer boundary of the protrusion 101a at the top of the substrate 101 has a curved shape, and the opposing edges of the substrate 101 defining the outer boundary of the substrate 101 at the bottom of the substrate 101 have curved shapes. Furthermore, the boundary between the third pixel region AA3 and the second non-pixel region NA2 at the bottom of the substrate 101 has a curved shape.

[0068] Furthermore, in exemplary embodiments, the substrate 101 may have a shape corresponding to the shape of the display area DA. As an example, at least one region of the substrate 101 (e.g., at least one corner) may have a slanted shape, a stepped shape, a curved shape, etc., corresponding to the shape of the display area DA. However, the exemplary embodiments of this disclosure are not limited thereto. For example, the substrate 101 may have a corner with a right angle (e.g., a right angle corner indicated by a dashed line in the figure), regardless of the shape of the display area DA.

[0069] Although reference Figures 1 to 10 An exemplary embodiment in which the display area DA includes three pixel regions (e.g., a first pixel region AA1, a second pixel region AA2, and a third pixel region AA3) is disclosed, but it will be understood that the exemplary embodiments disclosed herein are not limited thereto. For example, as Figure 11As shown, in an exemplary embodiment, the display area DA may be configured to include only two pixel areas (e.g., first pixel area AA1 and second pixel area AA2) that are arranged adjacent to each other and separated from each other by a first non-pixel area NA1 inserted between them.

[0070] Optionally, in an exemplary embodiment, in addition to the first pixel region AA1, the second pixel region AA2, and the third pixel region AA3, the display region DA may further include at least one pixel region. For example, as Figure 12 As shown, in an exemplary embodiment, the display area DA may further include a fourth pixel area AA4, which includes a fourth pixel PXL4, disposed opposite to the third pixel area AA3. The first pixel area AA1, the second pixel area AA2, and the first non-pixel area NA1 are interposed between the third pixel area AA3 and the fourth pixel area AA4. In this case, the first non-pixel area NA1 may be disposed at the central portion of the display area DA and may be surrounded by the first pixel area AA1, the second pixel area AA2, the third pixel area AA3, and the fourth pixel area AA4.

[0071] Furthermore, in one exemplary embodiment, at least one opening OPN may be provided in the first non-pixel region NA1. Optionally, in one exemplary embodiment, the first non-pixel region NA1 may not include the at least one opening OPN. For example, the substrate 101 may or may not include the opening OPN provided in the first non-pixel region NA1.

[0072] Figure 13 Pixels are shown according to an exemplary embodiment of this disclosure. For ease of explanation, Figure 13 The diagram illustrates any pixel PXL positioned in the i-th (i is a natural number) horizontal row and j-th (j is a natural number) vertical row of the display area DA. Here, natural numbers refer to positive integers and do not include zero. Pixel PXL can be any one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. In an exemplary embodiment, all pixels arranged in the display area DA (e.g., the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3) may have substantially the same structure. It will be understood that the structure of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is not limited to... Figure 13 The structure shown is illustrated. For example, the structure of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be modified in various ways. (Refer to...) Figure 13 According to an exemplary embodiment of the present disclosure, a pixel PXL includes an organic light-emitting diode (OLED) and a pixel circuit PXC for controlling the drive current provided to the OLED.

[0073] An organic light-emitting diode (OLED) is coupled between a first power supply ELVDD and a second power supply ELVSS. As an example, the anode electrode of the OLED may be coupled to the first power supply ELVDD via a pixel circuit PXC, and the cathode electrode of the OLED may be coupled to the second power supply ELVSS. The OLED emits light with a brightness corresponding to the driving current supplied from the pixel circuit PXC.

[0074] The pixel circuit PXC controls the driving current flowing through the organic light-emitting diode (OLED) in each frame cycle in accordance with the data signal provided through the corresponding data line (e.g., the j-th data line). For this purpose, the pixel circuit PXC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0075] The first electrode of the first transistor T1 (also referred to herein as the driving transistor T1) is coupled to the first power supply ELVDD via the fifth transistor T5, and the second electrode of the first transistor T1 is coupled to the anode electrode of the organic light-emitting diode (OLED) via the sixth transistor T6. Furthermore, the gate electrode of the first transistor T1 is coupled to the first node N1. The voltage of the first transistor T1 and the first node N1 correspondingly control the driving current flowing from the first power supply ELVDD to the second power supply ELVSS via the OLED.

[0076] The second transistor T2 is coupled between the corresponding data line Dj and the first electrode of the first transistor T1. Furthermore, the gate electrode of the second transistor T2 is coupled to the corresponding scan line (e.g., the i-th scan line Si). When a scan signal is provided to the i-th scan line Si, the second transistor T2 is turned on, thereby electrically coupling the data line Dj and the first electrode of the first transistor T1 to each other. Here, the scan signal can be set to a signal with a gate on-state voltage.

[0077] The third transistor T3 is coupled between the second electrode of the first transistor T1 and the first node N1. Furthermore, the gate electrode of the third transistor T3 is coupled to the i-th scan line Si. When a scan signal is provided to the i-th scan line Si, the third transistor T3 is turned on, thereby electrically coupling the second electrode of the first transistor T1 and the first node N1 to each other. Therefore, if the third transistor T3 is turned on, the first transistor T1 is diode-coupled.

[0078] A fourth transistor T4 is coupled between the first node N1 and the initialization power supply Vint. Furthermore, the gate electrode of the fourth transistor T4 is coupled to the i-th initialization control line CLI. When the initialization control signal is provided to the i-th initialization control line CLI, the fourth transistor T4 is turned on, thereby providing the voltage of the initialization power supply Vint to the first node N1. Here, the initialization control signal can be set to a signal with a gate on-state voltage, and the voltage of the initialization power supply Vint can be set to the lowest voltage of the data signal or less.

[0079] The i-th initialization control line CLI is the control line for initializing the pixel PXL located on the i-th horizontal row. An initialization control signal with a gate-on voltage is provided to the i-th initialization control line CLI before the scan signal is provided to the i-th scan line Si. As an example, the i-th initialization control line CLI may be coupled to the scan line of the directly adjacent previous horizontal row (e.g., the (i-1)-th scan line Si-1). In this case, the scan signal provided to the (i-1)-th scan line Si-1 (e.g., the current scan signal of the directly adjacent previous horizontal row) can be used as the initialization control signal for the i-th horizontal row. As described above, when the pixel PXL is initialized using the scan signal of another horizontal row, the pixel PXL can be initialized without setting a control line driver for generating a separate initialization control signal.

[0080] The fifth transistor T5 is coupled between the first power supply ELVDD and the first transistor T1. Furthermore, the gate electrode of the fifth transistor T5 is coupled to a corresponding emitter control line (e.g., the i-th emitter control line) Ei. When the emitter control signal is provided to the i-th emitter control line Ei, the fifth transistor T5 is turned off; otherwise, it is turned on. Here, the emitter control signal can be set to a signal with a gate cutoff voltage.

[0081] The sixth transistor T6 is coupled between the first transistor T1 and the organic light-emitting diode (OLED). Furthermore, the gate electrode of the sixth transistor T6 is coupled to the i-th emission control line Ei. When the emission control signal is provided to the i-th emission control line Ei, the sixth transistor T6 is turned off; otherwise, it is turned on.

[0082] The seventh transistor T7 is coupled between the initialization power supply Vint and the anode electrode of the organic light-emitting diode (OLED). Furthermore, the gate electrode of the seventh transistor T7 is coupled to the i-th scan line Si. When a scan signal is provided to the i-th scan line Si, the seventh transistor T7 is turned on, thereby providing the voltage of the initialization power supply Vint to the anode electrode of the OLED.

[0083] The storage capacitor Cst is coupled between the first power supply ELVDD and the first node N1. The storage capacitor Cst stores the voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0084] Figure 14 and Figure 15 An exemplary embodiment according to this disclosure is shown. Figure 13 The timing diagram corresponding to the driving method of the pixel shown.

[0085] First, refer to Figure 14 During each frame period, a transmit control signal with a gate cutoff voltage is provided to the i-th transmit control line Ei. When the transmit control signal is provided to the i-th transmit control line Ei, the fifth transistor T5 and the sixth transistor T6 of the pixel PXL located in the i-th horizontal row are turned off. Therefore, the pixel PXL is set to a non-transmitting state.

[0086] Subsequently, when a scan signal is provided to the i-th initialization control line CLI (e.g., the (i-1)-th scan line Si-1), the fourth transistor T4 of the pixel PXL in the i-th horizontal row is turned on. When the fourth transistor T4 is turned on, the voltage of the initialization power supply Vint is provided to the first node N1. Then, the first node N1 is initialized to the voltage of the initialization power supply Vint.

[0087] After the first node N1 is initialized to the voltage of the initialization power supply Vint, a scan signal is provided to the i-th scan line Si. When the scan signal is provided to the i-th scan line Si, the second transistor T2, the third transistor T3, and the seventh transistor T7 of the pixel PXL located on the i-th horizontal row are turned on.

[0088] When the seventh transistor T7 is turned on, the voltage of the initialization power supply Vint is supplied to the anode electrode of the organic light-emitting diode (OLED). Then, the parasitic capacitors structurally formed in the OLED are discharged, thus improving the ability to accurately display black grayscale levels.

[0089] For example, the parasitic capacitor of an OLED is charged with a predetermined voltage corresponding to the current supplied in the previous frame period. When a black grayscale level is to be displayed in the current frame, the OLED remains in a non-emitting state during the corresponding frame period. However, when the parasitic capacitor of the OLED remains charged, light can be easily emitted from the OLED due to a small leakage current.

[0090] Optionally, when the parasitic capacitor of the OLED is charged before each pixel PXL emits light, the leakage current of the first transistor T1 first charges the parasitic capacitor of the OLED. Therefore, the OLED can stably remain in a non-emitting state during the frame period in which the corresponding pixel PXL displays a black grayscale level.

[0091] When the third transistor T3 is turned on, the first transistor T1 is coupled in a diode manner.

[0092] When the second transistor T2 is turned on, the data signal provided by the data line Dj of the corresponding pixel PXL is transmitted to the first electrode of the first transistor T1. At this time, since the first node N1 is initialized to the voltage of the initialization power supply Vint, which is lower than the minimum voltage of the data signal, the first transistor T1 is turned on. When the first transistor T1 is turned on, the voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data signal is applied to the first node N1. Therefore, the storage capacitor Cst stores the voltage corresponding to the data signal applied to the first node N1 and the threshold voltage of the first transistor T1.

[0093] After the voltage corresponding to the data signal and the threshold voltage of the first transistor T1 are stored in the storage capacitor Cst, the supply of the transmit control signal to the i-th transmit control line Ei is stopped. Therefore, the voltage of the i-th transmit control line Ei can be converted into the gate turn-on voltage.

[0094] When the voltage of the i-th emission control line Ei becomes the gate turn-on voltage, the fifth transistor T5 and the sixth transistor T6 turn on. Then, a current path is formed, allowing the drive current to flow from the first power supply ELVDD through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the organic light-emitting diode (OLED) to the second power supply ELVSS. At this time, the first transistor T1 controls the amount of drive current flowing through the OLED in accordance with the voltage of the first node N1. The OLED then emits light with a brightness corresponding to the amount of drive current.

[0095] Pixel PXL generates light with a brightness corresponding to the data signal while repeating the above process. It will be understood that the pixel structure of pixel PXL (e.g., the structure of pixel circuit PXC) and its driving method are not limited to those described above. Figure 13 and Figure 14 The exemplary implementation described is available, and various modifications and implementations are possible.

[0096] The i-th transmit control signal provided to the i-th transmit control line Ei is provided in an overlapping manner with the i-th scan signal. As a result, the pixel PXL located on the i-th horizontal row can remain in a non-transmitting state during the period in which data signals are transmitted to and stored in pixel PXL. Furthermore, the i-th transmit control signal can be provided in an overlapping manner with the i-th initialization control signal (or the (i-1)-th scan signal). As a result, the pixel PXL located on the i-th horizontal row can remain in a non-transmitting state during the period in which pixel PXL is initialized. Various methods can be used to set the timing of the transmit control signal provision.

[0097] Furthermore, in an exemplary embodiment, the emission of pixels PXL disposed on multiple horizontal rows can be controlled simultaneously. For example, for every two consecutive horizontal rows, emission control signals can be provided simultaneously to pixels PXL disposed on two consecutive horizontal rows. As an example, the i-th emission control line Ei and the (i+1)-th emission control line Ei+1 can be coupled to each other to achieve a substantially integrated emission control line.

[0098] When the i-th transmit control line Ei and the (i+1)-th transmit control line Ei+1 are coupled to each other, as Figure 15 As shown, the transmission control signals provided to the i-th transmission control line Ei and the (i+1)-th transmission control line Ei+1 may overlap with the initialization control signals (e.g., the (i-1)-th scan signal) provided to at least the i-th initialization control line CLI (e.g., the (i-1)-th scan line Si-1), the scan signal provided to the i-th scan line Si, the initialization control signal (e.g., the i-th scan signal) provided to the (i+1)-th initialization control line CLI+1 (e.g., the i-th scan line Si), and the scan signal provided to the (i+1)-th scan line Si+1. The (i+1)-th scan line Si+1 may be coupled to the (i+2)-th initialization control line CLI+2. In this case, the (i+1)-th scan signal provided to the (i+1)-th scan line Si+1 may be used as the (i+2)-th initialization control signal for initializing the pixel PXL disposed on the (i+2)-th horizontal row. The implementation of the exemplary embodiments described herein results in a simplification of the structure of the transmission control driver used to provide transmission control signals to the pixel PXL. For example, according to an exemplary embodiment of this disclosure, the number of transmission control stages provided in the transmission control driver can be reduced to approximately half. Here, the transmission control driver may also be referred to as a transmission control driver circuit.

[0099] Figure 16 A display panel according to an exemplary embodiment of the present disclosure is shown. For example, Figure 16 An exemplary embodiment is shown relating to the structure of a display panel that may be disposed in a display device according to an exemplary embodiment of the present disclosure. Figure 16 In, with Figures 1 to 12 Components that are similar to or the same as other components are indicated by similar reference numerals, and their further detailed descriptions will be omitted.

[0100] Reference Figure 16In one exemplary embodiment, the display panel 100 includes a display area DA in which a plurality of pixels (e.g., first pixel PXL1, second pixel PXL2, and third pixel PXL3) displaying an image are disposed, and at least one driver driving the display area DA. As an example, in addition to the display area DA, the display panel 100 may also include at least one of a first scan driver 110a, a second scan driver 110b, a first transmit control driver 120a, a second transmit control driver 120b, and a data driver 130. However, the exemplary embodiments of this disclosure are not limited thereto. For example, in one exemplary embodiment of this disclosure, all of the aforementioned drivers 110a, 110b, 120a, 120b, and 130 may be disposed outside the display panel 100 and electrically coupled to the pixels PXL1, PXL2, and PXL3 of the display area DA via at least one pad unit and / or at least one circuit board.

[0101] In an exemplary embodiment, the display area DA includes a first pixel area AA1, a second pixel area AA2, and a third pixel area AA3. Furthermore, the first pixel area AA1 and the second pixel area AA2 may be separated from each other, and a first non-pixel area NA1 is interposed between the first pixel area AA1 and the second pixel area AA2.

[0102] The first pixel region AA1 includes a first pixel PXL1, and first gate control lines and data lines D1 to Dp (p is a natural number) coupled to the first pixel PXL1. Here, the first gate control line refers to the control line used to control the driving of the first pixel PXL1. For example, the first gate control line may include at least some of the following lines: first scan lines S10, S11, S12, ..., first initialization control lines (e.g., the first scan line on the directly adjacent previous horizontal row), and first emission control lines E11, E12, ..., which control the driving timing of the first pixel PXL1.

[0103] As an example, a first group of first horizontal pixels PXL1 can be set on the first horizontal row of the first pixel region AA1, and a tenth scan line S10, an eleventh scan line S11, and an eleventh emission control line E11 can be provided for each pixel in the first group of first horizontal pixels PXL1 to provide an initialization control signal (or previous scan signal), a scan signal (or current scan signal), and an emission control signal. Furthermore, a second group of first horizontal pixels PXL1 can be set on the second horizontal row of the first pixel region AA1, and an eleventh scan line S11, a twelfth scan line S12, and a twelfth emission control line E12 can be provided for each pixel in the second group of first horizontal pixels PXL1 to provide an initialization control signal (or previous scan signal), a scan signal (or current scan signal), and an emission control signal.

[0104] In an exemplary embodiment, each initialization control line for initializing the first pixel PXL1 may be coupled to and / or integrated with the current scan line of the previous horizontal row. However, the exemplary embodiments of this disclosure are not limited thereto. Furthermore, in an exemplary embodiment, the first emission control lines E11, E12, ... may form a pair for every at least two first emission control lines to be coupled to and / or integrated with each other. However, the exemplary embodiments of this disclosure are not limited thereto. The type and / or number of control lines included in the first gate control lines may vary depending on the structure of the first pixel PXL1.

[0105] The first non-pixel region NA1 is located to one side of the first pixel region AA1. Since no pixels are set in the first non-pixel region NA1, it can be designated as a non-display area.

[0106] The second pixel region AA2 is located on one side of the first non-pixel region NA1. For example, the second pixel region AA2 and the first pixel region AA1 can be arranged adjacent to each other, with the first non-pixel region NA1 inserted between the second pixel region AA2 and the first pixel region AA1.

[0107] The second pixel region AA2 includes a second pixel PXL2, and second gate control lines and data lines Dp+q+1 to Dp+q+r (p, q, and r are natural numbers) coupled to the second pixel PXL2. Here, the second gate control line refers to the control line that controls the driving of the second pixel PXL2. For example, the second gate control line may include at least some of the following lines: second scan lines S20, S21, S22, ..., second initialization control lines (e.g., second scan lines on the directly adjacent previous horizontal row), and second emission control lines E21, E22, ..., which control the driving timing of the second pixel PXL2. As an example, a first group of second horizontal pixels PXL2 can be set on the first horizontal row of the second pixel region AA2, and a twentieth scan line S20, a twenty-first scan line S21, and a twenty-first emission control line E21 can be provided to each pixel in the first group of second horizontal pixels PXL2 with an initialization control signal (or previous scan signal), a scan signal (or current scan signal), and an emission control signal. In addition, a second group of second horizontal pixels PXL2 can be set on the second horizontal row of the second pixel area AA2, and a twenty-first scan line S21, a twenty-second scan line S22 and a twenty-second emission control line E22 can be provided for each pixel in the second group of second horizontal pixels PXL2 to provide initialization control signal (or previous scan signal), scan signal (or current scan signal) and emission control signal.

[0108] In an exemplary embodiment, each initialization control line initializing the second pixel PXL2 may be coupled to and / or integrated with the current scan line of the previous horizontal row. However, the exemplary embodiments of this disclosure are not limited thereto. Furthermore, in an exemplary embodiment, the second emission control lines E21, E22, ... may form a pair for every at least two second emission control lines to be coupled to and / or integrated with each other. However, the exemplary embodiments of this disclosure are not limited thereto. The type and / or number of control lines included in the second gate control lines may vary depending on the structure of the second pixel PXL2.

[0109] The third pixel region AA3 is located on one side of the first pixel region AA1, the second pixel region AA2, and the first non-pixel region NA1. For example, the third pixel region AA3 can be located at the lower end of the first pixel region AA1, the second pixel region AA2, and the first non-pixel region NA1.

[0110] The third pixel region AA3 includes the third pixel PXL3, the third gate control line, and data lines D1 to Dp+q+r. Here, the third gate control line refers to the control line that controls the driving of the third pixel PXL3. For example, the third gate control line may include at least some of the following lines: third scan lines S31, S32, ... that control the driving timing of the third pixel PXL3; third initialization control lines (e.g., the last first scan line of the first pixel region AA1 and the last second scan line of the second pixel region AA2, or the third scan line of the directly adjacent preceding horizontal row); and third emission control lines E31, E32, ...

[0111] In an exemplary embodiment, each initialization control line initializing the third pixel PXL3 may be coupled to and / or integrated with the current scan line of the previous horizontal row. However, the exemplary embodiments of this disclosure are not limited thereto. Furthermore, in an exemplary embodiment, the third emitt control lines E31, E32, ... may form a pair for every at least two third emitt control lines to be coupled to and / or integrated with each other. However, the exemplary embodiments of this disclosure are not limited thereto. The type and / or number of control lines included in the third gate control lines may vary depending on the structure of the third pixel PXL3.

[0112] The first scan driver 110a may be located on one side of the first pixel region AA1 and the third pixel region AA3. As an example, the first scan driver 110a may be located on the left side of the first pixel region AA1 and the third pixel region AA3. The first scan driver 110a sequentially provides scan signals to the first scan lines S10, S11, S12, ... and the third scan lines S31, S32, ...

[0113] The second scan driver 110b may be located on one side of the second pixel region AA2 and the third pixel region AA3. As an example, the second scan driver 110b may be located on the right side of the second pixel region AA2 and the third pixel region AA3. The second scan driver 110b sequentially provides scan signals to the second scan lines S20, S21, S22, ... and the third scan lines S31, S32, ...

[0114] In an exemplary embodiment, the second scan driver 110b can provide scan signals to the second scan lines S20, S21, S22, ... in synchronization with the time when providing scan signals to the first scan lines S10, S11, S12, ... That is, the first pixel region AA1 and the second pixel region AA2 can be scanned simultaneously.

[0115] The first transmit control driver 120a may be located on one side of the first pixel region AA1 and the third pixel region AA3. As an example, the first transmit control driver 120a may be located on the left side of the first pixel region AA1 and the third pixel region AA3. The first transmit control driver 120a sequentially provides transmit control signals to the first transmit control lines E11, E12, ... and the third transmit control lines E31, E32, ...

[0116] The second transmit control driver 120b may be located on one side of the second pixel region AA2 and the third pixel region AA3. As an example, the second transmit control driver 120b may be located on the right side of the second pixel region AA2 and the third pixel region AA3. The second transmit control driver 120b sequentially provides transmit control signals to the second transmit control lines E21, E22, ... and the third transmit control lines E31, E32, ...

[0117] In an exemplary embodiment, the second transmit control driver 120b can provide transmit control signals to the second transmit control lines E21, E22, ... synchronously with the time when the transmit control signals are provided to the first transmit control lines E11, E12, ... That is, the first pixel region AA1 and the second pixel region AA2 can be driven simultaneously. In an exemplary embodiment, depending on the structure of the pixels PXL1, PXL2 and PXL3 arranged in the display area DA and / or their driving method, the first transmit control driver 120a and the second transmit control driver 120b can be omitted.

[0118] The data driver 130 receives image data from an external source (e.g., a timing controller, etc.) and generates data signals corresponding to the image data. For each horizontal cycle, the data driver 130 provides data signals to data lines D1 to Dp+q+r in synchronization with the scan signals provided to the first scan lines S10, S11, S12, ... and the second scan lines S20, S21, S22, ... and the third scan lines S31, S32, ...

[0119] Figure 17 and Figure 18 Exemplary embodiments according to this disclosure are shown respectively. Figure 16 The first scan driver and the second scan driver are shown in the diagram. Figure 17 and Figure 18 The present invention discloses an exemplary embodiment in which each of the first scan driver and the second scan driver is driven by two clock signals. However, the exemplary embodiments disclosed herein are not limited thereto. For example, in the exemplary embodiments, the number and / or type of clock signals used to drive the first scan driver and the second scan driver may vary.

[0120] First, refer to Figure 17 In one exemplary embodiment, the first scan driver 110a includes a first sub-scan driver 111 and a second sub-scan driver 112. For ease of explanation, Figure 17 The illustration shows an exemplary embodiment in which the second sub-scan driver 112 uses the output signal of the first sub-scan driver 111 (e.g., the current scan signal provided to the last horizontal row of the first pixel region AA1) as a start signal. However, the exemplary embodiments of this disclosure are not limited thereto. For example, in one exemplary embodiment of this disclosure, the second sub-scan driver 112 may be driven by a separate start signal.

[0121] The first sub-scan driver 111 includes a plurality of first scan levels SST11, SST12, ... The first sub-scan driver 111 uses a first start signal FLM1 and a first clock signal CLK1 and a second clock signal CLK2 to sequentially provide scan signals to the first scan lines S11, S12, ... In an exemplary embodiment, when at least one initialization control line (e.g., a tenth scan line S10) is further provided for initializing a first pixel PXL1 disposed on a first horizontal row of the first pixel region AA1, the first sub-scan driver 111 may further include at least one first scan level for providing a scan signal (or initialization control signal) to the tenth scan line S10 before providing a scan signal to the eleventh scan line S11.

[0122] The second sub-scan driver 112 includes multiple third scan levels SST31, SST32, ... The second sub-scan driver 112 uses the output signal of the first sub-scan driver 111 (e.g., the current scan signal provided to the last horizontal line of the first pixel region AA1) (or a separate start signal) and the first clock signal CLK1 and the second clock signal CLK2 to sequentially provide scan signals to the third scan lines S31, S32, ...

[0123] Reference Figure 18 In one exemplary embodiment, the second scan driver 110b includes a third sub-scan driver 113 and a fourth sub-scan driver 114. For ease of explanation, Figure 18 The illustration shows an exemplary embodiment in which the fourth sub-scan driver 114 uses the output signal of the third sub-scan driver 113 (e.g., the current scan signal provided to the last horizontal row of the second pixel region AA2) as a start signal. However, the exemplary embodiments of this disclosure are not limited thereto. For example, in one exemplary embodiment of this disclosure, the fourth sub-scan driver 114 may be driven by a separate start signal.

[0124] The third sub-scan driver 113 includes a plurality of second scan levels SST21, SST22, ... The third sub-scan driver 113 uses a second start signal FLM2 and a first clock signal CLK1 and a second clock signal CLK2 to sequentially provide scan signals to the second scan lines S21, S22, ... In an exemplary embodiment, the second start signal FLM2 may be provided synchronously with the first start signal FLM1. In an exemplary embodiment, when at least one initialization control line (e.g., the twentieth scan line S20) is further provided for initializing the second pixel PXL2 disposed on the first horizontal row of the second pixel region AA2, the third sub-scan driver 113 may further include at least one second scan level for providing a scan signal (or initialization control signal) to the twentieth scan line S20 before providing a scan signal to the twentieth scan line S21.

[0125] The fourth sub-scan driver 114 includes a plurality of third scan levels SST31, SST32, ... The fourth sub-scan driver 114 uses the output signal of the third sub-scan driver 113 (e.g., the current scan signal provided to the last horizontal line of the second pixel region AA2) (or a separate start signal) and a first clock signal CLK1 and a second clock signal CLK2 to sequentially provide scan signals to the third scan lines S31, S32, ... In an exemplary embodiment, the third scan levels SST31, SST32, ... disposed in the second sub-scan driver 112 and the fourth sub-scan driver 114 may have substantially the same construction and thus can be driven synchronously with each other.

[0126] In one exemplary embodiment of this disclosure, there are no specific limitations on the construction of the first scan levels SST11, SST12, ..., the second scan levels SST21, SST22, ..., and the third scan levels SST31, SST32, .... That is, various types of scan level circuits can be used to implement the first scan levels SST11, SST12, ..., the second scan levels SST21, SST22, ..., and the third scan levels SST31, SST32, ....

[0127] Figure 19 and Figure 20 Exemplary embodiments according to this disclosure are shown respectively. Figure 16 The first and second transmit control drivers are shown in the diagram. Figure 19 and Figure 20 The present invention discloses an exemplary embodiment in which each of the first and second transmit control drivers is driven by two clock signals. However, the exemplary embodiments disclosed herein are not limited thereto. For example, the number and / or type of clock signals used to drive the first and second transmit control drivers may vary.

[0128] First, refer to Figure 19 In one exemplary embodiment, the first transmit control driver 120a includes a first sub-transmit control driver 121 and a second sub-transmit control driver 122. For ease of explanation, Figure 19 The illustration shows an exemplary embodiment in which the second sub-emission control driver 122 uses the output signal of the first sub-emission control driver 121 (e.g., an emission control signal provided to the last horizontal row of the first pixel region AA1) as a start signal. However, the exemplary embodiments of this disclosure are not limited thereto. For example, in one exemplary embodiment of this disclosure, the second sub-emission control driver 122 may be driven by a separate start signal.

[0129] The first sub-transmit control driver 121 includes a plurality of first transmit control stages EST11, EST12, ... . The first sub-transmit control driver 121 uses a third start signal EFLM1 and a third clock signal CLK3 and a fourth clock signal CLK4 to sequentially provide transmit control signals to the first transmit control lines E11, E12, E13, E14, ... In an exemplary embodiment, when the first transmit control lines E11, E12, E13, E14, ... form a pair for each plurality of first transmit control lines (e.g., each pair of first transmit control lines) to be coupled to each other, the first sub-transmit control driver 121 may sequentially provide transmit control signals to the pairs of first transmit control lines E11 and E12, E13 and E14, ...

[0130] The second sub-transmit control driver 122 includes a plurality of third transmit control levels EST31, EST32, ... . The second sub-transmit control driver 122 uses the output signal of the first sub-transmit control driver 121 (e.g., a transmit control signal provided to the last horizontal row of the first pixel region AA1) (or a separate start signal) and a third clock signal CLK3 and a fourth clock signal CLK4 to sequentially provide transmit control signals to the third transmit control lines E31, E32, E33, E34, ... . In an exemplary embodiment, when the third transmit control lines E31, E32, E33, E34, ... form a pair for each plurality of third transmit control lines (e.g., each pair of third transmit control lines) to be coupled to each other, the second sub-transmit control driver 122 may sequentially provide transmit control signals to the pairs of third transmit control lines E31 and E32, E33 and E34, ...

[0131] Reference Figure 20 In one exemplary embodiment, the second transmit control driver 120b includes a third sub-transmit control driver 123 and a fourth sub-transmit control driver 124. For ease of explanation, Figure 20 The illustration shows an exemplary embodiment in which the fourth sub-emission control driver 124 uses the output signal of the third sub-emission control driver 123 (e.g., an emission control signal provided to the last horizontal row of the second pixel region AA2) as a start signal. However, the exemplary embodiments of this disclosure are not limited thereto. For example, in one exemplary embodiment of this disclosure, the fourth sub-emission control driver 124 may be driven by a separate start signal.

[0132] The third sub-transmit control driver 123 includes multiple second transmit control stages EST21, EST22, ... . The third sub-transmit control driver 123 sequentially provides transmit control signals to the second transmit control lines E21, E22, E23, E24, ... using a fourth start signal EFLM2 and a third clock signal CLK3 and a fourth clock signal CLK4. In an exemplary embodiment, the fourth start signal EFLM2 may be provided synchronously with the third start signal EFLM1. When the second transmit control lines E21, E22, E23, E24, ... form a pair for each plurality of second transmit control lines (e.g., each pair of second transmit control lines) to be coupled to each other, the third sub-transmit control driver 123 may sequentially provide transmit control signals to the pairs of second transmit control lines E21 and E22, E23 and E24, ...

[0133] The fourth sub-emit control driver 124 includes a plurality of third transmit control stages EST31, EST32, ... . The fourth sub-emit control driver 124 uses the output signal of the third sub-emit control driver 123 (e.g., a transmit control signal provided to the last horizontal row of the second pixel region AA2) (or a separate start signal) to sequentially provide transmit control signals to the third transmit control lines E31, E32, E33, E34, ... In an exemplary embodiment, when the third transmit control lines E31, E32, E33, E34, ... form a pair for each plurality of third transmit control lines (e.g., each pair of third transmit control lines) to be coupled to each other, the fourth sub-emit control driver 124 may sequentially provide transmit control signals to the pairs of third transmit control lines E31 and E32, E33 and E34, ... In an exemplary embodiment, the third transmit control stages EST31, EST32, ... provided in the second sub-emit control driver 122 and the fourth sub-emit control driver 124 may have substantially the same construction and thus can be driven synchronously with each other.

[0134] In one exemplary embodiment of this disclosure, the construction of the first transmit control levels EST11, EST12, ..., the second transmit control levels EST21, EST22, ..., and the third transmit control levels EST31, EST32, ... is not specifically limited. For example, various types of transmit control levels can be used to implement the first transmit control levels EST11, EST12, ..., the second transmit control levels EST21, EST22, ..., and the third transmit control levels EST31, EST32, ....

[0135] according to Figures 16 to 20 The exemplary embodiment shown provides multiple scan drivers 110a and 110b, as well as multiple emission control drivers 120a and 120b, such that the display area DA can be smoothly driven even when the first gate control line and the second gate control line are separated from each other. However, in the exemplary embodiment described above, multiple scan levels SST and / or multiple emission control levels EST are provided to drive a horizontal row. Therefore, limitations may arise in reducing the area of ​​the second non-pixel region NA2.

[0136] Figure 21 and Figure 22 Each shows a display panel according to an exemplary embodiment of the present disclosure. Figure 21 and Figure 22 In, with Figure 16 Components that are similar or identical to those in the text are indicated by similar reference numerals, and their further detailed descriptions will be omitted.

[0137] First, refer to Figure 21In one exemplary embodiment, the first scan driver 110a and the second scan driver 110b described in the above exemplary embodiments are integrated into a single scan driver 110. For example, the integrated scan driver 110 may be located on either side (e.g., the left side) of the display area DA, and sequentially drive the first, second, and third scan lines S10 / S20, S11 / S21, S12 / S22, ..., S31, S32, ... in units of horizontal rows of the display area DA.

[0138] Furthermore, the first transmit control driver 120a and the second transmit control driver 120b described in the above exemplary embodiments can also be integrated into a single transmit control driver 120. For example, the integrated transmit control driver 120 can be located on either side (e.g., the right side) of the display area DA, and sequentially drives the first, second, and third transmit control lines E11 / E21, E12 / E22, ..., E31, E32, ... in units of horizontal rows of the display area DA. The transmit control driver 120 can be located on the same side as the scan driver 110, or on a different side. As an example, the scan driver 110 can be located on the left side of the display area DA, and the transmit control driver 120 can be located on the right side of the display area DA, such as... Figure 21 As shown in the image.

[0139] The first coupling line CNL1 can be disposed in the first non-pixel region NA1, thereby driving the first pixel region AA1, the second pixel region AA2, and the third pixel region AA3 using a scan driver 110 and an emitt control driver 120. Here, the first coupling line CNL1 can connect the corresponding lines among the first gate lines and the second gate lines disposed in the first pixel region AA1 and the second pixel region AA2.

[0140] As an example, the first initialization control lines (e.g., the tenth scan line S10 and the twentieth scan line S20) disposed on the first horizontal rows of the first pixel region AA1 and the second pixel region AA2 can be coupled to each other via any one of the first coupling lines CNL1 (e.g., the first first coupling line), and the first current scan lines (e.g., the eleventh scan line S11 and the twenty-first scan line S21) disposed on the first horizontal rows can be coupled to each other via another of the first coupling lines CNL1 (e.g., the second first coupling line). Furthermore, the first emission control lines (e.g., the eleventh emission control line E11 and the twenty-first emission control line E21) disposed on the first horizontal rows can be coupled to each other via another of the first coupling lines CNL1 (e.g., the third first coupling line). In this manner, the first gate control lines and the second gate control lines disposed on each horizontal row of the first pixel region AA1 and the second pixel region AA2 can be coupled to each other via each of the first coupling lines CNL1.

[0141] In an exemplary embodiment, each of the scan driver 110 and the transmit control driver 120 may be configured to be divided into two blocks. For example, as Figure 22 As shown, the odd-numbered scan stage block 110c, which provides scan signals for the odd-numbered scan lines So of the display area DA, and the even-numbered scan stage block 110d, which provides scan signals for the even-numbered scan lines Se of the display area DA, can be located on different sides of the display area DA. Similarly, the odd-numbered transmission control stage block 120c, which provides transmission control signals for the odd-numbered transmission control lines Eo, and the even-numbered transmission control stage block 120d, which provides transmission control signals for the even-numbered transmission control lines Ee, can be located on different sides of the display area DA.

[0142] In this scenario, although each of the scan driver 110 and the transmit control driver 120 is divided into two blocks 110c and 110d or 120c and 120d located on different sides of the display area DA, the area of ​​the stage circuitry disposed in the display panel 100 can be approximately the same as... Figure 21 The corresponding area is similar in the exemplary implementation. For example, with Figure 16 Compared to the exemplary implementation, the area of ​​the stage circuit can be reduced to about half.

[0143] according to Figure 21 and Figure 22In the exemplary embodiment described above, the area occupied by the driving circuit in the display panel 100 is reduced, thus the area of ​​the second non-pixel region NA2 can be reduced. However, in the above exemplary embodiment, multiple first coupling lines CNL1 corresponding to the number of first gate control lines and second gate control lines disposed in the first pixel region AA1 and the second pixel region AA2 are disposed in the first non-pixel region NA1. Therefore, the area of ​​the first non-pixel region NA1 can be increased.

[0144] Figures 23 to 26 Each shows a region of a display panel according to an exemplary embodiment of the present disclosure. Figures 23 to 26 The structure of the display panel 100 is shown in the illustration to highlight the main features of each exemplary embodiment. Therefore, illustrations and further descriptions of some components that are similar to or the same as those in the exemplary embodiments described above will be omitted.

[0145] First, refer to Figure 23 In one exemplary embodiment, first emission control lines E1i, E1i+1, E1i+2, and E1i+3 are disposed on respective horizontal rows in the first pixel region AA1. Each of the first emission control lines E1i, E1i+1, E1i+2, and E1i+3 may be coupled to at least one adjacent first emission control line.

[0146] For example, the i-th first transmission control line E1i and the (i+1)-th first transmission control line E1i+1, respectively located on the i-th horizontal row and the (i+1)-th horizontal row of the first pixel region AA1, can be coupled to each other to be provided with the same first transmission control signal. As an example, the i-th first transmission control line E1i and the (i+1)-th first transmission control line E1i+1 can be coupled together to the k-th (k is a natural number) transmission control level ESTk, and thus, the first transmission control signal is simultaneously provided from the k-th transmission control level ESTk.

[0147] Furthermore, the (i+2)th first transmit control line E1i+2 and the (i+3)th first transmit control line E1i+3, respectively located on the (i+2)th and (i+3)th horizontal rows of the first pixel region AA1, can be coupled to each other, and thus, are provided with the same first transmit control signal. As an example, the (i+2)th first transmit control line E1i+2 and the (i+3)th first transmit control line E1i+3 can be jointly coupled to the (k+1)th transmit control level ESTk+1, and thus, the first transmit control signal is simultaneously provided from the (k+1)th transmit control level ESTk+1.

[0148] Similarly, second emission control lines E2i, E2i+1, E2i+2, and E2i+3 are disposed on each horizontal row in the second pixel region AA2. Each of the second emission control lines E2i, E2i+1, E2i+2, and E2i+3 can be coupled to at least one adjacent second emission control line. For example, the i-th second emission control line E2i and the (i+1)-th second emission control line E2i+1 disposed on the i-th horizontal row and the (i+1)-th horizontal row of the second pixel region AA2, respectively, can be coupled to each other and thus provided with the same second emission control signal. Furthermore, the (i+2)-th second emission control line E2i+2 and the (i+3)-th second emission control line E2i+3 disposed on the (i+2)-th horizontal row and the (i+3)-th horizontal row of the second pixel region AA2, respectively, can be coupled to each other and thus provided with the same second emission control signal.

[0149] In this exemplary embodiment, the simultaneously driven emission control lines among the first emission control lines E1i, E1i+1, E1i+2, and E1i+3 and the second emission control lines E2i, E2i+1, E2i+2, and E2i+3 disposed on the respective horizontal rows of the first pixel region AA1 and the second pixel region AA2 are electrically coupled to each other through any one of the first couplers CNL1 disposed in the first non-pixel region NA1. For example, the i-th first emission control line E1i and the (i+1)-th first emission control line E1i+1 disposed on the i-th horizontal row and the (i+1)-th horizontal row of the first pixel region AA1, respectively, and the i-th second emission control line E2i and the (i+1)-th second emission control line E2i+1 disposed on the i-th horizontal row and the (i+1)-th horizontal row of the second pixel region AA2, respectively, can be jointly coupled through the k-th first coupler CNL1k. In this scenario, the i-th first transmit control line E1i and the (i+1)-th first transmit control line E1i+1, as well as the i-th second transmit control line E2i and the (i+1)-th second transmit control line E2i+1, can simultaneously receive a first transmit control signal and a second transmit control signal from any transmit control level (such as, for example, the k-th transmit control level ESTk) provided in the transmit control driver 120.

[0150] Similarly, the (i+2)th and (i+3)th first emission control lines E1i+2 and E1i+3 respectively located in the (i+2)th and (i+3)th horizontal rows of the first pixel region AA1, and the (i+2)th and (i+3)th second emission control lines E2i+2 and E2i+3 respectively located in the (i+2)th and (i+3)th horizontal rows of the second pixel region AA2, can be coupled to any one of the first couplers CNL1. As an example, the (i+2)th and (i+3)th first emission control lines E1i+2 and E1i+3, and the (i+2)th and (i+3)th second emission control lines E2i+2 and E2i+3 can be coupled together to the (k+1)th first coupler CNL1k+1. In this scenario, the (i+2)th first transmit control line E1i+2 and the (i+3)th first transmit control line E1i+3, as well as the (i+2)th second transmit control line E2i+2 and the (i+3)th second transmit control line E2i+3, can simultaneously receive a first transmit control signal and a second transmit control signal from any transmit control level (such as, for example, the (k+1)th transmit control level ESTk+1) provided in the transmit control driver 120.

[0151] Here, when a coupling line is said to couple at least two gate control lines together, it will be understood that the coupling line connects the at least two gate control lines to each other. For example, as Figure 23 As shown, the i-th first transmit control line E1i and the (i+1)-th first transmit control line E1i+1, as well as the i-th second transmit control line E2i and the (i+1)-th second transmit control line E2i+1, are coupled to the same coupling wire (e.g., the k-th first coupling wire CNL1k). Therefore, the i-th first transmit control line E1i and the (i+1)-th first transmit control line E1i+1 are jointly coupled to the k-th first coupling wire CNL1k, and the i-th second transmit control line E2i and the (i+1)-th second transmit control line E2i+1 are jointly coupled to the k-th first coupling wire CNL1k. That is, the k-th first coupling wire CNL1k is jointly coupled to the i-th first transmit control line E1i and the (i+1)-th first transmit control line E1i+1, as well as the i-th second transmit control line E2i and the (i+1)-th second transmit control line E2i+1.

[0152] Reference Figure 1 and Figure 23In one exemplary embodiment, the substrate 101 of the display device includes a first protrusion 101a, a second protrusion 101a disposed opposite to the first protrusion 101a, and a cutout region 101b disposed between the first protrusion 101a and the second protrusion 101a. A first pixel region AA1 is disposed on the first protrusion 101a. The first pixel region AA1 includes a first row of first pixels PXL1 and a first gate control line (e.g., E1i) coupled to the first row of first pixels PXL1, and a second row of first pixels PXL1 and a second gate control line (e.g., E1i+1) coupled to the second row of first pixels PXL1. A second pixel region AA2 is disposed on the second protrusion 101a. The second pixel region AA2 includes a first row of second pixels PXL2 and a third gate control line (e.g., E2i) coupled to the first row of second pixels PXL2, and a second row of second pixels PXL2 and a fourth gate control line (e.g., E2i+1) coupled to the second row of second pixels PXL2. A first non-pixel region NA1 is disposed in the notch region 101b. A first coupling line (e.g., CNL1k) is disposed in the first non-pixel region NA1. The first coupling line (e.g., CNL1k) is coupled to a first gate control line (e.g., E1i), a second gate control line (e.g., E1i+1), a third gate control line (e.g., E2i), and a fourth gate control line (e.g., E2i+1).

[0153] In the manner described above, the simultaneously driven emission control lines among the first emission control lines E1i, E1i+1, E1i+2, and E1i+3 and the second emission control lines E2i, E2i+1, E2i+2, and E2i+3, which are set on each horizontal row of the first pixel region AA1 and the second pixel region AA2, are coupled together through a first coupler line (e.g., either CNL1k or CNL1k+1) in the first non-pixel region NA1. Therefore, with Figure 21 and Figure 22 Compared to the exemplary implementation shown, the number of first coupling wires CNL1k and CNL1k+1 disposed in the first non-pixel region NA1 can be reduced.

[0154] Figure 23 The present disclosure discloses an exemplary embodiment in which transmission control level ESTk and transmission control level ESTk+1 in the transmission control driver 120 are sequentially arranged on the same side of the display area DA (e.g., on one side of the first pixel area AA1 or the second pixel area AA2). However, the exemplary embodiments disclosed herein are not limited thereto. For example, as Figure 24 As shown, in an exemplary embodiment, the emission control levels ESTk and ESTk+1 may be alternately disposed on one side of the first pixel region AA1 and on one side of the second pixel region AA2.

[0155] Furthermore, despite Figure 23 and Figure 24 The present disclosure only discloses an exemplary embodiment in which the simultaneously driven transmission control lines among the first transmission control lines E1i, E1i+1, E1i+2, and E1i+3 and the second transmission control lines E2i, E2i+1, E2i+2, and E2i+3 are coupled to a first coupling line (e.g., either CNL1k or CNL1k+1). However, it will be understood that the exemplary embodiments of this disclosure are not limited thereto. For example, as... Figure 25 and Figure 26 As shown, in an exemplary embodiment, the initialization control lines and scan lines that are driven simultaneously among the first initialization control lines CL1i, CL1i+1, CL1i+2 and CL1i+3, the second initialization control lines CL2i, CL2i+1, CL2i+2 and CL2i+3, the first scan lines S1i, S1i+1, S1i+2 and S1i+3, and the second scan lines S2i, S2i+1, S2i+2 and S2i+3 can be coupled to a first coupling line (e.g., any one of CNL1i, CNL1i+1, CNL1i+2 and CNL1i+3).

[0156] As an example, the i-th first scan line S1i and the i-th second scan line S2i respectively disposed on the i-th horizontal row of the first pixel region AA1 and the i-th horizontal row of the second pixel region AA2, and the (i+1)-th first initialization control line CL1i+1 and the (i+1)-th second initialization control line CL2i+1 respectively disposed on the (i+1)-th horizontal row of the first pixel region AA1 and the (i+1)-th horizontal row of the second pixel region AA2 can be jointly coupled to the i-th coupling line CNL1i disposed in the first non-pixel region NA1. Furthermore, the i-th first scan line S1i and the i-th second scan line S2i, and the (i+1)-th first initialization control line CL1i+1 and the (i+1)-th second initialization control line CL2i+1 can be jointly coupled to the i-th scan level SSTi disposed in the scan driver 110, thus providing the i-th scan signal (or the (i+1)-th initialization control signal) simultaneously from the i-th scan level SSTi.

[0157] Furthermore, the (i+1)th first scan line S1i+1 and the (i+1)th second scan line S2i+1 respectively set on the (i+1)th horizontal row of the first pixel region AA1 and the second pixel region AA2, as well as the (i+2)th first initialization control line CL1i+2 and the (i+2)th second initialization control line CL2i+2 respectively set on the (i+2)th horizontal row of the first pixel region AA1 and the second pixel region AA2, can be coupled together to the (i+1)th first coupling line CNL1i+1 set in the first non-pixel region NA1. The (i+1)th first scan line S1i+1 and the (i+1)th second scan line S2i+1, as well as the (i+2)th first initialization control line CL1i+2 and the (i+2)th second initialization control line CL2i+2, can be coupled together to the (i+1)th scan level SSTi+1 provided in the scan driver 110. Therefore, the (i+1)th scan signal (or the (i+2)th initialization control signal) is simultaneously provided from the (i+1)th scan level SSTi+1.

[0158] In the manner described above, the initialization control lines CL1i, CL1i+1, CL1i+2, and CL1i+3, the second initialization control lines CL2i, CL2i+1, CL2i+2, and CL2i+3, and the first scan lines S1i, S1i+1, S1i+2, and S1i+3 and the second scan lines S2i, S2i+1, S2i+2, and S2i+3, which are driven simultaneously, can be coupled to a first coupling line (e.g., any one of CNL1i, CNL1i+1, CNL1i+2, and CNL1i+3) to be driven by the same scan level (e.g., any one of SSTi, SSTi+1, SSTi+2, and SSTi+3). Therefore, with Figure 21 and Figure 22 Compared to the exemplary implementation shown, the number of first coupling wires CNL1 disposed in the first non-pixel region NA1 can be reduced.

[0159] Additionally, the scan levels SSTi, SSTi+1, SSTi+2, and SSTi+3 set in the scan driver 110 can be sequentially set on the same side of the display area DA (e.g., on one side of the first pixel area AA1 or the second pixel area AA2), such as... Figure 25 As shown in the diagram. Optionally, scan levels SSTi, SSTi+1, SSTi+2, and SSTi+3 can be alternately set on one side of the first pixel region AA1 and one side of the second pixel region AA2, as shown in the diagram. Figure 26 As shown in the image.

[0160] according to Figures 23 to 26In the exemplary embodiment shown, at least two first gate control lines and at least two second gate control lines, which are substantially simultaneously driven by substantially the same drive signal, are integrally coupled through a first coupling line (e.g., CNL1k or CNL1i) in the first non-pixel region NA1. According to the above exemplary embodiment, the first pixel region AA1 and the second pixel region AA2 are driven by a scan driver 110 and / or an emitt control driver 120. As a result, the area of ​​the second non-pixel region NA2 can be reduced.

[0161] Furthermore, according to the above exemplary embodiment, the first control line and the second control line to which the same control signal is applied are integrally coupled through a first coupling wire in the first non-pixel region NA1. As a result, the number of first coupling wires CNL1k, CNL1k+1, CNL1i, CNL1i+1, CNL1i+2, and CNL1i+3 provided in the first non-pixel region NA1 can be reduced. As an example, when utilizing... Figures 23 to 26 In the exemplary implementation, with Figure 21 and Figure 22 Compared to the exemplary implementation shown, the number of first coupling wires CNL1k, CNL1k+1, CNL1i, CNL1i+1, CNL1i+2, and CNL1i+3 can be reduced to about half.

[0162] Therefore, according to the above exemplary embodiments, the line structure of the first non-pixel region NA1 can be simplified, thereby effectively reducing the area of ​​the first non-pixel region NA1.

[0163] Figure 27 and Figure 28 Each shows a region of a display panel according to an exemplary embodiment of the present disclosure. Figure 27 and Figure 28 In this document, components that are similar to or the same as those in the exemplary embodiments described above are indicated by similar reference numerals, and further detailed descriptions of these components will be omitted.

[0164] First, refer to Figure 27 A pair of first emission control lines E1i and E1i+1, or E1i+2 and E1i+3, may be coupled to each other on both sides of the first pixel region AA1. As an example, the pair of first emission control lines E1i and E1i+1, or E1i+2 and E1i+3, may be coupled to each other in a second non-pixel region NA2 on the left side of the first pixel region AA1 and a first non-pixel region NA1 on the right side of the first pixel region AA1.

[0165] Furthermore, a pair of second emission control lines E2i and E2i+1, or E2i+2 and E2i+3, may be coupled to each other on both sides of the second pixel region AA2. As an example, the pair of first emission control lines E2i and E2i+1, or E2i+2 and E2i+3, may be coupled to each other in a first non-pixel region NA1 on the left side of the second pixel region AA2 and a second non-pixel region NA2 on the right side of the second pixel region AA2.

[0166] Therefore, the display panel 100 according to this exemplary embodiment further includes second coupling lines CNL2k and CNL2k+1, each of which is disposed on one side of the first pixel region AA1 or the second pixel region AA2. For example, the display panel 100 may include a k-th second coupling line CNL2k on one side of the first pixel region AA1 or the second pixel region AA2, the k-th second coupling line CNL2k coupling the i-th first transmission control line E1i and the (i+1)-th first transmission control line E1i+1, or the i-th second transmission control line E2i and the (i+1)-th second transmission control line E2i+1. As an example, the kth second coupling line CNL2k can be located on the opposite side of the kth transmit control level ESTk, which provides transmit control signals to the transmit control lines coupled to it (e.g., the i-th first transmit control line E1i and the (i+1)-th first transmit control line E1i+1, and the i-th second transmit control line E2i and the (i+1)-th second transmit control line E2i+1).

[0167] Next, refer to Figure 28 In one exemplary embodiment, the first scan lines S1i, S1i+1, S1i+2, and S1i+3, and the first initialization control lines CL1i, CL1i+1, CL1i+2, and CL1i+3, which are driven substantially simultaneously by substantially the same signal, are coupled to each other on both sides of the first pixel region AA1. As an example, the i-th first scan line S1i and the (i+1)-th first initialization control line CL1i+1 may be coupled to each other in a second non-pixel region NA2 on the left side of the first pixel region AA1 and a first non-pixel region NA1 on the right side of the first pixel region AA1.

[0168] Furthermore, the second scan lines S2i, S2i+1, S2i+2, and S2i+3, and the second initialization control lines CL2i, CL2i+1, CL2i+2, and CL2i+3, which are driven substantially simultaneously by substantially the same signal, can be coupled to each other on both sides of the second pixel region AA2. As an example, the i-th second scan line S2i and the (i+1)-th second initialization control line CL2i+1 can be coupled to each other in the first non-pixel region NA1 on the left side of the second pixel region AA2 and the second non-pixel region NA2 on the right side of the second pixel region AA2.

[0169] Therefore, the display panel 100 according to this exemplary embodiment further includes third coupling lines CNL3i, CNL3i+1, CNL3i+2, and CNL3i+3, each of which is disposed on one side of the first pixel region AA1 or the second pixel region AA2. For example, the display panel 100 may include an i-th third coupling line CNL3i on one side of the first pixel region AA1 or the second pixel region AA2, the i-th third coupling line CNL3i coupling the i-th first scan line S1i and the (i+1)-th first initialization control line CL1i+1, or the i-th second scan line S2i and the (i+1)-th second initialization control line CL2i+1. As an example, the i-th third coupling line CNL3i can be located on the opposite side of the i-th scan level SSTi, which provides scan signals (or initialization control signals) to the scan lines and initialization control lines coupled thereto (e.g., the i-th first scan line S1i and the i-th second scan line S2i, and the (i+1)-th first initialization control line CL1i+1 and the (i+1)-th second initialization control line CL2i+1).

[0170] according to Figure 27 and Figure 28 In the exemplary embodiment shown, although at least one of the first coupling lines CNL1k, CNL1k+1, CNL1i, CNL1i+1, CNL1i+2, and CNL1i+3 may be disconnected in or near the first non-pixel region NA1, the first gate control line and the second gate control line can still be driven normally. Therefore, according to the above exemplary embodiment, driving stability is ensured.

[0171] Figure 29 and Figure 30 Each shows a region of a display panel according to an exemplary embodiment of the present disclosure. Figure 29 and Figure 30In this document, components that are similar to or the same as those in the exemplary embodiments described above are indicated by similar reference numerals, and further detailed descriptions of these components will be omitted.

[0172] Reference Figure 29 and Figure 30 ,and Figure 21 and Figure 22 Similar to the exemplary embodiment shown, the first gate control line and the second gate control line, respectively disposed on the horizontal rows of the first pixel region AA1 and the second pixel region AA2, are coupled to each other through each first coupling line. Furthermore, with... Figure 27 and Figure 28 Similar to the exemplary implementation shown, the second coupling wires CNL2k and CNL2k+1 and / or the third coupling wires CNL3i, CNL3i+1, CNL3i+2 and CNL3i+3 are disposed on one side of the first pixel region AA1 or the second pixel region AA2.

[0173] According to the above exemplary embodiment, the area occupied by the driving circuit in the display panel 100 is reduced, thus the area of ​​the second non-pixel region NA2 can be reduced. Furthermore, although at least one of the first coupling lines CNL1 in the first non-pixel region NA1 may be disconnected, the first gate control line and the second gate control line can still be driven normally.

[0174] Figure 31 An area of ​​a display panel according to yet another exemplary embodiment of this disclosure is shown. Figure 31 In this document, components that are similar to or the same as those in the exemplary embodiments described above are indicated by similar reference numerals, and their detailed descriptions will be omitted.

[0175] Reference Figure 31 ,and Figure 12Similar to the exemplary implementation shown, in one exemplary implementation, the display panel 100 includes an opening OPN disposed in a first non-pixel region NA1. Furthermore, a first coupling line CNL1k and a first coupling line CNL1k+1 may be disposed at the upper and lower ends of the opening OPN in the first non-pixel region NA1, respectively. As an example, the kth first coupling line CNL1k may couple the i-th first transmission control line E1i and the (i+1)-th first transmission control line E1i+1, as well as the i-th second transmission control line E2i and the (i+1)-th second transmission control line E2i+1, via the first non-pixel region NA1 at the upper end of the opening OPN. Furthermore, the (k+1)th first coupling line CNL1k+1 can couple the (i+2)th first transmit control line E1i+2 and the (i+3)th first transmit control line E1i+3, as well as the (i+2)th second transmit control line E2i+2 and the (i+3)th second transmit control line E2i+3, via the first non-pixel region NA1 at the lower end of the open OPN.

[0176] As described above, in the display device according to the exemplary embodiments of the present disclosure, the structure and / or shape of the display panel 100 can be modified and implemented in various ways.

[0177] According to an exemplary embodiment of this disclosure, a display device includes a first pixel region and a second pixel region separated from each other, with a first non-pixel region interposed between the first pixel region and the second pixel region. As a result, the number of coupling lines disposed in the first non-pixel region is reduced in the exemplary embodiment of this disclosure. Therefore, the line structure of the first non-pixel region can be simplified, and consequently, the area of ​​the first non-pixel region can be reduced.

[0178] Although this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the claims.

Claims

1. A display device, comprising: A first pixel region, the first pixel region including a plurality of first pixels and a plurality of first gate control lines coupled to the plurality of first pixels; A second pixel region separated from the first pixel region, wherein the second pixel region includes a plurality of second pixels and a plurality of second gate control lines coupled to the plurality of second pixels; A first non-pixel region is disposed between the first pixel region and the second pixel region; and Multiple first coupling lines are disposed in the first non-pixel region, wherein one of the multiple first coupling lines couples together at least two first gate control lines disposed in the first pixel region and at least two second gate control lines disposed in the second pixel region.

2. The display device according to claim 1, wherein the first gate control line includes at least some of a plurality of first scan lines, a plurality of first initialization control lines, and a plurality of first emission control lines that control the driving of the plurality of first pixels, and The second gate control line includes at least some of the following: multiple second scan lines, multiple second initialization control lines, and multiple second emission control lines that control the driving of the plurality of second pixels.

3. The display device according to claim 2, wherein, One of the multiple first coupling lines will be coupled together with the i-th first emission control line and the i+1-th first emission control line respectively set on the i-th horizontal row and the i+1-th horizontal row of the first pixel region, and the i-th second emission control line and the i+1-th second emission control line respectively set on the i-th horizontal row and the i+1-th horizontal row of the second pixel region, where i is a natural number.

4. The display device according to claim 3, further comprising: A second coupling wire is disposed on one side of the first pixel region or the second pixel region, wherein the second coupling wire couples the i-th first emission control line and the (i+1)-th first emission control line, or the i-th second emission control line and the (i+1)-th second emission control line.

5. The display device according to claim 3, further comprising: A transmit control driver, comprising a k-th transmit control stage, which provides transmit control signals for the i-th first transmit control line and the (i+1)-th first transmit control line, as well as the i-th second transmit control line and the (i+1)-th second transmit control line, where k is a natural number.

6. The display device according to claim 5, wherein the emission control driver includes a plurality of emission control stages sequentially disposed on one side of the first pixel region or the second pixel region, wherein the plurality of emission control stages includes the k-th emission control stage.

7. The display device according to claim 5, wherein the emission control driver includes a plurality of emission control stages alternately disposed on one side of the first pixel region and one side of the second pixel region, wherein the plurality of emission control stages includes the k-th emission control stage.

8. The display device according to claim 2, wherein, One of the multiple first coupling lines will be coupled together with the i-th first scan line and the i-th second scan line respectively set on the i-th horizontal row of the first pixel region and the i-th horizontal row of the second pixel region, as well as the i+1-th first initialization control line and the i+1-th second initialization control line respectively set on the i+1-th horizontal row of the first pixel region and the i+1-th horizontal row of the second pixel region, where i is a natural number.

9. The display device according to claim 8, further comprising: The third coupling wire is disposed on one side of the first pixel region or the second pixel region, wherein the third coupling wire couples the i-th first scan line and the (i+1)-th first initialization control line, or the i-th second scan line and the (i+1)-th second initialization control line.

10. The display device according to claim 8, further comprising: A scan driver, the scan driver including an i-th scan level, the i-th scan level providing scan signals for the i-th first scan line, the i-th second scan line, the (i+1)-th first initialization control line and the (i+1)-th second initialization control line.

11. The display device according to claim 10, wherein the scan driver comprises: Multiple scan levels are sequentially arranged on one side of the first pixel region or the second pixel region, wherein the multiple scan levels include the i-th scan level.

12. The display device according to claim 10, wherein the scan driver comprises: Multiple scan levels are alternately disposed on one side of the first pixel region and one side of the second pixel region, wherein the multiple scan levels include the i-th scan level.

13. The display device according to claim 1, further comprising: A third pixel region is disposed on one side of the first pixel region and the second pixel region and contacts the first pixel region and the second pixel region, wherein the third pixel region includes a plurality of third pixels.

14. The display device according to claim 13, further comprising: A fourth pixel region is disposed opposite to the third pixel region, wherein the first pixel region, the second pixel region, and the first non-pixel region are interposed between the third pixel region and the fourth pixel region.

15. The display device according to claim 14, further comprising: An opening is provided in the first non-pixel region.

16. The display device according to claim 1, further comprising: A substrate, wherein the plurality of first pixels and the plurality of second pixels are arranged on one surface of the substrate. The substrate includes a plurality of protrusions corresponding to the first pixel region and the second pixel region, and a recess corresponding to the first non-pixel region.

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