A charge balancing method for touch capacitance monitoring

Abstract

The application belongs to the technical field of intelligent electronic equipment control and monitoring, and relates to a charge balance type touch capacitance monitoring method; a charge balance type touch capacitance monitoring chip is applied to monitor a touch capacitance CX, and the specific steps are as follows: (1) charging the touch capacitance, (2) discharging the touch capacitance, (3) discharging the capacitance CDC, (4) pulse number statistics, counting the discharging frequency of the capacitance CDC by using a counter module; (5) average value calculation: an AVERAGE average module calculates the average value of the pulse number in a period, (6) difference calculation: the difference between the sampling value and the average value is calculated in an A-B subtracter, (7) touch judgment: when the difference is greater than a critical value LN, it is considered that the capacitance CX is touched; the method has excellent electromagnetic compatibility and strong anti-interference, and the final judgment result is not affected by the power voltage; as long as the CDC is adjusted, the sensitivity can be adjusted, and the judgment result is accurate.

Description

Technical fields:

[0001] This invention belongs to the field of intelligent electronic device control and monitoring technology. It relates to a device for monitoring changes in touch capacitance voltage, which uses these changes to control the opening and closing of mechanical equipment. Specifically, it relates to a charge balance-based touch capacitance monitoring method, which can accurately and sensitively sense changes in touch capacitance. Background technology:

[0002] Capacitive sensing technology is based on the principle that when an object's surface is touched or undergoes any other change, the dielectric properties of a certain area within the object change, thereby altering the object's capacitance—that is, generating a voltage change. Compared to resistive touch technology, the capacitance change is much faster. The speed of change can be further increased by enhancing the dielectric properties of the surface material. Capacitive sensors can directly or indirectly sense various parameters, including electric fields, motion, chemical properties, acceleration, fluid properties, and pressure. The sensor surface consists of electrodes surrounding a certain medium; with the aid of a detection circuit and an excitation voltage, this medium can convert the capacitance change into a changing voltage.

[0003] In the prior art, Chinese Patent Publication No. CN114356145A discloses a touch detection circuit, a touch device, and an electronic device. The circuit includes: a first delay unit, a delay phase-locked loop (PLL) unit, and a detection unit; the PLL unit includes a phase detection module and a second delay module; the first delay unit generates a first clock signal based on a reference clock signal and a capacitor under test; the second delay module generates a second clock signal based on the reference clock signal and a variable capacitor; the phase detection module is adapted to receive the first clock signal and the second clock signal, and generate a corresponding output signal based on the relationship between a first delay time of the first clock signal and a second delay time of the second clock signal, until the PLL unit reaches a locked state; the detection unit is adapted to determine whether a touch has occurred based on the output signal of the phase detection module. Chinese Patent Publication No. CN110412348A discloses a count value generation circuit, a physical quantity sensor module, and a structure monitoring device, which can improve the accuracy of the count value. The counting value generation circuit includes: a first counting unit that counts the edges of a reference signal synchronously with the input signal and generates a first count value; a time digital value generation unit that generates a time digital value corresponding to the phase difference between the reference signal and the input signal; a count accumulation value synthesis unit that outputs an integer multiple of the first count value and the difference between the time digital value; and a count value generation unit that generates a count value based on the difference between a first output value and a second output value output from the count accumulation value synthesis unit.

[0004] Currently, the detection of electrical data of touch capacitors is easily affected by interference and has poor electromagnetic compatibility; moreover, the power supply voltage has a significant impact on the detection of touch capacitor data, while stabilizing the power supply voltage increases costs; therefore, we are working to design a touch capacitor monitoring device with strong anti-interference capabilities that is unaffected by the power supply voltage. Summary of the Invention:

[0005] The purpose of this invention is to overcome the shortcomings of the existing technology and to design a charge-balanced touch capacitance monitoring method to address the problems of weak anti-interference ability and dependence on power supply voltage in existing touch capacitance monitoring devices or methods.

[0006] To achieve the above objectives, the present invention relates to a charge-balanced touch capacitance monitoring method, which uses a charge-balanced touch capacitance monitoring chip to monitor the touch capacitance CX. The specific process is as follows:

[0007] (1) Touch capacitor charging: The clock prescaler module periodically controls the opening and closing of switches TI and TII, and the states of switches TI and TII are opposite. When the state value of switch TI is 1, switch TI is closed, and the first power supply is connected in series with switch TI, touch capacitor CX, and the first ground line in sequence. Since the state values ​​of switches TI and TII are opposite, the state value of switch TII is 0. At this time, switch TII is open, that is, the line between touch capacitor CX and capacitor CMOD is disconnected, and the first power supply charges touch capacitor CX. The charge in touch capacitor CX gradually increases until the voltage across touch capacitor CX is the voltage VDD of the first power supply. When the state value of switch TIII is 1, switch TIII is closed, that is, the line between capacitor CMOD and capacitor CDC is connected. The state of switch TIII is opposite to the state of switch TIV. When the state value of switch TIII is 1, the state value of switch TIV is 0, and switch TIV is open, that is, capacitor CDC is disconnected from the fourth ground line.

[0008] (2) Discharging the touch capacitor: When the state value of switch TI is 0, switch TI disconnects the series line between the first power supply and the touch capacitor CX. The state value of switch TII is 1. The touch capacitor CX is connected in series with the capacitor CMOD through switch TII. The charge in the touch capacitor CX is charged into the capacitor CMOD. The voltage across the capacitor CMOD is VMOD. When the voltage of the charged capacitor CMOD rises from 0 to equal the voltage of the touch capacitor CX, that is, when the voltage values ​​are both 0.5VDD, the charging process stops. When the touch capacitor CX and the capacitor CDC reach equilibrium, the touch capacitor CX reaches a steady state. The average voltage of the capacitor CMOD is 0.5VDD. The average voltage of the touch capacitor CX is 0.5VDD. Therefore, the amount of charge transferred from the touch capacitor CX to the capacitor CMOD is 0.5VDD*CX.

[0009] (3) Discharging of capacitor CDC: When the voltage across capacitor CMOD is too high, the voltage is input to comparator CMP through pin p. Comparator CMP outputs a comparison result signal, which is transmitted to the NAND gate module. The judgment result is input to the flip-flop through the QN terminal of the NAND gate module. The flip-flop generates an adjustment signal based on the judgment result. The adjustment signal is used to adjust the control switch TIII through the output line of the flip-flop QB terminal. The state value of switch TIII becomes 0, and switch TIII is open, that is, the line between capacitor CMOD and capacitor CDC is in the open state. At the same time, the adjustment signal is input to the second inverter through the flip-flop pin QB terminal. The second inverter outputs signal CLK-CDC. The state value of CLK_CDC is 1 at this time. The signal CLK-CDC output by the second inverter controls switch TIV to close, that is, capacitor CDC is connected to the fourth ground line, and capacitor CDC discharges to remove excess charge.

[0010] When the voltage across capacitor CMOD is relatively low (VMOD voltage), the voltage input to comparator CMP is processed sequentially by a NAND gate module and a DFF flip-flop to output an adjustment signal. This signal controls the state of switch TIII to be 1, closing switch TIII. The voltages VMOD and VCDC of capacitors CMOD and CDC are equal. The adjustment signal is then input to the second inverter via the flip-flop. The second inverter outputs signal CLK-CDC, and the state of CLK_CDC is 0 at this time, causing switch TIV to open.

[0011] (4) Pulse count: The signal CLK-CDC output by the second inverter is simultaneously transmitted to the counter module, and the counter module receives the second fixed clock signal; CLK-CDC and the second fixed clock signal are processed by the internal counting of the counter module, and the counter module outputs the sampled value, which is marked as SAMP[11:0].

[0012] (5) Average value calculation: The counter module inputs SAMP[11:0] into the AVERAGE averaging module and processes it to obtain the average value STD[11:0] of multiple sampling periods;

[0013] (6) Difference calculation: The AVERAGE module inputs the average value STD[11:0] into the AB subtractor, and the counter module inputs SAMP[11:0] into the AB subtractor. The difference between SAMP[11:0] and STD[11:0] is calculated internally by the AB subtractor and recorded as DLT[11:0].

[0014] (7) Touch detection: Compare the output DLT[11:0] of the AB module with the set threshold LN. When the value of DLT[11:0] is greater than the threshold LN, it is considered that the capacitor CX has been touched. The value of LN is set to 8-30. The sensitivity of the touch capacitor CX is selected according to the value of LN.

[0015] The principle and method of the charge balance type touch capacitance monitoring chip of the present invention for monitoring touch capacitance CX are as follows:

[0016] (1) The states of switch TIII and switch TIV are reversed. In one clock cycle, when the state value of switch TIII is 1, switch TIII is closed and capacitor CDC is charged. The amount of charge is 0.5VDD*CDC. At this time, capacitor CMOD and capacitor CDC are connected in parallel. The voltage VMOD across capacitor CMOD and the voltage VCDC across capacitor CDC are equal. When the state value of switch TIII is 0, switch TIII is open. Then the state value of switch TIV is 1 and switch TIV is closed. At this time, capacitor CDC is in the discharge state.

[0017] (2) The capacitor CMOD is used as a charging capacitor. The amount of charge that the first power supply charges the capacitor CMOD through switches TI and TII is equal to the amount of charge that discharges the capacitor CMOD through switches TIII and TIV. That is, the amount of charge charged is equal to the amount of charge discharged. The discharge of the capacitor CMOD is achieved by the discharge of the capacitor CDC. Since the voltage across the capacitor CMOD is equal to the voltage across the capacitor CDC, the voltage of the capacitor CMOD decreases as the voltage of the capacitor CDC decreases. The excess charge in the capacitor CMOD is discharged through the capacitor CDC. Assuming that the number of pulses CLK_PRS that charge the capacitor CMOD in one sampling period is M, and the number of pulses CLK_CDC that discharge the capacitor CMOD is N, N is the sampling value SAMP[11:0]. According to the law of conservation of charge, the following equation can be obtained:

[0018] 0.5VDD*CX*M=0.5VDD*CDC*N, that is: CX*M=CDC*N; (1)

[0019] CX is the capacitance value of the touch capacitor CX, and CDC is the capacitance value of the capacitor CDC.

[0020] With M fixed, when the touch capacitor CX changes, N will change linearly with the capacitance. By monitoring N, the information of the touch capacitor CX can be obtained. VDD in equation (1) can be canceled out, so that DLT[11:0] is independent of VDD, that is, the sensitivity is independent of VDD. As long as CDC is adjusted, the sensitivity of monitoring the touch capacitor CX can be adjusted.

[0021] A charge-balanced touch capacitive monitoring chip includes a touch channel and a touch judgment module. The touch channel adopts a charge-balanced touch capacitive monitor structure and is used to sense touch. The touch channel is electrically connected to the touch judgment module, which is used to compare the data difference input from the touch channel with a set value. When the data difference is greater than the set value, it is determined that the touch sensing module has been touched.

[0022] A charge-balanced touch capacitance monitor, the main structure of which includes a touch sensing module, a control and analysis module, and a data processing module; the touch sensing module, control and analysis module, and data processing module are sequentially and electrically connected; wherein...

[0023] The touch sensing module uses the principle of charge balancing to build a sensing circuit through touch capacitors, which is used to output induced voltage to the outside.

[0024] Control and Analysis Module: This module processes and analyzes the voltage input to the touch sensing module, outputs control signals, controls the operation of the touch sensing module based on the control signals, and transmits the control signals to the data processing module.

[0025] Data processing module: Used to statistically analyze the control signals input by the control analysis module, process and calculate them to obtain data differences, and input the data differences into the touch judgment module.

[0026] The touch sensing module includes a first clock signal input terminal, a clock prescaler module (PRS), a first power supply, a first inverter, a switch TI, an input pin panel, a touch capacitor CX, a first ground line, a switch TII, a capacitor CMOD, a second ground line, a capacitor CDC, a third ground line, a switch TIV, a fourth ground line, and a switch TIII. The first fixed clock signal CLK at the first clock signal input terminal is connected to the input terminal of the clock prescaler module. The first fixed clock signal is input to the clock prescaler module, which processes the first fixed clock signal to obtain the CLK_PRS pulse. The clock prescaler module outputs a CLK_PRS pulse. The output of the clock prescaler module is connected in parallel to a first inverter and the first contact of switch TII. The output of the rounded end of the first inverter is connected to the first contact of switch TI, and the connection of switch TI is connected to the first power supply. The second contact of switch TI is connected in series with the touch capacitor CX and the first ground wire. When the second contact of switch TI is closed to the external interface of touch capacitor CX, the first power supply is connected in series with switch TI, touch capacitor CX, and the first ground wire, charging touch capacitor CX. The external interface of touch capacitor CX is also connected to the output of the input pin panel. The input pin panel receives all inputs to the circuit, converting and transmitting external signals to the touch capacitor CX, such as external touch signals. The touch capacitor CX's external interface is also connected to the second contact of switch TII. The connection terminal of switch TII is connected in parallel with the input terminal of capacitor CMOD, the connection terminal of switch TIII, and the comparator CMP pin p of the control analysis module. Capacitor CMOD is connected in series with the second ground, and the voltage across CMOD is VMOD. CMOD acts as a collector capacitor, providing voltage regulation. The first contact of switch TIII is connected in series with capacitor CDC and the third ground. In a series connection, when the first contact terminal of switch TIII is closed and connected to the first input terminal of capacitor CDC, capacitor CMOD can be connected in sequence with switch TIII, capacitor CDC, and the third ground line to form a series circuit; the second input terminal of capacitor CDC is connected to the connection terminal of switch TIV, and the first contact terminal of switch TIV is connected to the fourth ground line. When the first contact terminal of switch TIV is connected to the fourth ground line, the first contact terminal of switch TIII is disconnected from the first input terminal of capacitor CDC, and capacitor CDC discharges to the fourth ground line through switch TIV; switches TIII and TIV are also connected to and controlled by the control analysis module.

[0027] The control and analysis module includes a second power supply, a first resistor, a comparator CMP, a NAND gate module, a fifth ground line, a flip-flop, a second inverter, a second resistor, a fifth ground line, and a second clock signal input terminal. The p-pin of the comparator CMP is connected to the connection terminal of the switch TII. The N-pin of the comparator CMP is connected in parallel with the first and second resistors, both with a resistance of 100kΩ. The N-pin of the comparator CMP receives the same voltage value as the second resistor. The input terminal of the first resistor is connected to the second power supply, and the input terminal of the second resistor is connected in series with the fifth ground line. The O-pin of the comparator CMP is connected to the B-pin of the NAND gate module, and the output of the O-pin of the comparator CMP is the input of the B-pin of the NAND gate module. The QN-pin of the NAND gate module is connected to the D-pin of the flip-flop, and the output of the QN-pin of the NAND gate module serves as the input of the D-pin of the flip-flop. The C-pin of the flip-flop is connected to the second clock signal input terminal, which is also connected to a number... The counter module pin CLK of the processing module is connected; the second clock signal input terminal receives the same clock signal as the first clock signal input terminal, and the flip-flop pin C receives the second fixed clock signal; the flip-flop Q terminal is connected to the NAND gate module pin A, and the output of the flip-flop Q terminal serves as the input of the NAND gate module pin A; the flip-flop QB terminal is connected to the second contact terminal of switch TIII, and the output of the flip-flop QB terminal controls the closed state of switch TIII; the flip-flop QB terminal is also connected to the input terminal of the second inverter, and the output of the flip-flop QB terminal is processed by the second inverter to obtain the signal CLK-CDC; the output terminal of the second inverter is connected to the counter module pin INC, and the second inverter inputs CLK-CDC to the counter module pin INC; the output terminal of the second inverter is also connected to the second contact terminal of switch TIV, and the CLK-CDC output by the second inverter controls the closed state of switch TIV.

[0028] The data processing module includes a counter module, an AVERAGE averaging module, and an AB subtractor. The CLK pin of the counter module receives a second fixed clock signal. The two inputs of the counter module are the signal CLK_CDC and the second fixed clock signal, respectively. CLK is a clock signal with a fixed frequency. The two signals are processed by the counter module internally. The counter module outputs a sampled value marked as SAMP[11:0], where [11:0] indicates that the number of bits for sampling is 12. The output of the counter module is connected to the input of the AVERAGE averaging module. SAMP[11:0] is used as the input of the AVERAGE averaging module and is processed to obtain the average value STD[11:0] of multiple sampling periods. The output of the AVERAGE averaging module is connected to the B pin of the AB subtractor. The AVERAGE averaging module inputs the average value STD[11:0] to the B pin of the AB subtractor. The output of the counter module is also connected to the A pin of the AB subtractor. After SAMP[11:0] and STD[11:0] are processed by the AB subtractor internally, the output is DLT[11:0].

[0029] The switches TI, TII, TIII, and TIV are ideal switches.

[0030] Furthermore, the charge-balanced touch capacitance monitoring chip also includes a sampling channel and a trimming module. The sampling channel adopts a charge-balanced touch capacitance monitor structure. The output terminals of the sampling channel and the touch channel are respectively connected to the receiving terminal of the trimming module. The output terminal of the trimming module is connected to the receiving terminal of the touch judgment module.

[0031] The sampling channel is used to acquire data detected by the charge-balanced touch capacitive monitor in the absence of touch.

[0032] The adjustment module is used to correct the data collected by the touch channel, eliminate interference factors in the absence of touch, and input the corrected collected data into the touch judgment module.

[0033] The adjustment module has the following structure: it includes a DIV12BIT module, a MUL12BIT module, and a SUB12BIT module. The DIV12BIT module has pins A and B. Pin A of the DIV12BIT module acquires input SAMP0_[11:0], which is the current sampled value in the sampling channel. Pin B of the DIV12BIT module acquires input STD0_[11:0], which is the current sampled value in the sampling channel. The average values ​​SAMP0_[11:0] and STD0_[11:0] are processed internally by the DIV12BIT module and output as DIV[12:0]. The output of the DIV12BIT module is connected to pin B of the MUL12BIT module, which has pins A and B. DIV[12:0] serves as the input to pin B of the MUL12BIT module, and the input to pin A of the MUL12BIT module is the average value STD1_[11:0] of the touch channel. [12:0] and STD1_[11:0] are processed internally by the MUL12BIT module and output as STD1_VAL[11:0]. STD1_VAL[11:0] is the average value of the adjusted touch channel. The output of the MUL12BIT module is connected to pin B of the SUB12BIT module. STD1_VAL[11:0] serves as the input of pin B of the SUB12BIT module. The input SAMP1_[11:0] of pin A of the SUB12BIT module is the touch channel value. The current sampled values, STD1_VAL[11:0] and SAMP1_[11:0], are processed internally by the SUB12BIT module to output DLT1_[11:0]. The output DLT1_[11:0] is the difference of the adjusted touch channel. This final output difference is compared with LN to determine whether the touch capacitor CX has been touched. When DLT1_[11:0] is greater than LN, it is considered that there is a touch. The value range of LN is set between 8 and 30. The adjustment module uses the following formula for the adjustment algorithm:

[0034] DIV[12:0]=SAMP0_[11:0] / STD0_[11:0]

[0035] STD1_VAL[11:0]=STD1_[11:0]*DIV[12:0]

[0036] DLT1_[11:0]=SAMP01_[11:0]-STD1_VAL[11:0].

[0037] Compared with existing technologies, the charge-balanced touch capacitance monitoring method designed in this invention has the following advantages: 1. The CLK_PRS used in this invention is generated by a pseudo-random sequence. In one sampling period, the number of CLK_PRS pulses is fixed, but the CLK_PRS pulse period is randomly varied. This algorithm has great benefits for electromagnetic compatibility and anti-interference. 2. Charge balance is achieved by capacitor charging and discharging, 0.5VDD*CX*M=0.5VDD*CDC*N. VDD can be canceled out in the equation, ultimately making DLT[11:0] independent of VDD, that is, the sensitivity is independent of VDD. The sensitivity can be adjusted by adjusting CDC. 3. The reference channel adjustment algorithm is adopted to further improve anti-interference. The designed charge-balanced touch capacitance monitor is applied to SC series touch chips. The charge-balanced touch capacitance monitor and its chip can also be applied to intelligent devices such as touch switches for large machinery, electronic touch screens, and robot body surface touch sensing. Attached image description:

[0038] Figure 1 This is a schematic block diagram of the modular structure of the charge-balanced touch capacitive monitoring chip involved in this invention.

[0039] Figure 2 This is a schematic diagram illustrating the structural principle of the charge balance type touch capacitive monitor involved in this invention.

[0040] Figure 3 This is a schematic diagram illustrating the structural principle of the touch sensing module involved in this invention.

[0041] Figure 4 This is a schematic diagram of the structural principle of the control analysis module involved in this invention.

[0042] Figure 5 This is a schematic diagram illustrating the structural principle of the data processing module involved in this invention.

[0043] Figure 6 This is a schematic diagram illustrating the structural principle of the adjustment module involved in this invention. Detailed implementation method:

[0044] The present invention will be further described below with reference to the embodiments and accompanying drawings.

[0045] Example 1:

[0046] This embodiment relates to a charge-balanced touch capacitance monitor, such as... Figure 1 As shown, the main structure includes a touch sensing module 1, a control and analysis module 2, and a data processing module 3; the touch sensing module 1, control and analysis module 2, and data processing module 3 are sequentially connected by electrical information.

[0047] Touch sensing module 1 uses the principle of charge balancing to build a sensing circuit through touch capacitors, which is used to output induced voltage to the outside.

[0048] Control and analysis module 2: It is used to process and analyze the voltage input to touch sensing module 1, output control signals, control the operation of touch sensing module 1 according to the control signals, and transmit the control signals to data processing module 3 at the same time.

[0049] Data processing module 3: It is used to process and calculate the control signals input by the statistical control analysis module 2, obtain the data difference, and input the data difference into the touch judgment module 5.

[0050] like Figure 2 , 3As shown, the touch sensing module 1 includes a first clock signal input terminal 6, a clock prescaler module (PRS) 7, a first power supply 8, a first inverter (INV) 9, a switch TI 10, an input pin pad (PAD) 11, a touch capacitor CX 12, a first ground line 13, a switch TII 14, a capacitor CMOD 15, a second ground line 16, a capacitor CDC 17, a third ground line 18, a switch TIV 19, a fourth ground line 20, and a switch TIII 21. The first clock signal input terminal 6 connects to the input terminal of the clock prescaler module (PRS) 7 with a first fixed clock signal CLK. The first clock signal input terminal 6 inputs the first fixed clock signal (CLK) to the clock prescaler module (PRS) 7. The prescaler module (PRS) 7 processes the first fixed clock signal (CLK) to obtain the CLK_PRS pulse. The clock prescaler module (PRS) 7 outputs the CLK_PRS pulse, the period of which varies randomly, but the number of CLK_PRS pulses within one sampling period is fixed. This structure has a significant effect on electromagnetic compatibility and anti-interference. The output of the clock prescaler module (PRS) 7 is connected in parallel to the first inverter (INV) 9 and the first contact terminal of switch TII14. The output terminal of the first inverter is connected to the first contact terminal of switch TI10, and the connection terminal of switch TI10 is connected to the first power supply 8 (voltage VDD). The switch TI10... The second contact terminal is connected in series with the touch capacitor CX12 and the first ground line 13. When the second contact terminal of the switch TI10 is closed to the external interface of the touch capacitor CX12, the first power supply 8 is connected in series with the switch TI10, the touch capacitor CX12, and the first ground line 13, and the first power supply 8 charges the touch capacitor CX12. The external interface of the touch capacitor CX12 is also connected to the output terminal of the input pin disk (PAD) 11. The input pin disk (PAD) 11 receives the input (CIN) of the entire circuit and is used to receive external signals and convert and transmit them to the touch capacitor CX12, such as external touch. The external interface of the touch capacitor CX12 is also connected to the second contact terminal of the switch TI14. The connection is as follows: the connection terminal of switch TII14 is connected in parallel with the input terminal of capacitor CMOD15, the connection terminal of switch TIII21, and the p-pin of comparator CMP24 of control analysis module 2; capacitor CMOD15 is connected in series with the second ground line 16, and the voltage across capacitor CMOD15 is VMOD. Capacitor CMOD15 is a collector capacitor and plays a role in voltage regulation; the first contact terminal of switch TIII21 is connected in series with capacitor CDC17 and the third ground line 18. When the first contact terminal of switch TIII21 is closed and connected to the first input terminal of capacitor CDC17, capacitor CMOD15 can be connected in series with switch TIII21, capacitor CDC17, and the third ground line 18 to form a series circuit.The second input terminal of capacitor CDC17 is connected to the connection terminal of switch TIV19. The first contact terminal of switch TIV19 is connected to the fourth ground line 20. When the first contact terminal of switch TIV19 is connected to the fourth ground line 20, the first contact terminal of switch TIII21 is disconnected from the first input terminal of capacitor CDC17, and capacitor CDC17 discharges to the fourth ground line 20 through switch TIV19. Switches TIII21 and TIV19 are also connected to and controlled by control analysis module 2.

[0051] like Figure 2 , 4As shown, the control analysis module 2 includes a second power supply 22, a first resistor 23, a comparator CMP24, a NAND gate module 25, a fifth ground line 29, a flip-flop (DFF) 26, a second inverter 27, a second resistor 28, a fifth ground line 29, and a second clock signal input terminal 30. The p-pin of the comparator CMP24 is connected to the connection terminal of the switch TII14. The N-pin of the comparator CMP24 is connected in parallel with the first resistor 23 and the second resistor 28, both with a resistance of 100kΩ. The N-pin of the comparator CMP24 receives the same voltage value as the second resistor 28. The input terminal of resistor 23 is connected to the second power supply 22 (voltage VDD), and the input terminal of the second resistor 28 is connected in series with the fifth ground line 29. The O terminal of comparator CMP24 is connected to pin B of NAND gate module 25, and the output of the O terminal of comparator CMP24 is the input of pin B of NAND gate module 25. The QN terminal of NAND gate module 25 is connected to pin D of flip-flop (DFF) 26, and the output of the QN terminal of NAND gate module 25 is the input of pin D of flip-flop (DFF) 26. The C terminal of flip-flop (DFF) 26 is connected to the second clock signal input terminal 30, which is also connected to the data processing... The counter module (CNT) 31 of the processing module 3 is connected to pin CLK; the second clock signal input terminal 30 and the first clock signal input terminal 6 receive the same clock signal; the flip-flop (DFF) 26 pin C receives the second fixed clock signal (CLK); the flip-flop (DFF) 26 Q is connected to pin A of NAND gate module 25, and the output of the flip-flop (DFF) 26 Q is used as the input of pin A of NAND gate module 25; the flip-flop (DFF) 26 QB is connected to the second contact terminal of switch TIII 21, and the output of the flip-flop (DFF) 26 QB controls the closing of switch TIII 21. The flip-flop (DFF) 26 pin QB is also connected to the input of the second inverter 27. The output of the flip-flop (DFF) 26 pin QB is processed by the second inverter 27 to obtain the signal CLK-CDC. The output of the second inverter 27 is connected to the counter module (CNT) 31 pin INC. The second inverter 27 inputs CLK_CDC to the counter module (CNT) 31 pin INC. The output of the second inverter 27 is also connected to the second contact of the switch TIV19. The CLK_CDC output by the second inverter 27 controls the closed state of the switch TIV19.

[0052] like Figure 2 , 5As shown, the data processing module 3 includes a counter module (CNT) 31, an AVERAGE averaging module 32, and an AB subtractor 33. The CLK pin of the counter module (CNT) 31 receives a second fixed clock signal (CLK). The purpose of the counter module (CNT) 31 is to record the number of CLK-CDC within one sampling period. The two inputs of the counter module (CNT) 31 are the signal CLK_CDC and the second fixed clock signal (CLK), where CLK is a clock signal with a fixed frequency. The two signals are processed by the internal counting of the counter module (CNT) 31, and the output sample value of the counter module (CNT) 31 is marked as SAMP[11:0], where [11:0] represents the sampled value. The number of bits is 12; the output of the counter module (CNT) 31 is connected to the input of the AVERAGE module 32, and SAMP[11:0] is used as the input of the AVERAGE module 32 to process and obtain the average value STD[11:0] of multiple sampling periods; the output of the AVERAGE module 32 is connected to pin B of the AB subtractor 33, and the AVERAGE module 32 inputs the average value STD[11:0] to pin B of the AB subtractor 33; the output of the counter module (CNT) 31 is also connected to pin A of the AB subtractor 33, and SAMP[11:0] and STD[11:0] are processed internally by the AB subtractor 33 and output as DLT[11:0].

[0053] The switches TI, TII14, TIII21, and TIV19 involved in this embodiment are ideal switches.

[0054] Example 2:

[0055] This embodiment uses the charge-balanced touch capacitance monitor described in Embodiment 1 to construct a charge-balanced touch capacitance monitoring chip. The charge-balanced touch capacitance monitoring chip includes a touch channel and a touch judgment module 5. The touch channel adopts a charge-balanced touch capacitance monitor structure and is used to sense touch. The touch channel is electrically connected to the touch judgment module 5. The touch judgment module 5 is used to compare the data difference input from the touch channel with a set value. When the data difference is greater than the set value, it is determined that the touch sensing module 1 has been touched.

[0056] The specific process of monitoring the touch capacitor CX12 by the charge balance touch capacitor monitoring chip involved in this embodiment is as follows:

[0057] (1) Touch Capacitor Charging: The clock prescaler module (PRS) 7 periodically controls the opening and closing of switches TI10 and TII14, with the states of switches TI10 and TII14 being opposite. When the state value of switch TI10 is 1, switch TI10 is closed, and the first power supply 8 is connected in series with switch TI10, touch capacitor CX12, and the first ground wire 13. Since the state values ​​of switches TI10 and TII14 are reversed, the state value of switch TII14 is 0, at which time switch TII14 is open, that is, the line between touch capacitor CX12 and capacitor CMOD15 is disconnected. The first power supply 8 charges the touch capacitor CX12, and the charge in the touch capacitor CX12 gradually increases until the voltage across the touch capacitor CX12 is the voltage VDD of the first power supply 8. When the state value of switch TIII21 is 1, switch TIII21 is closed, that is, the line between capacitor CMOD15 and capacitor CDC17 is in a connected state. The state of switch TIII21 is opposite to the state of switch TIV19. When the state value of switch TIII21 is 1, the state value of switch TIV19 is 0, switch TIV19 is open, that is, capacitor CDC17 is disconnected from the fourth ground line 20.

[0058] (2) Touch capacitor discharge: When the state value of switch TI10 is 0, switch TI10 disconnects the series line between the first power supply 8 and the touch capacitor CX12. The state value of switch TII14 is 1. The touch capacitor CX12 is connected in series with the capacitor CMOD15 through switch TII14. The charge in the touch capacitor CX12 is charged into the capacitor CMOD15. The voltage across the capacitor CMOD15 is VMOD. When the voltage of the charged capacitor CMOD15 rises from 0 to equal the voltage of the touch capacitor CX12, that is, when the voltage values ​​are both 0.5VDD, the charging process stops. When the touch capacitor CX12 and the capacitor CDC17 reach equilibrium, the touch capacitor CX12 reaches a steady state. The average voltage of the capacitor CMOD15 is 0.5VDD. The average voltage of the touch capacitor CX12 is 0.5VDD. Therefore, the amount of charge transferred from the touch capacitor CX12 to the capacitor CMOD15 is 0.5VDD*CX.

[0059] (3) Discharging capacitor CDC17: When the voltage across capacitor CMOD15 is too high (VMOD charging voltage), the voltage is input to comparator CMP24 through pin p. Comparator CMP24 outputs a comparison result signal, which is transmitted to NAND gate module 25. The judgment result is input to flip-flop (DFF) 26 through the QN terminal of NAND gate module 25. Flip-flop (DFF) 26 generates an adjustment signal based on the judgment result. The adjustment signal is used to adjust control switch TIII21 through the output line of flip-flop (DFF) 26's QB terminal. The state value of III21 changes to 0, and switch TIII21 is open, meaning the line between capacitor CMOD15 and capacitor CDC17 is disconnected. At the same time, the adjustment signal is input to the second inverter 27 through the QB pin of flip-flop (DFF) 26. The second inverter 27 outputs the signal CLK-CDC, and the state value of CLK_CDC is 1 at this time. The signal CLK-CDC output by the second inverter 27 controls switch TIV19 to close, meaning that capacitor CDC17 is connected to the fourth ground line 20, and capacitor CDC17 discharges to remove excess charge.

[0060] When the voltage VMOD across capacitor CMOD15 is relatively low, the voltage input to comparator CMP24 is processed sequentially by NAND gate module 25 and DFF flip-flop to output an adjustment signal, controlling the state value of switch TIII21 to 1. Switch TIII21 is closed, and the voltage VMOD of capacitor CMOD15 and the voltage VCDC of capacitor CDC17 are equal. The adjustment signal is input to the second inverter 27 via flip-flop (DFF) 26. The second inverter 27 outputs the signal CLK-CDC. The state value of CLK_CDC is 0 at this time, and switch TIV19 is open.

[0061] (4) Pulse count: The signal CLK-CDC output by the second inverter 27 is simultaneously transmitted to the counter module (CNT) 31. The counter module (CNT) 31 receives the second fixed clock signal (CLK). CLK-CDC and the second fixed clock signal (CLK) are counted and processed internally by the counter module (CNT) 31. The counter module (CNT) 31 outputs the sampled value, which is marked as SAMP[11:0].

[0062] (5) Average value calculation: The counter module (CNT) 31 inputs SAMP[11:0] into the AVERAGE averaging module 32 and processes it to obtain the average value STD[11:0] of multiple sampling periods;

[0063] (6) Difference calculation: The AVERAGE module 32 inputs the average value STD[11:0] into the AB subtractor 33, and the counter module (CNT) 31 inputs SAMP[11:0] into the AB subtractor 33. The difference between SAMP[11:0] and STD[11:0] is calculated internally by the AB subtractor 33 and recorded as DLT[11:0].

[0064] (7) Touch detection: Compare the output DLT[11:0] of the AB module with the set threshold LN. When the value of DLT[11:0] is greater than the threshold LN, it is considered that the capacitor CX has been touched. The value range of LN is set to 8-30. According to the adjustment of the value of LN, the appropriate sensitivity of the touch capacitor CX12 is selected.

[0065] The principle of the charge balance type touch capacitance monitoring chip involved in this embodiment for monitoring the touch capacitance CX12 is as follows:

[0066] (1) The states of switches TIII21 and TIV19 are reversed. In one clock cycle, when the state value of switch TIII21 is 1, switch TIII21 is closed, charging capacitor CDC17 with a charge of 0.5VDD*CDC. At this time, capacitor CMOD15 and capacitor CDC17 are connected in parallel, and the voltage VMOD across capacitor CMOD15 and the voltage VCDC across capacitor CDC17 are equal. When the state value of switch TIII21 is 0, switch TIII21 is open, and the state value of switch TIV19 is 1, switch TIV19 is closed, and capacitor CDC17 is in the discharge state.

[0067] (2) Capacitor CMOD15 is used as a charging capacitor. The amount of charge that the first power supply 8 charges to capacitor CMOD15 through switches TI10 and TII14 is equal to the amount of charge that discharges to capacitor CMOD15 through switches TIII21 and TIV19. That is, the amount of charge charged is equal to the amount of charge discharged. The discharge of capacitor CMOD15 is achieved through the discharge of capacitor CDC17. Since the voltage across capacitor CMOD15 is equal to the voltage across capacitor CDC17, the voltage of capacitor CDC17 decreases, and the voltage of capacitor CMOD15 also decreases. The excess charge in capacitor CMOD15 is discharged through capacitor CDC17. Assuming that the number of pulses CLK_PRS that charge capacitor CMOD15 in one sampling period is M, and the number of pulses CLK_CDC that discharge capacitor CMOD15 is N, N is the sampling value SAMP[11:0]. According to the law of conservation of charge, the following equation can be obtained:

[0068] 0.5VDD*CX*M=0.5VDD*CDC*N, that is: CX*M=CDC*N;

[0069] CX is the capacitance value of the touch capacitor CX12, and CDC is the capacitance value of the capacitor CDC17.

[0070] With M fixed, when the touch capacitor CX12 changes (e.g., whether or not a finger touches the touch capacitor CX12), N will change linearly with the capacitance. By monitoring N, the information of the touch capacitor CX12 can be obtained.

[0071] Example 3:

[0072] The charge-balanced touch capacitive monitoring chip described in Example 2 incorporates an internal sampling channel. Both the sampling channel and the touch channel utilize a charge-balanced touch capacitive monitoring structure. The sampling channel also generates sampled values, which are used to adjust the sampled values ​​obtained by the touch channel within the chip structure. When the chip is subjected to external interference, fluctuations occur in the sampled values ​​of both the sampling channel and the touch channel. The sampling channel corrects the data obtained by the touch channel, eliminating external interference. To further improve the anti-interference capability of the touch chip, an additional adjustment module 4 is applied, using an adjustment algorithm structure to fine-tune the sampled values ​​output by the counter module.

[0073] The charge-balanced touch capacitive monitoring chip described in this embodiment also includes a sampling channel and a trimming module 4. The sampling channel adopts a charge-balanced touch capacitive monitoring device structure. The output terminals of the sampling channel and the touch channel are respectively connected to the receiving terminal of the trimming module 4. The output terminal of the trimming module 4 is connected to the receiving terminal of the touch judgment module 5.

[0074] The sampling channel is used to acquire data detected by the charge-balanced touch capacitive monitor in the absence of touch.

[0075] The adjustment module 4 is used to correct the data collected by the touch channel, eliminate interference factors in the absence of touch, and input the corrected collected data into the touch judgment module 5.

[0076] The structure of adjustment module 4 is as follows: Figure 6As shown, the structure of the trimming module 4 is as follows: The trimming module 4 includes a DIV12BIT module 34, a MUL12BIT module 35, and a SUB12BIT module 36. The DIV12BIT module 34 sets pins A and B. Pin A of the DIV12BIT module 34 acquires input SAMP0_[11:0], where SAMP0_[11:0] is the current sampled value in the sampling channel. Pin B of the DIV12BIT module 34 acquires input STD0_[11:0], where STD0_[11:0] is the current sampled value in the sampling channel. The current average values ​​of the samples, SAMP0_[11:0] and STD0_[11:0], are processed internally by the DIV12BIT module 34 and output as DIV[12:0]. The output of the DIV12BIT module 34 is connected to pin B of the MUL12BIT module 35. The MUL12BIT module 35 has pins A and B. DIV[12:0] serves as the input of pin B in the MUL12BIT module 35, and the input of pin A in the MUL12BIT module 35 is the average value of the touch channel, STD1_[11:0]. :0];DIV[12:0] and STD1_[11:0] are processed internally by the MUL12BIT module 35 and output as STD1_VAL[11:0]. STD1_VAL[11:0] is the average value of the adjusted touch channel; the output terminal of the MUL12BIT module 35 is connected to pin B of the SUB12BIT module 36. STD1_VAL[11:0] serves as the input of pin B of the SUB12BIT module 36, and the input of pin A of the SUB12BIT module 36 is SAMP1_[11:0]. This is the current sampled value of the touch channel. STD1_VAL[11:0] and SAMP1_[11:0] are processed internally by the SUB12BIT module 36 to output DLT1_[11:0]. The output DLT1_[11:0] is the difference of the touch channel after adjustment. This final output difference is compared with LN to determine whether the touch capacitor CX12 has been touched. When DLT1_[11:0] is greater than LN, it is considered that there is a touch. The value range of LN is set between 8 and 30. The calculation formula of the adjustment algorithm used by the adjustment module 4 is as follows:

[0077] DIV[12:0]=SAMP0_[11:0] / STD0_[11:0]

[0078] STD1_VAL[11:0]=STD1_[11:0]*DIV[12:0]

[0079] DLT1_[11:0]=SAMP01_[11:0]-STD1_VAL[11:0].

Claims

1. A charge-balanced touch capacitance monitoring method, characterized in that: The touch capacitance CX is monitored using a charge-balanced touch capacitance monitoring chip. The specific steps are as follows: (1) Touch capacitor charging: The clock prescaler module periodically controls the opening and closing of switches TI and TII, and the states of switches TI and TII are opposite; when the state value of switch TI is 1, switch TI is closed, and the first power supply is connected in series with switch TI, touch capacitor CX, and the first ground line in sequence. Since the state values ​​of switches TI and TII are opposite, the state value of switch TII is 0. At this time, switch TII is open, that is, the line between touch capacitor CX and capacitor CMOD is disconnected, and the first power supply charges touch capacitor CX. The charge in touch capacitor CX gradually increases until the voltage across touch capacitor CX is the voltage VDD of the first power supply; when the state value of switch TIII is 1, switch TIII is closed, that is, the line between capacitor CMOD and capacitor CDC is connected; the state of switch TIII is opposite to the state of switch TIV. When the state value of switch TIII is 1, the state value of switch TIV is 0, switch TIV is open, that is, capacitor CDC is disconnected from the fourth ground line; (2) Discharging the touch capacitor: When the state value of switch TI is 0, switch TI disconnects the series line between the first power supply and the touch capacitor CX. The state value of switch TII is 1. The touch capacitor CX is connected in series with the capacitor CMOD through switch TII. The charge in the touch capacitor CX is charged into the capacitor CMOD. The voltage across the capacitor CMOD is VMOD. When the voltage of the charged capacitor CMOD rises from 0 to equal the voltage of the touch capacitor CX, that is, when the voltage values ​​are both 0.5VDD, the charging process stops. When the touch capacitor CX and the capacitor CDC reach equilibrium, the touch capacitor CX reaches a steady state. The average voltage of the capacitor CMOD is 0.5VDD. The average voltage of the touch capacitor CX is 0.5VDD. Then the amount of charge transferred from the touch capacitor CX to the capacitor CMOD is 0.5VDD*CX. (3) Discharging of capacitor CDC: When the voltage value across capacitor CMOD is higher than the charging voltage of VMOD than 0.5VDD, the voltage is input to comparator CMP through pin p. Comparator CMP outputs comparison result signal. The comparison result signal is transmitted to NAND gate module. The judgment result is input to flip-flop through QN terminal of NAND gate module. Flip-flop generates adjustment signal according to judgment result. The adjustment signal is adjusted by the output line of flip-flop QB terminal to control switch TIII. The state value of switch TIII becomes 0 and switch TIII is open, that is, the line between capacitor CMOD and capacitor CDC is in the open state. At the same time, the adjustment signal is input to second inverter through flip-flop pin QB terminal. Second inverter outputs signal CLK_CDC. The state value of CLK_CDC is 1 at this time. The signal CLK_CDC output by second inverter controls switch TIV to close, that is, capacitor CDC is connected to the fourth ground line. Capacitor CDC discharges to remove excess charge. When the voltage VMOD across capacitor CMOD is lower than 0.5VDD, the voltage of input comparator CMP is processed sequentially by NAND gate module and DFF flip-flop to output adjustment signal, controlling the state value of switch TIII to 1, switch TIII is closed, and the voltage VMOD of capacitor CMOD and the voltage VCDC of capacitor CDC are equal. The adjustment signal is input to the second inverter via a trigger. The second inverter outputs the signal CLK_CDC. At this time, the state value of CLK_CDC is 0, and the switch TIV is open. (4) Pulse count: The signal CLK_CDC output by the second inverter is simultaneously transmitted to the counter module, and the counter module receives the second fixed clock signal; CLK_CDC and the second fixed clock signal are processed by the counter module internally, and the counter module outputs the sampled value, which is marked as SAMP[11:0]; (5) Average value calculation: The counter module inputs SAMP[11:0] into the AVERAGE averaging module and processes it to obtain the average value STD[11:0] of multiple sampling periods; (6) Difference calculation: The AVERAGE module inputs the average value STD[11:0] into the AB subtractor, and the counter module inputs SAMP[11:0] into the AB subtractor. The difference between SAMP[11:0] and STD[11:0] is calculated internally by the AB subtractor and recorded as DLT[11:0]. (7) Touch detection: Compare the output DLT[11:0] of the AB subtractor with the set threshold LN. When the value of DLT[11:0] is greater than the threshold LN, it is considered that the capacitor CX has been touched. The value of LN is in the range of 8-30. The sensitivity of the touch capacitor CX is selected by adjusting the value of LN.

2. The charge balance type touch capacitance monitoring method according to claim 1, characterized in that: The principle and method by which the charge-balanced touch capacitance monitoring chip monitors the touch capacitance CX are as follows: (1) The states of switch TIII and switch TIV are reversed. In one clock cycle, when the state value of switch TIII is 1, switch TIII is closed and capacitor CDC is charged. The amount of charge is 0.5VDD*CDC. At this time, capacitor CMOD and capacitor CDC are connected in parallel. The voltage VMOD across capacitor CMOD and the voltage VCDC across capacitor CDC are equal. When the state value of switch TIII is 0, switch TIII is open. Then the state value of switch TIV is 1 and switch TIV is closed. At this time, capacitor CDC is in the discharge state. (2) As a charging capacitor, the amount of charge that the first power supply charges the capacitor CMOD through switches TI and TII is equal to the amount of charge that the capacitor CMOD discharges through switches TIII and TIV. That is, the amount of charge charged is equal to the amount of charge discharged. The discharge of the capacitor CMOD is achieved through the discharge of the capacitor CDC. Since the voltage across the capacitor CMOD is equal to the voltage across the capacitor CDC, the voltage of the capacitor CMOD decreases as the voltage of the capacitor CDC decreases. The excess charge in the capacitor CMOD is discharged through the capacitor CDC. Assuming that the number of pulses CLK_PRS that charge the capacitor CMOD in one sampling period is M, and the number of pulses CLK_CDC that discharge the capacitor CMOD is N, N is the sampling value SAMP[11:0]. According to the law of conservation of charge, the following equation can be obtained: 0.5VDD*CX*M=0.5VDD*CDC*N, that is: CX*M=CDC*N; (1) CX is the capacitance value of the touch capacitor CX, and CDC is the capacitance value of the capacitor CDC. With M fixed, when the touch capacitor CX changes, N will change linearly with the capacitance. By monitoring N, the information of the touch capacitor CX can be obtained. VDD in equation (1) can be canceled out, so that DLT[11:0] is independent of VDD, that is, the sensitivity is independent of VDD. As long as CDC is adjusted, the sensitivity of monitoring the touch capacitor CX can be adjusted.

3. A charge-balance touch capacitance monitoring chip applied to the charge-balance touch capacitance monitoring method of claim 1, characterized in that: The charge-balanced touch capacitance monitoring chip includes a touch channel and a touch judgment module. The touch channel adopts a charge-balanced touch capacitance monitor structure and is used to sense touch. The touch channel is electrically connected to the touch detection module. The touch detection module compares the data difference input from the touch channel with a set value. When the data difference is greater than the set value, the touch sensing module is considered to have been touched.

4. The charge balance type touch capacitance monitoring method according to claim 3, characterized in that: The charge-balanced touch capacitance monitor's main structure includes a touch sensing module, a control and analysis module, and a data processing module; the touch sensing module, control and analysis module, and data processing module are sequentially and electrically connected; wherein... The touch sensing module uses the principle of charge balancing to build a sensing circuit through touch capacitors, which is used to output induced voltage to the outside. Control and Analysis Module: This module processes and analyzes the voltage input to the touch sensing module, outputs control signals, controls the operation of the touch sensing module based on the control signals, and transmits the control signals to the data processing module. Data processing module: Used to statistically analyze the control signals input by the control and control analysis module, process and calculate the data difference, and input the data difference into the touch judgment module.

5. The charge balance type touch capacitance monitoring method according to claim 4, characterized in that: The touch sensing module includes a first clock signal input terminal, a clock prescaler module (PRS), a first power supply, a first inverter, a switch TI, an input pin panel, a touch capacitor CX, a first ground line, a switch TII, a capacitor CMOD, a second ground line, a capacitor CDC, a third ground line, a switch TIV, a fourth ground line, and a switch TIII. The first fixed clock signal CLK at the first clock signal input terminal is connected to the input terminal of the clock prescaler module. The first fixed clock signal is input to the clock prescaler module, which processes the first fixed clock signal to obtain CLK_PRS. The clock prescaler module outputs a CLK_PRS pulse. The output of the clock prescaler module is connected in parallel to a first inverter and the first contact of switch TII. The output of the first inverter (round end) is connected to the first contact of switch TII, and the connection of switch TII is connected to the first power supply. The second contact of switch TII is connected in series with the touch capacitor CX and the first ground. When the second contact of switch TII is closed to the external interface of touch capacitor CX, the first power supply is connected in series with switch TII, touch capacitor CX, and the first ground, charging touch capacitor CX. The external interface of touch capacitor CX is also connected to the input pin. The output terminal of the circuit is connected, and the input pin of the circuit receives external signals and converts them to transmit them to the touch capacitor CX. The external interface of the touch capacitor CX is also connected to the second contact terminal of switch TII. The connection terminal of switch TII is connected in parallel with the input terminal of capacitor CMOD, the connection terminal of switch TIII, and the comparator CMP pin p terminal of the control analysis module. Capacitor CMOD is connected in series with the second ground. The voltage across capacitor CMOD is VMOD. Capacitor CMOD is a collector capacitor and plays a role in voltage regulation. The first contact terminal of switch TIII is connected in series with capacitor CDC and the third ground. When the first contact terminal of switch TIII is closed and connected to the first input terminal of capacitor CDC, capacitor CMOD can be connected in series with switch TIII, capacitor CDC, and the third ground line to form a series circuit. The second input terminal of capacitor CDC is connected to the connection terminal of switch TIV, and the first contact terminal of switch TIV is connected to the fourth ground line. When the first contact terminal of switch TIV is connected to the fourth ground line, the first contact terminal of switch TIII is disconnected from the first input terminal of capacitor CDC, and capacitor CDC discharges to the fourth ground line through switch TIV. Switches TIII and TIV are also connected to and controlled by the control analysis module.

6. The charge balance type touch capacitance monitoring method according to claim 5, characterized in that: The control analysis module includes a second power supply, a first resistor, a comparator CMP, a NAND gate module, a fifth ground line, a flip-flop, a second inverter, a second resistor, a fifth ground line, and a second clock signal input terminal. The p-pin of the comparator CMP is connected to the connection terminal of the switch TII. The N-pin of the comparator CMP is connected in parallel with the first and second resistors, both with a resistance of 100kΩ. The N-pin of the comparator CMP receives the same voltage value as the second resistor. The input terminal of the first resistor is connected to the second power supply, and the input terminal of the second resistor is connected in series with the fifth ground line. The 0-pin of the comparator CMP is connected to the B-pin of the NAND gate module, and the output of the 0-pin of the comparator CMP is the output of the NAND gate module pin. The input of B is connected to the NAND gate module QN terminal and the flip-flop pin D terminal. The output of the NAND gate module QN terminal serves as the input of the flip-flop pin D terminal. The flip-flop pin C terminal is connected to the second clock signal input terminal, which is also connected to the counter module pin CLK terminal of the data processing module. The second clock signal input terminal receives the same clock signal as the first clock signal input terminal. The flip-flop pin C terminal receives the second fixed clock signal. The flip-flop Q terminal is connected to the NAND gate module pin A terminal, and the output of the flip-flop Q terminal serves as the input of the NAND gate module pin A terminal. The flip-flop pin QB terminal is connected to the second contact terminal of switch TIII, and the output of the flip-flop pin QB terminal controls the closed state of switch TIII. The QB pin of the trigger is also connected to the input of the second inverter. The output of the QB pin is processed by the second inverter to obtain the signal CLK_CDC. The output of the second inverter is connected to the INC pin of the counter module. The second inverter inputs CLK_CDC to the INC pin of the counter module. The output of the second inverter is also connected to the second contact of the switch TIV. The CLK_CDC output by the second inverter controls the closed state of the switch TIV.

7. The charge balance type touch capacitance monitoring method according to claim 6, characterized in that: The data processing module includes a counter module, an AVERAGE averaging module, and an AB subtractor. The CLK pin of the counter module receives a second fixed clock signal. The two inputs of the counter module are the signal CLK_CDC and the second fixed clock signal, respectively. CLK is a clock signal with a fixed frequency. The two signals are processed by the counter module internally. The counter module outputs a sampled value marked as SAMP[11:0], where [11:0] indicates that the number of bits for sampling is 12. The output of the counter module is connected to the input of the AVERAGE averaging module. SAMP[11:0] is used as the input of the AVERAGE averaging module and is processed to obtain the average value STD[11:0] of multiple sampling periods. The output of the AVERAGE averaging module is connected to the B pin of the AB subtractor. The AVERAGE averaging module inputs the average value STD[11:0] to the B pin of the AB subtractor. The output of the counter module is also connected to the A pin of the AB subtractor. After SAMP[11:0] and STD[11:0] are processed by the AB subtractor internally, the output is DLT[11:0].

8. The charge balance type touch capacitance monitoring method according to claim 7, characterized in that: The switch T Switches TII, TIII, and TIV are ideal switches.

9. The charge balance type touch capacitance monitoring method according to claim 8, characterized in that: The charge-balanced touch capacitance monitoring chip also includes a sampling channel and a trimming module. The sampling channel adopts a charge-balanced touch capacitance monitor structure. The output terminals of the sampling channel and the touch channel are respectively connected to the receiving terminal of the trimming module. The output terminal of the trimming module is connected to the receiving terminal of the touch judgment module. The sampling channel is used to acquire data detected by the charge-balanced touch capacitive monitor in the absence of touch. The adjustment module is used to correct the data collected by the touch channel, eliminate interference factors in the absence of touch, and input the corrected collected data into the touch judgment module.

10. The charge balance type touch capacitance monitoring method according to claim 9, characterized in that: The adjustment module has the following structure: it includes a DIV12BIT module, a MUL12BIT module, and a SUB12BIT module. The DIV12BIT module has pins A and B. Pin A of the DIV12BIT module acquires input SAMP0_[11:0], which is the current sampled value in the sampling channel. Pin B of the DIV12BIT module acquires input STD0_[11:0], which is the current sampled value in the sampling channel. The average values ​​SAMP0_[11:0] and STD0_[11:0] are processed internally by the DIV12BIT module and output as DIV[12:0]. The output of the DIV12BIT module is connected to pin B of the MUL12BIT module, which has pins A and B. DIV[12:0] serves as the input to pin B of the MUL12BIT module, and the input to pin A of the MUL12BIT module is the average value STD1_[11:0] of the touch channel. [12:0] and STD1_[11:0] are processed internally by the MUL12BIT module and output as STD1_VAL[11:0]. STD1_VAL[11:0] is the average value of the adjusted touch channel. The output of the MUL12BIT module is connected to pin B of the SUB12BIT module. STD1_VAL[11:0] serves as the input of pin B of the SUB12BIT module. The input SAMP1_[11:0] of pin A of the SUB12BIT module is the touch channel value. The current sampled values, STD1_VAL[11:0] and SAMP1_[11:0], are processed internally by the SUB12BIT module to output DLT1_[11:0]. The output DLT1_[11:0] is the difference of the adjusted touch channel. This final output difference is compared with LN to determine whether the touch capacitor CX has been touched. When DLT1_[11:0] is greater than LN, it is considered that there is a touch. The value range of LN is set between 8 and 30. The adjustment module uses the following formula for the adjustment algorithm: DIV[12:0]=SAMP0_[11:0] / STD0_[11:0] STD1_VAL[11:0]=STD1_[11:0]*DIV[12:0] DLT1_[11:0]=SAMP1_[11:0]-STD1_VAL[11:0].

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