Test method and device of isolation unit, storage medium and test chip

Abstract

The application discloses a test method and device of an isolation unit, a storage medium and a test chip, wherein the test method of the isolation unit comprises the following steps: inputting an output signal of a first power domain into a second power domain, isolating the input signal by using an isolation unit in the second power domain, and obtaining an output value after isolation; performing logical AND operation processing on a signal with a first output value, and inputting the processed signal into a first pin of a chip; performing logical OR operation processing on a signal with a second output value, and inputting the processed signal into a second pin of the chip; and determining whether the isolation unit has a fault according to output values of the first pin and the second pin. According to the embodiment, the test logic of the ISO isolation unit built in the chip can test the fault of the ISO isolation unit, improve the test efficiency and coverage of the chip, and thus reduce the test time of the chip and the cost of the chip in the final chip mass production test.

Description

Technical Field

[0001] This application relates to the field of electronic technology, specifically to a testing method, apparatus, storage medium, and test chip for an isolation unit. Background Technology

[0002] Today, with the increasing scale and complexity of integrated circuits and the decreasing relative gate count of pins on chips, the controllability and observability of circuits have significantly decreased. Traditional testing methods struggle to comprehensively and effectively verify the correctness of complex integrated circuit designs and manufacturing processes. Testability methods offer a solution to this problem by appropriately adding dedicated test circuits to improve circuit controllability and observability, thereby reducing the difficulty and complexity of circuit testing, increasing testing efficiency, and lowering costs.

[0003] To achieve better power efficiency, large-scale SoC chips often incorporate multiple power supply designs. This necessitates isolating certain signals in the power switch area using isolation units to achieve a stable state. This allows the normal operation of other power domain circuits on the chip to be maintained even when one power domain is turned off.

[0004] Typically, SOC chips are tested using SCAN to examine the chip's registers and combinational logic. However, the applicant found that ISO isolation units are often untestable. The usual practice is to add a functional test, such as the SW_domian power-down test, during chip testing to ensure the correctness of the ISO isolation units and the correctness of the chip's low-power mode. However, this leads to excessively long mass production testing time, increases chip testing costs, and consequently affects the chip's cost. Summary of the Invention

[0005] In view of this, this application provides a testing method, apparatus, storage medium, and test chip for isolation cells to solve the problems of low testing efficiency and excessive time consumption in the prior art for testing isolation cells in chip testing.

[0006] This application provides a testing method for isolation cells, applied to chips, comprising:

[0007] The output signal of the first power domain is input to the second power domain;

[0008] In the second power domain, the input signal is isolated by an isolation unit, and multiple isolated output values ​​are obtained after isolation. The multiple isolated output values ​​include multiple first output values ​​and multiple second output values.

[0009] Each of the signals whose output value is the first output value is subjected to a logical AND operation, and the processed signal is input to the first pin of the chip;

[0010] Each of the signals whose output value is the second output value is subjected to a logical OR operation, and the processed signal is input to the second pin of the chip;

[0011] The presence or absence of a fault in the isolation unit is determined based on the output values ​​of the first and second pins.

[0012] Optionally, the method further includes:

[0013] The power domain in the chip is divided into a power-down domain and a power-on domain.

[0014] The power domain that can be powered off is defined as the first power domain, and the power domain that cannot be powered off is defined as the second power domain.

[0015] Optionally, the method further includes:

[0016] After the chip is powered on, the test mode of the isolation unit is enabled through the security register and the preset CP pad; or

[0017] After the chip is powered on, the test mode of the isolation unit is activated through a preset working sequence.

[0018] Optionally, before isolating the input signal in the second power domain using an isolation unit, the method further includes:

[0019] The low-dropout linear regulator in the first power domain is turned off by controlling the test pin of the chip, thereby powering down the first power domain.

[0020] Optionally, determining whether the isolation unit is faulty based on the output values ​​of the first pin and the second pin includes:

[0021] If the output signal of the first pin is set to the second output value, it is determined that the isolation unit associated with the first pin is faulty;

[0022] If the output signal of the second pin is set to the first output value, it is determined that the isolation unit associated with the second pin is faulty.

[0023] Optionally, the step of calculating the output signal of the first pin or the second pin includes:

[0024] The waveform data of the output signal of the first pin or the second pin is stored as a waveform file;

[0025] The data in the waveform file is analyzed to calculate the output result of the output signal.

[0026] This application also provides a test apparatus for isolation cells, applied to a chip, comprising:

[0027] The input module is used to input the output signal of the first power domain to the second power domain;

[0028] An isolation module is used to isolate the input signal in the second power domain through an isolation unit and obtain multiple isolated output values, the multiple isolated output values ​​including multiple first output values ​​and multiple second output values;

[0029] The first processing module is used to perform a logical AND operation on each of the signals whose output value is a first output value, and input the processed signal to the first pin of the chip;

[0030] The second processing module is used to perform a logical OR operation on each of the signals whose output value is the second output value, and input the processed signal to the second pin of the chip.

[0031] The determination module is used to determine whether the isolation unit is faulty based on the output values ​​of the first pin and the second pin.

[0032] Optionally, the determining module specifically includes:

[0033] The first determining submodule is used to determine that the isolation unit associated with the first pin is faulty when the output signal of the first pin is set to the second output value.

[0034] The second determining module is used to determine that the isolation unit associated with the second pin is faulty when the output signal of the second pin is set to the first output value.

[0035] This application also provides a storage medium storing a plurality of instructions adapted for loading by a processor to execute the steps in the above-described method for testing isolated units.

[0036] This application also provides a test chip, including a test circuit, which is used to perform the above-described test method for the isolation unit.

[0037] Optionally, the test chip further includes an AND gate, the input of which is connected to an isolation unit in the second power domain, and the output of which is connected to a first pin of the test chip.

[0038] Optionally, the test chip further includes an OR gate, the input of which is connected to an isolation unit in the second power domain, and the output of which is connected to a second pin of the test chip.

[0039] As can be seen from the above, the testing method for the isolation unit provided in this application allows the output signal of the first power domain to be input to the second power domain. In the second power domain, the input signal is isolated by the isolation unit, and the isolated output value is obtained. The signal with the first output value is processed by a logical AND operation, and the processed signal is input to the first pin of the chip. The signal with the second output value is processed by a logical OR operation, and the processed signal is input to the second pin of the chip. The presence of a fault in the isolation unit is determined based on the output values ​​of the first and second pins. This embodiment utilizes the test logic of a self-built ISO isolation unit within the chip to detect faults in the ISO isolation unit, improving the chip's testing efficiency and coverage. This, in turn, reduces the chip's testing time and cost during final mass production testing. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic flowchart of a testing method for an isolation unit according to an embodiment of this application;

[0042] Figure 2 This is a test circuit diagram of an isolation unit according to an embodiment of this application;

[0043] Figure 3 This is a test circuit diagram of another isolation unit according to an embodiment of this application;

[0044] Figure 4 This is a schematic flowchart of a testing method for another isolation unit according to an embodiment of this application;

[0045] Figure 5 This is a schematic diagram of a test device for an isolation unit according to an embodiment of this application;

[0046] Figure 6 This is another schematic diagram of the test device for the isolation unit according to an embodiment of this application. Detailed Implementation

[0047] In existing technologies, SOC chips are tested by SCAN to test the chip's registers and combinational logic; by MBIST to test ROM and RAM modules; by FLASH BIST to test FLASH; and by ATEST mode to test analog modules such as USBPHY, PLL, OSC, etc.

[0048] While SOC chips can be tested via SCAN to examine almost all registers and combinational logic units, including level shifters, ISO isolation units cannot be tested. The common practice is to supplement chip testing with a functional test, such as a SW_domian power-down test, to ensure the correctness of ISO isolation units and the correctness of the entire chip's low-power mode. Existing technologies require firmware flashing for functional testing, leading to excessively long mass production testing times, increasing chip testing costs, and consequently affecting chip cost. Therefore, this application proposes a new testing method for isolation units.

[0049] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0050] Please see Figure 1 This is a flowchart illustrating a testing method for an isolation unit according to an embodiment of this application.

[0051] In this embodiment, the testing method for the isolation unit includes the following steps:

[0052] Step 101: Input the output signal of the first power domain to the second power domain.

[0053] In one embodiment, the testing method for the isolation unit of this embodiment is applied to a chip such as a SOC chip, which may include an integrated circuit with multiple power domains. These multiple power domains can be powered by different power supply voltages. For example, when the first power domain is powered up, it takes some time for the power supply voltage VCC1 to become available or ready for use. Similarly, when the second power domain is powered up, it takes some time for the power supply voltage VCC2 to become available or ready for use. Both power supply voltages VCC1 and VCC2 can be provided by a power control module (PCM) located in the always-on power domain. The power control module can be an on-chip PCM within the integrated circuit or an off-chip PCM external to the integrated circuit. In some embodiments, one of the plurality of power supply voltages VCC1 and VCC2 may be the core voltage at which the processor core operates, and the other of the plurality of power supply voltages VCC1 and VCC2 may be the input / output voltage at which the input / output circuit (I / O circuit) operates. The processor core may be used to control the input / output circuit.

[0054] In one embodiment, typically, the SOC chip will test the chip's registers and combinational logic via SCAN; test the ROM and RAM modules via MBIST; test the FLASH via FLASH BIST; and test analog modules such as USB PHY, PLL, OSC, etc. via ATEST mode.

[0055] For example, please refer to Figure 2 In the diagram above, all signals from the SW_domain need to be isolated by an ISO isolation unit before entering the AON_domain module. When the SW_domain is powered on, the signals are unaffected. When the SW_domain is powered off, the ISO isolation unit needs to isolate those signals to a fixed state; otherwise, the AON_domain circuitry will be affected.

[0056] Step 102: In the second power domain, the input signal is isolated by an isolation unit, and the isolated output value is obtained.

[0057] In one embodiment, in low-power systems, unused power domains are often turned off to reduce energy consumption. For example, when a smartphone is making a call, the power domain of the LCD display can be temporarily powered off, while another power domain of the communication module remains powered on to save power.

[0058] Isolation cells are commonly incorporated into low-power systems to prevent interference between different power domains when powered on and off. However, in some special applications, the isolation signal input of the isolation cell is bound to a specific potential. Since the potential of the isolation signal input cannot be changed, system testers cannot determine whether the isolation cell operates correctly under all conditions. Therefore, in one embodiment, the output signal of the first power domain can be input to a second power domain, where the input signal is isolated by the isolation cell, and the isolated output value is obtained.

[0059] The aforementioned isolation unit may include a normal function mode and a test mode (IOS Test Mode). Specifically, the test mode of the isolation unit can be enabled after the output signal of the first power domain is input to the second power domain. For example, ISO_TEST_LOGIC is a test circuit that operates in test mode. The entire test circuit operates in the AON_domain, and the power supply will not be turned off at this time.

[0060] Step 103: Perform a logical AND operation on the signal whose output value is the first output value, and input the processed signal to the first pin of the chip.

[0061] Step S104: Perform a logical OR operation on the signal whose output value is the second output value, and input the processed signal to the second pin of the chip.

[0062] Step 105: Determine whether the isolation unit is faulty based on the output values ​​of the first and second pins.

[0063] In one embodiment, see further. Figure 3Here, SW LDO is the LDO (Low Dropout Linear Regulator) analog module in the SOC chip, providing voltage to the SW domain circuitry. SW_domain Logic is the circuitry in the SW domain power domain of the SOC chip. ISO_TEST_LOGIC is the test circuit operating in ISO test mode; the entire test circuit operates in the AON_domain, and the power supply is not turned off. ISO refers to a specific isolation unit; signals from the SW domain entering the AON domain must pass through ISO isolation. PAD_A0 / A1 / A2 are the chip pins. A1, A2...AN are signals with isolation level 1. B1, B2...BN are signals with isolation level 0. In this embodiment, since each signal needs to be isolated by an ISO isolation unit, and signals with different isolation values ​​also need to be processed through different isolation units, the number of isolated output values ​​obtained after isolating the input signals is multiple. In this embodiment, the isolated output values ​​of the signals A1, A2...AN, etc., which are isolated to 1, can be defined as the first output value, and the isolated output values ​​of the signals B1, B2...BN, etc., which are isolated to 0, can be defined as the second output value. It should be noted that the above N signals need to be isolated by N isolation units respectively, so the number of the first output value and the second output value after processing is also multiple.

[0064] Specifically, the chip internally performs a logical AND operation on all signals isolated as 1, and outputs the AND result to the chip's A0 pin. It also performs a logical OR operation on all signals isolated as 0, and outputs the OR result to the chip's A1 pin. In isolation test mode, if pin A0 equals 0, it indicates a fault in the chip's isolation unit; if pin A1 equals 1, it indicates a fault in the chip's isolation unit; otherwise, the chip's isolation unit is functioning normally.

[0065] As can be seen from the above, the testing method for the isolation unit provided in this application embodiment can input the output signal of the first power domain to the second power domain, isolate the input signal through the isolation unit in the second power domain, obtain the isolated output value, perform a logical AND operation on the signal with the output value as the first output value, and input the processed signal to the first pin of the chip, perform a logical OR operation on the signal with the output value as the second output value, and input the processed signal to the second pin of the chip, and determine whether the isolation unit is faulty based on the output values ​​of the first and second pins. This embodiment utilizes the test logic of the self-built ISO isolation unit inside the chip to detect the faults of the ISO isolation unit, improve the chip testing efficiency and coverage, and thus reduce the chip testing time and chip cost during the final chip mass production testing.

[0066] Based on the testing method for the isolation unit described in the previous embodiment, the following will provide further detailed examples.

[0067] In this embodiment, the test method device for the isolation unit will be specifically integrated into an electronic device as an example for explanation.

[0068] Please see Figure 4 , Figure 4 Another schematic flowchart illustrating the testing method for the isolation unit provided in this embodiment of the invention. The method flow may include:

[0069] Step 201: Input the output signal of the first power domain to the second power domain.

[0070] In one embodiment, to meet the low power consumption requirements of the chip, the SOC can be divided into multiple power domains. Different power domains can be powered on and off independently. Specifically, this can include two power domains: SW_domain and AON_domain. SW_domain is a power-down domain, while AON_domain is a non-power-down domain that needs to be always on. That is, before inputting the output signal of the first power domain to the second power domain, the method may further include: dividing the power domains in the chip into a power-down domain and a non-power-down domain; designating the power-down domain as the first power domain and the non-power-down domain as the second power domain.

[0071] It should be noted that, in this embodiment, modules corresponding to functions that need to be constantly active in the electronic device can run in the non-power-discarding power domain (i.e., the second power domain) of the chip. This ensures the continuous operation of the function. Modules corresponding to functions that are only used occasionally can run in the power-discarding power domain (i.e., the first power domain) of the chip. This way, the function only needs to be powered on and started through the power-discarding power domain when needed. For example, communication and network functions in a mobile phone need to run continuously, so the communication and network modules can run in the non-power-discarding power domain of the chip. Functions such as screen display or sound playback only need to be turned on when the user needs them, so the screen display module and speaker module corresponding to these functions can run in the power-discarding power domain of the chip. By dividing the power domain into power-discarding and non-power-discarding power domains in this embodiment, power consumption can be reduced, thereby improving the device's battery life.

[0072] Step 202: The low-dropout linear regulator of the first power domain is turned off by controlling the test pin of the chip, so as to power down the first power domain.

[0073] In one embodiment, since some signals in the power switch area need to be isolated by an isolation unit to achieve a stable state, it is possible to turn off a certain power domain without affecting the normal operation of other power domain circuits on the chip. Specifically, the low-dropout linear regulator of the first power domain can be turned off by controlling the test pin of the chip, thereby powering down the first power domain. The aforementioned test pin can be, for example, a... Figure 3 In the PAD_A2 pin, for example, you can directly disable SW_LDO through the PAD_A2 pin, causing the SW domain power domain to power down.

[0074] Step 203: After the chip is powered on, the test mode of the isolation unit is enabled through the confidential register and the preset CP pad, or the test mode of the isolation unit is enabled through the preset working sequence.

[0075] Specifically, after the chip powers on and initializes, it enters ISO test mode. In this mode, the ISO_TEST_LOGIC test circuit starts working, and the entire test circuit operates in the AON_domain without powering off. Then, the isolated unit's test mode can be entered through methods such as a secret register, a special CP PAD, or a special sequence.

[0076] Step 204: In the second power domain, the input signal is isolated by the isolation unit, and the isolated output value is obtained.

[0077] In one embodiment, the output signal of the first power domain can be input to the second power domain. In the second power domain, the input signal is isolated by an isolation unit, and the isolated output value is obtained. The isolation unit is used to isolate the signal between the first and second power domains. Specifically, the isolation unit is designed to isolate signals between different power domains to prevent signal transmission errors or even malfunctions in circuits within different power domains due to differences in operating power supply voltages. Specifically, the isolation unit performs decoding and decoding processing on the signals from different power domains to achieve isolated signal transmission between them. The signals mentioned here can be divided into external signals and internal signals; for example, external signals are signals from the first power domain, and internal signals are signals from the second power domain.

[0078] Specifically, in this embodiment, the ISO_test_logic circuit inside the chip isolates the signals in the SW domain and performs subsequent logic operations on them separately.

[0079] Step 205: Perform a logical AND operation on the signal whose output value is the first output value, and input the processed signal to the first pin of the chip.

[0080] Step 206: Perform a logical OR operation on the signal whose output value is the second output value, and input the processed signal to the second pin of the chip.

[0081] Step 207: Determine whether the isolation unit is faulty based on the output values ​​of the first and second pins.

[0082] In one embodiment, the step of determining whether the isolation unit is faulty based on the output values ​​of the first pin and the second pin may include: if the output signal of the first pin is set to the second output value, then it is determined that the isolation unit associated with the first pin is faulty; if the output signal of the second pin is set to the first output value, then it is determined that the isolation unit associated with the second pin is faulty.

[0083] For details, please refer to [link / reference]. Figure 3 The ISO isolation unit is checked by examining the chip pin PAD_A0. If PAD_A0 equals 0, the ISO isolation unit is faulty; otherwise, it is normal. Similarly, the ISO isolation unit is checked by examining the chip pin PAD_A1. If PAD_A1 equals 1, the ISO isolation unit is faulty; otherwise, it is normal.

[0084] In one embodiment, the step of calculating the output signal of the first pin or the second pin may include: storing the waveform data of the output signal of the first pin or the second pin as a waveform file, and analyzing the data in the waveform file to calculate the output result of the output signal. The waveform file is the main simulation output result and debugging target of the digital chip system. The waveform file may contain waveform signals, and processing these waveform signals yields the output value of the output signal.

[0085] As can be seen from the above, the testing method for the isolation unit provided in this application embodiment can input the output signal of the first power domain to the second power domain, control the low-dropout linear regulator of the first power domain to be turned off through the chip's test pin, so that the first power domain is powered down. After the chip is powered on, the test mode of the isolation unit is enabled through the confidential register and the preset CP pad, or through the preset working sequence. In the second power domain, the input signal is isolated by the isolation unit, and the isolated output value is obtained. The signal with the output value of the first output value is processed by a logical AND operation, and the processed signal is input to the first pin of the chip. The signal with the output value of the second output value is processed by a logical OR operation, and the processed signal is input to the second pin of the chip. The presence of a fault in the isolation unit is determined based on the output values ​​of the first and second pins. This embodiment utilizes the test logic of the self-built ISO isolation unit inside the chip, which can detect the fault of the ISO isolation unit, improve the chip's testing efficiency and coverage, and thus reduce the chip's testing time and cost during the final chip mass production test.

[0086] In one embodiment, this application also provides a testing apparatus for an isolation unit, such as... Figure 6 As shown, it includes:

[0087] Input module 301 is used to input the output signal of the first power domain to the second power domain;

[0088] The isolation module 302 is used to isolate the input signal in the second power domain through the isolation unit and obtain the isolated output value;

[0089] The first processing module 303 is used to perform a logical AND operation on the signal whose output value is the first output value, and input the processed signal to the first pin of the chip;

[0090] The second processing module 304 is used to perform a logical OR operation on the signal whose output value is the second output value, and input the processed signal to the second pin of the chip.

[0091] The determination module 305 is used to determine whether the isolation unit is faulty based on the output values ​​of the first pin and the second pin.

[0092] In one embodiment, please continue to refer to Figure 6 The determination module 305 may specifically include:

[0093] The first determination submodule 3051 is used to determine that the isolation unit associated with the first pin is faulty when the output signal of the first pin is set to the second output value.

[0094] The second determination module 3052 is used to determine that the isolation unit associated with the second pin is faulty when the output signal of the second pin is set to the first output value.

[0095] As described above, the testing device for the isolation unit provided in this embodiment of the invention can input the output signal of the first power domain to the second power domain. In the second power domain, the input signal is isolated by the isolation unit, and the isolated output value is obtained. The signal with the first output value is processed by a logical AND operation, and the processed signal is input to the first pin of the chip. The signal with the second output value is processed by a logical OR operation, and the processed signal is input to the second pin of the chip. The presence of a fault in the isolation unit is determined based on the output values ​​of the first and second pins. This embodiment utilizes the test logic of the self-built ISO isolation unit within the chip to detect faults in the ISO isolation unit, improving the chip's testing efficiency and coverage, thereby reducing chip testing time and cost during final chip mass production testing.

[0096] In addition, embodiments of this application also provide a storage medium storing a plurality of instructions adapted for loading by a processor to execute the steps in the above-described testing method for the isolation unit.

[0097] Embodiments of this application also provide an electronic device, including a processor and a memory. The memory stores a computer program, which, when executed by the processor, performs the aforementioned test method for the isolation unit. The electronic device may be a mobile phone, tablet computer, smartwatch, or other terminal device.

[0098] The electronic device of this application, by implementing the test method of the isolation unit, can input the output signal of the first power domain to the second power domain. In the second power domain, the input signal is isolated by the isolation unit, and the isolated output value is obtained. The signal with the first output value is processed by a logical AND operation, and the processed signal is input to the first pin of the chip. The signal with the second output value is processed by a logical OR operation, and the processed signal is input to the second pin of the chip. The presence of a fault in the isolation unit is determined based on the output values ​​of the first and second pins. This embodiment utilizes the test logic of a self-built ISO isolation unit within the chip to detect faults in the ISO isolation unit, improving the chip's testing efficiency and coverage, thereby reducing chip testing time and cost during final chip mass production testing.

[0099] Embodiments of this application also provide a test chip, including a test circuit, which is used to perform the above-described test method for the isolation unit.

[0100] In one embodiment, the test chip further includes an AND gate, the input of which is connected to an isolation unit in a second power domain, and the output of which is connected to a first pin of the test chip.

[0101] In one embodiment, the test chip further includes an OR gate, the input of which is connected to an isolation unit in a second power domain, and the output of which is connected to a second pin of the test chip.

[0102] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0103] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0104] The above description has been provided to enable any person skilled in the art to implement and use this application. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A testing method for isolation cells, applied to a chip, characterized in that, include: The output signal of the first power domain is input to the second power domain; In the second power domain, the input signal is isolated by an isolation unit, and multiple isolated output values ​​are obtained. The multiple isolated output values ​​include multiple first output values ​​and multiple second output values, wherein the first output value is logic 1 and the second output value is logic 0. Perform a logical AND operation on the signals of each of the first output values, and input the processed signals to the first pin of the chip; Perform a logical OR operation on the signals of each of the second output values, and input the processed signals to the second pin of the chip; The presence or absence of a fault in the isolation unit is determined based on the output values ​​of the first and second pins.

2. The testing method for the isolation unit according to claim 1, characterized in that, The method further includes: The power domain in the chip is divided into a power-down domain and a power-on domain. The power domain that can be powered off is defined as the first power domain, and the power domain that cannot be powered off is defined as the second power domain.

3. The testing method for the isolation unit according to claim 1, characterized in that, The method further includes: After the chip is powered on, the test mode of the isolation unit is enabled through the security register and the preset CP pad; or After the chip is powered on, the test mode of the isolation unit is activated through a preset working sequence.

4. The testing method for the isolation unit according to claim 1, characterized in that, Before isolating the input signal in the second power domain using an isolation unit, the method further includes: The low-dropout linear regulator in the first power domain is turned off by controlling the test pin of the chip, thereby powering down the first power domain.

5. The testing method for the isolation unit according to claim 1, characterized in that, The step of determining whether the isolation unit is faulty based on the output values ​​of the first pin and the second pin includes: If the output signal of the first pin is set to the second output value, it is determined that the isolation unit associated with the first pin is faulty; If the output signal of the second pin is set to the first output value, it is determined that the isolation unit associated with the second pin is faulty.

6. The testing method for the isolation unit according to claim 5, characterized in that, The process of obtaining the output value of the first pin or the second pin includes: The waveform data of the output signal of the first pin or the second pin is stored as a waveform file; The data in the waveform file is analyzed to calculate the output result of the output signal.

7. A testing device for isolation units, applied to a chip, characterized in that, include: The input module is used to input the output signal of the first power domain to the second power domain; An isolation module is used to isolate the input signal in the second power domain through an isolation unit and obtain multiple isolated output values ​​after isolation. The multiple isolated output values ​​include multiple first output values ​​and multiple second output values, wherein the first output value is logic 1 and the second output value is logic 0. The first processing module is used to perform a logical AND operation on each of the signals whose output value is a first output value, and input the processed signal to the first pin of the chip; The second processing module is used to perform a logical OR operation on each of the signals whose output value is the second output value, and input the processed signal to the second pin of the chip. The determination module is used to determine whether the isolation unit is faulty based on the output values ​​of the first pin and the second pin.

8. The testing apparatus for the isolation unit according to claim 7, characterized in that, The determining module specifically includes: The first determining submodule is used to determine that the isolation unit associated with the first pin is faulty when the output signal of the first pin is set to the second output value. The second determining module is used to determine that the isolation unit associated with the second pin is faulty when the output signal of the second pin is set to the first output value.

9. A storage medium, characterized in that, The storage medium stores a plurality of instructions adapted for loading by a processor to execute the steps in the test method for the isolation unit according to any one of claims 1 to 6.

10. A test chip, characterized in that, Includes a test circuit, said test circuit being used to perform the test method for the isolation unit according to any one of claims 1 to 6.

11. The test chip according to claim 10, characterized in that, The test chip also includes an AND gate, the input of which is connected to an isolation unit in the second power domain, and the output of which is connected to the first pin of the test chip.

12. The test chip according to claim 10, characterized in that, The test chip also includes an OR gate, the input of which is connected to an isolation unit in the second power domain, and the output of which is connected to a second pin of the test chip.

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