Usb chip and operating method thereof

Abstract

The USB chip includes a positive data pin, a negative data pin, a first transceiver circuit, a second transceiver circuit, a switching circuit, and a control circuit. During the high-speed handshake phase, the control circuit controls the switching circuit to a second state to disconnect the connection between the positive and negative data pins and the first termination impedance circuit, and actuates the second transceiver circuit to alternately transmit a second voltage signal at the positive and negative data pins. During the high-speed transmission phase, the control circuit controls the switching circuit to a first state to connect the positive and negative data pins to the first termination impedance circuit, and actuates the first transceiver circuit to alternately transmit a first voltage signal with a voltage level greater than the second voltage signal at the positive and negative data pins.

Description

Technical Field

[0001] This invention relates to a USB technology, and more particularly to a USB chip and its operating method. Background Technology

[0002] The USB (Universal Serial Bus) interface offers the advantages of hot-swapping and plug-and-play functionality, and can also be used to supply or receive power. With technological advancements, USB versions have been continuously updated. USB 2.0, for example, supports low-speed transmission (e.g., 1.5 megabits per second (Mbps),) full-speed transmission (e.g., 12 Mbps), and high-speed transmission (e.g., 480 Mbps).

[0003] Devices supporting USB 2.0 and equipped with USB connectors typically perform speed identification when connecting to another device with a USB connector to determine whether the data transfer is at low, full, or high speed. This identification is achieved through a handshake signal (referred to here as the handshake signal), and the voltage level of this handshake signal must conform to the specification. However, the circuitry used to generate the handshake signal (referred to here as the handshake circuit) may experience some power loss, causing the handshake signal voltage level to deviate from the specification. For example, power loss might result in a handshake signal voltage level lower than the specified voltage. Therefore, the power loss is usually compensated for by increasing the operating voltage of the handshake circuit.

[0004] However, increasing the operating voltage increases the overall power consumption of devices with USB connectors, rather than saving power. Furthermore, increasing the operating voltage requires additional components (e.g., low dropout regulators, LDOs), which takes up circuit design space in devices with USB connectors. Summary of the Invention

[0005] In view of the above, the present invention provides a USB chip and a method for operating the same. According to some embodiments, the present invention can make the voltage level of the handshake signal conform to the specified voltage without increasing the operating voltage. According to some embodiments, the present invention can increase the available space in circuit design.

[0006] According to some embodiments, a USB chip includes a positive data pin, a negative data pin, a first transceiver circuit, a second transceiver circuit, a switching circuit, and a control circuit. The first transceiver circuit, when actuated, alternately transmits a first voltage signal via the positive and negative data pins. The second transceiver circuit, when actuated, alternately transmits a second voltage signal via the positive and negative data pins. The second voltage level of the second voltage signal is greater than the first voltage level of the first voltage signal. The switching circuit, in a first state, connects the positive data pin to the first termination impedance circuit and connects the negative data pin to the first termination impedance circuit. In a second state, the switching circuit disconnects the positive data pin from the first termination impedance circuit and disconnects the negative data pin from the first termination impedance circuit. The control circuit, during a high-speed handshake phase, controls the switching circuit to the second state; when the switching circuit is controlled to the second state, actuates the second transceiver circuit; during a high-speed transmission phase, controls the switching circuit to the first state; and when the switching circuit is controlled to the first state, actuates the first transceiver circuit.

[0007] According to some embodiments, a USB chip includes a positive data pin, a negative data pin, a first transceiver circuit, a second transceiver circuit, a switching circuit, and a control circuit. The operation method of the USB chip includes, during a high-speed handshake phase, controlling the switching circuit to a second state by the control circuit; actuating the second transceiver circuit while the switching circuit is controlled to the second state; controlling the switching circuit to a first state during a high-speed transmission phase; and actuating the first transceiver circuit while the switching circuit is controlled to the first state. In the first state, the switching circuit connects the positive data pin to the first termination impedance circuit and also connects the negative data pin to the first termination impedance circuit. In the second state, the switching circuit disconnects the positive data pin from the first termination impedance circuit and also disconnects the negative data pin from the first termination impedance circuit. When actuated, the first transceiver circuit alternately transmits a first voltage signal via the positive and negative data pins. When actuated, the second transceiver circuit alternately transmits a second voltage signal via the positive and negative data pins. The second voltage level of the second voltage signal is greater than the first voltage level of the first voltage signal.

[0008] In summary, according to some embodiments, by using two transceiver circuits that emit different voltage levels, the voltage level of the handshake signal during the high-speed handshake phase and the voltage level of the signal during the high-speed transmission phase (hereinafter referred to as the handshake completion signal) can be made to conform to the specification voltage without increasing the operating voltage. In some embodiments, since no additional components (e.g., linear regulators) are required to increase the operating voltage, the available space in the circuit design can be increased. For example, in addition to reducing the overall power consumption of the USB chip by half, the circuit design space can also be increased. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a USB chip and its application according to some embodiments of the present invention.

[0010] Figure 2 This is a flowchart illustrating the operation method of a USB chip according to some embodiments of the present invention.

[0011] Figure 3 This is a schematic diagram of the signal timing of the handshake procedure in some embodiments of the present invention.

[0012] Figure 4 This is a schematic diagram illustrating the application of the second transceiver circuit in some embodiments of the present invention.

[0013] Figure 5 This is a schematic diagram illustrating the application of the first transceiver circuit in some embodiments of the present invention.

[0014] Figure 6 This is a schematic diagram of a USB chip according to some embodiments of the present invention. Detailed Implementation

[0015] The terms "first" and "second" as used herein are used to distinguish the elements referred to, not to order or limit the differences between the elements, nor to limit the scope of the invention. Furthermore, the term "connection" as used herein refers to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other; for example, if the text describes a first device connected to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0016] Reference Figure 1This is a block diagram illustrating a USB chip 10 and its application according to some embodiments of the present invention. The USB chip 10 includes a positive data pin D+_A, a negative data pin D-_A, a first transceiver circuit 21, a second transceiver circuit 23, a switching circuit 30, and a control circuit 40. The positive data pin D+_A and the negative data pin D-_A are connected to the first transceiver circuit 21 and the second transceiver circuit 23. The switching circuit 30 is connected to the positive data pin D+_A, the negative data pin D-_A, and a first terminating impedance circuit 50. The control circuit 40 is connected to the first transceiver circuit 21, the second transceiver circuit 23, and the switching circuit 30.

[0017] In some embodiments, the positive data pin D+_A and the negative data pin D-_A can be implemented using a USB connector (hereinafter referred to as connector 60). In some embodiments, the USB chip 10 can be implemented as a USB host device and can connect to a USB slave device 100. The USB host device can be an electronic device with a USB female connector (or a Type-C connector), such as a personal computer, mobile device, digital television (such as a set-top box), or USB hub. The USB slave device 100 can be an electronic device with a USB male connector (or a Type-C connector), such as a personal computer, mobile device, photographic equipment, digital television (such as a set-top box), or game console.

[0018] The following explanation will use USB chip 10 as an example of a USB host device.

[0019] The USB version of connector 60 of USB chip 10 corresponds to the USB version of connector 160 of USB slave device 100, and connector 60 is connected to connector 160. For example, according to Figure 1 The USB version definition (using USB 2.0 as an example here) specifies that connector 60 has the following pins: positive data pin D+_A, negative data pin D-_A, and power conversion pin V. Bus _A and ground pin GND_A connect to the positive data pin D+_B, negative data pin D-_B, and power conversion pin V of connector 160. Bus _B and ground pin GND_B. Switching power supply pin V Bus _A is used to supply power from USB chip 10 to USB slave device 100. For example, the power conversion pin V Bus A 5-volt (V) voltage is supplied from the power management circuit 70 of the USB chip 10 to the power management circuit 170 of the USB slave device 100.

[0020] The power management circuit 70 of the USB chip 10 has a power supply to provide the operating voltage for the components of the USB chip 10 (e.g., the first transceiver circuit 21, the second transceiver circuit 23, the switching circuit 30, and the control circuit 40). Similarly, the power management circuit 170 of the USB slave device 100 supplies power to the components of the USB slave device 100 to enable their operation. In some embodiments, the USB slave device 100 may obtain power in addition to obtaining power from the USB chip 10, or it may obtain power through other means. For example, the USB slave device 100 may have a built-in power supply or may use an external power supply via a power adapter. The ground pin GND_A is used to supply the ground potential from the power management circuit 70 of the USB chip 10 to the power management circuit 170 of the USB slave device 100, so that the USB slave device 100 has a ground potential. The ground pin GND_A obtains the ground potential from the ground terminal of the power management circuit 70. The ground terminal is used to provide the ground potential of the USB chip 10.

[0021] In some embodiments, the USB chip 10 has multiple different transmission modes depending on the USB version it supports, to support multiple different transmission rates. For example, if the USB chip 10 supports USB 2.0, it has a low-speed transmission mode, a full-speed transmission mode, and a high-speed transmission mode to support low-speed, full-speed, and high-speed transmission. When connecting to the USB slave device 100, the USB chip 10 needs to determine the transmission modes it and the USB slave device 100 possess, and then transmit at a transmission rate supported by both itself and the USB slave device 100.

[0022] For example, such as Figure 1 As shown, the USB chip 10 has a low-speed full-speed transceiver module 90 and a high-speed transceiver module 20. The USB slave device 100 has a low-speed full-speed transceiver module 190 and a high-speed transceiver module 120. The low-speed full-speed transceiver module 90 and the low-speed full-speed transceiver module 190 are used to provide low-speed transmission in low-speed transmission mode and full-speed transmission in full-speed transmission mode for the USB chip 10 and the USB slave device 100, respectively. The high-speed transceiver module 20 and the high-speed transceiver module 120 are used to provide high-speed transmission in high-speed transmission mode for the USB chip 10 and the USB slave device 100, respectively. The high-speed transceiver module 20 can be implemented by a first transceiver circuit 21 and a second transceiver circuit 23.

[0023] In some embodiments, when the USB chip 10 detects a high voltage level on the negative data pin D-_A, it determines that the USB slave device 100 is in a low-speed transmission mode, and therefore the USB chip 10 and the USB slave device 100 perform low-speed transmission. When the USB chip 10 detects a high voltage level on the positive data pin D+_A, it further performs a handshake procedure (described in detail later). Through the handshake procedure, it is determined whether both the USB chip 10 and the USB slave device 100 have a high-speed transmission mode. If both the USB chip 10 and the USB slave device 100 have a high-speed transmission mode, then the USB chip 10 and the USB slave device 100 perform high-speed transmission. If one or both of the USB chip 10 and the USB slave device 100 do not have a high-speed transmission mode, then the USB chip 10 and the USB slave device 100 perform full-speed transmission.

[0024] Specifically, when the USB pull-up resistor R of device 100 pu When the negative data pin D-_B of the USB slave device 100 is connected, it indicates that the USB slave device 100 is in low-speed transmission mode, and the negative data pins D-_B and D-_A are pulled up to a high voltage level (e.g., 3.3V). When the pull-up resistor R of the USB slave device 100... pu When connecting the positive data pin D+_B of the USB slave device 100 (e.g.) Figure 1 As shown, the positive data pins D+_B and D+_A are pulled up to a high voltage level (e.g., 3.3V), indicating that the USB slave device 100 is not in low-speed transmission mode. Therefore, the USB chip 10 needs to perform a handshake procedure to determine whether to perform full-speed or high-speed transmission with the USB slave device 100.

[0025] Reference Figure 2 This is a flowchart illustrating the operation method of the USB chip 10 according to some embodiments of the present invention. In some embodiments, the operation method is adapted to be executed by the control circuit 40. First, during the high-speed handshake phase of the handshake procedure, the control circuit 40 controls the switching circuit 30 to a second state (step S201). When the switching circuit 30 is controlled to the second state, the control circuit 40 actuates the second transceiver circuit 23 (step S203) to start the second transceiver circuit 23. During the high-speed transmission phase of the handshake procedure, the control circuit 40 controls the switching circuit 30 to a first state (step S205). When the switching circuit 30 is controlled to the first state, the control circuit 40 actuates the first transceiver circuit 21 (step S207) to start the first transceiver circuit 21. In some embodiments, when the high-speed transmission phase of the handshake procedure is entered, it indicates that both the USB chip 10 and the USB slave device 100 have a high-speed transmission mode, and the handshake is successful, thus allowing high-speed data transmission to begin and the handshake procedure to end.

[0026] like Figure 1 As shown, in the first state, the switching circuit 30 connects the positive data pin D+_A to the first terminating impedance circuit 50 and also connects the negative data pin D-_A to the first terminating impedance circuit 50. When the first transceiver circuit 21 is activated, it alternately transmits a first voltage signal (i.e., a handshake completion signal) via the positive data pin D+_A and the negative data pin D-_A. In the second state, the switching circuit 30 disconnects the connection between the positive data pin D+_A and the first terminating impedance circuit 50 and also disconnects the connection between the negative data pin D-_A and the first terminating impedance circuit 50. When the second transceiver circuit 23 is activated, it alternately transmits a second voltage signal (i.e., a handshake signal) via the positive data pin D+_A and the negative data pin D-_A.

[0027] Compared to the first voltage signal, which is generated when the connection between the first terminating impedance circuit 50 and the positive data pin D+_A is connected, and the connection between the first terminating impedance circuit 50 and the negative data pin D-_A is connected, the second voltage signal is generated when the connection between the first terminating impedance circuit 50 and the positive data pin D+_A is disconnected, and the connection between the first terminating impedance circuit 50 and the negative data pin D-_A is disconnected. Furthermore, the headroom of the first transceiver circuit 21 is less than that of the second transceiver circuit 23. Therefore, the second voltage level of the second voltage signal is greater than the first voltage level of the first voltage signal. Thus, by emitting two transceiver circuits with different voltage levels (i.e., the first transceiver circuit 21 and the second transceiver circuit 23), the voltage level of the handshake signal during the high-speed handshake phase and the voltage level of the handshake completion signal during the high-speed transmission phase can be made to conform to the standard voltage without increasing the operating voltage. The standard voltage for the handshake signal is 0.8V, and the standard voltage for the handshake completion signal is 0.4V.

[0028] In some embodiments, when the switching circuit 30 is controlled to the first state, the control circuit 40 also disables the second transceiver circuit 23. When the switching circuit 30 is controlled to the second state, the control circuit 40 also disables the first transceiver circuit 21. That is, only the second transceiver circuit 23 operates during the high-speed handshake phase, and only the first transceiver circuit 21 operates during the high-speed transmission phase. This ensures that the first transceiver circuit 21 and the second transceiver circuit 23 do not interfere with each other, and that the first voltage signal and the second voltage signal do not interfere with each other.

[0029] like Figure 1As shown, in some embodiments, the switching circuit 30 includes a first switch 31 and a second switch 33. The first switch 31 and the second switch 33 can be implemented by electronic switches (e.g., transistors). In some embodiments, the first terminating impedance circuit 50 includes a first terminating impedance R1 and a second terminating impedance R2. The first terminating impedance R1 and the second terminating impedance R2 can be composed of passive components (e.g., resistors, capacitors, inductors). In a preferred embodiment, the first terminating impedance R1 and the second terminating impedance R2 are implemented by resistors, for example, both the first terminating impedance R1 and the second terminating impedance R2 have a resistance of 45 ohms (Ω). The first switch 31 is connected between the positive data pin D+_A and the first terminating impedance R1. The second switch 33 is connected between the negative data pin D-_A and the second terminating impedance R2. In some embodiments, in a first state, the first switch 31 conducts the connection between the positive data pin D+_A and the first terminating impedance R1, and the second switch 33 conducts the connection between the negative data pin D-_A and the second terminating impedance R2. In the second state, the first switch 31 disconnects the connection between the positive data pin D+_A and the first terminating impedance R1, and the second switch 33 disconnects the connection between the negative data pin D-_A and the second terminating impedance R2.

[0030] like Figure 1 As shown, in some embodiments, the control circuit 40 includes a logic controller 41. The logic controller 41 may be a programmable logic controller (PLC). The switching of the state of the switching circuit 30 is controlled by the logic controller 41, and the first transceiver circuit 21 and the second transceiver circuit 23 are actuated by the logic controller 41. For example, during the high-speed handshake phase, the logic controller 41 sends a high-level (e.g., logic level "1") switching signal, the switching circuit 30 responds to the high-level switching signal to switch from the first state to the second state, and the logic controller 41 sends an enable signal to the second transceiver circuit 23 to actuate the second transceiver circuit 23. During the high-speed transmission phase, the logic controller 41 sends a low-level (e.g., logic level "0") switching signal, the switching circuit 30 responds to the low-level switching signal to switch from the second state to the first state, and the logic controller 41 sends an enable signal to the first transceiver circuit 21 to actuate the first transceiver circuit 21.

[0031] Reference Figure 3 This is a signal timing diagram of the handshake procedure in some embodiments of the present invention. First, the USB chip 10 is connected to the USB slave device 100, and the positive data pins D+_B and D+_A are pulled up to a high voltage level (e.g., 3.3V). Figure 3During time period T1), USB chip 10 enters the handshake procedure. Here, since the positive data pin D+_A is connected to the positive data pin D+_B, and the negative data pin D-_A is connected to the negative data pin D-_B, the positive data pins D+_A and D+_B have the same voltage level, and the negative data pins D-_A and D-_B also have the same voltage level. For ease of explanation, in... Figure 3 The timing diagram only depicts the signals of the positive data pin D+_A and the negative data pin D-_A.

[0032] Next, the control circuit 40 of the USB chip 10 generates a reset signal and, in response to the reset signal, resets the positive data pin D+_A and the negative data pin D-_A to a low voltage level (e.g., 0V or practically 0V). Figure 3 The duration of the reset period T2). In some embodiments, the duration (i.e., period T2) of the reset positive data pin D+_A and negative data pin D-_A to a low voltage level is not less than 10 milliseconds (ms). In some embodiments, such as Figure 1 As shown, the control circuit 40 includes a processor 43. The processor 43 is used to generate a reset signal when entering the handshake procedure. The processor 43 may be a central processing unit. In some embodiments, when the positive data pin D+_A and the negative data pin D-_A are reset to a low voltage level (i.e., time period T2), the switching circuit 30 is in a first state. That is, during time period T2, the connection between the positive data pin D+_A and the first terminating impedance circuit 50 is turned on, and the connection between the negative data pin D-_A and the first terminating impedance circuit 50 is also turned on.

[0033] After the positive data pin D+_A and the negative data pin D-_A are reset to a low voltage level, if the USB slave device 100 is in high-speed transmission mode, the USB slave device 100 inputs current (e.g., 17.78 milliamperes (mA)) to the negative data pins D-_B and D-_A through an internal current source (not shown in the figure). This is because the pull-up resistor R connected to the positive data pin D+_B at this time... pu The circuit has not yet been disconnected, therefore the current flows through the first terminating impedance circuit 50 to generate a third voltage signal on the negative data pin D-_A. In other words, the third voltage signal is generated via USB from device 100. The duration of the third voltage signal (e.g., ...) Figure 3The time period T3 shown is 1ms to 7ms, and the voltage level of the third voltage signal is 0.8V. In some embodiments, the third voltage signal is implemented by the chirp state K signal of the USB slave device 100 (hereinafter referred to as the first chirp state K signal). The first chirp state K signal means that the positive data pin D+_A and the negative data pin D-_A are in state K, or the positive data pin D+_B and the negative data pin D-_B are in state K. State K is when the positive data pin D+_A is at a low voltage level (e.g., 0V or substantially 0V) and the negative data pin D-_A is at a high voltage level (e.g., greater than 0V), or the positive data pin D+_B is at a low voltage level and the negative data pin D-_B is at a high voltage level. In some embodiments, when the third voltage signal is generated (i.e., time period T3), the switching circuit 30 is in the first state.

[0034] In some embodiments, after the positive data pin D+_A and the negative data pin D-_A are reset to a low voltage level (i.e., time period T2), if the USB slave device 100 does not have a high-speed transmission mode, the USB slave device 100 does not generate a third voltage signal. If the USB chip 10 does not detect the third voltage signal, it continues the actions in time period T2 until the handshake procedure ends, and after the handshake procedure ends, the USB chip 10 begins full-speed transmission with the USB slave device 100. Similarly, in some embodiments, if the USB chip 10 does not have a high-speed transmission mode, the USB chip 10 ignores the third voltage signal from the USB slave device 100 and continues the actions in time period T2 until the handshake procedure ends. After the handshake procedure ends, the USB chip 10 begins full-speed transmission with the USB slave device 100.

[0035] In some embodiments, such as Figure 3 As shown, during the handshake procedure (e.g., after time period T3), the control circuit 40 generates a switching phase signal HSTXVM to determine whether the operation is in the high-speed handshake phase or the high-speed transmission phase.

[0036] In some embodiments, when the negative data pin D-_A has a third voltage signal from the USB slave device 100, the control circuit 40 generates a switching phase signal indicating a high-speed handshake phase and operates in the high-speed handshake phase. For example, as Figure 1 and Figure 3As shown, when the processor 43 detects the third voltage signal and the USB chip 10 is in high-speed transmission mode, it generates a switching phase signal HSTXVM indicating the high-speed handshake phase T4 to the logic controller 41. The logic controller 41 operates in the high-speed handshake phase T4 in response to the switching phase signal HSTXVM indicating the high-speed handshake phase T4. The switching phase signal HSTXVM can indicate the high-speed handshake phase T4 by being high (e.g., logic level "1").

[0037] In some embodiments, when the USB chip 10 has a high-speed transmission mode, the control circuit 40 generates a switching phase signal HSTXVM indicating the high-speed handshake phase T4 when it detects a third voltage signal and the duration of the third voltage signal (i.e., time period T3) is less than a time threshold. The time threshold can be 100 microseconds (μs) or conform to the USB 2.0 protocol specification. The time threshold can be pre-stored in the processor 43 or input to the processor 43.

[0038] In some embodiments, such as Figure 3 As shown, after entering the high-speed handshake phase T4, the second transceiver circuit 23 alternately transmits a second voltage signal on the positive data pin D+_A and the negative data pin D-_A. In some embodiments, the second voltage level of the second voltage signal is 0.8V. In some embodiments, the second voltage signal transmitted on the negative data pin D-_A is implemented using the chirp state K signal of the second transceiver circuit 23 (hereinafter referred to as the second chirp state K signal), and the second voltage signal transmitted on the positive data pin D+_A is implemented using the chirp state J signal of the second transceiver circuit 23 (hereinafter referred to as the second chirp state J signal). That is, in the high-speed handshake phase T4, the second transceiver circuit 23 transmits a serial signal formed by alternating arrangements of the second chirp state J signal and the second chirp state K signal, for example, in the order of "second chirp state J signal, second chirp state K signal, second chirp state J signal, second chirp state K signal, etc." The second chirp state K signal of the second transceiver circuit 23 is similar to the first chirp state K signal of the USB slave device 100, and therefore will not be described again here. The second chirp state J signal refers to the positive data pin D+_A and the negative data pin D-_A being in state J, or the positive data pin D+_B and the negative data pin D-_B being in state J. State J is when the positive data pin D+_A is at a high voltage level (e.g., greater than 0V) and the negative data pin D-_A is at a low voltage level (e.g., 0V or actually 0V), or the positive data pin D+_B is at a high voltage level and the negative data pin D-_B is at a low voltage level.

[0039] In some embodiments, during the high-speed handshake phase, when the number of times the second voltage signal is transmitted on the positive data pin D+_A and the negative data pin D-_A is not less than a threshold number, the control circuit 40 generates a switching phase signal indicating the high-speed transmission phase and operates in the high-speed transmission phase. An example is given where the second voltage signal transmitted on the negative data pin D-_A is the second chirp state K signal, and the second voltage signal transmitted on the positive data pin D+_A is the second chirp state J signal. Figure 1 and Figure 3 As shown, in the high-speed handshake phase T4, the processor 43 accumulates the number of times the second chirp state J signal and the second chirp state K signal are respectively transmitted. If this number is not less than a threshold number (e.g., the number of times the second chirp state J signal is transmitted is not less than the threshold number and the number of times the second chirp state K signal is transmitted is not less than the threshold number), the processor 43 generates a switching phase signal HSTXVM indicating the high-speed transmission phase T5 to the logic controller 41. The logic controller 41 operates in the high-speed transmission phase T5 in response to the switching phase signal HSTXVM indicating the high-speed transmission phase T5. The switching phase signal HSTXVM can indicate the high-speed transmission phase T5 with a low level (e.g., logic level "0"). In some embodiments, the threshold number is 3 times or conforms to the USB 2.0 protocol specification. In some embodiments, the threshold number is 8 times. In some embodiments, the threshold number can be pre-stored in the processor 43 or input to the processor 43.

[0040] In some embodiments, when the number of times the second chirp state J signal is transmitted (referred to herein as the first number) is the same as the number of times the second chirp state K signal is transmitted (referred to herein as the second number) (i.e., the first number and the second number are the same), the processor 43 begins to compare the first number or the second number with a count threshold to determine whether the first number and the second number are not less than the count threshold. For example, if the count threshold is 8 times, it determines whether one or both of the first number and the second number are not less than 8 times. In some embodiments, the first number and the second number can be added together and then compared with the count threshold to determine whether the summed first number and the second number are not less than the count threshold. For example, if the count threshold is 8 times, the count threshold is first multiplied by 2 to serve as the count threshold for comparison, and then it is determined whether the summed first number and the second number are not less than the count threshold for comparison (i.e., whether the summed first number and the second number are not less than 16 times).

[0041] In some embodiments, such as Figure 3As shown, after entering the high-speed transmission phase T5, the first transceiver circuit 21 alternately transmits a first voltage signal at the positive data pin D+_A and the negative data pin D-_A. In some embodiments, the first voltage level of the first voltage signal is 0.4V. In some embodiments, the first voltage signal transmitted at the negative data pin D-_A is implemented using the chirp state K signal of the first transceiver circuit 21 (hereinafter referred to as the third chirp state K signal), and the first voltage signal transmitted at the positive data pin D+_A is implemented using the chirp state J signal of the first transceiver circuit 21 (hereinafter referred to as the third chirp state J signal). That is, in the high-speed transmission phase T5, the first transceiver circuit 21 transmits a serial signal formed by the alternating arrangement of the third chirp state J signal and the third chirp state K signal, for example, the arrangement order is "third chirp state J signal, third chirp state K signal, third chirp state J signal, third chirp state K signal, etc." The difference between the second chirp state K signal and the second chirp state J signal of the second transceiver circuit 23 is that the voltage level of the third chirp state K signal of the first transceiver circuit 21 is 0.4V, while the voltage level of the second chirp state K signal is 0.8V. The difference between the second chirp state J signal and the second chirp state J signal of the second transceiver circuit 23 is that the voltage level of the third chirp state J signal of the first transceiver circuit 21 is 0.4V, while the voltage level of the second chirp state J signal is 0.8V.

[0042] In some embodiments, such as Figure 1 As shown, the USB chip 10 also includes a detection circuit 80. The detection circuit 80 is connected to the control circuit 40, the positive data pin D+_A, and the negative data pin D-_A. The detection circuit 80 is used to detect the voltage levels on the positive data pin D+_A and the negative data pin D-_A. Figure 3 As shown, after the positive data pin D+_A and the negative data pin D-_A are reset to a low voltage level (i.e., time period T2), when the voltage level on the positive data pin D+_A and the negative data pin D-_A is greater than the voltage threshold, the detection circuit 80 generates a high-level (e.g., logic level "1") detection signal NSQ_HST, and when the voltage level on the positive data pin D+_A and the negative data pin D-_A is not greater than the voltage threshold, the detection circuit 80 generates a low-level (e.g., logic level "0") detection signal NSQ_HST. Based on the level of the detection signal NSQ_HST, the control circuit 40 can determine which stage (time period) of the handshake process is currently in, which stage (time period) of the handshake process to enter, or whether the connection between the USB chip 10 and the USB slave device 100 has been disconnected. In some embodiments, the voltage threshold can be 0.6V. In a preferred embodiment, the voltage threshold can be 0.585V.

[0043] For example, such as Figure 3As shown, in the high-speed handshake phase T4, the detection circuit 80 detects the second voltage level of the second voltage signal on the positive data pin D+_A and the negative data pin D-_A. When the detected second voltage level is not greater than the voltage threshold, the detection circuit 80 sends a low-level detection signal NSQ_HST to indicate that the USB slave device 100 has a high-speed transmission mode and the handshake is successful. At this time, the USB chip 10 can enter the high-speed transmission phase T5. The control circuit 40 responds to the low-level detection signal NSQ_HST and generates a switching phase signal HSTXVM indicating the high-speed transmission phase T5, and operates in the high-speed transmission phase T5. For example, the processor 43 responds to the low-level detection signal NSQ_HST and generates a switching phase signal HSTXVM indicating the high-speed transmission phase T5, so that the logic controller 41 operates in the high-speed transmission phase T5.

[0044] Because the USB 2.0 protocol specification only stipulates that after three sets of serial signals consisting of chirp state J and chirp state K signals appear in the high-speed handshake phase T4 (i.e., three chirp state J signals and three chirp state K signals appear), the high-speed transmission phase T5 must begin within 500μs. Therefore, under the condition of conforming to the protocol specification, in addition to comparing whether the number of times the second voltage signal is sent on the positive data pin D+_A and the negative data pin D-_A is not less than the number threshold, the detection circuit 80 can also detect the second voltage level of the second voltage signal to determine whether to enter the high-speed transmission phase T5.

[0045] In some embodiments, during the high-speed handshake phase, and in preparation for entering the high-speed transmission phase, the second voltage level of the second voltage signal on the positive data pin D+_A and the negative data pin D-_A is pulled down by the second termination impedance circuit 150 of the USB slave device 100 to a level not exceeding a voltage threshold. Specifically, as Figure 1 As shown, when the USB slave device 100 is in high-speed transmission mode and the handshake is successful, the USB slave device 100 disconnects the pull-up resistor R. pu The connection between the positive data pin D+_B and the negative data pin D-_B is established, and the second terminating impedance circuit 150 of the USB slave device 100 is connected to the positive data pin D+_A and the negative data pin D-_A of the USB chip 10. Therefore, the second voltage level of the second voltage signal on the positive data pin D+_A and the negative data pin D-_A is pulled down by the voltage drop of the second terminating impedance circuit 150, preventing it from exceeding a voltage threshold. For example, the second voltage level is pulled down from 0.8V to 0.5V without exceeding the voltage threshold.

[0046] In some embodiments, such as Figure 1As shown, similar to the first terminating impedance circuit 50, the second terminating impedance circuit 150 includes a third terminating impedance R3 and a fourth terminating impedance R4 connected to the positive data pin D+_B and the negative data pin D-_B, respectively. The third terminating impedance R3 and the fourth terminating impedance R4 can be composed of passive components (e.g., resistors, capacitors, inductors). In a preferred embodiment, the third terminating impedance R3 and the fourth terminating impedance R4 are implemented by resistors, for example, both of which have a resistance value of 45Ω. In some embodiments, the first terminating impedance R1, the second terminating impedance R2, the third terminating impedance R3, and the fourth terminating impedance R4 are implemented by resistors and have the same resistance value.

[0047] Reference Figure 4 This is a schematic diagram illustrating the application of the second transceiver circuit 23 in some embodiments of the present invention. For ease of explanation, Figure 4 Only the positive data pin D+_A and its associated circuitry (such as the first switch 31 and the first terminating impedance R1) are depicted, as well as the positive data pin D+_B and its associated circuitry (such as the third terminating impedance R3). From Figure 4 It can be seen that during the high-speed handshake phase, and when preparing to enter the high-speed transmission phase, the second transceiver circuit 23 is connected to the third terminating impedance R3, causing the second voltage level emitted by the second transceiver circuit 23 on the positive data pin D+_A to be pulled down by the third terminating impedance R3 and not exceed the voltage threshold.

[0048] Reference Figure 5 This is a schematic diagram illustrating the application of the first transceiver circuit 21 in some embodiments of the present invention. For ease of explanation, Figure 5 Only the positive data pin D+_A and its associated circuitry (such as the first switch 31 and the first terminating impedance R1) are depicted, as are the positive data pin D+_B and its associated circuitry (such as the third terminating impedance R3). In some embodiments, the first transceiver circuit 21 is a current-driven transceiver circuit. For the sake of brevity, only the first voltage signal on the positive data pin D+_A is described here, such as... Figure 5As shown, the first transceiver circuit 21 has a current source I1 and is driven by the current source I1. The current value of the current source I1 can be 17.78mA. During the high-speed transmission phase, the second terminating impedance circuit 150 is connected in parallel with the first terminating impedance circuit 50 (that is, the third terminating impedance R3 is connected in parallel with the first terminating impedance R1). Assuming that both the third terminating impedance R3 and the first terminating impedance R1 are resistors with a resistance of 45Ω, during the high-speed transmission phase, the first transceiver circuit 21 outputs a first voltage signal with a first voltage level of 0.4V on the positive data pin D+_A based on the current source I1, the first terminating impedance R1, and the third terminating impedance R3. This conforms to the USB 2.0 protocol specification for the voltages of the positive data pin D+_A and the negative data pin D-_A during the high-speed transmission phase. In some embodiments, the current source I1 can be implemented by internal circuitry.

[0049] Refer again Figure 4 In some embodiments, the second transceiver circuit 23 is a voltage-driven transceiver circuit. For the sake of brevity, only the second voltage signal on the positive data pin D+_A will be described here. Due to certain process factors, the operating voltage V DDL The voltage value is limited. For example, the operating voltage V DDL The voltage is limited to 0.8V. The USB 2.0 protocol specification stipulates that the positive data pin D+_A and the negative data pin D-_A are 0.8V during the high-speed handshake phase. However, some circuit designs may cause power loss, resulting in a voltage drop. Therefore, to achieve this without increasing the operating voltage V... DDL Under certain conditions, the second transceiver circuit 23 can be designed to produce no voltage drop or only a slight voltage drop, so that the second voltage level of the second voltage signal of the second transceiver circuit 23 can conform to the specified voltage. For example, compared to a current-driven transceiver circuit, a voltage-driven transceiver circuit is less likely to produce a voltage drop.

[0050] like Figure 4 As shown, the second transceiver circuit 23 is subjected to the operating voltage V DDL Driven. In some embodiments, the second transceiver circuit 23 may consist of an inverter and a transistor for assisting the inverter (referred to herein as an auxiliary transistor). Since the inverter and the auxiliary transistor may produce no voltage drop or only a very small voltage drop, the second transceiver circuit 23 can transmit the operating voltage V DDL It is output as the second voltage signal to the positive data pin D+_A (because during the high-speed handshake phase, the pull-up resistor R connected to the positive data pin D+_B is...). pu(The connection between the first terminating impedance R1 and the positive data pin D+_A is not yet disconnected.) This complies with the USB 2.0 protocol specification for the voltages of the positive data pin D+_A and the negative data pin D-_A during the high-speed handshake phase.

[0051] Reference Figure 6 This is a schematic diagram of a USB chip 10 according to some embodiments of the present invention. In some embodiments, such as Figure 1 As shown, the first terminal impedance circuit 50 is located inside the USB chip 10. In other embodiments, such as Figure 6 As shown, the first terminating impedance circuit 50 is located outside the USB chip 10. The USB chip 10 also includes a connector 200 for the first terminating impedance circuit 50 to connect to. That is, both the connector 200 and the connector 60 are external input / output ports of the USB chip 10.

[0052] In summary, according to some embodiments, by using two transceiver circuits that output different voltage levels, the voltage level of the handshake signal during the high-speed handshake phase and the voltage level of the signal during the high-speed transmission phase can be made to conform to the specification voltage without increasing the operating voltage. In some embodiments, since no additional components (e.g., linear regulators) are required to increase the operating voltage, the available space in the circuit design can be increased. For example, in addition to reducing the overall power consumption of the USB chip by half, the circuit design space can also be increased.

[0053] Explanation of reference numerals in the attached figures:

[0054] 10: USB chip

[0055] 20: High-speed transceiver module

[0056] 21: First transceiver circuit

[0057] 23: Second transceiver circuit

[0058] 30: Switching circuit

[0059] 31: First Switch

[0060] 33: Second Switch

[0061] 40: Control Circuit

[0062] 41: Logic Controller

[0063] 43: Processor

[0064] 50: First terminating impedance circuit

[0065] R1: First terminating impedance

[0066] R2: Second terminating impedance

[0067] 60: Connector

[0068] D+_A: Positive data pin

[0069] D-_A: Negative data pin

[0070] V Bus _A: Power supply conversion pin

[0071] GND_A: Ground pin

[0072] 70: Power Management Circuit

[0073] 80: Detection circuit

[0074] 90: Low-speed full-speed transceiver module

[0075] 200: Connection end

[0076] 100: USB slave device

[0077] 120: High-speed transceiver module

[0078] 150: Second terminal impedance circuit

[0079] R3: Third terminating impedance

[0080] R4: Fourth terminating impedance

[0081] 160: Connector

[0082] D+_B: Positive data pin

[0083] D-_B: Negative data pin

[0084] V Bus _B: Power supply conversion pin

[0085] GND_B: Ground pin

[0086] 170: Power Management Circuit

[0087] 190: Low-speed full-speed transceiver module

[0088] R pu Pull-up resistor

[0089] S201~S207: Steps

[0090] T1~T3: Time period

[0091] T4: High-speed handshake phase

[0092] T5: High-speed transmission stage

[0093] HSTXVM: Switching Phase Signal

[0094] NSQ_HST: Detection signal

[0095] I1: Current source

[0096] V DDL Operating voltage

Claims

1. A USB chip, comprising: Positive data pin; Negative data pin; The first transceiver circuit is configured to alternately transmit a first voltage signal via the positive data pin and the negative data pin when actuated. The second transceiver circuit is configured to, when actuated, alternately transmit a second voltage signal via the positive data pin and the negative data pin, wherein the second voltage level of the second voltage signal is greater than the first voltage level of the first voltage signal. A switching circuit is used to, in a first state, connect the positive data pin to the first terminal impedance circuit and connect the negative data pin to the first terminal impedance circuit; in a second state, the switching circuit disconnects the positive data pin from the first terminal impedance circuit and disconnects the negative data pin from the first terminal impedance circuit. as well as Control circuit, used to During the high-speed handshake phase, the switching circuit is controlled to the second state; When the switching circuit is controlled to the second state, the second transceiver circuit is actuated; During the high-speed transmission phase, the switching circuit is controlled to be in the first state; as well as When the switching circuit is controlled to the first state, the first transceiver circuit is actuated.

2. The USB chip of claim 1, wherein, The control circuit generates a switching phase signal to determine whether it is operating in the high-speed handshake phase or the high-speed transmission phase.

3. The USB chip of claim 2, wherein, When the negative data pin has a third voltage signal from the USB slave device, and the duration of the third voltage signal is less than a time threshold, the control circuit generates the switching phase signal indicating the high-speed handshake phase and operates in the high-speed handshake phase.

4. The USB chip of claim 2, wherein, When the second voltage signal is transmitted to the positive data pin and the negative data pin a number of times that number of transmissions is not less than a threshold, the control circuit generates a switching phase signal indicating the high-speed transmission phase and operates in the high-speed transmission phase.

5. The USB chip of claim 2, further comprising a detection circuit connected to the control circuit, the positive data pin and the negative data pin, the detection circuit configured to detect the second voltage level of the second voltage signal on the positive data pin and the negative data pin, wherein, When the detected second voltage level is not greater than a voltage threshold, the control circuit generates a switching phase signal indicating the high-speed transmission phase and operates in the high-speed transmission phase, wherein the second voltage level of the second voltage signal on the positive data pin and the negative data pin is pulled down by the second termination impedance circuit of the USB slave device and is not greater than the voltage threshold.

6. The USB chip of claim 1, wherein, The first transceiver circuit is a current-driven transceiver circuit, and the second transceiver circuit is a voltage-driven transceiver circuit.

7. The USB chip of claim 1, wherein, When the switching circuit is controlled to the first state, the control circuit also disables the second transceiver circuit.

8. The USB chip as described in claim 1, wherein, When the switching circuit is controlled to the second state, the control circuit also disables the first transceiver circuit.

9. The USB chip of claim 1, wherein, The first terminal impedance circuit is located inside the USB chip.

10. A method of operating a USB chip, wherein, The USB chip includes a positive data pin, a negative data pin, a first transceiver circuit, a second transceiver circuit, a switching circuit, and a control circuit. The operation method includes: During the high-speed handshake phase, the control circuit controls the switching circuit to the second state; When the switching circuit is controlled to the second state, the second transceiver circuit is actuated; During the high-speed transmission phase, the switching circuit is controlled to be in the first state; as well as When the switching circuit is controlled to the first state, the first transceiver circuit is actuated; In the first state, the switching circuit connects the positive data pin to the first terminal impedance circuit and connects the negative data pin to the first terminal impedance circuit. In the second state, the switching circuit disconnects the positive data pin from the first terminal impedance circuit and disconnects the negative data pin from the first terminal impedance circuit. When the first transceiver circuit is activated, it alternately transmits a first voltage signal via the positive data pin and the negative data pin. When the second transceiver circuit is activated, it alternately transmits a second voltage signal via the positive data pin and the negative data pin, wherein the second voltage level of the second voltage signal is greater than the first voltage level of the first voltage signal.

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