Low Dropout Linear Regulator
By using two bias voltage generation circuits and a capacitor coupling method in a low-dropout linear regulator, the chip area problem caused by a large internal compensation capacitor value is solved, and the stability and area of the regulator are balanced.
Patent Information
- Application Number
- CN202310186692.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-02-21
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2043-02-21
AI Technical Summary
In existing low-dropout linear regulators, the capacitance of the internal compensation capacitor is relatively large, which occupies a large chip area and is difficult to reduce without affecting stability.
Two bias voltage generating circuits are used to provide bias voltages for the two load circuits of the error amplifier respectively, and a first capacitor is coupled between the output voltage terminal and the input terminal of the second load circuit to reduce the AC variation transmitted to the first load circuit, and the equivalent compensation capacitance is increased by utilizing the amplification effect of the current variation.
The internal compensation capacitor value is significantly reduced without affecting the stability, reducing the chip area while ensuring the normal operation of the low-dropout linear regulator.
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Figure CN116501117B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a low-dropout linear regulator. Background Art
[0002] A low dropout regulator (LDO) generates a regulated output voltage to power a chip. LDO circuits are widely used in power management chips to power internal circuits. Traditional LDO circuits use internal compensation capacitors to ensure stability. The larger the capacitance of these internal compensation capacitors, the larger the chip area they occupy. Therefore, it is desirable to minimize the capacitance of these internal compensation capacitors without compromising the stability of the LDO circuit. Summary of the Invention
[0003] Embodiments described herein provide a low dropout linear regulator.
[0004] According to a first aspect of the present disclosure, a low-voltage dropout linear regulator is provided. The low-voltage dropout linear regulator includes a first bias voltage generating circuit, a second bias voltage generating circuit, an error amplifier, an output power transistor, a feedback circuit, and a first capacitor. The first bias voltage generating circuit is configured to generate a first bias voltage and provide the first bias voltage to a first load circuit in the error amplifier via a first node. The second bias voltage generating circuit is configured to generate a second bias voltage and provide the second bias voltage to a second load circuit in the error amplifier via a second node. The error amplifier is configured to generate an error voltage based on a reference voltage from a reference voltage terminal and a feedback voltage from a feedback circuit, and provide the error voltage to a control terminal of the output power transistor. A first terminal of the output power transistor is coupled to an input voltage terminal. A second terminal of the output power transistor is coupled to an output voltage terminal. The feedback circuit is configured to divide the output voltage of the low-voltage dropout linear regulator to generate a feedback voltage. A first terminal of the first capacitor is coupled to the output voltage terminal. A second terminal of the first capacitor is coupled to a second node.
[0005] In some embodiments of the present disclosure, an error amplifier includes: a first constant current source, a differential input circuit, a first load circuit, a second load circuit, and an error voltage generating circuit. The differential input circuit is configured to generate a first shunt and a second shunt based on a reference voltage, a feedback voltage, and a first constant current from the first constant current source, output the first shunt via a third node, and output the second shunt via a fourth node. The sum of the first shunt and the second shunt is equal to the first constant current. The ratio of the first shunt to the second shunt is inversely proportional to the voltage difference between the reference voltage and the feedback voltage. The first load circuit is configured to generate a first load current based on the voltage at the first node and output the first load current via the third node. The second load circuit is configured to generate a second load current based on the voltage at the second node and output the second load current via the fourth node. The error voltage generating circuit is configured to generate an error voltage based on the voltage at the third node and the voltage at the fourth node.
[0006] In some embodiments of the present disclosure, a differential input circuit includes: a first transistor and a second transistor. The control electrode of the first transistor is coupled to a reference voltage terminal. The first electrode of the first transistor is coupled to the first electrode of the second transistor and a first constant current source. The second electrode of the first transistor is coupled to a third node. The control electrode of the second transistor is coupled to a feedback circuit. The second electrode of the second transistor is coupled to a fourth node.
[0007] In some embodiments of the present disclosure, the first load circuit includes a third transistor, wherein a control electrode of the third transistor is coupled to the first node, and a first electrode of the third transistor is coupled to the second voltage terminal.
[0008] The second electrode of the third transistor is coupled to the third node.
[0009] In some embodiments of the present disclosure, the second load circuit includes a fourth transistor, wherein a control electrode of the fourth transistor is coupled to the second node, and a first electrode of the fourth transistor is coupled to the second voltage terminal.
[0010] The second electrode of the fourth transistor is coupled to the fourth node.
[0011] In some embodiments of the present disclosure, the error voltage generating circuit includes: fifth to tenth transistors. The control electrode of the fifth transistor is coupled to the third bias voltage terminal. The first electrode of the fifth transistor is coupled to the fourth node. The second electrode of the fifth transistor is coupled to the first electrode of the seventh transistor. The control electrode of the sixth transistor is coupled to the third bias voltage terminal. The first electrode of the sixth transistor is coupled to the third node. The second electrode of the sixth transistor is coupled to the first electrode of the eighth transistor. The control electrode of the seventh transistor is coupled to the first voltage terminal. The second electrode of the seventh transistor is coupled to the control electrode and the second electrode of the ninth transistor and the control electrode of the tenth transistor. The control electrode of the eighth transistor is coupled to the first voltage terminal. The second electrode of the eighth transistor is coupled to the second electrode of the tenth transistor and the control electrode of the output power transistor. The first electrode of the ninth transistor is coupled to the input voltage terminal and the first electrode of the tenth transistor.
[0012] In some embodiments of the present disclosure, a first bias voltage generating circuit includes: an eleventh transistor, a twelfth transistor, and a first resistor. A first end of the first resistor is coupled to a first reference current source and a control electrode of the eleventh transistor. A second end of the first resistor is coupled to a second electrode of the eleventh transistor, a control electrode of the twelfth transistor, and a first node. A first electrode of the eleventh transistor is coupled to a second electrode of the twelfth transistor. A first electrode of the twelfth transistor is coupled to a second voltage terminal.
[0013] In some embodiments of the present disclosure, the second bias voltage generating circuit includes: a thirteenth transistor, a fourteenth transistor, and a second resistor. A first end of the second resistor is coupled to a second reference current source and a control electrode of the thirteenth transistor. A second end of the second resistor is coupled to a second electrode of the thirteenth transistor, a control electrode of the fourteenth transistor, and a second node. A first electrode of the thirteenth transistor is coupled to a second electrode of the fourteenth transistor. A first electrode of the fourteenth transistor is coupled to a second voltage terminal.
[0014] In some embodiments of the present disclosure, the ratio of the width to length of the fourteenth transistor to the fourth transistor is 1:K. The ratio of the width to length of the twelfth transistor to the third transistor is 1:K. The ratio of the width to length of the fourteenth transistor to the twelfth transistor is 1:1. K is greater than 1.
[0015] In some embodiments of the present disclosure, the feedback circuit includes a third resistor and a fourth resistor. A first end of the third resistor is coupled to a first end of the fourth resistor and an output terminal of the feedback circuit. A second end of the third resistor is coupled to the output voltage terminal. A second end of the fourth resistor is coupled to the second voltage terminal.
[0016] In some embodiments of the present disclosure, the low voltage dropout linear regulator further includes a protection circuit configured to limit the voltage difference between the control electrode and the first electrode of the output power tube.
[0017] In some embodiments of the present disclosure, the protection circuit includes a fifteenth transistor and a sixteenth transistor. The control electrode of the fifteenth transistor is coupled to the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor. The first electrode of the fifteenth transistor is coupled to the input voltage terminal. The control electrode of the sixteenth transistor is coupled to the second electrode of the sixteenth transistor and the control electrode of the output power transistor.
[0018] In some embodiments of the present disclosure, the protection circuit further includes a voltage regulator diode, wherein the anode of the voltage regulator diode is coupled to the control electrode of the output power tube, and the cathode of the voltage regulator diode is coupled to the input voltage terminal.
[0019] According to a second aspect of the present disclosure, a low-voltage-dropout linear regulator is provided. The low-voltage-dropout linear regulator includes an output power transistor, first to sixteenth transistors, a first capacitor, first to fourth resistors, and a first constant current source. The control electrode of the first transistor is coupled to a reference voltage terminal. The first electrode of the first transistor is coupled to the first electrode of the second transistor and the first constant current source. The second electrode of the first transistor is coupled to the second electrode of the third transistor and the first electrode of the sixth transistor. The control electrode of the second transistor is coupled to the first terminal of the third resistor and the first terminal of the fourth resistor. The second electrode of the second transistor is coupled to the second electrode of the fourth transistor and the first electrode of the fifth transistor. The control electrode of the third transistor is coupled to the second electrode of the eleventh transistor and the control electrode of the twelfth transistor. The first electrode of the third transistor is coupled to the second voltage terminal. The control electrode of the fourth transistor is coupled to the second electrode of the thirteenth transistor and the control electrode of the fourteenth transistor. The first electrode of the fourth transistor is coupled to the second voltage terminal. The control electrode of the fifth transistor is coupled to the third bias voltage terminal. The second electrode of the fifth transistor is coupled to the first electrode of the seventh transistor. The control electrode of the sixth transistor is coupled to the third bias voltage terminal. The second electrode of the sixth transistor is coupled to the first electrode of the eighth transistor. The control electrode of the seventh transistor is coupled to the first voltage terminal. The second electrode of the seventh transistor is coupled to the control electrode and the second electrode of the ninth transistor and the control electrode of the tenth transistor. The control electrode of the eighth transistor is coupled to the first voltage terminal. The second electrode of the eighth transistor is coupled to the second electrode of the tenth transistor and the control electrode of the output power transistor. The first electrode of the ninth transistor is coupled to the input voltage terminal and the first electrode of the tenth transistor. The first end of the first resistor is coupled to the first reference current source and the control electrode of the eleventh transistor. The second end of the first resistor is coupled to the second electrode of the eleventh transistor. The first electrode of the eleventh transistor is coupled to the second electrode of the twelfth transistor. The first electrode of the twelfth transistor is coupled to the second voltage terminal. The first end of the second resistor is coupled to the second reference current source and the control electrode of the thirteenth transistor. The second end of the second resistor is coupled to the second electrode of the thirteenth transistor. The first electrode of the thirteenth transistor is coupled to the second electrode of the fourteenth transistor. The first electrode of the fourteenth transistor is coupled to the second voltage terminal. The first electrode of the output power transistor is coupled to the input voltage terminal. The second electrode of the output power transistor is coupled to the output voltage terminal and the second end of the third resistor. The second end of the fourth resistor is coupled to the second voltage terminal. The control electrode of the fifteenth transistor is coupled to the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor. The first electrode of the fifteenth transistor is coupled to the input voltage terminal. The control electrode of the sixteenth transistor is coupled to the second electrode of the sixteenth transistor and the control electrode of the output power transistor. The first end of the first capacitor is coupled to the output voltage terminal. The second end of the first capacitor is coupled to the control electrode of the fourth transistor.
[0020] In some embodiments of the present disclosure, the ratio of the width to length of the fourteenth transistor to the fourth transistor is 1:K. The ratio of the width to length of the twelfth transistor to the third transistor is 1:K. The ratio of the width to length of the fourteenth transistor to the twelfth transistor is 1:1. K is greater than 1.
[0021] In some embodiments of the present disclosure, the low voltage drop linear regulator further includes a Zener diode, wherein the anode of the Zener diode is coupled to the control electrode of the output power tube, and the cathode of the Zener diode is coupled to the input voltage terminal.
[0022] According to a third aspect of the present disclosure, a chip is provided, which includes the low-dropout linear regulator according to the first aspect or the second aspect of the present disclosure.
[0023] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising the chip according to the third aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.
[0025] Figure 1 is an exemplary circuit diagram of a low dropout linear regulator;
[0026] Figure 2 is a schematic block diagram of a low dropout linear regulator according to an embodiment of the present disclosure;
[0027] Figure 3 is an exemplary circuit diagram of a low dropout linear regulator according to an embodiment of the present disclosure; and
[0028] Figure 4 is another exemplary circuit diagram of a low dropout linear regulator according to an embodiment of the present disclosure.
[0029] In the drawings, reference numerals having the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION
[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.
[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.
[0032] In all embodiments of the present disclosure, since the source and drain of the metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of the N-type transistor and the P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the MOS transistor is referred to as the control electrode, and the other two ends of the MOS transistor are referred to as the first electrode and the second electrode, respectively. In addition, for the convenience of unified expression, in this context, the base of the bipolar transistor (BJT) is referred to as the control electrode, the emitter of the BJT is referred to as the first electrode, and the collector of the BJT is referred to as the second electrode. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).
[0033] Figure 1 An exemplary circuit diagram of a low voltage drop linear regulator is shown. The low voltage drop linear regulator 100 includes: an error amplifier 110, an output power tube Mout, a resistor Rf1, a resistor Rf2, and a Miller capacitor Cc. The error amplifier 110 includes a current source I1 and a first transistor M1 to a tenth transistor M10. Figure 1 In the example, vdda represents the power supply of the error amplifier 110, vssa represents the ground potential, AVCC represents the input voltage of the low-voltage dropout linear regulator 100, and Vreg represents the output voltage of the low-voltage dropout linear regulator 100. The control electrodes of the fifth transistor M5 and the sixth transistor M6 are coupled to the third bias voltage terminal Vb3. The control electrodes of the third transistor M3 and the fourth transistor M4 are coupled to the fourth bias voltage terminal Vb4. Figure 1 An external load current source Iload and an external load capacitor Cload are also shown in the example.
[0034] The low-dropout linear regulator 100 has two poles: one at the control electrode of the output power transistor Mout, and the other at the second electrode of the output power transistor Mout. A Miller capacitor Cc couples the output voltage terminal (i.e., the second electrode of the output power transistor Mout) to the second electrode of the third transistor M3. The placement of the Miller capacitor Cc (as an internal compensation capacitor) in the low-dropout linear regulator 100 isolates these two poles from each other in the frequency domain, thereby maintaining a stable output voltage Vreg.
[0035] The equivalent capacitance of the Miller capacitor Cc can be calculated as: req1 =gm_out×ro×Cc. Where gm_out represents the transconductance of the output power tube Mout, ro represents the equivalent output resistance value at the output voltage end, and Cc represents the capacitance value of the Miller capacitor Cc.
[0036] The capacitance of the Miller capacitor Cc is generally large. If the capacitance of the Miller capacitor Cc can be reduced without affecting the stability of the output voltage Vreg, the chip area of the low-dropout linear regulator can be reduced.
[0037] The embodiments of the present disclosure provide a low voltage dropout linear regulator, which can significantly reduce the internal compensation capacitance (capacitance of the Miller capacitor) while ensuring the stability and normal operation of the low voltage dropout linear regulator. Figure 2 A schematic block diagram of a low-dropout linear regulator 200 according to an embodiment of the present disclosure is shown. The low-dropout linear regulator 200 includes: a first bias voltage generating circuit 220, a second bias voltage generating circuit 230, an error amplifier 210, an output power transistor Mout, a feedback circuit 240, and a first capacitor Cc.
[0038] The first bias voltage generating circuit 220 is coupled to the first load circuit (at the Figure 2 (not shown). The first bias voltage generating circuit 220 is configured to generate a first bias voltage and provide the first bias voltage to the first load circuit in the error amplifier 210 via the first node N1. In some embodiments of the present disclosure, the first bias voltage generating circuit 220 may generate the first bias voltage based on the first reference current Iref1.
[0039] The second bias voltage generating circuit 230 is coupled to the second load circuit (at the second node N2) in the error amplifier 210. Figure 2(not shown). The second bias voltage generating circuit 230 is configured to generate a second bias voltage and provide the second bias voltage to the second load circuit in the error amplifier 210 via the second node N2. In some embodiments of the present disclosure, the second bias voltage generating circuit 230 may generate the second bias voltage based on the second reference current Iref2.
[0040] The error amplifier 210 is coupled to the first bias voltage generating circuit 220 via a first node N1. The error amplifier 210 is coupled to the second bias voltage generating circuit 230 via a second node N2. The error amplifier 210 is configured to generate an error voltage based on a reference voltage Vref from a reference voltage terminal and a feedback voltage Vfb from a feedback circuit 240, and provide the error voltage to the control electrode of the output power transistor Mout.
[0041] The control electrode of the output power transistor Mout is coupled to the output terminal of the error amplifier 210. The first electrode of the output power transistor Mout is coupled to the input voltage terminal AVCC. The second electrode of the output power transistor Mout is coupled to the output voltage terminal. The low voltage drop linear regulator 200 outputs the output voltage Vreg from the output voltage terminal.
[0042] The feedback circuit 240 is coupled to the output voltage terminal and the error amplifier 210. The feedback circuit 240 is configured to divide the output voltage Vreg of the low dropout linear regulator 200 to generate a feedback voltage Vfb.
[0043] A first terminal of the first capacitor Cc (also referred to as a Miller capacitor or a compensation capacitor) is coupled to the output voltage terminal, and a second terminal of the first capacitor Cc is coupled to the second node N2 (ie, the output terminal of the second bias voltage generating circuit 230 ).
[0044] According to the embodiment of the present disclosure, the low-voltage difference linear regulator 200 uses two bias voltage generating circuits (a first bias voltage generating circuit 220 and a second bias voltage generating circuit 230) to provide bias voltages for the two load circuits in the error amplifier 210 respectively and couples the first capacitor Cc between the output voltage terminal and the input terminal of the second load circuit (the output terminal of the second bias voltage generating circuit 230). In this way, the AC variation of the output voltage Vreg is only transmitted to the second load circuit and not to the first load circuit. The second load circuit can amplify the AC variation of the output voltage Vreg, thereby amplifying the current variation at the control electrode of the output power tube Mout. The equivalent capacitance value of the first capacitor Cc can be calculated as: C req2=K×gm_out×ro×Cc. Where gm_out represents the transconductance of the output power tube Mout, ro represents the equivalent output resistance value at the output voltage terminal, Cc represents the capacitance value of the first capacitor Cc, and K represents the amplification factor of the current change at the control electrode of the output power tube Mout. K is greater than 1. In this way, the equivalent compensation capacitance of the first capacitor Cc becomes K times larger. Therefore, Figure 1 Compared with the example of FIG. 1 , when the equivalent compensation capacitance is equal, the capacitance value of the first capacitor Cc can be reduced, thereby reducing the area of the low voltage drop linear regulator 200.
[0045] Figure 3 FIG. 1 shows an exemplary circuit diagram of a low voltage dropout linear regulator 300 according to an embodiment of the present disclosure. Figure 3 An external load current source Iload and an external load capacitor Cload are also shown in the example.
[0046] exist Figure 3 In the low-dropout linear regulator 300 shown, the error amplifier 310 includes a first constant current source I1 , a differential input circuit 311 , a first load circuit 312 , a second load circuit 313 , and an error voltage generating circuit 314 .
[0047] The first constant current source I1 may be coupled to the first voltage terminal V1 and configured to output a first constant current I1 .
[0048] The differential input circuit 311 is coupled to the first constant current source I1, a reference voltage terminal, and the output terminal of the feedback circuit 340. The differential input circuit 311 is coupled to the first load circuit 312 and the error voltage generating circuit 314 via a third node N3. The differential input circuit 311 is coupled to the second load circuit 313 and the error voltage generating circuit 314 via a fourth node N4. The differential input circuit 311 is configured to generate a first shunt Is1 and a second shunt Is2 based on the reference voltage Vref, the feedback voltage Vfb, and the first constant current I1 from the first constant current source I1, output the first shunt Is1 via the third node N3, and output the second shunt Is2 via the fourth node N4. The sum of the first shunt Is1 and the second shunt Is2 equals the first constant current I1. The ratio of the first shunt Is1 to the second shunt Is2 is inversely proportional to the voltage difference between the reference voltage Vref and the feedback voltage Vfb. When the voltage difference between the reference voltage Vref and the feedback voltage Vfb increases, the ratio of the first shunt Is1 to the second shunt Is2 decreases, so the first shunt Is1 decreases and the second shunt Is2 increases. When the voltage difference between the reference voltage Vref and the feedback voltage Vfb decreases, the ratio of the first shunt Is1 to the second shunt Is2 increases, so the first shunt Is1 increases and the second shunt Is2 decreases.
[0049] The first load circuit 312 is coupled to the first bias voltage generating circuit 320 via the first node N1. The first load circuit 312 is coupled to the differential input circuit 311 and the error voltage generating circuit 314 via the third node N3. The first load circuit 312 is configured to generate a first load current according to the voltage at the first node N1 and output the first load current via the third node N3.
[0050] The second load circuit 313 is coupled to the second bias voltage generating circuit 330 via the second node N2. The second load circuit 313 is coupled to the differential input circuit 311 and the error voltage generating circuit 314 via the fourth node N4. The second load circuit 313 is configured to generate a second load current according to the voltage at the second node N2 and output the second load current via the fourth node N4.
[0051] The error voltage generating circuit 314 is coupled to the differential input circuit 311 and the first load circuit 312 via a third node N3. The error voltage generating circuit 314 is coupled to the differential input circuit 311 and the second load circuit 313 via a fourth node N4. The error voltage generating circuit 314 is configured to generate an error voltage based on the voltage at the third node N3 and the voltage at the fourth node N4. The voltage at the third node N3 is determined by the first shunt current Is1 and the first load current. The voltage at the fourth node N4 is determined by the second shunt current Is2 and the second load current.
[0052] In some embodiments of the present disclosure, the error voltage is equivalent to an amplified value of the voltage difference between the reference voltage Vref and the feedback voltage Vfb.
[0053] exist Figure 3 In the example, the differential input circuit 311 includes a first transistor M1 and a second transistor M2. The control electrode of the first transistor M1 is coupled to the reference voltage terminal. The first electrode of the first transistor M1 is coupled to the first electrode of the second transistor M2 and the first constant current source I1. The second electrode of the first transistor M1 is coupled to the third node N3. The control electrode of the second transistor M2 is coupled to the feedback circuit 340. The second electrode of the second transistor M2 is coupled to the fourth node N4.
[0054] The first load circuit 312 includes a third transistor M3 , wherein a control electrode of the third transistor M3 is coupled to the first node N1 , a first electrode of the third transistor M3 is coupled to the second voltage terminal V2 , and a second electrode of the third transistor M3 is coupled to the third node N3 .
[0055] The second load circuit 313 includes a fourth transistor M4 , wherein a control electrode of the fourth transistor M4 is coupled to the second node N2 , a first electrode of the fourth transistor M4 is coupled to the second voltage terminal V2 , and a second electrode of the fourth transistor M4 is coupled to the fourth node N4 .
[0056] The error voltage generating circuit 314 includes: fifth to tenth transistors M5, M10. A control electrode of the fifth transistor M5 is coupled to the third bias voltage terminal Vb3. A first electrode of the fifth transistor M5 is coupled to the fourth node N4. A second electrode of the fifth transistor M5 is coupled to the first electrode of the seventh transistor M7. A control electrode of the sixth transistor M6 is coupled to the third bias voltage terminal Vb3. A first electrode of the sixth transistor M6 is coupled to the third node N3. A second electrode of the sixth transistor M6 is coupled to the first electrode of the eighth transistor M8. A control electrode of the seventh transistor M7 is coupled to the first voltage terminal V1. A second electrode of the seventh transistor M7 is coupled to the control electrode and second electrode of the ninth transistor M9 and the control electrode of the tenth transistor M10. A control electrode of the eighth transistor M8 is coupled to the first voltage terminal V1. A second electrode of the eighth transistor M8 is coupled to the second electrode of the tenth transistor M10 and the control electrode of the output power transistor Mout. A first electrode of the ninth transistor M9 is coupled to the input voltage terminal AVCC and the first electrode of the tenth transistor M10.
[0057] The first bias voltage generating circuit 320 includes an eleventh transistor M11, a twelfth transistor M12, and a first resistor R1. A first end of the first resistor R1 is coupled to a first reference current source Iref1 and the control electrode of the eleventh transistor M11. A second end of the first resistor R1 is coupled to the second electrode of the eleventh transistor M11, the control electrode of the twelfth transistor M12, and a first node N1. A first electrode of the eleventh transistor M11 is coupled to the second electrode of the twelfth transistor M12. A first electrode of the twelfth transistor M12 is coupled to the second voltage terminal V2.
[0058] The second bias voltage generating circuit 330 includes a thirteenth transistor M13, a fourteenth transistor M14, and a second resistor R2. A first end of the second resistor R2 is coupled to the second reference current source Iref2 and the control electrode of the thirteenth transistor M13. A second end of the second resistor R2 is coupled to the second electrode of the thirteenth transistor M13, the control electrode of the fourteenth transistor M14, and a second node N2. A first electrode of the thirteenth transistor M13 is coupled to the second electrode of the fourteenth transistor M14. A first electrode of the fourteenth transistor M14 is coupled to the second voltage terminal V2.
[0059] Feedback circuit 340 includes a third resistor R3 and a fourth resistor R4. A first end of the third resistor R3 is coupled to a first end of the fourth resistor R4 and to the output terminal of feedback circuit 340. A second end of the third resistor R3 is coupled to the output voltage terminal. A second end of the fourth resistor R4 is coupled to the second voltage terminal V2. In one example, R3:R4 = 13:4, where R3 represents the resistance value of the third resistor R3, and R4 represents the resistance value of the fourth resistor R4.
[0060] exist Figure 3In the example, the fourteenth transistor M14 and the fourth transistor M4 can form a current mirror. The twelfth transistor M12 and the third transistor M3 can form a current mirror. The width-to-length ratio of the fourteenth transistor M14 to the fourth transistor M4 can be set to 1:K, the width-to-length ratio of the twelfth transistor M12 to the third transistor M3 can be set to 1:K, and the width-to-length ratio of the fourteenth transistor M14 to the twelfth transistor M12 can be set to 1:1. K is greater than 1. In this way, the equivalent capacitance value of the first capacitor Cc can be calculated as: C req2 =K×gm_out×ro×Cc. Where gm_out represents the transconductance of the output power tube Mout, ro represents the equivalent output resistance value of the output voltage terminal, and Cc represents the capacitance value of the first capacitor Cc. Therefore, Figure 1 Compared with the example of FIG. 3 , when the equivalent compensation capacitance is equal, the capacitance value of the first capacitor Cc can be reduced, thereby reducing the area of the low voltage drop linear regulator 300.
[0061] It should be understood by those skilled in the art that Figure 3 The internal structures of the error amplifier 310, the first bias voltage generating circuit 320, the second bias voltage generating circuit 330, and the feedback circuit 340 are exemplary. The error amplifier 310, the first bias voltage generating circuit 320, the second bias voltage generating circuit 330, and the feedback circuit 340 may also be implemented by other circuits. The embodiments of the present disclosure do not limit the specific implementation of the error amplifier 310, the first bias voltage generating circuit 320, the second bias voltage generating circuit 330, and the feedback circuit 340.
[0062] Figure 4 FIG. 4 shows another exemplary circuit diagram of a low voltage dropout linear regulator 400 according to an embodiment of the present disclosure. Figure 3 Based on the low-voltage dropout linear regulator 300 shown, the low-voltage dropout linear regulator 400 further includes a protection circuit 450. The protection circuit 450 is coupled to the control electrode and the first electrode of the output power transistor Mout. The protection circuit 450 is configured to limit the voltage difference between the control electrode and the first electrode of the output power transistor Mout.
[0063] In some embodiments of the present disclosure, the protection circuit 450 includes a fifteenth transistor M15 and a sixteenth transistor M16. The control electrode of the fifteenth transistor M15 is coupled to the second electrode of the fifteenth transistor M15 and the first electrode of the sixteenth transistor M16. The first electrode of the fifteenth transistor M15 is coupled to the input voltage terminal AVCC. The control electrode of the sixteenth transistor M16 is coupled to the second electrode of the sixteenth transistor M16 and the control electrode of the output power transistor Mout.
[0064] In some embodiments of the present disclosure, the protection circuit 450 further includes a voltage regulator diode Z1 , wherein the anode of the voltage regulator diode Z1 is coupled to the control electrode of the output power transistor Mout, and the cathode of the voltage regulator diode Z1 is coupled to the input voltage terminal AVCC. Figure 4 An exemplary circuit diagram showing that the protection circuit 450 includes a fifteenth transistor M15, a sixteenth transistor M16, and a Zener diode Z1.
[0065] In the case of a transient increase in the input voltage, the protection circuit 450 can prevent the gate oxide of the output power transistor Mout from being broken down.
[0066] exist Figure 3 and Figure 4 In the example, a high voltage signal is input from the first voltage terminal V1V1, and the second voltage terminal V2 is grounded. The first transistor M1, the second transistor M2, the ninth transistor M9, and the tenth transistor M10 are PMOS transistors. The third transistor M3 to the eighth transistor M8, the eleventh transistor M11 to the sixteenth transistor M16 are NMOS transistors. The seventh transistor M7, the eighth transistor M8, and the output power transistor Mout are high voltage transistors. Those skilled in the art should understand that based on the above inventive concept, Figure 3 and Figure 4 The variation of the circuit shown should also fall within the scope of protection of the present disclosure. In this variation, the above-mentioned transistor and voltage terminal may also have the same Figure 3 and Figure 4 Examples of different setups are shown.
[0067] The embodiments of the present disclosure further provide a chip. The chip includes a low voltage dropout linear regulator according to the embodiments of the present disclosure. The chip is, for example, a power management chip.
[0068] An embodiment of the present disclosure further provides an electronic device. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is, for example, a smart terminal device such as a tablet computer, a smart phone, etc.
[0069] In summary, the low-dropout linear regulator according to the embodiments of the present disclosure can significantly reduce the internal compensation capacitance while ensuring the stability and normal operation of the low-dropout linear regulator. Therefore, the area of the chip including the low-dropout linear regulator according to the embodiments of the present disclosure can be significantly reduced.
[0070] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.
[0071] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.
[0072] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.
Claims
1. A low-dropout linear regulator, comprising: a first bias voltage generating circuit, a second bias voltage generating circuit, an error amplifier, an output power tube, a feedback circuit, and a first capacitor; The first bias voltage generating circuit is configured to: generate a first bias voltage, and provide the first bias voltage to a first load circuit in the error amplifier via a first node; The second bias voltage generating circuit is configured to: generate a second bias voltage, and provide the second bias voltage to a second load circuit in the error amplifier via a second node; The error amplifier is configured to: generate an error voltage according to a reference voltage from a reference voltage terminal and a feedback voltage from the feedback circuit, and provide the error voltage to a control electrode of the output power transistor; The first electrode of the output power tube is coupled to the input voltage terminal, and the second electrode of the output power tube is coupled to the output voltage terminal; The feedback circuit is configured to: divide the output voltage of the low-dropout linear regulator to generate the feedback voltage; A first terminal of the first capacitor is coupled to the output voltage terminal, and a second terminal of the first capacitor is coupled to the second node.
2. The low-dropout linear regulator according to claim 1, wherein: The error amplifier includes: a first constant current source, a differential input circuit, a first load circuit, a second load circuit, and an error voltage generating circuit. The differential input circuit is configured to generate a first shunt and a second shunt according to the reference voltage, the feedback voltage, and a first constant current from a first constant current source, output the first shunt via a third node, and output the second shunt via a fourth node, wherein the sum of the first shunt and the second shunt is equal to the first constant current, and a ratio of the first shunt to the second shunt is inversely proportional to the voltage difference between the reference voltage and the feedback voltage; The first load circuit is configured to: generate a first load current according to the voltage of the first node, and output the first load current via the third node; The second load circuit is configured to: generate a second load current according to the voltage of the second node, and output the second load current via the fourth node; The error voltage generating circuit is configured to generate the error voltage according to a voltage of the third node and a voltage of the fourth node.
3. The low-dropout linear regulator according to claim 2, wherein: The differential input circuit includes: a first transistor and a second transistor, Wherein, the control electrode of the first transistor is coupled to the reference voltage terminal, the first electrode of the first transistor is coupled to the first electrode of the second transistor and the first constant current source, and the second electrode of the first transistor is coupled to the third node; A control electrode of the second transistor is coupled to the feedback circuit, and a second electrode of the second transistor is coupled to the fourth node.
4. The low-dropout linear regulator according to claim 2, wherein: The first load circuit includes: a third transistor, The control electrode of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the second voltage terminal, and the second electrode of the third transistor is coupled to the third node.
5. The low-dropout linear regulator according to claim 4, wherein: The second load circuit includes: a fourth transistor, The control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second voltage terminal, and the second electrode of the fourth transistor is coupled to the fourth node.
6. The low-dropout linear regulator according to any one of claims 2 to 5, wherein: The error voltage generating circuit includes: a fifth transistor to a tenth transistor, wherein the control electrode of the fifth transistor is coupled to the third bias voltage terminal, the first electrode of the fifth transistor is coupled to the fourth node, and the second electrode of the fifth transistor is coupled to the first electrode of the seventh transistor; a control electrode of a sixth transistor coupled to the third bias voltage terminal, a first electrode of the sixth transistor coupled to the third node, and a second electrode of the sixth transistor coupled to the first electrode of the eighth transistor; The control electrode of the seventh transistor is coupled to the first voltage terminal, and the second electrode of the seventh transistor is coupled to the control electrode and the second electrode of the ninth transistor and the control electrode of the tenth transistor; The control electrode of the eighth transistor is coupled to the first voltage terminal, and the second electrode of the eighth transistor is coupled to the second electrode of the tenth transistor and the control electrode of the output power transistor; A first electrode of the ninth transistor is coupled to the input voltage terminal and a first electrode of the tenth transistor.
7. The low-dropout linear regulator according to claim 5, wherein: The first bias voltage generating circuit includes: an eleventh transistor, a twelfth transistor, and a first resistor. The first end of the first resistor is coupled to the first reference current source and the control electrode of the eleventh transistor, and the second end of the first resistor is coupled to the second electrode of the eleventh transistor, the control electrode of the twelfth transistor, and the first node; The first electrode of the eleventh transistor is coupled to the second electrode of the twelfth transistor; The first electrode of the twelfth transistor is coupled to the second voltage terminal.
8. The low-dropout linear regulator according to claim 7, wherein: The second bias voltage generating circuit includes: a thirteenth transistor, a fourteenth transistor, and a second resistor. wherein a first end of the second resistor is coupled to a second reference current source and the control electrode of the thirteenth transistor, and a second end of the second resistor is coupled to the second electrode of the thirteenth transistor, the control electrode of the fourteenth transistor, and the second node; The first electrode of the thirteenth transistor is coupled to the second electrode of the fourteenth transistor; The first electrode of the fourteenth transistor is coupled to the second voltage terminal; Among them, the ratio of the width to length ratio of the fourteenth transistor to the fourth transistor is 1:K, the ratio of the width to length ratio of the twelfth transistor to the third transistor is 1:K, the ratio of the width to length ratio of the fourteenth transistor to the twelfth transistor is 1:1, and K is greater than 1.
9. The low-dropout linear regulator according to any one of claims 1 to 5 and 7 to 8, further comprising: protection circuits, Wherein, the protection circuit is configured to: limit the voltage difference between the control electrode and the first electrode of the output power tube.
10. A low-dropout linear regulator, comprising: an output power tube, a first transistor to a sixteenth transistor, a first capacitor, a first resistor to a fourth resistor, and a first constant current source, Wherein, the control electrode of the first transistor is coupled to the reference voltage terminal, the first electrode of the first transistor is coupled to the first electrode of the second transistor and the first constant current source, and the second electrode of the first transistor is coupled to the second electrode of the third transistor and the first electrode of the sixth transistor; The control electrode of the second transistor is coupled to the first end of the third resistor and the first end of the fourth resistor, and the second electrode of the second transistor is coupled to the second electrode of the fourth transistor and the first electrode of the fifth transistor; The control electrode of the third transistor is coupled to the second electrode of the eleventh transistor and the control electrode of the twelfth transistor, and the first electrode of the third transistor is coupled to the second voltage terminal; The control electrode of the fourth transistor is coupled to the second electrode of the thirteenth transistor and the control electrode of the fourteenth transistor, and the first electrode of the fourth transistor is coupled to the second voltage terminal; The control electrode of the fifth transistor is coupled to the third bias voltage terminal, and the second electrode of the fifth transistor is coupled to the first electrode of the seventh transistor; The control electrode of the sixth transistor is coupled to the third bias voltage terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the eighth transistor; The control electrode of the seventh transistor is coupled to the first voltage terminal, and the second electrode of the seventh transistor is coupled to the control electrode and the second electrode of the ninth transistor and the control electrode of the tenth transistor; The control electrode of the eighth transistor is coupled to the first voltage terminal, and the second electrode of the eighth transistor is coupled to the second electrode of the tenth transistor and the control electrode of the output power transistor; The first electrode of the ninth transistor is coupled to the input voltage terminal and the first electrode of the tenth transistor; A first end of the first resistor is coupled to a first reference current source and a control electrode of the eleventh transistor, and a second end of the first resistor is coupled to a second electrode of the eleventh transistor; The first electrode of the eleventh transistor is coupled to the second electrode of the twelfth transistor; The first electrode of the twelfth transistor is coupled to the second voltage terminal; A first end of the second resistor is coupled to a second reference current source and a control electrode of the thirteenth transistor, and a second end of the second resistor is coupled to a second electrode of the thirteenth transistor; The first electrode of the thirteenth transistor is coupled to the second electrode of the fourteenth transistor; The first electrode of the fourteenth transistor is coupled to the second voltage terminal; The first electrode of the output power tube is coupled to the input voltage terminal, and the second electrode of the output power tube is coupled to the output voltage terminal and the second end of the third resistor; The second end of the fourth resistor is coupled to the second voltage end; A control electrode of the fifteenth transistor is coupled to the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor, and the first electrode of the fifteenth transistor is coupled to the input voltage terminal; The control electrode of the sixteenth transistor is coupled to the second electrode of the sixteenth transistor and the control electrode of the output power tube; A first terminal of the first capacitor is coupled to the output voltage terminal, and a second terminal of the first capacitor is coupled to the control electrode of the fourth transistor.
Citation Information
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