Key matrix circuit arrangement and input device

Abstract

Provided is a key matrix circuit device and an input device capable of directly using a power supply voltage higher than an upper limit voltage that can be input in an information processing device. The key matrix circuit device includes: a key matrix having a plurality of switches and a plurality of voltage division resistors connected between a plurality of sensing terminals and the plurality of switches; and a wake-up circuit having an output terminal that outputs a switching signal that switches the information processing device to a power saving mode or a normal mode, a power supply terminal connected to a power supply, and a connection terminal connected to the power supply terminal and a plurality of scan terminals, the plurality of voltage division resistors having a resistance value that sets a voltage of the plurality of sensing terminals connected to a plurality of sensing ports of the information processing device to be equal to or lower than a predetermined voltage, and when the information processing device is in the power saving mode, if one of the plurality of switches is turned on so that a potential of the connection terminal becomes a first level, the wake-up circuit outputs the switching signal that switches to the normal mode from the output terminal.

Description

Technical Field

[0001] This invention relates to a key matrix circuit device and an input device. Background Technology

[0002] Conventionally, a button matrix circuit includes: a first power supply that does not supply power in sleep mode, a second power supply that continuously supplies power, a switch configured in a matrix shape, a plurality of first circuit elements on the scanning side, a plurality of second circuit elements on the sensing side, a third circuit element that carries current from the sensing side to the scanning side in sleep mode, and a fourth circuit element that outputs a start signal in response to pressing the switch in sleep mode. Power is continuously supplied to the third circuit element from the second power supply, and a voltage corresponding to the second power supply is applied to the plurality of second circuit elements on the sensing side from the third circuit element (see, for example, Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: JP 2010-282253 Summary of the Invention

[0006] -The problem the invention aims to solve-

[0007] Existing key matrix circuits are used in the operation panels of image forming devices such as printers. Since the second circuit element on the sensing side is composed of an integrated circuit (IC), its input voltage is limited to approximately +5V. Therefore, it is assumed that the voltage applied from the third circuit element to the second circuit element is approximately +5V, which can be input to the IC. This upper limit on the IC's input voltage is set to prevent damage to the IC.

[0008] However, key matrix circuits are sometimes used in environments where the power supply voltage is higher than the upper limit of the input voltage that an information processing device like an IC can withstand. For example, the output voltage of a vehicle battery is 12V or 24V.

[0009] Therefore, the objective is to provide a key matrix circuit device and an input device that can directly utilize a power supply voltage higher than the upper limit voltage that can be input in an information processing device.

[0010] -Solution methods-

[0011] The key matrix circuit device according to an embodiment of the present invention includes: a key matrix having a plurality of scanning terminals, a plurality of sensing terminals, a plurality of switches respectively connected between the plurality of scanning terminals and the plurality of sensing terminals and configured in a matrix shape, and a plurality of voltage divider resistors respectively connected between the plurality of sensing terminals and the plurality of switches; and a wake-up circuit having an output terminal having a switching signal that switches the mode of an information processing device to a power saving mode or a normal mode, an output terminal having a power supply terminal connected to a power supply, and a connection terminal having a connection terminal having a connection terminal having a resistance value that sets the voltage of the plurality of sensing terminals respectively connected to the plurality of sensing ports of the information processing device to a predetermined voltage, and when the information processing device is in the power saving mode, if at least any one of the plurality of switches is turned on and the potential of the connection terminal becomes a first level, then the wake-up circuit outputs a switching signal that switches the mode to the normal mode from the output terminal.

[0012] -Invention Effects-

[0013] A key matrix circuit device and an input device are provided that can directly utilize a power supply voltage higher than the upper limit voltage that can be input in an information processing device. Attached Figure Description

[0014] Figure 1 This is a diagram illustrating the input device 100 of the implementation method.

[0015] Figure 2 This is a diagram representing the keypad matrix circuit device 100A.

[0016] Figure 3 This is a diagram illustrating an example of the detailed circuit structure of the key matrix circuit device 100A.

[0017] Figure 4 This is a diagram illustrating the operation of the key matrix circuit device 100A.

[0018] Figure 5 This is a diagram illustrating the operation of the key matrix circuit device 100A.

[0019] Figure 6 It is a diagram showing the status signals, start-up preparation signals, switching signals, and the states of transistor 1, transistor 2, and transistor 3 during sleep mode, transition, and normal mode. Detailed Implementation

[0020] Hereinafter, embodiments of the key matrix circuit device and input device to which the present invention is applied will be described.

[0021] <Implementation Method>

[0022] Figure 1 This diagram illustrates the input device 100 according to an embodiment. The input device 100 is, as an example, mounted in a vehicle, and is used by the user of the vehicle to operate equipment mounted in the vehicle. Equipment mounted in the vehicle includes, for example, air conditioning and audio systems; in this case, the input device 100 is used as an operating device for the air conditioning or audio system. The vehicle is equipped with a power source (e.g., a battery) whose power supply voltage is higher than the upper limit voltage that can be input into an information processing device such as a microcomputer. Furthermore, while the method of mounting the input device 100 in a vehicle is described here, it is not limited to vehicles; it can also be mounted in aircraft, trains, etc., if a power source with a voltage higher than the upper limit voltage that can be input into an information processing device is used.

[0023] The input device 100 includes a housing 101, multiple operating sections 102, and a key matrix circuit device 100A. The housing 101 is, for example, installed in the interior of a vehicle, such as on the center console or dashboard. Figure 1 The upper surface of the housing 101 is an operation panel 101A, which is equipped with multiple operation units 102. Each operation unit 102 is a switch that can operate the air conditioner, audio, etc., to turn on / off, set the temperature, set the air volume, set the air outlet, set the volume, select the radio track, etc.

[0024] A button matrix circuit device 100A is provided on the back side (inside the housing 101) of the operation unit 102. The button matrix circuit device 100A has a button matrix, and multiple switches of the button matrix are provided on the back side of each operation unit 102. When each operation unit 102 is pressed, the switches of the button matrix located on the back side are turned on.

[0025] Figure 2 This is a diagram representing the keypad matrix circuit device 100A. Figure 2 The structural elements are simplified and represented as a block diagram. The keypad matrix circuit device 100A includes an MCU (Micro Computer Unit) 10, a controller 20, a regulator 40, a power switch 50, a battery terminal 100A1, a keypad matrix 110, an OR circuit 120, and a wake-up circuit 130. The MCU 10 is an example of an information processing device. The controller 20 is an example of a switching unit. The battery 30 is an example of a power supply. The regulator 40 is an example of a voltage conversion unit. The OR circuit 120 is an example of a logic OR circuit. Figure 2 The symbol represents one OR circuit 120, but in reality, there are multiple. Furthermore, Figure 2 In addition to the button matrix circuit device 100A, it also indicates the battery 30 connected to the battery terminal 100A1.

[0026] MCU10 is a control unit that performs a scan (button scan) in normal mode to detect the connection status (on or off) of all switches in the button matrix 110 and determine the switches that are set to be on. MCU10 has an output port 10A, multiple scan ports 10B, multiple sensing ports 10C, and a power supply terminal 10D. MCU10 outputs a status signal from output port 10A. The status signal indicates whether MCU10 is in normal mode or sleep mode. A status signal at level L (Low) indicates that MCU10 is in sleep mode, and a status signal at level H (High) indicates that MCU10 is in normal mode.

[0027] The so-called normal mode is the state where the sleep mode is deactivated and the MCU10 can perform various information processing tasks. Sleep mode is an example of a power-saving mode, where the MCU10's operation is restricted to save power, and it is in a standby state for startup. Furthermore, L level is an example of the first level, and H level is an example of the second level. When the MCU10 transitions from sleep mode to normal mode, the status signal output from output port 10A is set to H level.

[0028] To perform a scan (key scan) to detect the connection status (on or off) of all switches in the key matrix 110, the MCU 10 sequentially outputs key scan signals from multiple scan ports 10B. By performing this scan, it can detect which switch in the key matrix 110 is set to on. Furthermore, multiple sensing ports 10C are ports that input key sensing signals from the key matrix 110 representing the detection results during the scan. The MCU 10 determines the switch set to on based on the combination of the key scan signals and the key sensing signals. The power supply terminal 10D is a terminal that receives low-voltage DC power, such as +5V or +3.3V, which is converted by the regulator 40.

[0029] The controller 20 has an input terminal 20A and an output terminal 20B. If a low-level switching signal is input from the output terminal 130B of the wake-up circuit 130 to the input terminal 20A, a drive signal for turning on the power switch 50 is output from the output terminal 20B. When the power switch 50 is turned on, the power supply voltage +Vb of the battery 30 is supplied to the regulator 40. The regulator 40 converts the voltage to obtain low-voltage DC power such as +5V or +3.3V, which is then supplied to the power supply terminal 10D of the MCU 10, thereby switching the MCU 10 from sleep mode to normal mode. The controller 20 outputs a drive signal for turning on the power switch 50 based on the low-level switching signal and outputs a drive signal for turning off the power switch 50 based on the high-level switching signal. Additionally, the controller 20 may have functions other than those described here, such as a CAN transceiver used in a vehicle's CAN (Controller Area Network), but descriptions of functions other than turning on the power switch 50 are omitted here.

[0030] Battery 30 is the vehicle's battery, providing 12V DC power as an example. The output terminal 30A of battery 30 is connected via battery terminal 100A1 to the power terminal 130C of power switch 50 and wake-up circuit 130, supplying the battery 30 with its power supply voltage +Vb. Furthermore, the battery 30's power supply voltage +Vb is supplied to the output terminal 130B of wake-up circuit 130 via pull-up resistor 130B1. Regulator 40 is positioned between battery 30 and MCU 10, converting the battery 30's power supply voltage +Vb (+12V) to lower voltages such as +5V and +3.3V and outputting them to MCU 10. Power switch 50 is connected in series between the battery 30's output terminal 30A and the regulator 40's input terminal, switching on / off via a drive signal output from controller 20's output terminal 20B.

[0031] The button matrix 110 is connected to the OR circuit 120 and the MCU 10, and includes: multiple scan terminals 110A, multiple sensing terminals 110B, multiple switches configured in a matrix, and multiple voltage divider resistors connected between the multiple sensing terminals 110B and the multiple switches. Detailed application of the button matrix 110 is described below. Figure 3 To be described later, but Figure 2 The switches and voltage divider resistors are omitted, and each of the scan terminal 110A and the sensing terminal 110B is represented as one. Multiple switches are connected between the multiple scan terminals 110A and the multiple sensing terminals 110B, and are configured in a matrix. The multiple scan terminals 110A are respectively connected to the logic OR output terminals 120B of the OR circuit 120, which actually exists in multiple ways, and the multiple sensing terminals 110B are respectively connected to the multiple sensing ports 10C of the MCU 10.

[0032] When the MCU 10 is in sleep mode, if at least any one of the switches in the key matrix 110 is turned on, it cooperates with the OR circuit 120 and the wake-up circuit 130 to generate a start-up preparation signal. The start-up preparation signal is output from the connection terminal 130D of the wake-up circuit 130. Furthermore, in the key matrix 110, when the MCU 10 is in normal mode, key scan signals are input from multiple scan ports 10B of the MCU 10 via the OR circuit 120 to perform a scan (key scan) to detect the connection status (on or off) of each switch. Key sensing signals indicating the result of scanning the key matrix 110 are input from the sensing terminal 110B to multiple sensing ports 10C of the MCU 10.

[0033] Multiple OR circuits 120 are actually arranged in parallel between the keypad matrix 110 and the wake-up circuit 130. Each OR circuit 120 has one input terminal 120A1, 120A2, and one logic OR output terminal 120B. Input terminal 120A1 is one input terminal, and input terminal 120A2 is another input terminal. Since there are actually multiple OR circuits 120, it is assumed that there are multiple input terminals 120A1, 120A2, and multiple logic OR output terminals 120B for the purpose of explanation. Multiple input terminals 120A1 are connected to one connection terminal 130D of the wake-up circuit 130, and multiple input terminals 120A2 are respectively connected to multiple scan ports 10B of the MCU 10. Each OR circuit 120 outputs a signal from the logic OR output terminal 120B representing the logic OR of the signals input to input terminals 120A1 and 120A2.

[0034] The wake-up circuit 130 has an input terminal 130A, an output terminal 130B, a power supply terminal 130C, and a connection terminal 130D. The input terminal 130A is connected to the output port 10A of the MCU 10 and is input with the status signal output from the output port 10A.

[0035] The output terminal 130B is connected to the input terminal 20A of the controller 20, and is connected to the output terminal 30A of the battery 30 via the pull-up resistor 130B1, outputting a switching signal to switch the mode of the MCU 10.

[0036] Power terminal 130C is connected to output terminal 30A of battery 30. Power terminal 130C receives, for example, the power supply voltage +Vb, i.e., +12V DC power, from battery 30. Connection terminal 130D is connected to input terminal 120A1 of OR circuit 120.

[0037] When MCU10 is in sleep mode, if at least any one switch of key matrix 110 is turned on, a startup preparation signal is generated in cooperation with key matrix 110 and OR circuit 120. Wake-up circuit 130 outputs the startup preparation signal from connection terminal 130D. If wake-up circuit 130 generates the startup preparation signal, it outputs a low-level switching signal from output terminal 130B to controller 20. As a result, controller 20 turns on power switch 50, and the DC power supply voltage +Vb from battery 30 is converted by regulator 40 into low-voltage DC power such as +SV or +3.3V, and supplied to power terminal 10D of MCU10, putting MCU10 into normal mode. That is, the low-level switching signal is the startup signal that starts MCU10 through normal mode. The startup preparation signal is a signal generated during the preparation phase for the startup signal output by wake-up circuit 130.

[0038] Figure 3 This is a diagram illustrating an example of the detailed circuit structure of the key matrix circuit device 100A. Figure 3 The controller 20, regulator 40, power switch 50, etc. are omitted. Figure 3 The button matrix circuit device 100A shown has a button matrix 110, which, as an example, has 5 scanning terminals 110A, 5 sensing terminals 110B, and 25 switches 111.

[0039] Five scan terminals 110A are connected to five scan ports 10B of the MCU 10. Five sensing terminals 110B are connected to five sensing ports 10C of the MCU 10. Additionally, Figure 3 The power supply terminal 10D is omitted.

[0040] Here, regarding the 25 switches 111, Figure 3 The vertical arrangement in the diagram is called a column, and the horizontal arrangement is called a row. The five switches 111, connected to the five lines extending downwards from the five OR circuits 120, are contained in the same column. The direction of extension of each column is... Figure 3 The vertical direction of the axis is as follows. Furthermore, five switches 111, each connected to one of the five lines extending laterally from the five sensing ports 10C of the MCU 10, are contained in the same row. The extension direction of each row is... Figure 3 The horizontal axis. As an example, switch 111, represented by the dashed line, is located in the 5th column of the 4th row.

[0041] also, Figure 3The button matrix 110 of the button matrix circuit device 100A shown also has five voltage divider resistors 112. The five voltage divider resistors 112 are connected in series in each row to the line branching from the five switches 111 to the sensing terminal 110B towards ground. Ground is an example of a reference potential point. The resistance value of the voltage divider resistors 112 is set such that, for example, when the first transistor 131 of the wake-up circuit 130 of the MCU 10 in sleep mode is off, and the switch 111 in the 5th column of the 4th row is turned on, thus turning on the second transistor, the voltage applied to the sensing port 10C corresponding to the 4th row is set to a resistance value below the upper limit voltage (for example, +5V) that can be input to the MCU 10. Furthermore, when any switch 111 is turned on, the voltage applied to the corresponding sensing port 10C is always below the upper limit voltage (for example, +5V) that can be input to the MCU 10. The upper limit voltage that can be input in MCU10 is an example of a specified voltage, and the resistance value below the upper limit voltage that can be input in MCU10 is an example of a resistance value below the specified voltage that can be input in MCU10.

[0042] Since the OR circuit 120 is set to the same number of columns as the key matrix 110, therefore Figure 3 Five are set in the middle. OR circuit 120, as an example, has two diodes. One of the two diodes ( Figure 3 The anode of the diode on the left is input terminal 120A1. The five input terminals 120A1 are connected to one of the connection terminals 130D of the wake-up circuit 130. The other of the two diodes... Figure 3 The anode of the diode on the right side of the image is input terminal 120A2. The five input terminals 120A2 are respectively connected to the five scan ports 10B of the MCU10.

[0043] In each OR circuit 120, the cathodes of two diodes are interconnected to form a logic OR output terminal 120B. The five logic OR output terminals 120B are respectively connected to the five scan terminals 110A.

[0044] The wake-up circuit 130 has a first transistor 131, a first resistor 131A, a second transistor 132, a second resistor 132A, a third transistor 133, and a third resistor 133A. The second resistor 132A is an example of a pull-up resistor.

[0045] The first transistor 131 is an NPN transistor with a collector 131C, an emitter 131E, and a base 131B. It is turned on when the base 131B is at a high level (H). The collector 131C, emitter 131E, and base 131B are examples of the first current input terminal, the first current output terminal, and the first control terminal, respectively. A first resistor 131A is connected between the emitter 131E and the base 131B and is configured to pull the base 131B down to ground when the status signal output from the output port 10A is at a low level (L), thereby reliably turning off the first transistor 131.

[0046] The collector 131C is connected to the connection terminal 130D and the base 132B of the second transistor 132. The emitter 131E is connected to ground. The base 131B is connected to the output port 10A of the MCU 10. Therefore, when the status signal input from the output port 10A to the base 131B of the MCU 10 in sleep mode is at level L, the first transistor 131 is turned off. When the status signal input from the output port 10A to the base 131B of the MCU 10 in normal mode is at level H, the first transistor 131 is turned on.

[0047] The second transistor 132 is a PNP transistor with an emitter 132E, a collector 132C, and a base 132B. It is turned on when the base 132B is at an inductance (L) level. Emitter 132E, collector 132C, and base 132B are examples of the second current input terminal, second current output terminal, and second control terminal, respectively. The second resistor 132A is connected between the emitter 132E and the base 132B.

[0048] The emitter 132E is connected to the power terminal 130C of the wake-up circuit 130, and is connected to the battery 30 (see reference 130C). Figure 2 Collector 132C is connected to the base 133B of the third transistor 133. Base 132B is connected to the collector 131C of the first transistor 131 via connection terminal 130D. When the MCU 10 is in sleep mode and the button matrix 110 is not operated, the power supply voltage +Vb of the battery 30 is supplied to the base 132B via the second resistor 132A, and the base 132B is pulled up to the power supply voltage +Vb, so the base 132B is at H level, and the second transistor 132 is off. When the MCU 10 is in sleep mode, if at least any one of the switches 111 of the button matrix 110 is operated to turn it on, it is connected to ground via the turned-on switch 111, so the base 132B is at L level, and the second transistor 132 is on. In addition, the second transistor 132 is also on when the MCU 10 is in normal mode. For these operations, using Figure 4 as well as Figure 5 To be described later.

[0049] The third transistor 133 is an NPN transistor with a collector 133C, an emitter 133E, and a base 133B. It is turned on when the base 133B is at a high voltage (H). The collector 133C, emitter 133E, and base 133B are, for example, the third current input terminal, the third current output terminal, and the third control terminal, respectively. The third resistor 133A is connected between the emitter 133E and the base 133B, configured to pull the base 133B down to ground when it is at a low voltage (L), thereby reliably turning off the third transistor 133.

[0050] The collector 133C is connected to the output terminal 130B of the wake-up circuit 130. The base 133B is connected to the collector 132C of the second transistor 132. The emitter 133E is connected to ground. When the second transistor 132 is turned on, power is supplied from the battery 30 through the second transistor 132, so the base 133B is at a high level (H), thereby turning on the third transistor 133. When the second transistor 132 is turned off, the base 133B is at a low level (L), therefore the third transistor 133 is turned off. That is, the third transistor 133 is switched on / off in conjunction with the second transistor 132.

[0051] Next, besides Figure 3 In addition, it also uses Figure 4 as well as Figure 5 This will explain the operation of the key matrix circuit device 100A. Figure 4 as well as Figure 5 This is a diagram illustrating the operation of the key matrix circuit device 100A. Figure 4 This indicates the operation of the key matrix circuit device 100A when the MCU10 transitions from sleep mode to normal mode. Figure 5 This indicates the operation of the key matrix circuit device 100A when the MCU10 is in normal mode. First, using... Figure 3 The following explains the case where MCU10 is in sleep mode.

[0052] When MCU10 is in sleep mode, such as Figure 3 As shown, when none of the switches 111 in the button matrix 110 are operated and all switches 111 are open, the power supply voltage +Vb to the battery 30 is supplied via the second resistor 132A, therefore the base 132B is at level H. Consequently, the second transistor 132 is off. Since the second transistor 132 is off, the third transistor 133 is also off, and the switching signal output from the output terminal 130B is at level H. This is because the output terminal 130B is connected to the battery 30 (see reference 130B1) via the pull-up resistor 130B1. Figure 2When transistor 33 is off, the voltage difference between the power supply voltage +Vb of battery 30 and the voltage difference between the pull-up resistor 130B1 (see reference) is calculated. Figure 2 The voltage obtained by the voltage drop of the signal is used as an H-level signal and generated in the output terminal 130B. In this state, since the switching signal is H-level, the MCU10 is still in sleep mode.

[0053] Next, in Figure 4 During the transition shown, when MCU10 is in sleep mode, for example, if switch 111 in the 4th row, 5th column (shown by the dashed line) is pressed and turned on, the turned-on switch 111 is connected to ground. Therefore, the potential of the base 132B of the second transistor 132 decreases to L level, thus turning on the second transistor 132. If the second transistor 132 is turned on, the third transistor 133 is also turned on. If the third transistor 133 is turned on, the output terminal 130B is connected to ground through the collector 133C and emitter 133E of the turned-on third transistor 133, thus the output terminal 130B becomes L level.

[0054] If output terminal 130B is at level L, controller 20 will turn on power switch 50, thus supplying low voltage power such as +5V or +3.3V to power terminal 10D of MCU10 from regulator 40, waking up MCU10 and putting it into normal mode. If MCU10 is in normal mode, the status signal output from output port 10A will be set to level H.

[0055] If MCU10 is in normal mode, the status signal output from output port 10A is at level H, then as follows Figure 5 As shown, transistor 131 is turned on. With transistor 131 on, its emitter 131E is connected to ground, so terminal 130D is at an L level, and the base 132B of transistor 132 is at an L level, thus transistor 132 is turned on. If transistor 132 is turned on, transistor 133 is also turned on. Therefore, transistors 131, 132, and 133 are all turned on.

[0056] Furthermore, if the connection terminal 130D is at a low level, then a low level is input to the input terminals 120A1 of the five OR circuits 120. Therefore, the output levels of the multiple scan ports 10B of the MCU 10 are reflected in the logic OR output terminals 120B of the five OR circuits 120. Thus, if high-level key scan signals are sequentially output from the multiple scan ports 10B, the five columns of the key matrix 110 can be sequentially set to high level, enabling scanning of the key matrix 110.

[0057] Figure 6This diagram illustrates the states of the status signals, start-up signal, switching signal, and the states of transistors 1, 2, and 3 during sleep mode, transition, and normal mode. As shown in the table above, in sleep mode, the status signal, start-up signal, and switching signal are at levels L, H, and H, respectively. Furthermore, during transition, the status signal, start-up signal, and switching signal are at levels L, L, and H, respectively. In normal mode, the status signal, start-up signal, and switching signal are at levels H, L, and L, respectively. If any switch 111 is turned on during transition in sleep mode, the start-up signal becomes level L, and the switching signal changes to level L, thus transitioning to normal mode.

[0058] Furthermore, as shown in the table below, in sleep mode, transistors 131, 132, and 133 are all off. During transition, transistors 131, 132, and 133 are off, on, and on respectively. In normal mode, transistors 131, 132, and 133 are all on. If any switch 111 is turned on in sleep mode and transition occurs, transistor 132 turns on, and subsequently transistor 133 turns on, changing the switching signal to level L to transition to normal mode. The on / off states of transistors 132 and 133 are linked.

[0059] As described above, the voltage divider resistors 112 of the button matrix 110 each have a resistance value that sets the voltage of the plurality of sensing terminals 110B, which are respectively connected to the plurality of sensing ports 10C of the MCU 10, below the upper limit voltage of the input of the MCU 10. Furthermore, if the wake-up circuit 130 is activated when at least one of the plurality of switches 111 is in sleep mode, causing the potential of the connection terminal 130D to become L level, then it outputs a switching signal from the output terminal 130B to switch the mode of the MCU 10 to the normal mode at an L level.

[0060] Therefore, a key matrix circuit device 100A and an input device 100 are provided that can directly utilize a power supply voltage +Vb (of battery 30) that is higher than the upper limit voltage that can be input in MCU10.

[0061] Furthermore, when detecting the operation to wake up the MCU 10, if at least any one of the multiple switches 111 is turned on, current flows from the battery 30 connected to the emitter 132E of the second transistor 132, through the base 132B, the connection terminal 130D, the OR circuit 120 containing the column of turned-on switches 111, and the turned-on switches 111 to ground. The base 132B becomes an L level, thus turning on the second transistor 132 and the third transistor 133. The L level switching signal is output from the output terminal 130B, thereby waking up the MCU 10. Therefore, when detecting the operation to wake up the MCU 10, it is not necessary to scan the key matrix 110. Therefore, a power-saving key matrix circuit device 100A and an input device 100 can be provided that realize the power saving when detecting the operation to wake up the MCU 10.

[0062] Furthermore, if the start-up preparation signal output from connection terminal 130D becomes level L, the power switch 50 located between regulator 40 and battery 30 is turned on. Regulator 40 is connected between battery 30 and power terminal 10D of MCU 10, converting the power supply voltage into an input voltage for MCU 10. Therefore, power can be supplied to MCU 10 according to the start-up preparation signal, waking up MCU 10 and allowing it to transition to normal mode.

[0063] Furthermore, the key matrix circuit device 100A also includes multiple OR circuits 120, each having multiple logic OR output terminals 120B respectively connected to multiple scan terminals 110A. The wake-up circuit 130 also has an input terminal 130A connected to the MCU 10 and inputting a status signal indicating the mode, and a first transistor 131. The first transistor 131 has a collector 131C connected to the connection terminal 130D and the power supply terminal 10D, an emitter 131E connected to ground, and a base 131B connected to the input terminal 130A. If a high-level signal is input to the base 131B, the first transistor 131 is turned on. The connection terminal 130D is connected to one input terminal 120A1 of the multiple OR circuits 120, and another input terminal 120A2 of the multiple OR circuits 120 is connected to multiple scan ports 10B of the MCU 10. The status signal is at a high level (H) when the MCU 10 is in normal mode. Therefore, if MCU10 is in normal mode, the first transistor 131 is turned on, so the connection terminal 130D is at the L level, and one input terminal 120A1 of the multiple OR circuits 120 is input with an L level signal. Therefore, the key scan signal input from the multiple scan ports 10B to another input terminal 120A2 becomes the state reflected in the logic OR output terminal 120B of the multiple OR circuits 120.

[0064] Furthermore, if the MCU10 is switched to normal mode via a switching signal, the first transistor 131 is turned on, pulling the potential of the connection terminal 130D down to the L level, thereby waking up the circuit 130 so that it can scan the connection state of the multiple switches 111 by scanning signals output from the multiple scan ports 10B. That is, with an L-level signal input to one input terminal 120A1 of the multiple OR circuits 120, the key matrix 110 can be scanned by a key scanning signal input from the multiple scan ports 10B to another input terminal 120A2.

[0065] Furthermore, the wake-up circuit 130 also includes: a second transistor 132 having an emitter 132E and a collector 132C connected to the power supply terminal 10D, and a base 132B connected to the connection terminal 130D and the collector 131C; the second transistor 132 is turned on if an L-level signal is input to the base 132B; and a second resistor 132A connecting the emitter 132E and the base 132B of the second transistor 132. The connection terminal 130D is connected to the power supply terminal 10D via the second transistor 132 and the second resistor 132A. Therefore, in the sleep mode when all switches 111 are not operated, the second transistor 132 is in the off state because the connection terminal 130D is connected to the battery 30 via the second resistor 132A and is therefore at a H-level. If any switch 111 is turned on, making terminal 130D low level, the second transistor 132 is turned on, and the low level switching signal is output from output terminal 130B, thereby enabling MCU10 to switch to normal mode.

[0066] Furthermore, when multiple switches 111 are open in sleep mode, the potential of connection terminal 130D is at level H. Therefore, the second transistor 132 is kept in the open state, reliably maintaining the sleep mode of MCU 10.

[0067] Furthermore, if at least any one of the multiple switches 111 is turned on when the MCU 10 is in sleep mode, causing the potential of the connection terminal 130D to become L level, then the second transistor 132 is turned on, thereby outputting a switching signal from the output terminal 130B to switch the mode to the normal mode. Therefore, the second transistor 132 being turned on reliably wakes up the MCU 10, allowing it to transition to the normal mode.

[0068] Furthermore, the wake-up circuit 130 also includes a third transistor 133, which has a third current input terminal 133C connected to the output terminal 130B, an emitter 133E connected to ground, and a base 133B connected to the collector 132C. The third transistor 133 is turned on when a high-level signal is input to the base 133B. The output terminal 130B is connected to the battery 30 via a pull-up resistor 130B1. The switching signal for switching the mode to the normal mode is a low-level signal. Therefore, by using the third transistor, which is turned on in conjunction with the second transistor 132, the switching signal can be set to a high level in sleep mode. When at least any one of the multiple switches 111 is turned on, the MCU 10 can be reliably woken up by the low-level switching signal, thus transitioning it to the normal mode.

[0069] Furthermore, when the status signal is at level L, indicating sleep mode, if at least any one of the multiple switches 111 is turned on, inputting an L-level signal to the base 132B, thus turning on the second transistor 132, the potential of the base 133B becomes H, thus turning on the third transistor 133, and the switching signal becomes L. Using the third transistor, which is turned on in conjunction with the second transistor 132, an L-level switching signal can be reliably generated to enable the MCU 10 to transition to normal mode (wake it up), allowing the MCU 10 to reliably transition to normal mode via the L-level switching signal.

[0070] Furthermore, in the input device 100, if the start-up preparation signal output from the connection terminal 130D becomes a low level, the power switch 50, located between the regulator 40 and the battery 30, is turned on. The regulator 40 is connected between the battery 30 and the power terminal 10D of the MCU 10, converting the power supply voltage into a voltage that can be input to the MCU 10. Therefore, power can be supplied to the MCU 10 according to the start-up preparation signal, enabling the MCU 10 to wake up and transition to normal mode.

[0071] Furthermore, the above description describes the wake-up circuit 130 having a first transistor 131, a second transistor 132, a third transistor 133, a first resistor 131A, a second resistor 132A, and a third resistor 133A. However, if the same operation can be performed, the circuit structure of the wake-up circuit 130 is not limited to this circuit structure.

[0072] Furthermore, the OR circuit 120 with two diodes has been described, but any circuit that can maintain rectification and output two inputs in a logical OR operation is acceptable, so the OR circuit 120 is not limited to the circuit structure described above.

[0073] Furthermore, the button matrix 110 is described as having 5 rows and 5 columns, but the button matrix 110 is not limited to this structure; the number of rows and columns can be arbitrary.

[0074] The key matrix circuit device and input device of the present invention have been described above according to exemplary embodiments. However, the present invention is not limited to the specific embodiments disclosed, and various modifications and alterations can be made without departing from the scope of the claims.

[0075] This international application claims priority based on Japanese Patent Application No. 2020-212587, filed on December 22, 2020, the entire contents of which are incorporated herein by reference.

[0076] Explanation of symbols

[0077] 10. MCU (Microcontroller Unit)

[0078] 10A output port

[0079] 10B Scan Port

[0080] 10C sensing port

[0081] 10D power terminals

[0082] 20 Controller (Switching Unit)

[0083] 30 batteries (power supply)

[0084] 40 Regulator (Voltage Conversion Unit)

[0085] 50 Power Switch

[0086] 100 Input Device

[0087] 100A Keypad Matrix Circuit Device

[0088] 110 Key Matrix

[0089] 110A Scan Terminal

[0090] 110B Sensing Terminal

[0091] 111 Switch

[0092] 112 voltage divider resistor

[0093] 120 OR circuit (logic OR circuit)

[0094] 120A1, 120A2 Input Terminals

[0095] 120B Logic OR Output Terminal

[0096] 130 Wake-up Circuit

[0097] 130A Input Terminal

[0098] 130B Output Terminal

[0099] 130B1 Pull-up Resistor

[0100] 130C power terminal

[0101] 130D connector

[0102] 131 Transistor 1

[0103] 131C Collector (First Current Input Terminal)

[0104] 131E Emitter (First Current Output Terminal)

[0105] 131B Base (Control Terminal 1)

[0106] 132 Second Transistor

[0107] 132E Emitter (Second Current Input Terminal)

[0108] 132C Collector (Second Current Output Terminal)

[0109] 132B Base (Control Terminal 1)

[0110] 133 Third transistor

[0111] 133C Collector (Third Current Input Terminal)

[0112] 133E Emitter (Third Current Output Terminal)

[0113] 133B Base (3rd control terminal).

Claims

1. A key matrix circuit device, comprising: A button matrix includes multiple scanning terminals, multiple sensing terminals, multiple switches connected between the multiple scanning terminals and the multiple sensing terminals and configured in a matrix, and multiple voltage-dividing resistors connected between the multiple sensing terminals and the multiple switches; and The wake-up circuit includes an output terminal that outputs a switching signal to a switching unit that switches the mode of the information processing device to a power-saving mode or a normal mode, a power supply terminal connected to a power source, and a connection terminal connected to the power supply terminal and the plurality of scanning terminals. The plurality of voltage divider resistors each have a resistance value that sets the voltage of the plurality of sensing terminals, which are respectively connected to the plurality of sensing ports of the information processing device, to below a predetermined voltage. When the information processing device is in the power-saving mode, if at least any one of the multiple switches is turned on, and the potential of the connection terminal becomes the first level, the wake-up circuit outputs a switching signal from the output terminal to switch the mode to the normal mode.

2. The key matrix circuit device according to claim 1, wherein, The key matrix circuit device further includes: The switching unit; A voltage conversion unit is connected between the power supply and the power terminal of the information processing device to convert the power supply voltage into a voltage that can be input to the information processing device. and A power switch is disposed between the voltage conversion unit and the power source. If the signal output from the connection terminal is the first level, the switching unit turns on the power switch.

3. The key matrix circuit device according to claim 1 or 2, wherein, The key matrix circuit device further includes: multiple logic OR circuits, each having multiple logic OR output terminals respectively connected to the multiple scanning terminals. The wake-up circuit also has: The input terminal is connected to the information processing device and is input with a status signal indicating the mode. and The first transistor has a first current input terminal connected to the connection terminal and the power supply terminal, a first current output terminal connected to a reference potential point, and a first control terminal connected to the input terminal. The first transistor is turned on when a signal of the second level is input to the first control terminal. The connection terminal is connected to one input terminal of the plurality of logic OR circuits. Another input terminal of the plurality of logic OR circuits is connected to a plurality of scanning ports of the information processing device. When the information processing device is in the normal mode, the status signal is the second level.

4. The key matrix circuit device according to claim 3, wherein, If the information processing device is switched to the normal mode by the switching signal, the first transistor is turned on, pulling down the potential of the connection terminal to the first level, so that the wake-up circuit is in a state in which the connection status of the multiple switches can be scanned by the scanning signals output from the multiple scanning ports.

5. The key matrix circuit device according to claim 3 or 4, wherein, The wake-up circuit also includes a second transistor, which has a second current input terminal connected to the power supply terminal, a second current output terminal, and a second control terminal connected to the connection terminal and the first current input terminal. If a signal of the first level is input to the second control terminal, the second transistor is turned on. The connection terminal is connected to the power supply terminal via the second transistor.

6. The key matrix circuit device according to claim 5, wherein, When the information processing device is in the power-saving mode and the plurality of switches are off, the potential of the connection terminal is the second level.

7. The key matrix circuit device according to claim 5 or 6, wherein, When the information processing device is in the power-saving mode, if at least any one of the plurality of switches is turned on so that the potential of the connection terminal becomes the first level, then the second transistor is turned on, and the wake-up circuit outputs a switching signal from the output terminal to switch the mode to the normal mode.

8. The key matrix circuit device according to any one of claims 5 to 7, wherein, The wake-up circuit also includes a third transistor, which has a third current input terminal connected to the output terminal, a third current output terminal connected to the reference potential point, and a third control terminal connected to the second current output terminal. If the second-level signal is input to the third control terminal, the third transistor is turned on. The output terminal is connected to the power supply via a pull-up resistor. The switching signal that switches the mode to the normal mode is the signal at the first level.

9. The key matrix circuit device according to claim 8, wherein, When the status signal is at the first level indicating the power-saving mode, if at least any one of the plurality of switches is turned on, and the signal at the first level is input to the second control terminal, and the second transistor is turned on, then the potential of the third control terminal becomes the second level, the third transistor is turned on, and thus the switching signal becomes the first level.

10. An input device comprising: The operation panel has multiple operating sections; and Key matrix circuit device, The key matrix circuit device has: The button matrix includes multiple scanning terminals, multiple sensing terminals, multiple switches connected between the multiple scanning terminals and the multiple sensing terminals and configured in a matrix, and multiple voltage-dividing resistors connected between the multiple sensing terminals and the multiple switches. The wake-up circuit includes an output terminal that outputs a switching signal to a switching unit that switches the mode of the information processing device to a power-saving mode or a normal mode, a power supply terminal connected to a power source, and a connection terminal connected to the power supply terminal and the plurality of scanning terminals. The plurality of voltage divider resistors each have a resistance value that sets the voltage of the plurality of sensing terminals, which are respectively connected to the plurality of sensing ports of the information processing device, to below a predetermined voltage. When the information processing device is in the power-saving mode, if at least any one of the multiple switches is turned on, and the potential of the connection terminal becomes the first level, the wake-up circuit outputs a switching signal from the output terminal to switch the mode to the normal mode.

11. The input device according to claim 10, wherein, The input device further includes: The switching unit; A voltage conversion unit is connected between the power supply and the power terminal of the information processing device to convert the power supply voltage into a voltage that can be input to the information processing device. and A power switch is disposed between the voltage conversion unit and the power source. If the signal output from the connection terminal is the first level, the switching unit turns on the power switch.

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