Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: providing a substrate including a target layer, the substrate including a target region for forming a target pattern layer and a dicing region corresponding to a dicing position; forming a mask sidewall on the substrate; using the mask sidewall as a mask to pattern the target layer to form discrete initial pattern layers, the initial pattern layers extending laterally, the direction perpendicular to the lateral direction being the longitudinal direction, and grooves being formed between adjacent initial pattern layers along the longitudinal direction; forming boundary definition grooves penetrating the initial pattern layers located at the boundary position between the target region and the dicing region along the lateral direction; forming a spacer layer filled in the grooves and the boundary definition grooves; using the spacer layer located in the boundary definition grooves and the spacer layer located in the grooves as stop layers along the lateral direction and the longitudinal direction respectively, and etching the initial pattern layers located in the dicing region, and the remaining initial pattern layers located in the target region are used as the target pattern layer. The embodiment of the present invention is beneficial to increasing the process window for etching the initial pattern layers in the dicing region.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of very large scale integrated circuits, the feature size of integrated circuits continues to decrease. To adapt to smaller feature sizes, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is also continuously shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and drain of the device is also shortened, so the control ability of the gate structure over the channel becomes worse, and the difficulty of the gate structure to pinch off the channel voltage becomes greater, making the subthreshold leakage phenomenon, namely the so-called Short-Channel Effects (SCE), more likely to occur.

[0003] Therefore, in order to reduce the influence of short-channel effects, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has a stronger control ability over the channel and can well suppress short-channel effects; and FinFETs have better compatibility with existing integrated circuit manufacturing compared to other devices.

[0004] In the semiconductor field, according to process requirements, it is usually also necessary to form fins with different pitches, or to remove the pseudo fins at unnecessary positions so that the graphic layer of the fins meets the design requirements. Currently, one approach is to achieve the above purposes through the Fin cut process. Among them, the Fin cut process generally includes the Cut first process and the Cut last process. Summary of the Invention

[0006] Technical Problem

[0007] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to increasing the process window for forming a target graphic layer from an initial graphic layer in an etching and cutting area.

[0008] Solution to the Problem

[0009] Technical Solution

[0010] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including a target layer, the substrate including a target area for forming a target pattern layer and a dicing area corresponding to a dicing position; forming discrete mask sidewalls on the substrate; using the mask sidewalls as a mask to pattern the target layer to form discrete initial pattern layers, the initial pattern layers extending in a transverse direction, a direction perpendicular to the transverse direction being a longitudinal direction, and grooves being formed between adjacent initial pattern layers along the longitudinal direction; forming boundary definition grooves penetrating the initial pattern layers located at the boundary position between the target area and the dicing area along the transverse direction; forming a spacer layer filling the grooves and the boundary definition grooves; using the spacer layer located in the boundary definition grooves and the spacer layer located in the grooves as stop layers along the transverse direction and the longitudinal direction respectively, etching the initial pattern layers located in the dicing area, and the remaining initial pattern layers located in the target area being used as the target pattern layer.

[0011] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate including a target area and a dicing area, the substrate including a target pattern layer discrete from the target area, the target pattern layer extending in a transverse direction, a direction perpendicular to the transverse direction being a longitudinal direction; a dicing groove located on the substrate in the dicing area, the dicing groove extending along the transverse direction, the dicing groove being connected to the target pattern layer along the transverse direction, or the dicing groove being arranged in parallel and spaced from the target pattern layer; a boundary definition groove located along the transverse direction between the dicing groove and the target pattern layer; a spacer layer filling between adjacent target pattern layers, between sidewalls of adjacent dicing grooves, and between the sidewalls of the dicing groove and the target pattern layer, the spacer layer filling the boundary definition groove.

[0012] Advantages of the Invention

[0013] Advantages

[0014] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages: In the method for forming a semiconductor structure provided by the embodiment of the present invention, after forming the initial pattern layer, a boundary definition groove is formed, which penetrates the initial pattern layer located at the boundary position between the target area and the cutting area in the transverse direction. The boundary definition groove is used to define the boundary of the target area, so that the initial pattern layer is disconnected in the transverse direction at the boundary position between the target area and the cutting area. Then, a spacer layer is formed to fill the groove and the boundary definition groove, so that the initial pattern layer is spaced apart by the spacer layer at the boundary position between the target area and the cutting area in the transverse direction, and the adjacent initial pattern layers in the longitudinal direction are also spaced apart by the spacer layer. During the process of etching the initial pattern layer located in the cutting area, the spacer layer can define the etching stop positions in the transverse and longitudinal directions, so that the spacer layer located in the boundary definition groove and the spacer layer located in the groove can be respectively used as the stop layers in the transverse and longitudinal directions. The embodiment of the present invention can correspondingly achieve self-aligned etching in the transverse and longitudinal directions, which is beneficial to increasing the process window for etching the initial pattern layer in the cutting area, reducing the process difficulty of forming the target pattern layer, and can precisely control the critical dimensions and patterns of the target pattern layer, thereby improving the profile quality and sidewall profile quality of the target pattern layer.

[0015] In an alternative solution, the target area is an active area, and the cutting area is an isolation area; the initial pattern layer is an initial fin, and the target pattern layer is a fin; the material of the spacer layer is a dielectric material; in the step of etching the initial pattern layer located in the cutting area, a cutting groove is formed in the spacer layer; after etching the initial pattern layer located in the cutting area, the forming method further includes: forming a filling isolation layer in the cutting groove; planarizing the filling isolation layer and the spacer layer with the top of the fin as the stop position; removing a part of the thickness of the filling isolation layer and the spacer layer to expose a part of the sidewall of the fin, and the remaining filling isolation layer and spacer layer are used as an isolation structure; the embodiment of the present invention can integrate the fin cutting process with the formation of the isolation structure, which is beneficial to improving the process integration and process compatibility, and is also beneficial to simplifying the process flow and improving the production and manufacturing efficiency.

[0016] Brief Description of the Drawings Description of the Drawings

[0017] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0018] Figures 5 to 8 It is a schematic structural diagram corresponding to each step in another method for forming a semiconductor structure.

[0019] Figures 9 to 10 It is a schematic structural diagram corresponding to each step in yet another method for forming a semiconductor structure.

[0020] Figures 11 to 28 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0021] Embodiment of the invention

[0022] Embodiment of the present invention

[0023] As can be seen from the background art, generally, fins with different pitches are formed by a fin cut process, or dummy fins at unnecessary positions are removed so that the pattern of the fins meets the design requirements. Among them, the fin cut process generally includes a cut first process and a cut last process.

[0024] However, at present, the process window of the fin cut process is getting smaller and the difficulty of the fin cut process is getting higher.

[0025] Taking the cut first process as an example, the reasons for the increasingly smaller process window of the fin cut process are analyzed. Refer to Figures 1 to 4 , which shows a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0026] Refer to Figure 1 , provide a substrate 1; form a plurality of discrete sidewalls on the substrate 1, and the sidewalls include a mask sidewall 2 and a dummy mask sidewall 3.

[0027] Refer to Figures 2 to 3 , remove the dummy mask sidewall 3. Among them, the step of removing the dummy mask sidewall 3 includes: forming a mask layer 4 on the substrate 1, and having a mask opening 5 in the mask layer that exposes the dummy mask sidewall 3; using the mask layer 4 as a mask to remove the dummy mask sidewall 3 exposed by the mask opening 5; removing the mask layer 4.

[0028] Refer to Figure 4 , after removing the dummy mask sidewall 3, using the mask sidewall 2 as a mask, pattern the substrate 1 to form fins 6.

[0029] Compared with the aspect ratio of the fins 6, the aspect ratio of the dummy mask sidewall 3 is smaller, and the difficulty of removing the dummy mask sidewall 3 is relatively low. However, in the above method, the dummy mask sidewall 3 is removed first. After removing the dummy mask sidewall 3, the mask sidewalls 2 have different pitches, and the pattern density of the mask sidewalls 2 is uneven. In the process of patterning the substrate 1 using the mask sidewalls 2 as a mask, the uneven pattern density of the mask sidewalls 2 easily causes uneven etching rates of the substrate 1 in each region, and further causes poor profile uniformity of the formed fins.

[0030] Another method is the cut last process. Figures 5 to 8 It is a schematic structural diagram corresponding to each step in another method for forming a semiconductor structure.

[0031] Reference Figure 5 , a substrate 11 is provided and fins are separately located on the substrate 11, and the fins include device fins 12 and dummy fins 13.

[0032] Combined with reference Figures 5 to 8 , the dummy fins 13 are removed. Among them, the steps of removing the dummy fins 13 include: forming a mask layer 14 covering the device fins 12 on the substrate 11, and a mask opening 15 exposing the dummy fins 13 is formed in the mask layer 14; using the mask layer 14 as a mask, removing the dummy fins 13 exposed by the mask opening 15; removing the mask layer 14.

[0033] After forming the fins, the dummy fins 13 are removed by the above method. The fins are formed by patterning the substrate with the mask sidewall as a mask pattern. Since the spacing between the mask sidewalls is the same and the pattern density consistency of the mask sidewalls is relatively high, in the step of forming the fins by patterning the substrate, the size consistency and profile morphology consistency of the fins are also relatively high.

[0034] However, compared with the aspect ratio of the mask sidewall, the aspect ratio of the fins is relatively large, resulting in great challenges in removing the dummy fins 13. Specifically, the mask layer 14 is usually formed by photolithography processes such as exposure and development. The aspect ratio of the dummy fins 13 is relatively large, and the aspect ratio of the mask opening 15 is also relatively large, resulting in a reduced process window for the photolithography process of forming the mask layer 14; the aspect ratio of the dummy fins 13 is relatively large, and in the process of removing the dummy fins 13 exposed by the mask opening 15, the aspect ratio of the etching process is also relatively large, resulting in a relatively high difficulty of the etching process.

[0035] There are also some other methods for fin cutting process. Reference Figures 9 to 10 , shows the corresponding structural schematic diagrams of each step in another method for forming a semiconductor structure.

[0036] Reference Figure 9 , a substrate 21 and initial fins 22 separately located on the substrate 21 are provided, and the substrate 21 includes an active region (not labeled) and an isolation region (not labeled); a covering layer 23 filled between the initial fins 22 is formed on the substrate 21.

[0037] Reference Figure 10 , after forming the covering layer 23, the initial fins 22 located in the isolation region are removed, and the remaining initial fins 22 located in the active region are used as fins 24.

[0038] By forming the covering layer 23, during the process of removing the initial fin 22 located in the isolation region, the covering layer 23 can define a stop position in the direction perpendicular to the extending direction of the initial fin 22. However, in the extending direction of the initial fin 22, since the etching objects are all of the same material, it is difficult to control the stop position of the etching, and thus it is difficult to control the remaining amount of the initial fin 22. This not only results in a low profile quality and sidewall perpendicularity of the formed fin 24, but also easily causes the critical dimension (CD) of the fin 24 not to meet the design requirements, and the process window of the fin cutting process is small.

[0039] Therefore, there is an urgent need for a method that can increase the process window of the fin patterning process and reduce the difficulty of the fin patterning process.

[0040] To solve the above technical problems, in the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming the initial pattern layer, a boundary definition groove is formed, penetrating the initial pattern layer located at the intersection position of the target region and the cutting region in the transverse direction. The boundary definition groove is used to define the boundary of the target region, so that the initial pattern layer is disconnected at the boundary position of the target region and the cutting region in the transverse direction. Then, a spacer layer is formed to fill the groove and the boundary definition groove, so that the initial pattern layer is separated by the spacer layer at the intersection position of the target region and the cutting region in the transverse direction, and the adjacent initial pattern layers in the longitudinal direction are also separated by the spacer layer. During the process of etching the initial pattern layer located in the cutting region, the spacer layer can define the etching stop positions in the transverse and longitudinal directions, so that the spacer layer located in the boundary definition groove and the spacer layer located in the groove can be respectively used as the stop layers in the transverse and longitudinal directions. The embodiment of the present invention can correspondingly achieve etching self-alignment in the transverse and longitudinal directions, which is beneficial to increasing the process window of etching the initial pattern layer in the cutting region, reducing the process difficulty of forming the target pattern layer, and being able to precisely control the critical dimension and pattern of the target pattern layer, thereby improving the profile quality and sidewall morphology quality of the target pattern layer.

[0041] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings. Figures 11 to 28 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0042] Refer to Figure 11 , a cross-sectional schematic diagram is shown. A substrate 200 is provided, including a target layer 100. The substrate 200 includes a target region A for forming a target pattern layer and a cutting region B corresponding to the cutting position.

[0043] The substrate 200 provides a process platform for subsequent process steps. The target layer 100 is a film layer to be patterned to form a target pattern layer. The target area A is the area where the subsequent target pattern layer is located, and the area on the substrate 200 other than the target area A is the dicing area B.

[0044] In this embodiment, the target layer 100 is an initial substrate, and the subsequent patterning of the initial substrate forms a substrate and fins protruding from the substrate. Accordingly, in this embodiment, the target pattern layer is the fins. The fins are used to form fin field-effect transistors (FinFETs). Accordingly, in this embodiment, the target area A is the active area (AA), and the dicing area B is the isolation area.

[0045] In this embodiment, the material of the initial substrate is silicon. In other embodiments, the material of the initial substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the initial substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0046] In other embodiments, the target pattern layer can also be a gate structure, a channel stack in a gate-all-around (GAA) transistor, a pattern transfer layer, or a dielectric isolation layer and other pattern layers. Among them, the pattern transfer layer can be a hard mask layer and other film layers, and the dielectric isolation layer can be a dielectric layer for isolating the back-end metal interconnects.

[0047] In this embodiment, the substrate 200 further includes a hard mask material layer 120 located on the target layer 100. Subsequently, the hard mask material layer 120 is patterned with the mask sidewall as the mask pattern to form a hard mask layer. Even if the mask sidewall is damaged during the patterning of the target layer 100, the target layer 100 can still be patterned with the hard mask layer as the mask, which is beneficial to improving the process stability of patterning the target layer 100 and the accuracy of pattern transfer; moreover, the subsequent process includes multiple etching processes, and the hard mask material layer 120 can also define the etching stop position in these etching processes to avoid etching damage to the underlying film layer. The material of the hard mask material layer 120 includes one or more of silicon nitride, titanium nitride, tungsten carbide, silicon oxide, silicon carbon oxide, and silicon carbonitride oxide. In this embodiment, the material of the hard mask material layer 120 is silicon nitride.

[0048] In this embodiment, the substrate 200 further includes an adhesion layer 110 located between the target layer 100 and the hard mask material layer 120. The adhesion layer 110 is used to improve the adhesion between the hard mask material layer 120 and the target layer 100 and reduce the stress generated between the film layers. In this embodiment, the material of the adhesion layer 110 is silicon oxide.

[0049] Combined with reference Figures 11 to 17 , discrete mask sidewalls 150 are formed on the substrate 200 (such as Figure 17As shown). The mask sidewall 150 is used as a mask for the patterned target layer 100.

[0050] The mask sidewall 150 is selected from materials that have an etching selectivity with respect to the target layer 100, so as to ensure that the mask sidewall 150 can serve as a mask for the patterned target layer 100. The materials of the mask sidewall 150 include materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon, aluminum oxide, titanium nitride or titanium oxide, nitrogen-doped tungsten, or tungsten-doped carbon. In this embodiment, the mask sidewall 150 can be formed by SADP or SAQP processes. Specifically, in this embodiment, taking the formation of the mask sidewall 150 by the SAQP process as an example, the steps of forming the mask sidewall 150 will be described in detail.

[0051] As Figures 11 to 14 shown, discrete core layers 140 are formed on the substrate 200 (as Figure 14 shown).

[0052] The core layer 140 is used to provide a supporting role for the formation of the mask sidewall. In this embodiment, a plurality of adjacent core layers 140 form a supporting core layer 140a, and a single core layer 140 forms a sacrificial core layer 140b.

[0053] In this embodiment, the steps of forming the core layer 140 include: as Figure 11 shown, a core material layer 160 is formed on the substrate 200; a discrete sacrificial layer 170 is formed on the core material layer 160; an initial sidewall 180 is formed on the sidewalls of the sacrificial layer 170; as Figure 12 shown, the sacrificial layer 170 is removed; as Figure 13 and Figure 14 shown, using the initial sidewall 180 as a mask, the core material layer 160 is patterned to form the core layer 140.

[0054] In this embodiment, after providing the substrate 200 and before forming the core material layer 160, the forming method further includes: forming a first etch stop layer 130 on the substrate 200. The first etch stop layer 130 is used to define the etch stop position of subsequent etching processes to avoid causing problems of etching non-uniformity.

[0055] In this embodiment, after the core material layer 160 is formed and before the sacrificial layer 170 is formed, the forming method further includes: forming a second etch stop layer 165 on the core material layer 160. The processes of forming the sacrificial layer 170 and the initial sidewall 180 both include a process combining deposition and etching. The second etch stop layer 165 is used to define the etch stop position in the etching processes of forming the sacrificial layer 170 and the initial sidewall 180, so as to avoid damaging the core material layer 160 below it and prevent the problem of inconsistent etching. Moreover, in the process of patterning the core material layer 160 with the initial sidewall 180 as the mask pattern, the second etch stop layer 165 can be patterned with the initial sidewall 180 as the mask first, and the patterned second etch stop layer 165 can also be used as the mask for patterning the core material layer 160, which is beneficial to improving the process stability and accuracy of pattern transfer.

[0056] In this embodiment, the core layer 140 extends in the transverse direction (as shown by the x direction in Figure 13 ), and is arranged at intervals in the longitudinal direction (as shown by the y direction in Figure 13 ), and the transverse direction is perpendicular to the longitudinal direction. In this embodiment, after the core material layer 160 is patterned to form the core layer 140, the forming method further includes: removing the initial sidewall 180 and the second etch stop layer 165.

[0057] As Figure 16 shown, a mask sidewall 150 is formed on the sidewall of the core layer 140.

[0058] In this embodiment, the step of forming the mask sidewall 150 includes: forming a sidewall film (not shown in the figure) that conformally covers the top surface and sidewalls of the core layer 140 and the top surface of the substrate 200; removing the sidewall film located on the top surface of the core layer 140 and the top surface of the substrate 200, and the remaining sidewall film located on the sidewalls of the core layer 140 serves as the mask sidewall 150.

[0059] As Figure 17 shown, the forming method further includes: after the mask sidewall 150 is formed, removing the core layer 140 to expose the substrate 200 below it, preparing for subsequent patterning of the substrate 200 with the mask sidewall 150.

[0060] With reference to Figures 13 to 15 , Figure 13 is a top view, Figure 14 is Figure 13 a cross-sectional view at the cc position, Figure 15 is a cross-sectional view based on Figure 14 . In this embodiment, the forming method further includes: after the core layer 140 is formed and before the mask sidewall 150 is formed, removing the sacrificial core layer 140b located in the cutting area B.

[0061] The process of subsequent etching of the initial pattern layer located in the cutting area B requires forming an etching mask for etching the initial pattern layer located in the cutting area B. By removing the sacrificial core layer 140b located in the cutting area B, it is beneficial to reduce the pattern complexity of the etching mask, thereby increasing the process window for forming the etching mask (for example: alleviating the limitation of lithography resolution). Moreover, a single core layer 140 constitutes the sacrificial core layer 140b, and removing the sacrificial core layer 140a located in the cutting area B has little impact on the spacing between the remaining core layers 140. When forming the mask sidewalls, the consistency of the spacing between the mask sidewalls is less affected, which is beneficial to alleviating the problem of etching rate differences caused by differences in pattern density consistency during the process of patterning the target layer 100 with the mask sidewalls as the mask pattern. Correspondingly, it is beneficial to ensure that the critical dimensions, profile morphology, and sidewall perpendicularity of the initial pattern layer can meet the design requirements. In addition, the aspect ratio of the core layer 140 is relatively small, and the difficulty of removing a single core layer 140 is relatively small.

[0062] In this embodiment, the step of removing the sacrificial core layer 140b located in the cutting area B includes: as Figure 13 and Figure 14 shown, forming a first pattern layer 143 on the core layer 140. The first pattern layer 143 has a first opening 41 above the sacrificial core layer 140b located in the cutting area B; as Figure 15 shown, using the first pattern layer 143 as a mask, etching the sacrificial core layer 140b along the first opening 41; removing the first pattern layer 143.

[0063] In this embodiment, the first pattern layer 143 is a photoresist layer. In this embodiment, before forming the first pattern layer 143, a first planarization layer 141 covering the core layer 140 and a first anti-reflection layer 142 located on the planarization layer 141 are also formed on the substrate 200. It should be noted that for the convenience of illustration and description, only the first planarization layer 141 and the first anti-reflection layer 142 are schematically shown in Figure 14 .

[0064] In other embodiments, in the step of forming the mask sidewalls, the sacrificial core layer and the mask sidewalls located on the sidewalls of the sacrificial core layer constitute a sacrificial pattern layer; after forming the mask sidewalls and before patterning the target layer, the sacrificial pattern layer located in the cutting area is removed. Specifically, removing the sacrificial pattern layer located in the cutting area may include: removing the sacrificial pattern layer located in the cutting area after forming the mask sidewalls and before removing the core layer.

[0065] In the process of removing the sacrificial pattern layer located in the cutting area, a pattern layer for use as an etching mask needs to be formed. The pattern layer is formed by a lithography process, and the lithography process usually requires a calibration process. After forming the mask sidewall, there are two film layers formed on the substrate: the core layer and the mask sidewall. By removing the sacrificial pattern layer located in the cutting area after forming the mask sidewall and before removing the core layer, it is beneficial to improve the contrast of the patterns on the substrate, thereby providing a clearer alignment mark for the calibration of the lithography process, and correspondingly facilitating the improvement of the calibration clarity and accuracy of the lithography process.

[0066] In some other embodiments, removing the sacrificial pattern layer located in the cutting area may further include: removing the mask sidewall in the sacrificial pattern layer located in the cutting area after removing the core layer and before patterning the target layer.

[0067] Reference Figure 18 , using the mask sidewall 150 as a mask, pattern the target layer 100 to form discrete initial pattern layers 210. The initial pattern layers 210 extend in the lateral direction (as shown by the x - direction in Figure 13 ), and the direction perpendicular to the lateral direction is the longitudinal direction (as shown by the y - direction in Figure 13 ). Grooves 220 are formed between adjacent initial pattern layers 210 along the longitudinal direction. The initial pattern layers 210 are used to form the target pattern layer through subsequent cutting processes.

[0068] In this embodiment, the target pattern layer is a fin, and the initial pattern layer 210 is correspondingly an initial fin.

[0069] In this embodiment, pattern the target layer 100 to form a substrate 230 and discrete initial fins on the substrate 230. The grooves 220 are surrounded by adjacent initial fins and the substrate 230.

[0070] In this embodiment, after forming the mask sidewall 150 and before patterning the target layer 100, the forming method further includes: using the mask sidewall 150 as a mask, pattern the hard mask material layer 120 to form a hard mask layer 240.

[0071] The hard mask layer 240 can protect the initial pattern layer 210 in subsequent processes. Specifically, the subsequent processes further include filling the trench 220 with a spacer layer, and forming the spacer layer includes a planarization process. The hard mask layer 240 can be used to define the stop position of the planarization process. Moreover, during the subsequent etching of the initial pattern layer 210 in the cutting area B, the hard mask layer 240 in the cutting area is also removed, exposing the top of the initial pattern layer 210 in the cutting area B. Correspondingly, in the step of etching the initial pattern layer 210 in the cutting area B, the spacer layer and the remaining hard mask layer 240 can serve as a mask for the initial pattern layer 210 in the cutting area B, thereby protecting the initial pattern layer 210 in the target area A and reducing the probability of incorrect etching of the initial pattern layer 210 in the target area A.

[0072] Reference Figures 19 to 20 , a top view is shown, and a boundary definition groove 250 is formed, penetrating the initial pattern layer 210 located transversely at the boundary position between the target area A and the cutting area B.

[0073] The boundary definition groove 250 is used to define the boundary of the target area A, so that the initial pattern layer 210 is disconnected transversely at the boundary position between the target area A and the cutting area B. Then, a spacer layer is formed to fill the trench 220 and the boundary definition groove 250, so that the initial pattern layer 210 is spaced apart by the spacer layer at the boundary position between the target area A and the cutting area B transversely, and the adjacent initial pattern layers 210 are also spaced apart by the spacer layer longitudinally. During the etching of the initial pattern layer 210 in the cutting area B, the spacer layer can define the etching stop positions transversely and longitudinally, which is beneficial to increasing the process window for forming the target pattern layer, reducing the process difficulty of forming the target pattern layer, and enabling precise control of the critical dimensions and patterns of the target pattern layer, thereby improving the profile quality and sidewall profile quality of the target pattern layer.

[0074] In this embodiment, the boundary definition groove 250 also penetrates the hard mask layer 240 located transversely at the boundary position between the target area A and the cutting area B. Transversely, the opening width of the boundary definition groove 250 should not be too small, otherwise it is easy to increase the process difficulty of etching the initial pattern layer 210 to form the boundary definition groove 250, and it is also difficult to control the sidewall perpendicularity of the remaining initial pattern layer 210 in the target area A; the opening width of the boundary definition groove 250 should not be too large transversely, otherwise it is easy to cause inconsistent etching rates of the initial pattern layers 210 of different types of patterns, and it is then difficult to precisely control the remaining initial pattern layer 210 in the target area A. Therefore, in actual processes, the opening width of the boundary definition groove 250 needs to be reasonably set according to actual process requirements.

[0075] In this embodiment, the step of forming the boundary definition groove 250 includes: As Figure 19As shown, a boundary definition mask layer 245 covering the initial pattern layer 210 is formed, and a boundary definition opening 51 is formed in the boundary definition mask layer 245 at a position transversely located at the junction of the target area A and the cutting area B; as Figure 20 shown, using the boundary definition mask layer 245 as a mask, along the boundary definition opening 51, the initial pattern layer 210 is etched to form a boundary definition groove 250; the boundary definition mask layer 245 is removed.

[0076] In this embodiment, the boundary definition mask layer 245 is located on the hard mask layer 240. Therefore, the boundary definition opening 51 exposes the hard mask layer 240. Accordingly, along the boundary definition opening 51, the hard mask layer 240 and the initial pattern layer 210 are etched in sequence. In this embodiment, longitudinally, the boundary of the boundary definition opening 51 may be located between the initial pattern layers 210.

[0077] In this embodiment, the process of etching the initial pattern layer 210 along the boundary definition opening 51 includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, which is beneficial to improving the etching profile controllability and etching accuracy, and correspondingly beneficial to precisely controlling the profile morphology, sidewall perpendicularity, and opening width of the boundary definition opening 51.

[0078] In this embodiment, for the convenience of illustration and description, in Figure 19 and Figure 20 the shape and position of the target area A are schematically shown by a dashed box. The area other than the target area A is the cutting area B.

[0079] Refer to Figure 21 to form a spacer layer 260 filled in the groove 220 and the boundary definition groove 250.

[0080] The spacer layer 260 is filled in the groove 220 and the boundary definition groove 250, so that the initial pattern layer 210 is spaced apart by the spacer layer 260 transversely at the junction of the target area A and the cutting area B, and the adjacent initial pattern layers 210 are also spaced apart by the spacer layer 260 longitudinally. During the process of etching the initial pattern layer 210 located in the cutting area B, the spacer layer 260 can define the etching stop positions transversely and longitudinally.

[0081] In this embodiment, the spacer layer 260 covers the sidewalls of the hard mask layer 240.

[0082] In this embodiment, the material of the spacer layer 260 is a dielectric material. In this embodiment, the target pattern layer is a fin. By selecting a dielectric material as the material of the spacer layer 260, after etching the initial fin located in the cutting area B subsequently, the spacer layer 260 can still be planarized and etched, so that the remaining spacer layer 260 is used to form an isolation structure to isolate adjacent fins. Thus, the process of forming the spacer layer 260 can be integrated with the fin cutting process and the process of forming the isolation structure, improving the process integration and process compatibility, and can also simplify the process flow and improve the production and manufacturing efficiency. Specifically, the material of the spacer layer 260 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbon oxide, and silicon carbon oxynitride. As an example, the material of the spacer layer 260 is silicon oxide.

[0083] In other embodiments, the spacer layer can be removed subsequently, which is correspondingly beneficial to improving the flexibility of the selection of the spacer layer material. For example: the material of the spacer layer can not be a dielectric material, and the material of the spacer layer can include Spin-On Carbon (SOC), amorphous carbon, Organic Dielectric layer (ODL), Silicon-Anti-reflective Coating (Si-ARC), Deep UV light absorbing Oxide (DUO), Dielectric Anti-reflective Coating (DARC), or Advanced Patterning Film (APF). The material of the spacer layer is a material that is easy to be removed, which is beneficial to reducing the difficulty of removing the spacer layer subsequently.

[0084] In this embodiment, the step of forming the spacer layer 260 includes: forming a spacer material layer (not shown in the figure) that fills the groove 220 and the boundary definition groove 250 and covers the hard mask layer 240; using the top of the hard mask layer 240 as the stop position to planarize the spacer material layer, and the remaining spacer material layer is used as the spacer layer 260.

[0085] In this embodiment, the process of forming the spacer material layer includes one or several of the flowing chemical vapor deposition (FCVD) process, atomic layer deposition (ALD) process, and spin-on process. The process of forming the spacer material layer is a process with high gap filling ability, which is beneficial to improving the filling ability of the spacer material layer in the groove 220 and the boundary definition groove 250, and correspondingly improving the formation quality of the spacer material layer. As an example, the flowing chemical vapor deposition process is used to form the spacer material layer.

[0086] In this embodiment, the process of planarizing the spacer material layer includes a chemical mechanical polishing process. The chemical mechanical polishing process is a global planarization technique, which is beneficial to improving the top surface flatness of the spacer layer 260 and also beneficial to improving the efficiency of planarizing the spacer material layer.

[0087] With reference to Figures 21 to 24 , taking the spacer layer 260 located in the boundary definition groove 250 and the spacer layer 260 located in the groove 220 as the stop layers along the transverse and longitudinal directions respectively, etch the initial pattern layer 210 located in the cutting area B, and the remaining initial pattern layer 210 located in the target area A is used as the target pattern layer 300 (as Figure 24 shown). In this embodiment, in the step of etching the initial pattern layer 210 located in the cutting area B, cutting grooves 30 are formed in the spacer layer 260.

[0088] In this embodiment, the spacer layer located in the boundary definition groove 250 and the spacer layer 260 located in the groove 220 can be respectively used as the stop layers along the transverse and longitudinal directions, and accordingly, self-aligned etching can be realized along the transverse and longitudinal directions, thereby increasing the process window for etching the initial pattern layer 210 located in the cutting area B, reducing the process difficulty of forming the target pattern layer 300, and being able to precisely control the critical dimensions and patterns of the target pattern layer 300, thereby improving the profile quality and sidewall profile quality of the target pattern layer 300. In this embodiment, the target pattern layer 300 is a fin, and the fin has relatively high profile quality and sidewall profile quality, and the critical dimensions of the fin are precisely controlled, which is beneficial to improving the performance of the FinFET device.

[0089] In this embodiment, the initial fins located in the cutting area B are etched to form residual pseudo fins 320 located in the cutting area B. By forming the residual pseudo fins 320, during the subsequent process of forming the isolation structure covering part of the sidewalls of the fins on the substrate 230, the residual pseudo fins 320 are located between adjacent fins and can play a role in dispersing stress, thereby being beneficial to reducing the probability of the fins being bent or tilted due to different stresses received by each fin.

[0090] The height of the residual pseudo fins 320 should not be too small, otherwise it is easy to reduce the stress dispersion effect of the residual pseudo fins 320; the height of the residual pseudo fins 320 should not be too large, otherwise it is easy to cause the distance between the top surface of the isolation structure and the residual pseudo fins 320 to be too small after the subsequent formation of the isolation structure, which is easy to increase the risk of leakage current. Therefore, in this embodiment, the height of the residual pseudo fins 320 is less than or equal to 20% of the fin height. As an example, the height of the residual pseudo fins 320 is less than or equal to

[0091] In this embodiment, etching the initial pattern layer 210 located in the cutting area B includes the following steps.

[0092] As Figure 21 and Figure 22 shown, Figure 21 is a top view, Figure 22 and Figure 21 is a cross-sectional view at the cc position. A second pattern layer 263 is formed on the spacer layer 260. The second pattern layer 263 has a second opening 61 located in the cutting area B. The second pattern layer 263 covers the initial pattern layer 210 of the target area A, and the second pattern layer 263 has a second opening 61 located in the cutting area B, which is used as a mask for etching the initial pattern layer 210.

[0093] In this embodiment, the second pattern layer 263 is a photoresist layer, and the second pattern layer 263 is formed by photolithography processes such as exposure and development. In this embodiment, since the adjacent initial pattern layers 210 are separated by the spacer layer 260 along the longitudinal direction, and the initial pattern layers 210 of the target area A and the cutting area B are separated by the spacer layer 260 along the transverse direction, therefore, along the longitudinal direction, the edge of the second opening 61 can be located between two adjacent initial pattern layers 210, and along the transverse direction, the edge of the second opening 61 can be located on the spacer layer 260 in the boundary definition groove 250, which is beneficial to increasing the overlay shift tolerance when forming the second opening 61, and further beneficial to improving the process window for forming the second pattern layer 263. In this embodiment, before forming the second pattern layer 263, the forming method further includes: forming a second planarization layer 261 and a second anti-reflection layer 262 on the spacer layer 260.

[0094] As Figure 23 and Figure 24 shown, Figure 23 is a partial enlarged view based on Figure 21 , Figure 24 and Figure 23 is a cross-sectional view at the cc position. Using the second pattern layer 263 as a mask, the initial pattern layer 210 below the second opening 61 is etched. In this embodiment, since the spacer layer 260 can serve as a stop layer both along the transverse and longitudinal directions to define the stop position for etching the initial pattern layer 210 in the cutting area B, it is beneficial to reducing the difficulty of etching the initial pattern layer 210 and improving the process selection flexibility of etching the initial pattern layer 210. For example, the etching process of the initial pattern layer 210 has a high etching selectivity for the initial pattern layer 210 and the spacer layer 260.

[0095] In this embodiment, in the step of etching the initial pattern layer 210 located in the cutting area B, the etching selectivity between the initial pattern layer 210 and the spacer layer 260 is at least 4:1. The relatively large etching selectivity between the initial pattern layer 210 and the spacer layer 260 can further improve the effect of defining the etching stop position of the spacer layer 260.

[0096] In this embodiment, the process of etching the initial pattern layer 210 located in the cutting area B includes an isotropic etching process. The isotropic etching process can reduce the damage to other film layers.

[0097] As an example, the process of etching the initial pattern layer 210 located in the cutting area B includes a wet etching process or a remote plasma etching process. Among them, the wet etching process is easy to achieve isotropic etching, and the wet etching process is simple to operate and low in cost. The wet etching process can also achieve a large etching selectivity. The remote plasma etching process has isotropic etching characteristics, and moreover, the remote plasma etching process also has a high etching selectivity. During the etching process, it is beneficial to reduce the loss of other film layers. Among them, the principle of the remote plasma etching process is to form a plasma outside the etching chamber (for example: generate plasma through a remote plasma generator), and then introduce it into the etching chamber and use the chemical reaction between the plasma and the layer to be etched for etching. Therefore, an isotropic etching effect can be achieved, and because there is no ion bombardment, other film layers will not be damaged. In other embodiments, other suitable etching processes can also be used to etch the initial pattern layer located in the cutting area, such as: inductively coupled plasma (ICP) etching or capacitively coupled plasma (CCP) etching and other etching processes.

[0098] In this embodiment, after forming the spacer layer 260 and before etching the initial pattern layer 210 located in the cutting area B, the forming method further includes: removing the hard mask layer 240 located in the cutting area B to expose the top of the initial pattern layer 210 in the cutting area B, so as to etch the initial pattern layer 210 in the cutting area B through the exposed top of the initial pattern layer 210.

[0099] In this embodiment, the target pattern layer 300 is a fin; after etching the initial pattern layer 210 located in the cutting area B, the forming method of the semiconductor structure further includes the following steps.

[0100] Reference Figures 25 to 27 , a filling isolation layer 270 is formed in the cutting groove 30.

[0101] By forming the fill isolation layer 270, it prepares for subsequent removal of a partial thickness of the fill isolation layer 270 and the spacer layer 260 to form an isolation structure. In this embodiment, the material of the fill isolation layer 270 is the same as that of the spacer layer 260, which is beneficial to improving process compatibility.

[0102] In this embodiment, the steps of forming the fill isolation layer 270 include: as Figure 25 shown, forming a fill isolation material layer 265 that fills the cutting groove 30 and covers the spacer layer 260 and the hard mask layer 240; as Figure 26 and Figure 27 shown, Figure 26 is a top view, Figure 27 is Figure 26 a cross-sectional view at the cc position, with the top of the fin as the stop position, to planarize the fill isolation material layer 265 and the spacer layer 260.

[0103] In this embodiment, a process with strong gap filling ability is used to form the fill isolation material layer 265, thereby improving the filling quality of the fill isolation material layer 265 in the cutting groove 30. Specifically, the process of forming the fill isolation layer 270 includes one or both of a flowable chemical vapor deposition process and an atomic layer deposition process.

[0104] In this embodiment, the process of planarizing the fill isolation material layer 265 and the spacer layer 260 includes a chemical mechanical polishing process.

[0105] Referring to Figure 28 , a partial thickness of the fill isolation layer 270 and the spacer layer 260 are removed to expose a partial sidewall of the fin, and the remaining fill isolation layer 270 and spacer layer 260 are used as the isolation structure 330. The isolation structure 330 is used to isolate adjacent fins. The isolation structure 330 covers the residual pseudo fin 320.

[0106] In this embodiment, integrating the Fin Cut process with the process of forming the isolation structure 330 is beneficial to improving process integration and process compatibility, and is also beneficial to simplifying the process flow and improving production and manufacturing efficiency. It should be noted that this embodiment takes retaining a part of the spacer layer 260 to form the isolation structure 330 as an example. In other embodiments, after etching the initial pattern layer in the cutting area, the forming method may further include: removing the spacer layer.

[0107] Correspondingly, the present invention also provides a semiconductor structure. Figure 26 and Figure 27 show a schematic structural diagram of an embodiment of the semiconductor structure of the present invention. Among them, Figure 26 is a top view, Figure 27 is Figure 26 a cross-sectional view at the cc position.

[0108] The semiconductor structure includes: a substrate 200, including a target area A and a dicing area B, the substrate 200 includes a target pattern layer 300 discrete from the target area A, the target pattern layer 300 extends in the transverse direction (such as Figure 26 shown by the x direction in Figure 26 ), and the direction perpendicular to the transverse direction is the longitudinal direction (such as Figure 23 shown by the y direction in Figure 24 ); a dicing groove 30 (such as Figure 20 shown), located on the substrate 200 in the dicing area B, the dicing groove 30 extends in the transverse direction, the dicing groove 30 is connected to the target pattern layer 300 in the transverse direction, or the dicing groove 30 is arranged in parallel and spaced from the target pattern layer 300; a boundary definition groove 250 (such as

[0109] shown), located between the dicing groove 250 and the target pattern layer 300 in the transverse direction; a spacer layer 260, filled between adjacent target pattern layers 300, between the side walls of adjacent dicing grooves 30, and between the side wall of the dicing groove 30 and the target pattern layer 300, the spacer layer 260 fills the boundary definition groove 250. The dicing groove 30 is formed by etching the initial pattern layer in the dicing area B, and the remaining initial pattern layer in the target area A is used as the target pattern layer 300.

[0110] The substrate 200 provides a platform for the process. The target area A is the area where the target pattern layer 300 is located, and the area on the substrate 200 other than the target area A is the cutting area B. In this embodiment, the target pattern layer 300 is a fin. The fin is used to form a fin field effect transistor. Correspondingly, in this embodiment, the target area A is the active area, and the cutting area B is the isolation area.

[0111] In this embodiment, the target pattern layer 300 is a fin. Therefore, the cross-sectional morphology quality and sidewall morphology quality of the fin are relatively high, and the critical dimensions of the fin are precisely controlled, which is beneficial to improving the performance of the FinFET device.

[0112] In this embodiment, the substrate 200 further includes a substrate 230 located at the bottom of the fin. The fin protrudes from the substrate 230 correspondingly. In this embodiment, the materials of the fin and the substrate 230 are silicon.

[0113] In other embodiments, the target pattern layer can also be a gate structure, a channel stack in a gate-all-around (GAA) transistor, a pattern transfer layer, or a dielectric isolation layer, etc. Among them, the pattern transfer layer can be a film layer structure such as a hard mask layer, and the dielectric isolation layer can be a dielectric layer for isolating the back-end metal interconnections.

[0114] The cutting groove 30 corresponds to the cutting (Cut) position of the initial pattern layer. The cutting groove 30 is formed by etching the initial pattern layer in the cutting area B. Therefore, the cutting groove 30 has the same extending direction as the target pattern layer 300.

[0115] In this embodiment, the semiconductor structure further includes: a residual pseudo-fin 320 located at the bottom of the cutting groove 30. The residual pseudo-fin 320 is retained in the semiconductor structure because when etching the initial fin in the cutting area B, a part of the initial fin is retained as the residual pseudo-fin 320.

[0116] By providing the residual pseudo-fin 320, during the subsequent process of forming an isolation structure covering part of the sidewalls of the fins on the substrate 230, the residual pseudo-fin 320 is located between adjacent fins and can play a role in dispersing stress, thereby being beneficial to improving the probability of the fins being bent or tilted due to different stresses received by each fin. In this embodiment, the height of the residual pseudo-fin 320 is less than or equal to 20% of the height of the fin. As an example, the height of the residual pseudo-fin 320 is less than or equal to

[0117] The boundary definition groove 250 is used to define the boundary of the target area A, so that the initial graphic layer 210 is disconnected horizontally at the boundary position between the target area A and the cutting area B. The spacer layer 260 fills the boundary definition groove 250, so that the spacer layer 260 spaces the initial graphic layer horizontally at the junction position between the target area A and the cutting area B. During the process of etching the initial graphic layer located in the cutting area B to form the cutting groove 30, the spacer layer 260 located in the boundary definition groove 250 can define the etching stop position horizontally, and can precisely control the critical dimensions and patterns of the target graphic layer 300, thereby improving the profile morphology quality and sidewall morphology quality of the target graphic layer 300, and increasing the process window for forming the target graphic layer 300.

[0118] The spacer layer 260 spaces the initial graphic layer horizontally at the junction position between the target area A and the cutting area B, and spaces the adjacent initial graphic layers vertically. During the process of etching the initial graphic layer located in the cutting area B to form the cutting groove 30, the spacer layer 260 can define the etching stop positions horizontally and vertically.

[0119] In this embodiment, the target graphic layer 300 is a fin; the material of the spacer layer 260 is a dielectric material. In this embodiment, the target graphic layer 300 is a fin. By selecting a dielectric material as the material of the spacer layer 260, the spacer layer 260 can be etched in the subsequent process, and the remaining spacer layer 260 is used to form an isolation structure to isolate adjacent fins. Furthermore, the process of forming the spacer layer 260, etching the initial fin located in the cutting area B, and forming the isolation structure can be integrated, improving the process integration degree and process compatibility, and also simplifying the process.

[0120] The material of the spacer layer 260 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbon oxide, and silicon carbon oxynitride. As an example, the material of the spacer layer 260 is silicon oxide.

[0121] In other embodiments, the spacer layer is removed subsequently, which is beneficial to improving the flexibility of the spacer layer material selection. For example: the material of the spacer layer may not be a dielectric material, and the material of the spacer layer may include spin-on carbon, amorphous carbon, organic dielectric layer, silicon-containing antireflection layer, deep ultraviolet light-absorbing oxide layer, dielectric antireflection coating, or advanced film. The material of the spacer layer is a material that is easy to remove, which is beneficial to reducing the difficulty of removing the spacer layer.

[0122] In this embodiment, the semiconductor structure further includes: a filling isolation layer 270 filled in the cutting groove 30. Subsequently, a part of the thickness of the filling isolation layer 270 and the spacer layer 260 is removed to form an isolation structure. The isolation structure is used to isolate adjacent fins, thereby integrating the fin cutting process and the process of forming the isolation structure, which is beneficial to improving the process integration degree and compatibility, and also beneficial to simplifying the process flow and improving the production and manufacturing efficiency.

[0123] In this embodiment, the material of the filling isolation layer 270 is the same as that of the spacer layer 260, which is beneficial to improving process compatibility.

[0124] The semiconductor structure can be formed by the formation method described in the foregoing embodiment, or can be formed by other formation methods. For the specific description of the semiconductor structure in this embodiment, reference can be made to the corresponding description in the foregoing embodiment, and details are not described herein again.

[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate including a target region and a cutting region, the substrate including a target pattern layer discrete from the target region, the target pattern layer extending laterally, and the direction perpendicular to the lateral direction being the longitudinal direction; the target pattern layer being a fin. Cutting grooves located on the substrate in the cutting region, the cutting grooves extending along the lateral direction, the cutting grooves being connected to the target pattern layer along the lateral direction, or the cutting grooves being arranged in parallel at intervals with the target pattern layer. Boundary definition grooves located laterally between the cutting grooves and the target pattern layer. Spacer layers filled between adjacent target pattern layers, between sidewalls of adjacent cutting grooves, and between sidewalls of the cutting grooves and the target pattern layer, the spacer layers filling the boundary definition grooves. Filling isolation layers filled in the cutting grooves. The thicknesses of the filling isolation layers and the spacer layers are such that sidewalls of the fins can be exposed, and the filling isolation layers and the spacer layers are used as isolation structures, and the top surface of the isolation structures is lower than the top surface of the fins.

2. The semiconductor structure according to claim 1, wherein, The target region is an active region, and the cutting region is an isolation region; the semiconductor structure further includes: residual pseudo fins located at the bottom of the cutting grooves.

3. The semiconductor structure according to claim 1, characterized in that, The target region is an active region, and the cutting region is an isolation region; the material of the spacer layer is a dielectric material.

4. The semiconductor structure according to claim 3, wherein The material of the filling isolation layer is the same as the material of the spacer layer.

5. The semiconductor structure according to claim 1, wherein The material of the spacer layer includes silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, carbon silicon oxide, carbon silicon oxynitride, spin-on carbon, amorphous carbon, organic dielectric layer, silicon-containing antireflection layer, deep ultraviolet light-absorbing oxide layer, dielectric antireflection coating, or advanced film.

6. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate including a target layer, the substrate including a target region for forming a target pattern layer and a cutting region corresponding to a cutting position. Forming discrete mask sidewalls on the substrate. Using the mask sidewalls as masks to pattern the target layer to form discrete initial pattern layers, the initial pattern layers extending laterally, the direction perpendicular to the lateral direction being the longitudinal direction, and grooves being formed between adjacent initial pattern layers along the longitudinal direction. Forming boundary definition grooves penetrating the initial pattern layers located at the junction position between the target region and the cutting region along the lateral direction. Forming spacer layers filled in the grooves and the boundary definition grooves. Using the spacer layers located in the boundary definition grooves and the spacer layers located in the grooves as stop layers along the lateral direction and the longitudinal direction respectively, etching the initial pattern layers located in the cutting region, and the remaining initial pattern layers located in the target region are used as target pattern layers.

7. The method for forming a semiconductor structure according to claim 6, wherein, The step of forming the mask sidewalls includes: forming discrete core layers on the substrate; forming the mask sidewalls on sidewalls of the core layers. The method for forming the semiconductor structure further includes: after forming the mask sidewalls and before patterning the target layer, removing the core layers.

8. The method for forming a semiconductor structure according to claim 7, wherein, In the step of forming the core layers, multiple adjacent core layers form a support core layer, and a single core layer forms a sacrificial core layer. The method for forming the semiconductor structure further includes: after forming the core layers and before forming the mask sidewalls, removing the sacrificial core layers located in the cutting region. Alternatively, in the step of forming the mask sidewall, the sacrificial core layer and the mask sidewall located on the sidewall of the sacrificial core layer form a sacrificial pattern layer; after forming the mask sidewall and before patterning the target layer, the sacrificial pattern layer located in the dicing area is removed.

9. The method for forming a semiconductor structure according to claim 8, wherein, Removing the sacrificial pattern layer located in the dicing area includes: after forming the mask sidewall and before removing the core layer, removing the sacrificial pattern layer located in the dicing area; Alternatively, after removing the core layer and before patterning the target layer, the mask sidewall in the sacrificial pattern layer located in the dicing area is removed.

10. The method for forming a semiconductor structure according to claim 6, wherein, In the step of providing the substrate, the substrate further includes a hard mask material layer located on the target layer; After forming the mask sidewall and before patterning the target layer, the method for forming the semiconductor structure further includes: using the mask sidewall as a mask to pattern the hard mask material layer to form a hard mask layer; The boundary definition groove also penetrates the hard mask layer located transversely at the boundary between the target area and the dicing area; in the step of forming the spacer layer, the spacer layer covers the sidewalls of the hard mask layer; After forming the spacer layer and before etching the initial pattern layer located in the dicing area, the method for forming the semiconductor structure further includes: removing the hard mask layer located in the dicing area to expose the top of the initial pattern layer in the dicing area.

11. The method for forming a semiconductor structure as described in claim 6, wherein, The step of forming the boundary definition groove includes: forming a boundary definition mask layer covering the initial pattern layer, and forming a boundary definition opening in the boundary definition mask layer located transversely at the boundary between the target area and the dicing area; using the boundary definition mask layer as a mask to etch the initial pattern layer along the boundary definition opening to form the boundary definition groove; removing the boundary definition mask layer.

12. The method for forming a semiconductor structure as claimed in claim 11, wherein, The process of etching the initial pattern layer along the boundary definition opening includes an anisotropic dry etching process.

13. The method for forming a semiconductor structure according to claim 6, wherein The process of forming the spacer layer includes one or more of a flowable chemical vapor deposition process, an atomic layer deposition process, and a spin coating process.

14. The method for forming a semiconductor structure according to claim 6, wherein, The process of etching the initial pattern layer located in the dicing area includes an isotropic etching process.

15. The method for forming a semiconductor structure according to claim 6, wherein, The process of etching the initial pattern layer located in the dicing area includes one or more of a wet etching process, a remote plasma etching process, an inductively coupled plasma etching process, and a capacitively coupled plasma etching process.

16. The method for forming a semiconductor structure according to claim 6, wherein, In the step of etching the initial pattern layer located in the dicing area, the etching selectivity between the initial pattern layer and the spacer layer is at least 4:

1.

17. The method for forming a semiconductor structure according to claim 6, wherein, The target pattern layer is a fin, a channel stack, a gate structure, a pattern transfer layer, or a dielectric isolation layer.

18. The method for forming a semiconductor structure according to claim 6, wherein The target area is an active area, and the dicing area is an isolation area; the initial pattern layer is an initial fin, and the target pattern layer is a fin; During the process of etching the initial pattern layer located in the dicing area, the initial fin located in the dicing area is etched to form a residual pseudo fin located in the dicing area.

19. The method for forming a semiconductor structure according to claim 6, wherein, The target area is an active area, and the dicing area is an isolation area; the initial pattern layer is an initial fin, and the target pattern layer is a fin; the material of the spacer layer is a dielectric material; In the step of etching the initial pattern layer located in the cutting area, cutting grooves are formed in the spacer layer; After etching the initial pattern layer located in the cutting area, the method for forming the semiconductor structure further includes: forming a filling isolation layer in the cutting grooves; Removing a part of the thickness of the filling isolation layer and the spacer layer to expose a part of the sidewalls of the fins, and the remaining filling isolation layer and spacer layer are used as an isolation structure.

20. The method for forming a semiconductor structure according to claim 19, wherein, The process for forming the filling isolation layer includes one or both of a flowable chemical vapor deposition process and an atomic layer deposition process.

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