Electronic device with a secondary phase generation circuit

Abstract

The present disclosure relates to electronic devices with a quadratic phase generation circuit. An electronic device can include wireless circuitry. The wireless circuitry can include a quadratic phase generator for an outputting a full interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator can include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator can receive a chirp count and a word length as inputs. The switch can be configured to switchably feed back one of two input values as a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator can output a full bandwidth chirp or a reduced bandwidth chirp. Bandwidth reduction can be achieved by scaling the two input values of the switch.

Description

[0001] Related application citation

[0002] This application is a divisional application of Chinese national application number 202210652822.2, filed on June 8, 2022, entitled "Electronic device with a secondary phase generation circuit".

[0003] This application claims priority to U.S. Patent Application No. 17 / 468482, filed September 7, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0004] This disclosure relates in general to electronic devices, and more specifically to electronic devices having wireless circuitry. Background Technology

[0005] Electronic devices often possess wireless capabilities. Wireless electronic devices have wireless circuitry that includes one or more antennas. Wireless circuitry is sometimes used to perform spatial ranging operations, where radio frequency signals are used to estimate the distance between the electronic device and external objects.

[0006] Designing a wireless circuit that accurately estimates this distance can be challenging. To perform spatial ranging operations, wireless circuits sometimes generate constant-amplitude zero-autocorrelation (CAZAC) sequences, such as the Zadoff-Chu sequence. However, the conventional generation of the Zadoff-Chu sequence still produces results with quantization errors, leading to inaccurate distance estimations. Summary of the Invention

[0007] Electronic devices may include wireless circuitry. Wireless circuitry may include spatial ranging circuitry and antennas. In one embodiment described herein as an example, the spatial ranging circuitry includes radar circuitry, such as frequency-modulated continuous wave (FMCW) radar circuitry. The radar circuitry may include a secondary phase generator in the transmission path. The secondary phase generator may output an interpolated constant amplitude zero autocorrelation (CAZAC) sequence, which may be fed back by one or more digital-to-analog converters (DACs) to generate an analog signal ultimately transmitted by the antenna. Because DACs have limited bandwidth and band edges are always subject to interference (e.g., by anti-aliasing circuitry), the CAZAC sequence must be interpolated. The secondary phase generator may include a switch, a numerically controlled oscillator for controlling the switch, a first integrator stage configured to receive signals from the switch, and a second integrator stage connected in series with the first integrator stage. When the numerically controlled oscillator outputs a value less than or equal to a threshold level, the switch may output a first value proportional to the chirp count q to the first integrator stage. When the numerically controlled oscillator output exceeds a threshold level, the switch can optionally output a second value proportional to the difference between the chirp count q and the word length M. The interpolation of the CAZAC sequence can be adjusted using a weighting coefficient b, thus allowing the transmission of chirps with variable bandwidth at a fixed DAC sampling frequency. The interpolated CAZAC sequence generated in this way exhibits q chirs, each with a different quadratic phase response, which translates into a linear instantaneous frequency response, with no frequency outliers between the chirs.

[0008] One aspect of this disclosure provides a wireless circuit comprising: at least one digital-to-analog converter (DAC) having an input and an output coupled to an antenna; and a secondary phase generator having: an output port coupled to the input of the at least one DAC, a first integrator stage having an input and an output, a second integrator stage having an input coupled to the output of the first integrator stage and an output connected to the output port, and a switch having a first input, a second input, and an output coupled to the input of the first integrator stage. The secondary phase generator can be configured to output a constant amplitude zero autocorrelation (CAZAC) sequence at the output port. CAZAC sequences are fully interpolated in almost all practical applications and are therefore sometimes referred to as interpolated CAZAC sequences. The first input of the switch can receive a first value, which is a function of a chirp count q that defines the number of chirps in the CAZAC sequence. The second input of the switch can receive a second value, which is a function of the chirp count q and a word length M that defines the number of samples in the CAZAC sequence. The first and second values ​​may optionally be multiplied by a scaling factor b to reduce the bandwidth of the secondary phase generator. The secondary phase generator may include a numerically controlled oscillator for controlling a switch configured to connect a first input of the switch to the output of the switch when the value output by the numerically controlled oscillator is less than or equal to a threshold, and to connect a second input of the switch to the output of the switch when the value output by the numerically controlled oscillator is greater than the threshold.

[0009] One aspect of this disclosure provides a method for operating a wireless circuit. The method may include receiving a digital signal at a digital-to-analog converter and converting the digital signal into an analog signal for transmission via an antenna, and outputting an interpolated constant-amplitude zero-autocorrelation (CAZAC) sequence from a secondary phase generator. The digital signal received at the digital-to-analog converter can be generated based on the interpolated CAZAC sequence output from the secondary phase generator. Operating the secondary phase generator may involve: controlling a switch to selectively output a first value and a second value to a first integrator stage, receiving a signal from the first integrator stage at a second integrator stage, and outputting the interpolated CAZAC sequence from the second integrator stage.

[0010] The method may further include: controlling a switch based on a value output from a numerically controlled oscillator, periodically incrementing the value output from the numerically controlled oscillator, and determining whether the value output from the numerically controlled oscillator exceeds a threshold. In response to determining that the value output from the numerically controlled oscillator does not exceed the threshold, the switch may output a first value to a first integrator stage. In response to determining that the value output from the numerically controlled oscillator exceeds the threshold, the switch may output a second value to the first integrator stage, wherein the second value is less than the first value.

[0011] One aspect of this disclosure provides an electronic device comprising: a baseband transmitter having a secondary phase generator configured to output an interpolated constant-amplitude zero autocorrelation (CAZAC) sequence; a digital-to-analog converter (DAC) having an input configured to receive a signal generated based on the interpolated CAZAC sequence and an output coupled to a first antenna; a first channel filter interposed between the baseband transmitter and the input of the DAC; an analog-to-digital converter (ADC) having an input coupled to the second antenna and an output having a digital signal generated thereon; a baseband receiver having an input configured to receive a signal generated based on the digital signal output from the ADC; and a second channel filter interposed between the output of the ADC and the input of the baseband receiver. The first and second channel filters may have the same bandwidth as the secondary phase generator. The electronic device may further include offset correction circuitry interposed between the output of the ADC and the second channel filter, and delay compensation circuitry coupled between the baseband transmitter and the baseband receiver. Attached Figure Description

[0012] Figure 1 It is a functional block diagram of an exemplary electronic device with wireless circuitry according to some implementation schemes.

[0013] Figure 2 This is a circuit diagram of an exemplary digital polarity transmitter circuit with a secondary phase generator according to some implementation schemes.

[0014] Figure 3 This is a circuit diagram of an exemplary IQ transmitter circuit with a secondary phase generator according to some implementation schemes.

[0015] Figure 4 This is a block diagram of an exemplary full-bandwidth secondary phase generator based on some implementation schemes.

[0016] Figure 5A It is based on the drawing of some implementation plans. Figure 4 The diagram shows the output phase of a full-bandwidth secondary phase generator.

[0017] Figure 5B It is based on the drawing of some implementation plans. Figure 4 A diagram showing the instantaneous frequency of a full-bandwidth quadratic phase generator.

[0018] Figure 5C It is based on the drawing of some implementation plans. Figure 4 A diagram illustrating the instantaneous frequency difference of a full-bandwidth secondary phase generator.

[0019] Figure 6 This is a block diagram of an exemplary band-limited secondary phase generator based on some implementation schemes.

[0020] Figure 7A It is based on the drawing of some implementation plans. Figure 6 A diagram illustrating the output phase of a band-limited secondary phase generator.

[0021] Figure 7B It is based on the drawing of some implementation plans. Figure 6 A diagram showing the instantaneous frequency of a band-limited secondary phase generator.

[0022] Figure 7C It is based on the drawing of some implementation plans. Figure 6 A diagram illustrating the instantaneous frequency difference of a band-limited secondary phase generator.

[0023] Figure 8 This is a block diagram of an exemplary secondary phase generator without a numerically controlled oscillator, based on some implementation schemes.

[0024] Figure 9A It is a diagram of the instantaneous frequency of a quadratic phase generator with four chirps and a word length of 101, based on some implementation schemes.

[0025] Figure 9B It is a diagram of the instantaneous frequency of a quadratic phase generator with five chirps and a word length of 101, based on some implementation schemes.

[0026] Figure 9C This is a diagram illustrating the instantaneous frequency of a secondary phase generator with negative seven chirps and a word length of 101, based on some implementation schemes.

[0027] Figure 10A It is a diagram of the sorted instantaneous frequencies of all chirp counts based on some implementation schemes.

[0028] Figure 10B It is a diagram of the sorted instantaneous frequency differences of all chirp counts based on some implementation schemes.

[0029] Figure 11 This is a flowchart illustrating exemplary steps for operating a secondary phase generator according to some implementation schemes.

[0030] Figure 12 This is a diagram of a wireless circuit with a channel filter configured with the same bandwidth as the secondary phase generator, according to some implementation schemes. Detailed Implementation

[0031] Figure 1The electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a wristband, a headset or handset, a device embedded in glasses; or other equipment worn on a user's head; or other wearable or micro-devices, televisions, computer monitors without an embedded computer, gaming devices, navigation devices, embedded systems (such as systems in which electronic equipment with a display is installed in a kiosk or vehicle), voice-controlled speakers connected to the wireless Internet, home entertainment devices, remote control devices, game controllers, peripheral user input devices, wireless base stations or access points, equipment that enables the functions of two or more of these devices; or other electronic equipment.

[0032] like Figure 1 As shown in the functional block diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as an outer casing) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations thereof. In some cases, housing 12 may be partially or entirely formed of dielectric or other low-conductivity materials (e.g., glass, ceramic, plastic, sapphire, etc.). In other cases, housing 12, or at least some of the structures constituting housing 12, may be formed of metallic elements.

[0033] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage circuitry 16. Storage circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage circuitry 16 may include storage devices and / or removable storage media integrated within device 10.

[0034] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application-specific integrated circuits, central processing units (CPUs), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage circuitry 16 (e.g., storage circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage circuitry 16 may be executed by processing circuitry 18.

[0035] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include: Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as...). Protocols for other short-range wireless communication links, such as This protocol may be any of the following: wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G, 4G (LTE), 5G, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS), Global Navigation Satellite System (GLONASS), etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols for signals transmitted at millimeter and centimeter wave frequencies or other desired distance detection protocols), or any other desired communication protocol. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies the physical connection method used to implement the protocol.

[0036] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be supplied from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays (e.g., touch-sensitive displays and / or force-sensitive displays), light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses for detecting motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice and joysticks, and other input-output devices may be coupled to device 10 via wired or wireless connections (e.g., some of the input-output devices 22 may be peripherals coupled to the main processing unit or other parts of device 10 via wired or wireless links).

[0037] Input-output circuitry 20 may include wireless circuitry 24 to support wireless communication. Wireless circuitry 24 (sometimes referred to herein as wireless communication circuitry 24) may include two or more antennas 40. Wireless circuitry 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, RF transmission lines, and / or any other circuitry for transmitting and / or receiving RF signals using antennas 40.

[0038] Wireless circuit 24 can transmit and / or receive radio frequency signals within a corresponding frequency band of a radio frequency (sometimes referred to herein as a communication band or simply a "band"). The frequency band processed by wireless circuit 24 may include a wireless local area network (WLAN) band (e.g., (IEEE 802.11) or other WLAN communication bands, such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz) and / or others Frequency bands (e.g., 1875MHz to 5160MHz); Wireless Personal Area Network (WPAN) frequency bands such as 2.4GHz Frequency bands or other WPAN communication bands; cellular telephone bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G NR frequency range 1 (FR1) band below 10 GHz, 5G NR frequency range 2 (FR2) band between 20 GHz and 60 GHz, etc.); other centimeter or millimeter wave bands between 10 GHz and 300 GHz; near-field communication bands (e.g., 13.56 MHz); satellite navigation bands (e.g., GPS bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) bands, BeiDou Navigation Satellite System (BDS) bands, etc.); ultra-wideband (UWB) bands operating under the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; communication bands under the 3GPP wireless communication standard family; communication bands under the IEEE 802.XX standard family, and / or any other desired bands of interest.

[0039] Antenna 40 can be formed using any desired antenna structure. For example, antenna 40 may include an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole, a combination of these designs, etc. Adjustable filter circuits, switching circuits, impedance matching circuits, and / or other antenna tuning components can be used to adjust the frequency response and wireless performance of antenna 40 over time.

[0040] The radio frequency signals processed by antenna 40 can be used to transmit wireless communication data between device 10 and external wireless communication devices (e.g., one or more other devices such as device 10). The wireless communication data can be transmitted bidirectionally or unidirectionally by wireless circuit 24. The wireless communication data may include, for example, data encoded into corresponding data packets, such as wireless data associated with telephone calls, streaming media content, internet browsing, wireless data associated with software applications running on device 10, email messages, etc.

[0041] Wireless circuit 24 may additionally or alternatively use antenna 40 to perform spatial ranging operations. When wireless circuit 24 both transmits wireless communication data and performs spatial ranging operations, one or more of the same antennas 40 may be used for both. In another embodiment, wireless circuit 24 may include a set of antennas 40 for transmitting wireless communication data only and a set of antennas 40 for performing spatial ranging operations only.

[0042] When performing spatial ranging operations, antenna 40 can transmit radio frequency (RF) signal 36. Wireless circuit 24 can transmit RF signal 36 in a corresponding RF frequency band (e.g., a band including frequencies greater than about 10 GHz, greater than about 20 GHz, less than 10 GHz, etc.). RF signal 36 can be reflected away from an object outside device 10 (such as external object 34). External object 34 can be, for example, the ground, a building, a wall, furniture, a ceiling, a person, a body part, an animal, a vehicle, a landscape or geographical feature, an obstacle, or any other object or entity outside device 10. Antenna 40 can receive reflected RF signal 38. Reflected signal 38 can be a reflected version of the transmitted RF signal 36, which is reflected away from external object 34 and transmitted back to device 10.

[0043] Control circuit 14 can process the transmitted radio frequency signal 36 and the received reflected signal 38 to detect or estimate the range (distance) R between device 10 and external object 34. If needed, control circuit 14 can also process the transmitted and received signals to identify the two-dimensional or three-dimensional spatial position (azimuth) of external object 34, the velocity of external object 34, and / or the angle of arrival of reflected signal 38. In one embodiment described herein as an example, wireless circuit 24 performs spatial ranging operations using a frequency modulated continuous wave (FMCW) radar scheme. This is merely illustrative, and other radar schemes or spatial ranging schemes (e.g., OFDM radar schemes, FSCW radar schemes, phase-coded radar schemes, etc.) can typically be used.

[0044] like Figure 1 As shown, wireless circuit 24 may include transmit (TX) circuitry 26. Transmit circuitry 26 may include a transmit signal generator, such as signal generator 50. Transmit signal generator 50 generates a signal for transmission via antenna 40. In some specific embodiments described herein as examples, transmit signal generator 50 includes a chirp generator that generates a chirped signal for transmission via antenna 40 (e.g., in an embodiment where wireless circuitry 24 uses an FMCW radar scheme). Therefore, transmit signal generator 50 may sometimes be referred to herein as a chirp generator. Transmit circuitry 26 may also include digital-to-analog converter (DAC) circuitry, such as DAC 30. DAC 30 converts the transmitted signal (e.g., the chirped signal) from the digital domain to the analog domain before transmission by antenna 40.

[0045] Wireless circuit 24 may also include receiving (RX) circuitry 28. Receiving circuitry 28 may include analog-to-digital converter (ADC) circuitry, such as ADC 32. ADC 32 converts the radio frequency signal received from antenna 40 from the analog domain to the digital domain for subsequent processing by control circuitry 14. Although for clarity, in Figure 1In the example, control circuitry 14 is shown separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18, and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). For example, wireless circuitry 24 may include a baseband processor, which can be considered part of processing circuitry 18.

[0046] The transmitting circuit 26 can be implemented using a variety of different RF transmitter architectures. Figure 2 Circuit 26, implemented as a digital polarity transmitter, is shown. Figure 2 As shown, the digital polarity transmitter circuit 26 may include: a transmit signal generator 50 configured to output a transmit signal, a differentiator 52 configured to differentiate with respect to time or calculate the derivative of the transmit signal, upsampling circuits 54 and 58, an oscillation circuit (such as a digitally controlled oscillator 56, a data converter (such as a digital-to-analog converter (DAC) 30)), a filtering circuit (such as a bandpass filter 60), and one or more power amplifiers 62.

[0047] According to some implementations, the transmit signal generator 50 can be configured to generate constant-amplitude zero-autocorrelation (CAZAC) sequences. As the name suggests, CAZAC sequences have two distinguishing properties. The first property of any CAZAC sequence is that the sequence has a constant amplitude. In other words, when the numbers in the CAZAC sequence are plotted on the complex plane, they will all lie on a circle. The second property of any CAZAC sequence is that the correlation between a given sequence and an offset version of that given sequence will be approximately zero. In other words, the two sequences are orthogonal. Generating orthogonal sequences with constant amplitude can be used in radar and many wireless applications. For high-quality transmission, it may be preferable to use the transmit signal generator 50 to generate interpolated CAZAC sequences.

[0048] One way to generate CAZAC sequences is to use a signal generator that can output a signal with a quadratic phase. This type of CAZAC sequence generator is sometimes called a quadratic phase generator. Figure 2The transmit signal generator 50 can be a quadratic phase generator capable of outputting one or more CAZAC sequences. The signal output from the quadratic phase generator 50 can be fed back to the digital-to-analog converter 30 via an upsampling circuit 58. The upsampling circuit 58 can perform upsampling or upconversion operations. The signal output from the quadratic phase generator 50 can also be fed back to the digitally controlled oscillator 56 via a differentiator 52 and an upsampling circuit 54. The differentiator 52 can be configured to calculate the derivative of the signal with a quadratic phase waveform with respect to time, which produces an instantaneous frequency that is a linear function of time. Therefore, the signal generator 50 is sometimes also referred to as a linear frequency generator or a linear instantaneous frequency generator. This linear instantaneous frequency can be upsampled or upconverted by the upsampling circuit 54 before being received by the digitally controlled oscillator 56. The digitally controlled oscillator 56 may have an output coupled to the control input of the digital-to-analog converter 30.

[0049] The digital-to-analog converter 30 can output a corresponding analog signal that can be filtered using a bandpass filter 60. The filtered signal can then be amplified by one or more power amplifiers 62 before being radiated by the antenna 40. This example, which includes at least upsampling circuitry, a digital-to-analog converter, a bandpass filter, and a power amplifier in the transmission path, is merely illustrative. If desired, the transmitter circuitry 26 may include: additional digital components coupled to or inserted before the DAC 30, fewer digital components, additional analog front-end components coupled to or inserted after the DAC 30, fewer analog front-end components and / or additional filters, switching or coupling circuitry. Because the DAC has a limited bandwidth and its band edges are almost always subject to interference (e.g., by associated anti-aliasing circuitry), the CAZAC sequence generated by the secondary phase generator 50 should be fully interpolated in almost all practical applications.

[0050] Figure 2 The digital polarity emitter architecture shown is merely an example. Figure 3 Circuit 26, implemented as an IQ transmitter, is shown. Figure 3 As shown, the IQ transmitter circuit 26 may include: a secondary phase generator 50 configured to output a signal with a secondary phase; an IQ conversion circuit (such as an IQ converter 70) configured to output in-phase (I) and quadrature (Q) signals; a first digital-to-analog converter (DAC) 74-1 configured to convert the in-phase signal to the analog domain; a second digital-to-analog converter (DAC) 74-2 configured to convert the quadrature signal to the analog domain; a digitally controlled oscillator 72 for controlling the two DACs 74-1 and DAC 74-2; a summing circuit (such as a combiner 76); a filtering circuit (such as a bandpass filter 78); and one or more power amplifiers 80. DACs 74-1 and DAC 74-2 may be... Figure 1 The boxes 30 in the text are collectively represented.

[0051] In some implementations, an upsampling circuit may be inserted between the IQ converter 70 and DACs 74-1 and 74-2. In such cases, the additional upsampling circuitry may be configured to upsample or upconvert the IQ signal prior to the digital-to-analog conversion step. In yet other implementations, a filtering circuit (such as a low-pass filter) may be inserted between the DAC and the combiner 76. If desired, an additional mixer may be inserted between the DAC and the combiner 76. For example, these additional mixers may be used to modulate the analog signal to an intermediate frequency range between the baseband frequency and the transmit RF. In such cases, another set of mixers may be inserted between the bandpass filter 78 and the power amplifier and used to further modulate the analog signal from the intermediate frequency range to the transmit RF.

[0052] The transmit path includes at least an IQ converter, multiple DACs, a DCO, a summing circuit, a bandpass filter, and a power amplifier. Figure 3 The examples are merely illustrative. If desired, the IQ transmitter circuitry 26 may include: additional digital components coupled to or inserted before the DAC 74, fewer digital components, additional analog front-end components coupled to or inserted after the DAC 74, fewer analog front-end components and / or additional filters, switching or RF coupling circuitry. Typically, the secondary phase generator 50 can be incorporated into any radar, analog front-end, or wireless communication architecture.

[0053] Figure 4 This is a block diagram illustrating a specific implementation of the secondary phase generator 50. (See diagram for example.) Figure 4 As shown, the secondary phase generator 50 may include: switches (such as switch 98), control circuitry (such as numerically controlled oscillator (NCO) 100), adder circuitry (such as adders 102 and 104), and delay circuitry (such as delay circuitry 106 and 108).

[0054] The secondary phase generator 50 is typically a function of two inputs: (1) a chirp count q and (2) a word length M. The chirp count q represents the total number of chirps in each sequence. The word length M represents the number of sampled elements for each CAZAC sequence as a function of time (e.g., M equals the number of samples per sequence). Typically, the chirp count q can be any positive or negative integer, such as ±3, ±4, ±5, ±6, ±7, ±8, ±9, ±(10 to 100) or more. The value of the word length M should be an integer such that the greatest common divisor of q and M is equal to 1. Typically, the word length M is at least greater than 10, 10 to 100, at least 100 or more, 100 to 200, at least 200 or more, etc. These values ​​are merely exemplary and are not intended to limit the scope of this embodiment.

[0055] The numerically controlled oscillator (NCO) 100 may have: a first input configured to receive the absolute value of a chirp count q, a second input configured to receive a word length M, and an output coupled to a switch 98. The oscillator 100 may output an integrator value at its output that determines the state of the switch 98. The switch 98 may have: a first switch input port configured to receive twice the chirp count q, a second switch input port configured to receive the amount of the chirp count q minus twice the difference between the product of the sign chirp count q and the word length M, and a switch output port. When the NCO 100 outputs an integrator value less than or equal to a threshold, the switch 98 may connect the first switch input port to the switch output port (e.g., causing the adder 102 to receive 2*q). When the NCO 100 outputs an integrator value greater than the threshold, the switch 98 may connect the second switch input port to the switch output port (e.g., causing the adder 102 to receive 2*(q – sign(q)*M)). The predetermined threshold can be equal to M (as an example). The threshold can be a fixed number or it can be programmable.

[0056] Adder 102 may have a first adder input, a second adder input, and an adder output coupled to the switch output port. Delay circuit 106 may have a first input coupled to the adder output of adder 102, a second input configured to receive a preset signal, and an output fed back to the second adder input of adder 102 via feedback path 110. The preset signal helps reset (initialize) delay circuit 106 to a predetermined (preset) value. Coupled in this way, adder 102, delay circuit 106, and feedback path 110 can operate as a first integrator (accumulator) stage.

[0057] Adder 104 may have a first adder input, a second adder input, and an adder output coupled to the output of delay circuit 106. Delay circuit 108 may have a first input coupled to the adder output of adder 104, a second input configured to receive a start signal, and an output fed back to the second adder input of adder 104 via feedback path 112. The start signal helps reset (initialize) delay circuit 106 to zero (by way of example). Coupled in this way, adder 104, delay circuit 108, and feedback path 112 can operate as a second integrator (accumulator) stage. The output of delay circuit 108 is coupled to the final output port Out of secondary phase generator 50, at which a signal with a secondary phase is generated. Typically, the preset signal and the start signal can be set to any suitable value for initializing or resetting secondary phase generator 50.

[0058] With this configuration, therefore Figure 4The secondary phase generator 50 is capable of summing two instantaneous frequency increments within a single symbol M sample, as shown in Equation 1 below:

[0059]

[0060] The weighted sum of zeros ensures that the secondary phase generator 50 produces the minimum quantization error.

[0061] Figure 5A It is for drawing a sequence. Figure 4 A diagram illustrating the output phase of a secondary phase generator 50 of the described type, where the chirp count q equals 3 and the word length M equals 100. The output phase is normalized (i.e., partitioned) by a coefficient π. Figure 5A As shown, the sequence can be divided into three chimes (since q = 3), each chime having a quadratic phase profile. The phase of the sequence wraps around three times and begins and ends with the same phase value. Unlike a conventional CAZAC sequence generator that outputs multiple identical chimes, the different chimes generated by the quadratic phase generator 50 are slightly different (e.g., each chime exhibits a different corresponding magnitude response). Therefore, a quadratic phase generator is defined as a circuit configured to output a signal with one or more chimes, each chime having a quadratic phase response, such as... Figure 5A As shown in the example.

[0062] Figure 5B Is drawing corresponding to Figure 5A A diagram illustrating the instantaneous frequency of the second-order phase profile. In other words, through differentiation or calculation. Figure 5A To obtain the derivative of the sample in Figure 5B The curve. For example... Figure 5B As shown, the sequence is again divided into three chirps (since q = 3), each chirp exhibiting a linear instantaneous frequency extending from approximately -π to approximately +π before wrapping around to -π. There are no frequency outliers between the chirps.

[0063] Figure 5C Is drawing corresponding to Figure 5B A graph of the instantaneous frequency difference of the linear instantaneous frequency profile. Similarly, through differentiation or calculation... Figure 5B To obtain the derivative of the sample in Figure 5C The curve. For example... Figure 5CAs shown, the instantaneous frequency difference can be two constant values: a higher value equal to the absolute value of q and a lower value equal to q minus the absolute value of M. Therefore, the difference between the higher value at the first input of the switch and the second value at the second input of the switch is proportional to the word length M. When the sequence wraps around between chimes (e.g., when wrapping from the first chime to the second chime and from the second chime to the third chime), this instantaneous frequency difference only switches to the lower value. These two constant values ​​can correspond to the values ​​at the input of switch 98 (see...). Figure 4 ).

[0064] The Δ between the higher and lower values ​​is equal to 2π. Therefore, combining... Figure 4 , Figure 5A , Figure 5B and Figure 5C The described quadratic phase generator 50 is sometimes referred to as a "full-bandwidth" quadratic phase generator. A full-bandwidth quadratic phase generator, which only requires switching between two constant instantaneous frequency differences, is fairly simple to implement in hardware (see example...). Figure 4 (The topology is similar), thus consuming less circuit area. Compared to a conventional CAZAC sequence generator, Figure 4 The implementation of the secondary phase generator also consumes less power and provides enhanced performance.

[0065] Related to full-bandwidth secondary phase generator Figure 4 The implementation shown in Figure 5 is merely illustrative. In other implementations, it may be desirable to limit or reduce the operating bandwidth of the secondary phase generator 50. Figure 6 Another specific embodiment of a secondary phase generator 50 with limited bandwidth that also delivers interpolated CAZAC sequences is shown. To properly scale the bandwidth, a scaling (weighting) factor b can be applied to the two inputs of the NCO switch. Specifically, the scaling factor b can be a fraction of the numerator value, which is a weighted average of the two switch input values, and the numerator value of the bit width of the summing circuit in the scaling integrator (accumulator) stage.

[0066] like Figure 6 As shown, switch 98 may have a first switch input port configured to receive the amount of chirp count q multiplied by twice the scaling factor b, minus the product of the sign chirp count q and the word length M. When the numerically controlled oscillator 100 outputs an integrator value greater than a threshold, switch 98 may connect the first switch input port to the switch output port (e.g., causing adder 102 to receive 2*b*q). When the numerically controlled oscillator 100 outputs an integrator value less than or equal to the threshold, switch 98 may connect a second switch input port to the switch output port (e.g., causing adder 102 to receive 2*b*(q – sign(q)*M)). The predetermined threshold may be equal to M (as an example). The threshold may be a fixed number or may be programmable. Figure 6 The remaining structure of the secondary phase generator 50 can be similar to that already relative to Figure 4 The structure is described, and need not be repeated in detail to avoid obscuring this implementation scheme.

[0067] With this configuration, therefore Figure 6 The secondary phase generator 50 is capable of summing two instantaneous frequency increments within a single symbol M sample, as shown in Equations 2 and 3 below:

[0068]

[0069]

[0070] Equation 2 represents the sum when q is positive, while Equation 3 represents the sum when q is negative. In either case, the zero-weighted sum ensures that the quadratic phase generator 50 produces minimal quantization error even with a band-limited scaling factor b.

[0071] Figure 7A It is for drawing a sequence. Figure 6 A diagram illustrating the output phase of a secondary phase generator 50 of the described type, where the chirp count q equals 3 and the word length M equals 100. The output phase is normalized (i.e., partitioned) by a coefficient π. Figure 7A As shown, the sequence can be divided into three chimes (since q = 3), each chime having a quadratic phase profile. The phase of the sequence wraps around three times and begins and ends with the same phase value. Unlike a conventional CAZAC sequence generator that outputs multiple identical chimes, the different chimes generated by the quadratic phase generator 50 are again slightly different (e.g., each chime is slightly offset in its phase representation).

[0072] Figure 7B Is drawing corresponding to Figure 7A A diagram illustrating the instantaneous frequency of the second-order phase profile. In other words, through differentiation... Figure 7A To obtain samples from Figure 7B The curve. For example... Figure 7B As shown, the sequence is again divided into three chirps (since q = 3), each chirp exhibiting a linear instantaneous frequency ranging from approximately -0.625π to approximately +0.625π before the loop returns. There are no frequency outliers between the chirps.

[0073] Figure 7C Is drawing corresponding to Figure 7B A diagram illustrating the instantaneous frequency difference of the linear instantaneous frequency profile. Similarly, by distinguishing... Figure 7B To obtain samples from Figure 7C The curve. For example... Figure 7CAs shown, the instantaneous frequency difference can be two constant values: a higher value equal to the absolute value of q scaled by a factor b, and a lower value equal to q minus the absolute value of M (also scaled by a factor b). When the sequence loops between chirs (e.g., from the first chirp to the second chirp and from the second chirp to the third chirp), this instantaneous frequency difference only switches to the lower value. These two constant values ​​can correspond to the values ​​at the input of switch 98 (see [reference]). Figure 6 ).

[0074] In this specific example, the Δ between the higher and lower values ​​can be equal to 1.25π, which corresponds to a scaling factor b = 1.25 / 2. Typically, the scaling factor b can be any fraction or value less than 1. As examples, the scaling factor b can be equal to 0.5, 0.6, 0.7, 0.8, 0.6–0.7, 0.5–0.8, less than 0.99, less than 0.9, less than 0.8, less than 0.7, less than 0.6, and less than 0.5, etc. Therefore, combining... Figure 6 , Figure 7A , Figure 7B and Figure 7C The described quadratic phase generator 50 is sometimes referred to as a "band-limited" or "reduced bandwidth" quadratic phase generator. Such band-limited quadratic phase generators, which only require switching between two constant instantaneous frequency differences, are fairly simple to implement in hardware (see, for example...). Figure 6 (The topology is such that it consumes a small amount of circuit area). Figure 6 The reduced-bandwidth secondary phase generator is specifically implemented to generate a precise band-limited version of the full-bandwidth CAZAC sequence without any approximations.

[0075] A reduced-bandwidth secondary phase generator with a numerically controlled oscillator and associated switches is shown. Figure 6 The implementation plan is merely illustrative. Figure 8 Another embodiment of a reduced-bandwidth secondary phase generator 50 excluding switch 98 and numerically controlled oscillator 100 is shown. This type of secondary phase generator 50 can be used when the following conditions are met:

[0076] |b*qb*M|∈2 M (4)

[0077] |b*q+b*M|∈2 M (5)

[0078] Condition 4 is used for a positive value of the chirp count q, while condition 5 is used for a negative value of the chirp count q. If either condition 4 or condition 5 is met, the summing circuit 102 can always receive the product b*q, thus eliminating the need for a separate NCO integrator switch. This helps to further minimize the circuit area of ​​the secondary phase generator 50. Operating in this way, the wraparound of the integrator stage performs the desired subtraction function. Figure 8 The remaining structure of the secondary phase generator 50 can be similar to that already relative to Figure 4 The structure is described, and need not be repeated in detail to avoid obscuring this implementation scheme.

[0079] As mentioned above, the chirp count q can be any positive or negative integer. The only restriction on the value of the word length M is that the greatest common divisor between q and M must be equal to 1. Figures 9A to 9C The instantaneous frequencies of a band-limited quadratic phase generator 50 with different q and M values ​​were plotted. Figure 9A This is a diagram illustrating the instantaneous frequency of a band-limited quadratic phase generator with four chimes (e.g., q = 4) and a word length M of 101. The greatest common divisor of 4 and 101 is 1. Figure 9A As shown, the sequence is divided into four chimes, each exhibiting a slightly different linear instantaneous frequency response ranging from approximately -0.625π to approximately +0.625π before the loop returns. There are no frequency outliers between the chimes.

[0080] Figure 9B This is a diagram illustrating the instantaneous frequency of a band-limited quadratic phase generator with five chimes (e.g., q = 5) and a word length M of 101. The greatest common divisor of 5 and 101 is 1. Figure 9B As shown, the sequence is divided into five chimes, each exhibiting a slightly different linear instantaneous frequency response ranging from approximately -0.625π to approximately +0.625π before the loop returns. There are no frequency outliers between the chimes.

[0081] Having a positive chirp count value q Figure 9A and Figure 9B The examples are merely illustrative. Figure 9C This is a diagram illustrating the instantaneous frequency of a band-limited quadratic phase generator with seven chimes (e.g., q = -7) and a word length M of 101. The greatest common divisor of 7 and 101 is 1. Figure 9C As shown, the sequence is divided into seven chimes, each exhibiting a slightly different linear instantaneous frequency response ranging from approximately -0.625π to approximately +0.625π before the loop returns. No frequency outliers exist between consecutive chimes. Figure 9C and Figure 9A and Figure 9B By comparison, it is clear that positive q produces an increased linear instantaneous frequency response, while negative q produces a decreased linear instantaneous frequency response (e.g., Figure 9A and Figure 9B The linear response exhibits an upward slope, while Figure 9C The linear response has a downward slope.

[0082] Figure 10AThis is a diagram plotting the sorted instantaneous frequencies of all chirp counts with a word length M of 101. In other words, it plots all chirp counts from... Figure 9A The instantaneous frequency sample point sorting will generate Figure 10A The sorting curve. Similarly, all from Figure 9B The instantaneous frequency sample point sorting will generate Figure 10A The sorting curve. All from Figure 9C The instantaneous frequency sample point sorting will similarly produce Figure 10A The sorting curve. In other words, the sorting instantaneous frequency sample output from the band-limited quadratic phase generator is independent of the magnitude of q.

[0083] Figure 10B This is a diagram showing the sorted instantaneous frequency differences of all chirp counts. For example... Figure 10B As shown, the frequency step size between samples is a constant value independent of the magnitude of q.

[0084] Figure 11 This is a flowchart illustrating the exemplary operations involved in controlling the secondary phase generator 50. At block 200, the numerically controlled oscillator 100 can be initialized to a certain initial integrator value. At block 202, the numerically controlled oscillator 100 can increment the integrator value within each integrator cycle by subtracting the word length M from the absolute value of q and then subtracting the difference between the modulus of the absolute value of (q,2) and 1.

[0085] At block 204, the numerically controlled oscillator 100 determines whether the integrator value is greater than the word length M. In response to determining that the current integrator value is less than or equal to M, the oscillator can instruct the corresponding switch 98 to output the higher value at the first switch input to the adder 102 (see operation at block 206). This value can then be accumulated by the first integrator stage, and after some delay, it can be propagated to the second integrator stage.

[0086] In response to determining that the current integrator value is greater than M (e.g., if an integrator overflow event has been detected), oscillator 100 may instruct the corresponding switch 98 to output the lower value at the second switch input to adder 102 (see operation of block 208). This value can then be accumulated by the first integrator stage, and after some delay, it can propagate to the second integrator stage. The NCO value can then be decremented (e.g., decremented by 2*M) to perform a wraparound.

[0087] Figure 11 The operations described are merely illustrative. At least some of the operations described may be modified or omitted; some of the operations described may be executed in parallel; additional procedures may be added or inserted between the operations described; the order of some operations may be reversed or changed; the timing of the operations described may be adjusted so that they occur at slightly different times, or the operations described may be distributed throughout the system.

[0088] Figure 12 An example of a wireless circuit 24 for a frequency-modulated continuous wave (FMCW) radar scheme using a secondary phase generator 50 is shown. Figure 12 As shown, wireless circuit 24 may have a transmit path and a receive path. The transmit path may include: a baseband (BB) transmitter (such as baseband transmitter 150), an IQ conversion circuit (such as IQ converter 152), a filtering circuit (such as reconstruction filter 154), an upsampling circuit (such as upsampler 156), a data converter (such as digital-to-analog converter (DAC) 158), and a transmit antenna 40-1. Baseband transmitter 150 may include a secondary phase generator 50 for outputting an interpolated CAZAC sequence to the IQ converter (e.g., ...). Figure 4 The type of full-bandwidth quadratic phase generator shown Figure 6 The type of reduced bandwidth secondary phase generator shown is or Figure 8 (Simplified secondary phase generator of the type shown).

[0089] The IQ converter 152 (sometimes referred to as an IQ modulator) can be configured to output corresponding in-phase (I) and quadrature (Q) signals. A reconstruction filter 154 can be interposed between the IQ converter 150 and the upsampler 156. Specifically, the reconstruction filter 154 can have the same bandwidth as the secondary phase generator 50 and is sometimes referred to as a channel filter. If the secondary phase generator 50 exhibits full bandwidth, the filter 154 should have a bandwidth matching the full bandwidth of the generator 50. If the secondary phase generator 50 exhibits reduced bandwidth, the filter 154 should have a relatively smaller bandwidth matching the smaller bandwidth of the generator 50. The signal output from the reconstruction filter 154 can be fed back to the digital-to-analog converter 158 via the upsampling circuit 156. The upsampling circuit 156 can perform upsampling or upconversion operations. The digital-to-analog converter 158 can output a corresponding analog signal for transmission that can be fed back to the antenna 40-1.

[0090] This example, which includes at least an IQ converter, a reconstruction filter, upsampling circuitry, and a digital-to-analog converter in the transmit path, is merely illustrative. If desired, the transmit path may include: additional digital components coupled to or inserted before the DAC 30, fewer digital components, additional analog front-end components coupled to or inserted after the DAC 30 (e.g., one or more bandpass filters, one or more power amplifiers, and one or more mixers, etc.), fewer analog front-end components and / or additional filters, and switching or coupling circuitry.

[0091] The receiving path may include: antenna 40-2, a data converter (such as analog-to-digital converter 160), offset correction circuitry (such as offset correction circuitry 162), downsampling circuitry (such as downsampler 164), filtering circuitry (such as reconstruction filter 166), IQ conversion circuitry (such as IQ converter 168), and baseband receiver 170. This example of performing spatial ranging operations in wireless circuitry 24 by transmitting radio frequency signals using a first antenna 40-1 and receiving corresponding reflected radio frequency signals using a second, different antenna 40-2 is merely illustrative. In other embodiments, the transmitting and receiving paths may be coupled to one or more antennas within the same antenna 40.

[0092] continue Figure 12 For example, the radio frequency signal received by antenna 40-2 can be fed back to analog-to-digital converter (ADC) 160 for conversion. ADC 160 converts analog radio frequency signals into their digital equivalents. Offset correction circuitry 162 can be inserted between ADC 1600 and downsampler 164. Offset correction circuitry 162 provides fine delay adjustment to help mitigate any potential offset or tailing that may occur before downsampling operation. Downsampler 164 performs downsampling or downconversion operations.

[0093] A reconstruction filter 166 can be inserted between the downsampler 164 and the IQ converter 168. Specifically, the reconstruction filter 166 may have the same bandwidth as the secondary phase generator 50 and is sometimes referred to as a channel filter. If the secondary phase generator 50 exhibits full bandwidth, the filter 166 should have a bandwidth matching the full bandwidth of the generator 50. If the secondary phase generator 50 exhibits reduced bandwidth or limited bandwidth, the filter 166 should have a relatively small bandwidth matching the limited bandwidth of the generator 50. The signal output from the reconstruction filter 166 can be fed back to the IQ converter 168. The IQ converter 168 (sometimes called an IQ demodulator) converts the in-phase (I) and quadrature (Q) signals into baseband signals that can be received and processed by the baseband receiver 170.

[0094] This example, which includes at least an IQ converter, a reconstruction filter, downsampling circuitry, offset correction circuitry (e.g., delay adjustment circuitry), and an analog-to-digital converter in the receive path, is merely illustrative. If desired, the receive path may include: additional analog front-end components coupled to or inserted before the ADC 160 (e.g., additional filters, switching, or coupling circuitry), fewer analog front-end components, additional digital components coupled to or inserted after the ADC 160, and / or fewer digital components.

[0095] Delay circuitry 172 may be coupled between baseband transmitter 150 and baseband receiver 170. Delay circuitry 172 may be configured to provide a fixed or adjustable delay amount to help compensate for any internal delay between the transmit and receive paths. Therefore, delay circuitry 172 may sometimes be referred to as internal delay compensation circuitry. Baseband transmitter 150 and baseband receiver 170 are sometimes collectively referred to as a baseband processor, which can be considered as part of wireless circuitry 24 and processing circuitry 18 (see, for example...). Figure 1 ).

[0096] The above text combined Figures 1-12 The methods and operations described and operated may be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). The software code used to perform these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1 The storage circuit 16). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of device 10 (e.g., Figure 1 The processing circuitry (e.g., 18) performs the execution. The processing circuitry may include a microprocessor, a central processing unit (CPU), an application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry. Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 8 and Figure 12 The components can be implemented using hardware (e.g., circuit components, digital logic gates, etc.) and / or using suitable software.

[0097] According to an embodiment, a wireless circuit is provided, the wireless circuit comprising: at least one digital-to-analog converter having an input and an output coupled to an antenna; and a secondary phase generator having: an output port coupled to the input of the at least one digital-to-analog converter, a first integrator stage having an input and an output, a second integrator stage having an input coupled to the output of the first integrator stage and an output connected to the output port, and a switch having a first input, a second input, and an output coupled to the input of the first integrator stage.

[0098] According to another embodiment, the first integrator stage includes: a first adder having a second input, an output, and a first input coupled to the output of a switch, and a first delay circuit having an input coupled to the output of the first adder and an output coupled to the second input of the first adder via a first feedback path.

[0099] According to another embodiment, the second integrator stage includes: a second adder having a first input, a second input, and an output coupled to the output of the first delay circuit, and a second delay circuit having an input coupled to the output of the second adder and an output coupled to the second input of the second adder via a second feedback path.

[0100] According to another embodiment, the first delay circuit is reset to a preset value, and the second delay circuit is reset to a starting value different from the preset value.

[0101] According to another embodiment, a first input terminal of the switch is configured to receive a first value, which is a function of a chirp count q that defines the number of chirps at the output port; and a second input terminal of the switch is configured to receive a second value that is different from the first value.

[0102] According to another embodiment, the secondary phase generator is configured to output an interpolated constant amplitude zero autocorrelation (CAZAC) sequence at an output port; a first input of the switch is configured to receive a first value, which is a function of a chirp count q that defines the number of chirps in the interpolated CAZAC sequence; and a second input of the switch is configured to receive a second value, which is a function of the chirp count q and a word length M that defines the number of samples in the interpolated CAZAC sequence.

[0103] According to another embodiment, the secondary phase generator further includes a numerically controlled oscillator for controlling a switch, the switch being configured to connect a first input terminal of the switch to the output terminal of the switch when the value output by the numerically controlled oscillator is less than or equal to a threshold, and to connect a second input terminal of the switch to the output terminal of the switch when the value output by the numerically controlled oscillator is greater than the threshold.

[0104] According to another embodiment, the secondary phase generator is configured to output an interpolated constant amplitude zero autocorrelation (CAZAC) sequence at an output port; the first input of the switch is configured to receive a first value, which is a function of: (1) a chirp count q that defines the number of chirps in the interpolated CAZAC sequence and (2) a scaling factor b that limits the bandwidth of the secondary phase generator; and the second input of the switch is configured to receive a second value, which is a function of: (1) the chirp count q, (2) the scaling factor b and (3) the word length M that defines the number of samples in the interpolated CAZAC sequence.

[0105] According to another embodiment, the secondary phase generator is configured to output an interpolated constant amplitude zero autocorrelation (CAZAC) sequence at an output port; a first input of a switch is configured to receive a first value, which is a function of a chirp count q that defines the number of chirps in the interpolated CAZAC sequence; a second input of the switch is configured to receive a second value, which is a function of the chirp count q and a word length M that defines the number of samples in the interpolated CAZAC sequence, and the difference between the first value at the first input of the switch and the second value at the second input of the switch is proportional to the word length M.

[0106] According to another embodiment, the secondary phase generator is configured to output an interpolated constant amplitude zero autocorrelation (CAZAC) sequence at an output port, and the secondary phase generator includes a numerically controlled oscillator coupled to a switch, the numerically controlled oscillator having a first input configured to receive a chirp count q that defines the number of chirps in the interpolated CAZAC sequence and a word length M that defines the number of samples in the interpolated CAZAC sequence, the chirp count q being a positive integer or a negative integer, and the chirp count q and the word length M having a greatest common divisor equal to 1.

[0107] According to another embodiment, the secondary phase generator is configured to generate a sequence with multiple chirps at the output port, and each chirp in the sequence has a secondary phase response different from the other chirps in the sequence.

[0108] According to an embodiment, a method for operating a wireless circuit is provided, the method comprising: receiving a digital signal at a digital-to-analog converter and converting the digital signal into an analog signal for transmission via an antenna; and outputting an interpolated constant amplitude zero autocorrelation (CAZAC) sequence from a secondary phase generator, wherein the digital signal received at the digital-to-analog converter is generated based on the interpolated CAZAC sequence output from the secondary phase generator, and outputting the interpolated CAZAC sequence from the secondary phase generator comprises: controlling a switch to selectively output a first value and a second value to a first integrator stage, receiving a signal from the first integrator stage at a second integrator stage, and outputting the interpolated CAZAC sequence from the second integrator stage.

[0109] According to another embodiment, outputting an interpolated CAZAC sequence from a secondary phase generator includes: receiving a first value and a second value at a first adder in a first integrator stage, delaying the signal output from the first adder, and feeding the delayed signal back to the first adder.

[0110] According to another embodiment, outputting an interpolated CAZAC sequence from a secondary phase generator includes: receiving a delayed signal at a second adder in a second integrator stage, delaying the signal output from the second adder, and feeding back the delayed signal output from the second adder to the second adder.

[0111] According to another embodiment, outputting an interpolated CAZAC sequence from a secondary phase generator includes: controlling a switch based on a value output from a numerically controlled oscillator, periodically incrementing the value output from the numerically controlled oscillator, and determining whether the value output from the numerically controlled oscillator exceeds a threshold.

[0112] According to another embodiment, outputting an interpolated CAZAC sequence from a secondary phase generator includes: in response to determining that the value output from the numerically controlled oscillator does not exceed a threshold, controlling a switch to output a first value to a first integrator stage; and in response to determining that the value output from the numerically controlled oscillator exceeds the threshold, controlling a switch to output a second value to the first integrator stage, the second value being less than the first value.

[0113] According to another implementation, the first value is proportional to the chirp count q, which defines the number of chirps in the interpolated CAZAC sequence, and the second value is proportional to the difference between the chirp count q and the word length M, which defines the total number of elements in the interpolated CAZAC sequence.

[0114] According to another embodiment, the method includes reducing the bandwidth of the secondary phase generator by multiplying the first and second values ​​by a scaling factor less than 1.

[0115] According to an embodiment, an electronic device is provided, comprising: a transmitter having a secondary phase generator configured to output a constant amplitude zero autocorrelation (CAZAC) sequence; a digital-to-analog converter having an input configured to receive a signal generated based on the CAZAC sequence and an output coupled to a first antenna; a first channel filter interposed between the transmitter and the input of the digital-to-analog converter, the first channel filter having the same bandwidth as the secondary phase generator; an analog-to-digital converter having an input coupled to a second antenna and an output having a digital signal generated thereon; a receiver having an input configured to receive a signal generated based on the digital signal output from the analog-to-digital converter; and a second channel filter interposed between the output of the analog-to-digital converter and the input of the receiver, the second channel filter having the same bandwidth as the secondary phase generator.

[0116] According to another embodiment, the electronic device includes: an offset correction circuit inserted between the output of the analog-to-digital converter and a second channel filter, and a delay compensation circuit coupled between the transmitter and the receiver.

[0117] The foregoing description is merely illustrative and various modifications can be made to the described implementation scheme. The described implementation scheme can be implemented independently or in any combination.

Claims

1. A circuit comprising: First integrator; The second integrator is coupled to the output of the first integrator; and A switch, the switch having The first input is configured to receive the first value of the function as an argument. The second input is configured to receive a second value, which is different from the first value and is a function of the parameter. The output is coupled to the first integrator; as well as An oscillator is configured to receive the absolute value of the parameter and control the switch.

2. The circuit according to claim 1, wherein the first integrator comprises: An adder having a first input coupled to the output of the switch; and A delay circuit having an input coupled to the adder and an output coupled to a second input of the adder.

3. The circuit according to claim 1, wherein the parameter includes a count value.

4. The circuit according to claim 1, wherein the parameter includes a chirp count q, the chirp count q defining the number of chirps at the output port of the circuit.

5. The circuit of claim 1, wherein the second value received at the second input of the switch is also a function of word length M.

6. The circuit of claim 1, wherein the oscillator is controlled based on the parameters.

7. The circuit of claim 6, wherein the oscillator is further controlled based on the word length M.

8. The circuit of claim 1, wherein the oscillator is controlled based on the number of samples in the output sequence generated by the circuit.

9. A circuit comprising: First integrator; The second integrator is coupled to the output of the first integrator; A switch, the switch having The first input is configured to receive the first value of the function as an argument. The second input is configured to receive a second value, which is different from the first value and is a function of the parameter. The output is coupled to the first integrator; as well as An oscillator is configured to control the switch based on the parameters.

10. The circuit of claim 9, wherein the first integrator comprises: An adder having a first input coupled to the output of the switch; and A delay circuit having an input coupled to the adder and an output coupled to a second input of the adder.

11. The circuit of claim 9, wherein the parameter includes a chirp count q, the chirp count q defining the number of chirps at the output port of the circuit.

12. The circuit of claim 9, wherein the second value is a function of word length M.

13. The circuit of claim 9, wherein the parameter includes word length M.

14. A circuit comprising: Output port; A first integrator has an input configured to receive a value that is a function of a chirp count q, which defines the number of chirps at the output port; and The second integrator is coupled to the output of the first integrator.

15. The circuit of claim 14, wherein the first integrator includes a first delay circuit configured to be reset to a preset value.

16. The circuit of claim 15, wherein the second integrator includes a second delay circuit configured to be reset to a starting value different from the preset value.

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