Methods for detecting and correcting the risk of CPU misordered code execution

Abstract

This invention provides a detection method to eliminate the risk of CPU out-of-order code execution, comprising the following steps: finding the statement that creates shared memory and the returned pointer; finding all read / write statements that read or write to shared memory through the pointer; if the current read / write statement is a data write statement, checking whether a read / write statement using the same pointer immediately follows the end of the statement; if the current read / write statement is a data read statement, checking whether a data write statement using the same pointer immediately follows the end of the statement; if two consecutive read / write statements exist, continuing to search whether there is a statement guaranteeing atomic memory operation before the current read / write statement; if such a statement guaranteeing atomic memory operation is found, then there is no risk of CPU out-of-order code execution; otherwise, there is a risk of out-of-order code execution.

Description

Technical Field

[0001] This invention relates to the field of computer application technology, and in particular to a method for detecting and correcting the risk of CPU code execution out of order. Background Technology

[0002] CPU utilization is divided into user mode, system mode, and idle mode, representing the time the CPU spends executing in user mode, the time spent executing in the system kernel, and the time spent executing idle system processes, respectively. Excessive CPU idle time negatively impacts program performance. In modern high-performance CPU designs, when the CPU is processing an instruction that causes it to idle, it will switch to processing the next instruction that can be executed immediately; this is out-of-order execution. The purpose of out-of-order execution is to reduce CPU idle time and improve program performance, but it increases the complexity of CPU design and the risk of program errors. Out-of-order execution is an important criterion for testing CPU stability. For such complex designs, CPU designers need extensive theoretical and practical experience. Otherwise, the manufactured CPUs may have the risk of executing code out of order.

[0003] This application proposes a simplified detection method to avoid such risks. This has significant application value for software vendors who need to port software from the mainstream x86 processor platform to a domestically produced processor platform.

[0004] Some of the technical terms used in this application are as follows:

[0005] Shared memory: A communication mechanism in Linux systems used between different processes; it maps the same block of memory data to different processes, allowing multiple processes to operate on this memory simultaneously.

[0006] Atomic memory operations: When one process reads or writes to memory, other processes are prohibited from operating on the same memory.

[0007] Memory barrier: A type of synchronization barrier instruction, which is a synchronization point in the CPU's random access to memory operations, so that all read or write operations before this point can be completed before the operation after this point can be executed. Summary of the Invention

[0008] To address at least one technical problem in the prior art, embodiments of the present invention provide a method for detecting and correcting the risk of CPU misordered code execution. This method can locate statements in the source code that pose a risk of CPU misordered execution and provides a correction method. To achieve the above technical objectives, the technical solution adopted by embodiments of the present invention is as follows:

[0009] In a first aspect, embodiments of the present invention provide a detection method for eliminating the risk of CPU executing code out of order, comprising the following steps:

[0010] Locate the statements in the program that create shared memory and the pointers they return, i.e., the shared memory pointers;

[0011] Find all read and write statements in the program that use this pointer to read or write shared memory, and analyze these read and write statements one by one in the order they appear.

[0012] If the current read / write statement is a data write statement, check if a read / write statement using the same pointer immediately follows the end of the statement; if the current read / write statement is a data read statement, check if a data write statement using the same pointer immediately follows the end of the statement.

[0013] If two consecutive read / write statements exist, continue searching for statements that guarantee atomic memory operations before the current read / write statement. If such statements guaranteeing atomic memory operations are found, then there is no risk of the CPU executing code out of order; continue analyzing the next read / write statement.

[0014] If the aforementioned atomic memory operation guarantee statements are not found, then there is a risk of out-of-order execution of code by the CPU.

[0015] Furthermore, the search procedure specifically uses regular expression matching to find statements that create shared memory, based on the API provided by the computer operating system.

[0016] Secondly, embodiments of the present invention provide a method for eliminating the risk of CPU out-of-order code execution, comprising:

[0017] When the detection method described above detects that there is a risk of out-of-order execution of code by the CPU, a statement that ensures the sequential execution of memory operations is inserted between the two consecutive read and write statements, namely a memory barrier statement.

[0018] The beneficial effects of the technical solution provided by this invention are as follows: This application offers an effective solution to the current immaturity of domestic CPU architecture and the risk of out-of-order code execution. This application, through static analysis of source code, detects statements that may cause CPU out-of-order execution risks when multi-process programs use shared memory to transfer communication data, and provides risk avoidance methods to ensure the correct operation of the source code. This application has significant application value for software vendors who need to port software from the mainstream x86 processor platform to a domestic processor platform. Attached Figure Description

[0019] Figure 1 This is a flowchart of the detection and correction method in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] In the description of the embodiments of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0023] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0024] like Figure 1 As shown in the figure, this invention proposes a detection method and a correction method to eliminate the risk of CPU misordered code execution, including the following steps:

[0025] Step S201: Locate the statement in the program that creates shared memory;

[0026] Specifically, you can use regular expressions to find statements that create shared memory, based on the APIs provided by your computer's operating system.

[0027] Step S202: Obtain the pointer to the shared memory to be created;

[0028] Specifically, the pointer returned after creating shared memory can be obtained based on the result of S201;

[0029] Step S203: Locate all read / write statements that use this pointer to read or write to shared memory;

[0030] Step S204: Check whether a read / write statement that meets the following characteristics immediately follows the end of the read / write statement: Based on the result of S203, if the current read / write statement is a data write statement, check whether a read / write statement using the same pointer immediately follows the end of the statement; if the current read / write statement is a data read statement, check whether a data write statement using the same pointer immediately follows the end of the statement; if so, proceed to the next step; otherwise, go to step S208.

[0031] Step S205: Based on the result of step S204, if two adjacent read / write statements that meet the above characteristics are found, continue to search whether there is a statement that guarantees atomic memory operation before these two read / write statements; if such a statement that guarantees atomic memory operation is found, then there is no risk of CPU out-of-order execution of code, and proceed to step S208.

[0032] Step S206: If the above-mentioned memory atomic operation guarantee statement is not found, then when the CPU executes these two read and write statements out of order, there is a risk of code execution in an out-of-order manner.

[0033] Step S207: If there is a risk of out-of-order execution of code due to CPU out-of-order execution, the correction method is to insert a statement between the two statements to ensure the sequential execution of memory operations, i.e., a memory barrier statement.

[0034] Step S208: CPU out-of-order execution carries no risk of code execution out of order;

[0035] In step S209, continue searching for other unprocessed statements that read or write to the shared memory. If such a statement exists, proceed to S204; otherwise, end the process.

[0036] The following are examples of memory barrier statements and pointers to shared memory in the C language;

[0037] / / Memory barrier statements under ARM architecture

[0038] #define dsb(opt) asmvolatile("dsb " #opt : : : "memory")

[0039] #define mb() dsb(sy)

[0040] / / io_buffer->data is a pointer to a shared memory block

[0041] / / This shared memory is a data block used to store data.

[0042] struct TcpData * ptd = io_buffer->data; ...

[0043] / / Assigning values ​​to shared memory

[0044] ptd->sip="127.0.0.1";

[0045] ptd->sport=1024; ...

[0046] / / Memory barrier to prevent out-of-order execution

[0047] mb()

[0048] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A detection method for eliminating the risk of CPU misordered code execution, characterized in that, Includes the following steps: Locate the statements in the program that create shared memory and the pointers they return, i.e., the shared memory pointers; Find all read and write statements in the program that use this pointer to read or write shared memory, and analyze these read and write statements one by one in the order they appear. If the current read / write statement is a data write statement, check if a data read statement using the same pointer immediately follows the end of the statement; if the current read / write statement is a data read statement, check if a data write statement using the same pointer immediately follows the end of the statement. If two consecutive read / write statements exist, continue searching for statements that guarantee atomic memory operations before the current read / write statement. If such statements guaranteeing atomic memory operations are found, then the CPU will execute the code out of order without the risk of executing it out of order. Continue analyzing the next read / write statement; If the aforementioned atomic memory operation guarantee statements are not found, then there is a risk of out-of-order execution of code by the CPU.

2. The detection method for eliminating the risk of CPU misordered code execution as described in claim 1, characterized in that, The search procedure for statements that create shared memory is specifically based on the API provided by the computer operating system, using regular expression matching to find statements that create shared memory.

3. A method for eliminating the risk of CPU misordered code execution, characterized in that, When the detection method described in claim 1 or 2 detects a risk of out-of-order execution of CPU code, a statement that ensures the sequential execution of memory operations, namely a memory barrier statement, is inserted between the two consecutive read and write statements.

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