Method and apparatus for receiving an enable margin for a memory interface

Abstract

The invention relates to a method and apparatus for calibrating a memory interface, wherein the method and apparatus are capable of periodically readjusting the placement of a receive enable signal (411) to place the receive enable signal (411) in an optimal position relative to a DQS signal from an external memory device to achieve maximum timing margin, regardless of voltage or temperature drift and / or process aging of the integrated circuit.

Description

Technical Field

[0001] The present invention relates to a method and apparatus for calibrating a memory interface, wherein the method and apparatus are capable of periodically rearranging the arrangement of a receive enable signal so that the receive enable signal is in an optimal position relative to a DQS signal from an external memory device to achieve maximum timing margin, regardless of voltage or temperature drift and / or process aging of the integrated circuit. Background Technology

[0002] DDR4 and DDR5 are among the many memory interface protocols used by integrated circuits to transfer data to and from external storage devices. In DDR4 and / or DDR5 memory subsystems, during a memory read operation, the memory controller in the host integrated circuit sends a read command to the external DRAM memory device. The external DRAM memory device responds by sending the read data back to the host. The external DRAM memory device also sends a strobe along with the read data, which the host uses to sample the read data. The strobe is commonly referred to as the Data strobe (DQS) signal, and the data is called the DQ.

[0003] For DDR4 or DDR5 memory protocols, Data strobe (DQS) is bidirectional. Therefore, the host memory controller interface needs a receive enable signal. This receive enable signal allows DQS to become, or be eligible to become, an input pin when an external storage device sends read data to the host memory controller. Otherwise, the receive enable signal will disable DQS.

[0004] According to the DDR4 or DDR5 protocol specification, the read strobe DQS (actually a pair of differential signals DQS_t and DQS_c) may be in a tri-state (or high-Z state) or an unknown state (1 or 0) before sending the read data DQ, and is driven by a deterministic toggling pattern during data transmission, and returns to a tri-state or unknown state after sending the last read data. Figure 1A This shows the unknown state of DQS before and after DQ.

[0005] For the host, an unknown state of DQS is undesirable because direct use would cause the unknown or X's to propagate into the DQ sampling logic, leading to incorrect data sampling. Therefore, the host typically uses an internally generated 'receive enable' signal to 'gate' or filter DQS. The 'receive enable' signal is asserted immediately after the DQS strobe transitions from an unknown state to a 0 state. Figure 1B As shown, after receiving the last read data sent by the external storage device, the 'receive enable' signal is immediately de-asserted.

[0006] Figure 2 A conceptual diagram of the circuitry is shown, illustrating the gated DQS gating pulse before it is used as a clock to sample the introduced DQ data (405). Figure 3A As shown, if the 'receive enable' signal is prematurely asserted before the DQS transitions from an unknown state to a 0 state, it will still pass the unknown pulse to the DQ sampling logic, which is undesirable because it leads to nondeterministic capture of the DQ. Figure 3B As shown, if the 'receive enable' signal is asserted too late after the first valid 0->1 transition in DQS, it will result in a shorter pulse on the gating strobe, or in the worst case, a lost pulse. The first DQ data (405) may not be captured correctly. Therefore, the 'receive enable' signal must be correctly timed so that DDR4 or DDR5 read data can be correctly transferred from the external storage device to the host.

[0007] Another problem faced by host memory controllers is that even if the receive enable signal is initially timed correctly, the timing can drift and become incorrect or inaccurate due to temperature and voltage drift, as well as process aging of integrated circuits and / or external storage devices. This means that the initial settings found during initial system startup may no longer be optimal.

[0008] Therefore, it would be advantageous to mitigate these drawbacks through methods and apparatus with a calibration memory interface, thereby enabling the host memory controller to periodically rearrange the arrangement of the receive enable signal so that the signal is in the optimal position relative to the DQS signal from the external memory device, and to continuously perform monitoring to ensure that the relative position is maintained, even if the position may drift due to voltage or temperature drift or process aging of the integrated circuit. Summary of the Invention

[0009] Therefore, the main objective of this invention is to provide a method and apparatus for calibrating a memory, which can determine the optimal relative timing position between a receive enable signal and a DQS signal.

[0010] Another object of the present invention is to provide a method and apparatus for calibrating a memory, which is able to maintain the optimal relative timing position between the receive enable signal and the DQS symbol even if the relative timing position may drift over time.

[0011] Other objects of the invention will become apparent from understanding the following detailed description of the invention or from using the invention in practice.

[0012] According to a preferred embodiment of the present invention, the following is provided:

[0013] A method for calibrating a memory interface includes the following steps:

[0014] i. The memory controller generates a gated strobe signal for DQ data from an external storage device, wherein the gated strobe signal is gated by a DQS signal and a receive enable signal from the external storage device, wherein the receive enable signal is generated by a receive enable generation circuit in the memory controller after propagating through a first delay element in the memory controller;

[0015] ii. When the sampling output value of the first sampling element is 1, the memory controller having the first sampling element samples a series of DQS pulses from the external storage device to obtain the value of the first delay element;

[0016] iii. The memory controller adjusts the value of the first delay element to position the output of the first delay element earlier to approximately the center of the first read preamble phase of the DQS signal from the external storage device;

[0017] iv. When the sampling output value of the third sampling element is at a transition from the first phase of the read preamble to the second phase of the read preamble, the memory controller uses the third sampling element to sample a series of DQS pulses from the external storage device to obtain the value of the third delay element; wherein the third delay element is connected after the first delay element;

[0018] v. The memory controller adjusts the second delay element such that the sampled output value of the second sampling element is in a suitable position before the transition from the low phase of the read preamble to the high phase of the first DQS pulse; the memory controller adjusts the fourth delay element such that the sampled output value of the fourth sampling element is in a suitable position after the transition from the low phase of the read preamble to the high phase of the first DQS pulse; wherein the sampled output value of the second sampling element and the output of the fourth sampling element are complementary; wherein the second delay element is connected between the first delay element and the third delay element; wherein the fourth delay element is connected after the third delay element.

[0019] vi. The memory controller periodically monitors the sampled output value of the second sampling element and the sampled output value of the fourth sampling element to ensure that the sampled output value of the second sampling element and the sampled output value of the fourth sampling element are complementary;

[0020] When the memory controller generates the gating signal, step (vi) is repeated.

[0021] In another embodiment of the invention, the following is provided:

[0022] A memory interface calibration method includes the following steps:

[0023] i. The memory controller generates a gating signal for DQ data from an external storage device, wherein the gating signal is gated by a DQS signal from the external storage device and a receive enable signal, wherein the receive enable signal is generated by a receive enable signal generation circuit in the memory controller after propagating through a first delay element in the memory controller.

[0024] ii. When the sampling output value of the first sampling element is 1, the memory controller having the first sampling element samples a series of DQS pulses from the external memory device to obtain the value of the first delay element;

[0025] iii. The memory controller adjusts the value of the first delay element to the position of the delay output of the first delay element 2.5 unit intervals (UI) earlier than the initial position of the delay output;

[0026] iv. When the sampling output value of the third sampling element is 0, the memory controller uses the third sampling element to sample a series of DQS pulses from the external storage device to obtain the value of the third delay element; wherein the third delay element is connected after the first delay element;

[0027] v. The memory controller adjusts the third delay element until the sampling output of the third sampling element is captured as 0 at the location of the delay output of the third delay element, wherein the second delay element is connected between the first delay element and the third delay element; wherein the fourth delay element is connected after the third delay element;

[0028] vi. The memory controller periodically monitors the sampled output value of the second sampling element and the sampled output value of the fourth sampling element to ensure that the sampled output value of the second sampling element is complementary to the sampled output value of the fourth sampling element;

[0029] When the memory controller generates the gating signal, step (vi) is repeated.

[0030] In another embodiment of the invention, the following is provided:

[0031] A memory interface calibration circuit, comprising:

[0032] A memory controller capable of generating gating signals for DQ data from an external storage device, the memory controller comprising:

[0033] Circuit for receiving enable signal generation;

[0034] Its features are,

[0035] The memory controller further includes a signal sampling circuit, which includes multiple sampling elements;

[0036] The memory controller further includes a signal delay circuit, which includes multiple delay elements;

[0037] The gating signal is gated by a DQS signal from the external storage device and a receive enable signal, which is generated by the receive enable signal generation circuit after being propagated through a first delay element in the signal delay circuit.

[0038] The sampling element in the signal sampling circuit is capable of sampling the DQS signal from the external storage device;

[0039] Each sampling output of the sampling element is gated by the delay output of the corresponding delay element. Attached Figure Description

[0040] Other aspects and advantages of the invention will become apparent upon detailed study in conjunction with the accompanying drawings, in which:

[0041] Figure 1A It is a timing diagram showing the unknown states of DQS before and after DQ.

[0042] Figure 1B It is a timing diagram showing the timing of the receive enable signal being asserted and deasserted.

[0043] Figure 2 The circuit diagram of a conventional receiver enable circuit is shown.

[0044] Figure 3A and 3B The timing diagram shows the receiver enable signal being asserted too early and too late, which causes problems for conventional circuits.

[0045] Figure 4 The apparatus of the present invention is shown.

[0046] Figure 5A This is a timing diagram of the DQS gating pulse under the prerequisite of receiving training enable.

[0047] Figure 5B It is a timing diagram showing the process of obtaining the value of the first delay element in step (ii) of the present invention.

[0048] Figure 5C The different types of DQS leading edges that can be configured from DDR5 DRAM are shown.

[0049] Figure 5D This is a timing diagram showing the first readout preamble phase of the DQS signal as explained in step (iii) of the present invention.

[0050] Figure 5E It is a timing diagram showing how steps (iv)(a) to (iv)(c) are repeated in this invention.

[0051] Figure 5F This is a timing diagram showing how step (v) is implemented in this invention.

[0052] Figure 5G It shows the same timing diagrams for both dqs_1 and dqs_3.

[0053] Figure 5H It shows the timing diagram of C1, C2, and C3 being pushed out because of C0.

[0054] Figure 6A , 6B Diagrams 6 and 6C are timing diagrams illustrating implementations of the present invention in certain DDR4 applications. Detailed Implementation

[0055] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, those skilled in the art will understand that the invention can be practiced without these specific details. In other instances, well-known methods, procedures, and / or components have not been described in detail so as not to obscure the invention.

[0056] The present invention will be more clearly understood from the following description of embodiments thereof, which are given by way of example only with reference to the accompanying drawings, which are not drawn to scale.

[0057] During initial system startup, the method and apparatus of the present invention provide a host memory controller that trains or calibrates the received enable signal (411) to place it in an optimal position relative to the DQS to obtain maximum timing margin.

[0058] like Figure 4 As shown, the present invention proposes a memory interface calibration circuit (401) comprising a memory controller capable of generating a gating signal (403) for DQ data (405) from an external storage device, the memory controller including a receive enable signal generation circuit (407). The memory controller also includes a signal sampling circuit comprising multiple sampling elements (F0, F1, F2, F3). The memory controller further includes a signal delay circuit comprising multiple delay elements (C0, C1, C2, C3). In one example, the signal sampling circuit has four sampling elements, namely a first sampling element (F0), a second sampling element (F1), a third sampling element (F2), and a fourth sampling element (F3), and corresponding four delay elements, namely a first delay element (C0), a second delay element (C1), a third delay element (C2), and a fourth delay element (C3). These delay elements and sampling elements are essential to the present invention. The second delay element (C1) is connected between the first delay element (C0) and the third delay element (C2); wherein the fourth delay element (C3) is connected after the third delay element (C2).

[0059] The gated strobe signal (403) is AND-gated by the DQS signal (409) from the external storage device and the receive enable signal (411), which is generated by the receive enable signal generation circuit (407) after propagating through the first delay element (C0) in the signal delay circuit. The sampling elements (F0, F1, F2, F3) in the signal sampling circuit are capable of sampling the DQS signal (409) from the external storage device; wherein each sampling output of the sampling element is gated by the delay output of the corresponding delay element.

[0060] The first delay element (C0) delays the receive enable signal (411) generated by the receive enable signal generation circuit (407), and uses the first delayed receive enable signal (hereinafter referred to as rxe_0) to sample the DQS strobe signal from the external storage device using the first sampling element (F0). The sampled output from the first sampling element (F0) is hereinafter referred to as dqs_0. Using the flip-flop structure of the first sampling element (F0), the dqs_0 signal from the first sampling element (F0) is used to represent a 'gated strobe' from a gating AND gate, but under the following two conditions. First, the sampling element is constructed with timing characteristics similar to the gating AND gate in both the start-up time and hold time. Second, the delays of the sampling element (F0) and the gating AND gate are matched at the outputs of the gating AND gate, the strobe signal, and the rxe_0 signal.

[0061] Similarly, the sampling output of the second sampling element (F1) is named dqs_1, the sampling output of the third sampling element (F2) is named dqs_2, and the sampling output of the fourth sampling element (F3) is named dqs_3. Dqs_1, dqs_2, and dqs_3 also represent the delayed samples of the 'gated selection'. Figure 2 As shown, the delayed output rxe_0 of the first delayed receive enable signal / first delayed element is also used for gated DQS strobe, where the final gated strobe is used to sample the incoming DQ data (405). The second delayed element (C1) delays rxe_0 to generate the second delayed receive enable signal rxe_1, which is then used to sample the DQS strobe signal again. The sampling output of the second sampling element (F1) is dqs_1. The third delayed element (C2) delays rxe_1 to generate the third delayed receive enable signal rxe_2, which is then used to sample the DQS strobe signal again. The sampling output of the third sampling element (F2) is dqs_2. The fourth delayed element (C3) delays rxe_2 to generate rxe_3, which is then used to sample the DQS strobe signal again. The sampling output of the second sampling element (F3) is dqs_3.

[0062] The delay amount of the first delay element (C0) can be controlled by the signal control_0. The delay amount of the second delay element (C1) can be controlled by the signal control_1. In some embodiments, the control_1 signal can be optionally fixed, such that the delay between rxe_0 and rxe_1 is fixed. The delay amount of the third delay element (C2) can be controlled by the signal control_2. In some embodiments, the control_2 signal can be optionally fixed, such that the delay between rxe_1 and rxe_2 is fixed. The delay amount of the fourth delay element (C3) can be controlled by the signal control_3. In some embodiments, the control_3 signal can be optionally fixed, such that the delay between rxe_2 and rxe_3 is fixed.

[0063] The present invention also proposes a memory interface calibration method, comprising the following steps. In step (i), the memory controller generates a gated strobe signal (403) for DQ data (405) from an external storage device, wherein the gated strobe signal (403) is gated by a DQS signal (409) from the external storage device and a receive enable signal (411), wherein the receive enable signal (411) is generated by a receive enable signal generation circuit (407) in the memory controller after propagation through a first delay element (C0) in the memory controller.

[0064] In step (ii), when the sampling output value of the first sampling element (F0) is 1, the memory controller with the first sampling element samples a series of DQS pulses from the external storage device to obtain the value of the first delay element (C0). Before step (ii) (receiving enable training) is completed, a prerequisite is that the external storage device must be precharged (all banks are closed and precharged) before configuring it to read-preamble training mode. An example of precharging the external storage device is to issue a mode register write (MRW) for the DDR5 interface or an issue a mode register set (MRS) for the DDR4, for use with the external storage device driving a DQS signal (409) in a deterministic 0 state, such as... Figure 5A As shown. Various methods can be used to precharge the external storage device, but it is important that the external storage device be configured to read the pre-training mode (i.e., external storage device driving DQS deterministic 0 state) before step (ii) (receiving enable training) can be implemented.

[0065] In step (ii), the following is a sub-step. In step (ii)(a), the first delay element (C0) in the host memory controller is set to minimum delay. Thus, the DQS strobe will be in a deterministic 0 state, as... Figure 5A As shown. Figure 5B As shown, in step (ii)(b), the memory controller is configured to send a read command to the external storage device to trigger the external storage device to send a series of DQS pulses (409), and the memory controller generates a read enable indication, which is then converted into a receive enable signal (411) by the receive enable signal generation circuit (407). Given that the first delay element (C0) is at minimum delay, the first sampling element (F0) will sample the early DQS strobe in state 0, i.e., dqs_0 = 0. In step (ii)(c), the first sampling element (F0) in the memory controller samples the DQS signal (409) from the external storage device. In step (ii)(d), the memory controller checks the sampled output dqs_0 of the first sampling element (F0). If the sampling output dqs_0 of the first sampling element (F0) is 0, steps (ii)(b) to (ii)(d) are repeated, and the memory controller increases the delay to the first delay element (C0) until the sampling output value dqs_0 of the first sampling element (F0) is 1. When the sampling output value dqs_0 of the first sampling element (F0) is 1, the value control_0 of the first delay element (C0) is recorded as A. From these steps, the left edge of the first DQS pulse is found.

[0066] Then, the process will exit the read preamble training mode so that the regular DQS pulse (409) is driven by the external storage device. It is important to note that the DQS signal (409) is now weakly pulled up to the HIGH state. As... Figure 5C As shown, memory interfaces such as DDR4 or DDR5 support several styles of the number of DQS preambles sent from external memory devices to the host memory controller.

[0067] In step (iii), the memory controller adjusts the value control_0 of the first delay element (C0) to position the delay output rxe_0 of the first delay element (C0) earlier, such that, according to... Figure 5C The read preamble configuration shown indicates that rxe_0 falls substantially at the center of the first read preamble phase (1P) of the DQS signal (409) from the external storage device. Figure 5DAs shown, based on different read preamble settings, we will subtract the value of control_0 recorded in step (ii) until the rxe_0 signal is located at the center of the first read preamble phase (1P).

[0068] In step (iv), as Figure 5E As shown, when the sampling output (dqs_2) value of the third sampling element (F2) transitions from the first phase of the read preamble to the second phase of the read preamble, the memory controller uses the third sampling element (F2) to sample a series of DQS pulses (409) from the external storage device to obtain the value of the third delay element (C2). The third delay element (C2) is connected after the first delay element (C0). Step (iv) includes the following sub-steps. In step (iv)(a), the memory controller sends a read command to the external storage device to trigger the sampling element. The external storage device sends a series of DQS pulses (409), and the memory controller generates a read enable indication, which is then converted into a receive enable signal (411) by the receive enable signal generation circuit (407). In step (iv)(b), the third sampling element (F2) in the memory controller samples the DQS signal (409) from the external storage device. In steps (iv)(c), the memory controller checks the sampled output (dqs_2) of the third sampling element (F2). Steps (iv)(a) to (iv)(c) are repeated, and the memory controller increases the delay to the third delay element (C2), control_2, until the sampled output (dqs_2) value of the third sampling element (F2) transitions from the first phase (1P) of the read preamble to the second phase (2P) of the read preamble. This transition can also be viewed as the rising edge of the DQS gating. When this transition is detected, the value of the third delay element (C2), control_2, is recorded as B. The dqs_2 signal will now fall on the transition edge from the first phase (1P) to the second phase (2P) of the read preamble.

[0069] The method and apparatus of the present invention ensure that the dqs_1 signal is positioned before the transition edge with some delay, and the dqs_3 signal is positioned after the transition edge with some delay. In step (v), the memory controller adjusts the second delay element (C1) such that the sampled output (dqs_1) value of the second sampling element (F1) is in the appropriate position (-delta) before the transition from the low phase of the read preamble to the high phase of the first DQS pulse; the memory controller adjusts the fourth delay element (C3) such that the sampled output (dqs_3) value of the fourth sampling element (F3) is in the appropriate position after the transition from the low phase of the read preamble to the high phase of the first DQS pulse. For example, the delay of the second delay element (C1) is set to B-delta, the delay of the third delay element (C2) is set to delta, and the delay of the fourth delay element (C3) is set to delta. The final delay on rxe_1 is B-delta, rxe_2 is B, and rxe_3 is B+delta. Figure 5F The results were described.

[0070] Importantly, the sampling output (dqs_1) value of the second sampling element (F1) and the output (dqs_3) of the fourth sampling element (F3) should always be complementary. After step (v), the initial receive enable calibration procedure is completed.

[0071] After the calibration process is completed, step (vi) is executed, in which the memory controller periodically monitors the sampled output value dqs_1 of the second sampling element and the sampled output value dqs_3 of the fourth sampling element (F3) to ensure that the sampled output values ​​dqs_1 of the second sampling element and dqs_3 of the fourth sampling element (F3) are complementary. Step (vi) includes the following sub-steps. In step (vi)(a), the memory controller periodically monitors the output value dqs_1 of the second sampling element and the output value dqs_3 of the fourth sampling element (F3). If dqs_1 and dqs_3 are both equal (i.e., both are 1 or both are zero), such as Figure 5GAs shown, this means that the DQS gating drifts due to changes in process / voltage / temperature over time. In step (vi)(b), if the output values ​​of the second sampling element and the fourth sampling element (F3) are both 0, the memory controller increases the value of the first delay element (C0); and if the output values ​​of the second sampling element (F1) and the fourth sampling element (F3) are both 1, the memory controller decreases the value of the first delay element (C0). Step (vi)(b) is repeated until the sampled output (dqs_1) value of the second sampling element (F1) is complementary to the sampled output (dqs_3) value of the fourth sampling element (F3). By increasing or decreasing C0, the invention essentially pushes out or pulls in the second delay element (C1), the third delay element (C2), and the fourth delay element (C3), since they follow C0, so dqs_1 and dqs_3 are again complementary. When the memory controller generates the gating signal (403), step (vi) is repeated to continuously adjust for changes in process / voltage / temperature. Figure 5H As shown, since rxe_0 is used for gating DQS input strobes, this ensures that there is always sufficient margin from the rise of rxe_0 to the rise of the first DQS strobe.

[0072] In some memory interface applications, particularly some DDR4 applications, it may be necessary to set the receive enable to 1 when the DQS strobe signal is set to 1. In this case, the above method can be performed with several modifications. In step (iii), instead of making rxe_0 fall approximately at the center of the first read preamble phase (1P) of the DQS signal (409), rxe_0 should be subtracted by 2.5 unit intervals (UI) from the value of A obtained from the first delay element (C0), such as... Figure 6A As shown. In step (iv), when the sampling output (dqs_2) value of the third sampling element (F2) is 0, the memory controller uses the third sampling element (F2) to sample a series of DQS pulses (409) from the external storage device to obtain the value of the third delay element (C2). Figure 6B As shown, in step (v), instead of adjusting the second delay element (C1) so that the second sampling element (F1) is in the correct position before the transition from the low phase of the read preamble to the high phase of the first DQS pulse and adjusting the fourth delay element (C3) so that the fourth sampling element (F3) is in the correct position after the transition from the low phase of the read preamble to the high phase of the first DQS pulse, the third delay element (C2) should be adjusted until dqs_2 captures 0 at the position of rxe_2. Figure 6CAs shown, in step (v), the present invention positions rxe_1 as B-delta and rxe_3 as B+delta. Thus, the initial calibration is completed. For periodic calibrations that take into account process / voltage / temperature drift, the present invention can detect events where dqs_1 and dqs_3 are equal. In step (vi)(b), C0 is decreased (if both dqs_1 and dqs_2 are 0) or increased (if both dqs_1 and dqs_2 are 1).

[0073] Although the invention has been shown and described herein in a manner considered to be its preferred embodiment, illustrating the superior results and advantages obtained by the invention compared to the prior art, the invention is not limited to these specific embodiments. Therefore, the forms of the invention shown and described herein are merely illustrative, and other embodiments may be chosen without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A memory interface calibration method, comprising the following steps: i. The memory controller generates a gated strobe signal (403) for DQ data (405) from an external storage device, wherein the gated strobe signal (403) is AND-gated by a DQS signal (409) from the external storage device and a receive enable signal (411), wherein the receive enable signal (411) is generated by a receive enable signal generation circuit (407) in the memory controller after propagation through a first delay element (C0) in the memory controller; ii. When the sampling output value of the first sampling element (F0) is 1, the memory controller having the first sampling element (F0) samples a series of DQS signals (409) from an external storage device to obtain the value of the first delay element (C0), the value of which is the delay amount; iii. The memory controller adjusts the value of the first delay element (C0) to position the delayed output (rxe_0) of the first delay element (C0) earlier at the fundamental center of the first read preamble phase of the DQS signal (409) from the external storage device; iv. When the sampling output (dqs_2) value of the third sampling element (F2) is converted from the first phase of the read preamble to the second phase of the read preamble, the memory controller uses the third sampling element (F2) to sample a series of DQS signals (409) from the external storage device to obtain the value of the third delay element (C2), the value of which is a delay amount; wherein the third delay element (C2) is connected after the first delay element (C0); v. The memory controller adjusts the second delay element (C1) such that the sampled output (dqs_1) value of the second sampling element (F1) is in a suitable position before the transition from the low phase of the read preamble to the high phase of the first DQS signal; the memory controller adjusts the fourth delay element (C3) such that the sampled output (dqs_3) value of the fourth sampling element (F3) is in a suitable position after the transition from the low phase of the read preamble to the high phase of the first DQS signal; wherein the sampled output (dqs_1) value of the second sampling element (F1) and the output (dqs_3) value of the fourth sampling element (F3) are complementary; wherein the second delay element (C1) is connected between the first delay element (C0) and the third delay element (C2); wherein the fourth delay element (C3) is connected after the third delay element (C2); vi. The memory controller periodically monitors the sampling output (dqs_1) value of the second sampling element (F1) and the sampling output (dqs_3) value of the fourth sampling element (F3) to ensure that the sampling output (dqs_1) value of the second sampling element (F1) and the sampling output (dqs_3) value of the fourth sampling element (F3) are complementary. When the memory controller generates the gate selection signal (403), step (vi) is repeated. The memory controller includes: Receive enable signal generation circuit (407); The memory controller further includes a signal sampling circuit, which includes a first sampling element (F0), a second sampling element (F1), a third sampling element (F2), and a fourth sampling element (F3). The memory controller further includes a signal delay circuit, which includes a first delay element (C0), a second delay element (C1), a third delay element (C2), and a fourth delay element (C3). The gated strobe signal (403) is gated by the DQS signal (409) from the external storage device and the receive enable signal (411), which is generated by the receive enable signal generating circuit (407) after propagating through the first delay element (C0) in the signal delay circuit. The sampling element in the signal sampling circuit is capable of sampling the DQS signal (409) from the external storage device; Wherein, each sampling output (dqs_0, dqs_1, dqs_2, dqs_3) of the first sampling element (F0), the second sampling element (F1), the third sampling element (F2), and the fourth sampling element (F3) is gated by the delayed output (rxe_0, rxe_1, rxe_2, rxe_3) of the corresponding first delay element (C0), the second delay element (C1), the third delay element (C2), and the fourth delay element (C3).

2. The memory interface calibration method as described in claim 1, wherein, Step (ii) includes the following sub-steps: (a) Set the first delay element (C0) in the memory controller to the minimum delay; (b) The memory controller sends a read command to the external storage device to trigger the external storage device to send a series of DQS signals (409); at the same time, the memory controller generates a read enable indication, and then the receive enable signal generation circuit (407) converts the read enable indication into a receive enable signal (411). (c) The first sampling element (F0) in the memory controller samples the DQS signal (409) from the external storage device; (d) The memory controller checks the sampling output (dqs_0) of the first sampling element (F0). If the sampling output (dqs_0) of the first sampling element (F0) is 0, repeat steps (b) to (d) and the memory controller increases the delay to the first delay element (C0) until the sampling output (dqs_0) of the first sampling element (F0) is 1; wherein, when the sampling output (dqs_0) of the first sampling element (F0) is 1, the delay amount of the first delay element (C0) is recorded.

3. The memory interface calibration method as described in claim 1, wherein step (iv) comprises the following sub-steps: (a) The memory controller sends a read command to the external storage device to trigger the external storage device to send a series of DQS signals (409); at the same time, the memory controller generates a read enable indication, and then the receive enable signal generation circuit (407) converts the read enable indication into a receive enable signal (411). (b) The third sampling element (F2) in the memory controller samples the DQS signal (409) from the external storage device; (c) The memory controller checks the sampling output (dqs_2) of the third sampling element (F2); Steps (a) to (c) are repeated, and the memory controller increases the delay to the third delay element (C2) until the sampled output (dqs_2) value of the third sampling element (F2) changes from the first phase (1P) of the read preamble to the second phase (2P) of the read preamble; wherein, When the transition is detected, the delay amount of the third delay element (C2) is recorded.

4. The memory interface calibration method as described in claim 1, wherein step (vi) includes the following sub-steps: (a) The memory controller periodically monitors the sampled output (dqs_1) value of the second sampling element (F1) and the sampled output (dqs_3) value of the fourth sampling element (F3); (b) If the sampling output (dqs_1) value of the second sampling element (F1) and the sampling output (dqs_3) value of the fourth sampling element (F3) are both 0, then the memory controller increases the delay of the first delay element (C0); and if the sampling output (dqs_1) value of the second sampling element (F1) and the sampling output (dqs_3) value of the fourth sampling element (F3) are both 1, then the memory controller decreases the delay of the first delay element (C0). Step (b) is repeated until the sampled output (dqs_1) value of the second sampling element (F1) is complementary to the sampled output (dqs_3) value of the fourth sampling element (F3).

5. A memory interface calibration method, comprising the following steps: i. The memory controller generates a gated strobe signal (403) for DQ data (405) from an external storage device, wherein the gated strobe signal (403) is AND-gated by a DQS signal (409) from the external storage device and a receive enable signal (411), wherein the receive enable signal (411) is generated by a receive enable signal generation circuit (407) in the memory controller after propagation through a first delay element (C0) in the memory controller; ii. When the sampling output value of the first sampling element (F0) is 1, the memory controller having the first sampling element (F0) samples a series of DQS signals (409) from the external storage device to obtain the value of the first delay element (C0), the value of which is the delay amount; iii. The memory controller adjusts the value of the first delay element (C0) to the position of the delay output (rxe_0) of the first delay element (C0) 2.5 unit intervals (UI) earlier than the initial position of the delay output (rxe_0). iv. When the sampling output (dqs_2) of the third sampling element (F2) is 0, the memory controller uses the third sampling element (F2) to sample a series of DQS signals (409) from the external storage device to obtain the value of the third delay element (C2); wherein the third delay element (C2) is connected after the first delay element (C0); v. The memory controller adjusts the third delay element (C2) until the sampling output (dqs_2) of the third sampling element (F2) captures 0 at the position of the delay output (rxe_2) of the third delay element (C2), wherein the second delay element (C1) is connected between the first delay element (C0) and the third delay element (C2); wherein the fourth delay element (C3) is connected after the third delay element (C2); vi. The memory controller periodically monitors the sampling output (dqs_1) value of the second sampling element (F1) and the sampling output (dqs_3) value of the fourth sampling element (F3) to ensure that the sampling output (dqs_1) value of the second sampling element (F1) is complementary to the sampling output (dqs_3) value of the fourth sampling element (F3). When the memory controller generates the gate selection signal (403), step (vi) is repeated, and the value of the third delay element (C2) is the delay amount; The memory controller includes: Receive enable signal generation circuit (407); The memory controller further includes a signal sampling circuit, which includes a first sampling element (F0), a second sampling element (F1), a third sampling element (F2), and a fourth sampling element (F3). The memory controller further includes a signal delay circuit, which includes a first delay element (C0), a second delay element (C1), a third delay element (C2), and a fourth delay element (C3). The gated strobe signal (403) is gated by the DQS signal (409) from the external storage device and the receive enable signal (411), which is generated by the receive enable signal generating circuit (407) after propagating through the first delay element (C0) in the signal delay circuit. The sampling element in the signal sampling circuit is capable of sampling the DQS signal (409) from the external storage device; Wherein, each sampling output (dqs_0, dqs_1, dqs_2, dqs_3) of the first sampling element (F0), the second sampling element (F1), the third sampling element (F2), and the fourth sampling element (F3) is gated by the delayed output (rxe_0, rxe_1, rxe_2, rxe_3) of the corresponding first delay element (C0), the second delay element (C1), the third delay element (C2), and the fourth delay element (C3).

6. The memory interface calibration method as described in claim 5, wherein, Step (ii) includes the following sub-steps: (a) Set the first delay element (C0) in the memory controller to the minimum delay; (b) The memory controller sends a read command to the external storage device to trigger the external storage device to send a series of DQS signals (409); at the same time, the memory controller generates a read enable indication, and then the receive enable signal generation circuit (407) converts the read enable indication into a receive enable signal (411). (c) The first sampling element (F0) in the memory controller samples the DQS signal (409) from the external storage device; (d) The memory controller checks the sampling output (dqs_0) of the first sampling element (F0). If the sampling output (dqs_0) of the first sampling element (F0) is 0, repeat steps (b) to (d) and the memory controller increases the delay to the first delay element (C0) until the sampling output (dqs_0) of the first sampling element (F0) is 1; wherein, when the sampling output (dqs_0) of the first sampling element (F0) is 1, the delay amount of the first delay element (C0) is recorded.

7. The memory interface calibration method as described in claim 5, wherein step (iv) comprises the following sub-steps: (a) The memory controller sends a read command to the external storage device to trigger the external storage device to send a series of DQS signals (409); at the same time, the memory controller generates a read enable indication, and then the receive enable signal generation circuit (407) converts the read enable indication into a receive enable signal (411). (b) The third sampling element (F2) in the memory controller samples the DQS signal (409) from the external storage device; (c) The memory controller checks the sampling output (dqs_2) of the third sampling element (F2); Steps (a) to (c) are repeated, and the memory controller increases the delay to the third delay element (C2) until the sampled output (dqs_2) of the third sampling element (F2) is 0; wherein, When the value of the sampling output (dqs_2) of the third sampling element (F2) is detected to be 0, the delay amount of the third delay element (C2) is recorded.

8. The memory interface calibration method as described in claim 5, wherein step (vi) comprises the following sub-steps: (a) The memory controller periodically monitors the sampled output (dqs_1) value of the second sampling element (F1) and the sampled output (dqs_3) value of the fourth sampling element (F3); (b) If the sampling output (dqs_1) value of the second sampling element (F1) and the sampling output (dqs_3) value of the fourth sampling element (F3) are both 0, then the memory controller decreases the delay of the first delay element (C0); and if the sampling output (dqs_1) value of the second sampling element (F1) and the sampling output (dqs_3) value of the fourth sampling element (F3) are both 1, then the memory controller increases the delay of the first delay element (C0). Step (b) is repeated until the sampled output (dqs_1) value of the second sampling element (F1) is complementary to the sampled output (dqs_3) value of the fourth sampling element (F3).

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