Time-to-digital converter and time margin extraction circuit therefor
By introducing a time margin extraction circuit into the time-to-digital converter and utilizing a combination of triggers and delay units, the problem of large quantization error was solved, resulting in a time-to-digital converter with higher accuracy and continuous measurement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 锐泰微(北京)电子科技有限公司
- Filing Date
- 2024-01-15
- Publication Date
- 2026-07-03
AI Technical Summary
Existing time-to-digital converters cannot quantize when the interval between input signals is less than the delay time of the delay unit, resulting in large quantization errors and poor performance.
Design a time margin extraction circuit, including multiple time margin extraction units and OR gates. By combining flip-flops and delay units, ensure the synchronous extraction of start and stop signals, eliminate the dead time of the flip-flops, and improve measurement accuracy and continuous measurement capability.
It improves the measurement accuracy of the time-to-digital converter, eliminates dead time, ensures continuous measurement capability, and improves quantization error.
Smart Images
Figure CN117872700B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a time-to-digital converter and its time margin extraction circuit. Background Technology
[0002] A Time-to-Digital Converter (TDC) is an instrument used in electronic instruments or signal processing to convert continuous analog quantities (time) into discrete digital quantities. The main function of a TDC is to quantize the time interval (pulse width) between the rising edges of the Start and Stop signals, convert it into digital code, and output it.
[0003] Figure 1 A schematic diagram of a time-to-digital converter according to the prior art is shown. Figure 1 The input signals are the start signal (Start) and the stop signal (Stop). When the rising edge of the start signal (Start) arrives, the signal begins to propagate in the delay chain to sequentially obtain the input signals DLL1 of the first D flip-flop to the nth (n>1, for example, 64) flip-flops. <1> -DLL1 <n>When the rising edge of the Stop signal arrives, which is the effective clock edge of the D flip-flops, the n D flip-flops respectively respond to the input signal DLL1. <1> -DLL1 <n>The sample is taken, and a set of thermometer codes Q1-Qn is output. Then, a thermometer code converter is used to convert the thermometer codes into binary code. However, when the input signal DLL1... When the time interval between the rising edge of the signal and the rising edge of the stop signal is less than the delay time t0 of the delay unit τ, TDC cannot quantize the time interval, resulting in a large quantization error and poor performance.
[0004] Therefore, a time margin extraction circuit needs to be proposed to extract the time margin that TDC cannot quantize during coarse quantization. Summary of the Invention
[0005] In view of the above problems, the purpose of this invention is to provide a time-to-digital converter and its time margin extraction circuit, thereby improving the measurement accuracy of the time-to-digital converter and its continuous measurement capability.
[0006] According to one aspect of the present invention, a time margin extraction circuit for a time-to-digital converter is provided. The time-to-digital converter includes a plurality of D flip-flops arranged sequentially. A first start signal is provided to a plurality of input signals to the input terminals of the plurality of D flip-flops via a delay chain, and a first stop signal is provided to the set terminals of the plurality of D flip-flops. The time margin extraction circuit includes: a plurality of time margin extraction units, each corresponding one-to-one with the plurality of D flip-flops of the time-to-digital converter; a first OR gate having a plurality of input terminals and an output terminal, wherein the plurality of input terminals respectively receive the first output signals of the plurality of time margin extraction units, and the output terminal provides a second start signal; and a second OR gate having a plurality of input terminals and an output terminal, wherein the plurality of input terminals respectively receive the plurality of time margin extraction units. The unit provides a second output signal and a second termination signal at the output terminal. Each time margin extraction unit includes: a first flip-flop, whose input terminal receives a first input signal and whose set terminal receives the first termination signal; a second flip-flop, whose input terminal is connected to the output terminal of the first flip-flop, whose set terminal is connected to the first input signal delayed by a first delay unit, and whose output terminal provides the first output signal; a third flip-flop, whose input terminal is connected to the output terminal of the first flip-flop, whose set terminal is connected to the second input signal delayed by a second delay unit, and whose output terminal provides the second output signal; a first pseudo-flip-flop, whose input and output terminals are floating, and whose set terminal is connected to the input terminal of the first flip-flop; and a second pseudo-flip-flop, whose set terminal and output terminal are floating, and whose input terminal is connected to the set terminal of the second flip-flop.
[0007] Optionally, the delay time of the first delay unit and the delay time of the second delay unit are the same.
[0008] Optionally, the output delay times of the first to third flip-flops are the same, and the delay times of the first delay unit and the second delay unit are equal to the output delay time of the flip-flops.
[0009] Optionally, the first delay unit includes a fourth flip-flop, with its input terminal connected to the power supply voltage, its set terminal serving as the input terminal of the first delay unit connected to the first input signal, and its output terminal connected to the set terminal of the second flip-flop.
[0010] Optionally, the second delay unit includes a fifth flip-flop, with its input terminal connected to the power supply voltage, its set terminal serving as the input terminal of the second delay unit connected to the second input signal, and its output terminal connected to the set terminal of the third flip-flop.
[0011] Optionally, the first input signal of the time margin extraction unit corresponding to the first D flip-flop is the power supply voltage, and the first input signal of the remaining time margin extraction units is the input signal of their corresponding D flip-flops.
[0012] Optionally, the second input signal of the time margin extraction unit corresponding to the last D flip-flop is the input signal of the first D flip-flop, and the second input signal of the remaining time margin extraction units is the input signal of the next D flip-flop of its corresponding D flip-flop.
[0013] Optionally, the time interval between the second start signal and the second stop signal represents a time margin that is not quantized by the time-to-digital converter.
[0014] According to another aspect of the present invention, a time-to-digital converter is provided, comprising a plurality of D flip-flops arranged sequentially, wherein a first start signal is provided via a delay chain to the input terminals of the plurality of D flip-flops via a plurality of input signals, and a first stop signal is provided to the set terminals of the plurality of D flip-flops; a thermometer code converter is provided for converting the output signals of the plurality of D flip-flops into binary code; and
[0015] The time margin extraction circuit described above is used to extract the time margin that has not been converted by the thermometer code converter.
[0016] Optionally, the time interval between the rising edges of the input signals of two adjacent D flip-flops is the same.
[0017] This invention provides a time-to-digital converter and its time margin extraction circuit. The time margin extraction circuit includes multiple time margin extraction units corresponding one-to-one with the D flip-flops of the time-to-digital converter. Each time margin extraction unit includes a first flip-flop, and a second and a third flip-flop whose input terminals are connected to the output terminals of the first flip-flop. The input and set terminals of the first flip-flop are respectively connected to the set terminal of the first pseudo-flip-flop and the input terminal of the second flip-flop. This allows the input and set terminals of the first flip-flop to be driven simultaneously, reducing the setup time of the first flip-flop. This improves the situation where the first and second flip-flops cannot meet the setup time requirement when the rising edge of the first termination signal appears before or after the input signal. Furthermore, the input terminals of the second and third flip-flops are both delayed using flip-flops, improving the measurement accuracy of the time-to-digital converter and ensuring that the time margin extraction circuit has no dead time, thus improving the continuous measurement capability of the time-to-digital converter. Attached Figure Description
[0018] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0019] Figure 1 A schematic diagram of the structure of a time-to-digital converter according to the prior art is shown;
[0020] Figure 2 A schematic diagram of a time margin extraction circuit is shown.
[0021] Figure 3 It shows Figure 2 The timing diagram of the time margin extraction circuit is shown.
[0022] Figure 4 A schematic diagram of the time margin extraction circuit according to an embodiment of the present invention is shown;
[0023] Figure 5 A timing diagram of a time margin extraction circuit according to an embodiment of the present invention is shown. Detailed Implementation
[0024] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.
[0025] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0026] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.
[0027] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.
[0028] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0029] Figure 2 A schematic diagram of a time margin extraction circuit is shown. Figure 3 It shows Figure 2 The timing diagram shown is of the time margin extraction circuit.
[0030] Figure 2 The time margin extraction circuit shown is applied to Figure 1 The time-to-digital converter shown is used to extract... Figure 1 The time margin cannot be quantized by the time-to-digital converter in the circuit. The time margin is the rising edge of the stop signal appearing on the input signal DLL1. rising edge and DLL1<i+1> Between the rising edges, the input signal DLL1 The time interval between the rising edge of the trigger signal and the rising edge of the stop signal. The input signals DLL1 of two adjacent flip-flops. With DLL1<i+1> The time difference between the rising edges is the delay time t0 of the delay unit τ, which can be used to design Figure 1 The delay time of all delay units τ is equal.
[0031] The time margin extraction circuit includes multiple time margin extraction units 100, each corresponding one-to-one with one of the n D flip-flops in the time-to-digital converter. Figure 2 Only one example is shown), OR gate OR1 and OR gate OR2. Each time margin extraction unit 100 includes flip-flop DFF1, flip-flop DFF2, flip-flop DFF3 and delay unit τ. Flip-flops DFF1-DFF3 are all rising-edge triggered D flip-flops, each having an input D, an output Q, and a set input CLK. The delay unit τ has the same delay time t0 as the delay unit τ in the time-to-digital converter.
[0032] join Figure 2 Taking the time margin extraction unit 100 corresponding to the i-th (n>i>1) flip-flop in the time-to-digital converter as an example, the input terminal of flip-flop DFF1 receives the input signal DLL1 of the i-th D flip-flop in the time-to-digital converter. The set terminal receives the stop signal (Stop), and the output terminal provides the output signal Q11. The input terminal of flip-flop DFF2 is connected to the output terminal of flip-flop DFF1, and the set terminal receives the input signal DLL1 of the (i+1)th D flip-flop in the time-to-digital converter.<i+1> The output terminal provides the output signal Q12. The input terminal of flip-flop DFF3 is connected to the output terminal of flip-flop DFF1. The set terminal receives the stop signal after the delay unit τ, and the output terminal provides the output signal Q13. The delay unit τ is used to delay the stop signal for a time t0 before outputting it.
[0033] Furthermore, when i=1, the corresponding time margin extraction unit 100 is slightly different. In this case, the input terminal of the flip-flop DFF1 is no longer connected to the input signal DLL1. Instead, it is connected to the power supply voltage VDD. When i=n, the corresponding time margin extraction unit 100 is also slightly different; that is, the set terminal of the flip-flop DFF2 is no longer connected to the input signal DLL1.<i+1> Instead, it connects to the input signal DLL1. <1> .
[0034] OR gate OR1 has n inputs and one output. The n inputs are connected to the outputs of the flip-flops DFF2 of the n time margin extraction units 100, and the output provides the start signal Start1.
[0035] OR gate OR2 has n inputs and one output. The n inputs are connected to the outputs of the flip-flops DFF3 of the n time margin extraction units 100, and the output provides the stop signal Stop1.
[0036] See Figure 3 DLL1 uses time margin as input signal <2> Take the time interval between the rising edge of the signal and the rising edge of the stop signal as an example.
[0037] In input signal DLL1 <2> After a rising edge occurs, time t1 (t1 < t0) elapses, the stop signal rises, and the input signal DLL1... <2> The corresponding time margin extraction unit 100 provides a high-level output signal Q11 to the input of flip-flop DFF2 and the input of flip-flop DFF3 through flip-flop DFF1.
[0038] Then, a rising edge appears at the set input of flip-flop DFF2, which is the input signal DLL1. <3> After the rising edge of the OR gate occurs, the flip-flop DFF2 outputs a high-level input signal Q12, causing the start signal Start1 provided by the OR gate to have a rising edge. Therefore, ignoring the delay of the flip-flop and the OR gate, the start signal Start1 has a rising edge after time t2 after the stop signal Stop has a rising edge, where t1 = t0 - t2.
[0039] After a delay of time t0, the set input of flip-flop DFF3 experiences a rising edge, providing a high-level output signal Q13. The OR gate OR2 then provides the rising edge of the stop signal Stop1. Therefore, ignoring the delays of the flip-flops and OR gates, the stop signal Stop1 experiences a rising edge after time t0 following the initial rise of the stop signal. Thus, the time interval between the rising edges of the start signal Start1 and the stop signal Stop1 is the required time margin.
[0040] The inventors of this application have discovered that the time margin extraction circuit has the following problems:
[0041] 1. The delay unit τ cannot produce accurate delay due to the mismatch between the driver and the load;
[0042] 1. Mismatch in the delay unit τ itself can also introduce significant errors in time margin extraction;
[0043] 1. The propagation delay of trigger DFF1 can lead to a large dead time. Dead time reflects the continuous measurement capability of the time-to-digital converter. After completing a measurement, a certain amount of time must be waited before another measurement can be performed; this time interval is called the dead time.
[0044] 1. The dead time introduced by the flip-flop ensures that the rising edge of the stop signal appears on the input signal DLL1. When the setup time is set, triggers DFF1 and DFF2 cannot meet the setup time requirement.
[0045] Based on this, the inventors of this application... Figure 2 The time margin extraction circuit shown has been improved to solve the above problems.
[0046] Figure 4 A schematic diagram of a time margin extraction circuit according to an embodiment of the present invention is shown. Figure 5 A timing diagram of a time margin extraction circuit according to an embodiment of the present invention is shown.
[0047] Figure 4 The time margin extraction circuit shown is also applied to Figure 1 The time-to-digital converter shown is used to extract... Figure 1 The time margin cannot be quantized by the time-to-digital converter in the present invention. In this embodiment, the time margin is the time margin that occurs at the rising edge of the stop signal on the input signal DLL1. The rising edge of the input signal DLL1<i+1> Between the rising edges of the stop signal Stop and the input signal DLL1<i+1> The time interval between the rising edges of two adjacent D flip-flops. (DLL1) With DLL1<i+1> The time difference between the rising edges is the delay time t0 of the delay unit τ, which can be used to design Figure 1 The delay times of the intermediate delay units τ are equal.
[0048] The time margin extraction circuit includes multiple time margin extraction units 200, each corresponding one-to-one with one of the n D flip-flops in the time-to-digital converter. Figure 4 Only one example is shown), OR gate OR1, and OR gate OR2. Each time margin extraction unit 200 includes flip-flops DFF1-DFF3, dummy flip-flops DMY1-DMY2, and first to second delay units. Flip-flops DFF1-DFF3 and dummy flip-flops DMY1-DMY2 are all rising-edge triggered D flip-flops, each with an input D, an output Q, and a set input CLK. The delay time t4 of the first and second delay units is the same.
[0049] join Figure 4 Take the time margin extraction unit 200 corresponding to the i-th (n>i>1) trigger in the time-to-digital converter as an example.
[0050] The input of flip-flop DFF1 receives the input signal DLL1 of the i-th flip-flop in the time-to-digital converter. The set terminal receives the stop signal, and the output terminal provides the output signal Q11.
[0051] The set input of dummy flip-flop DMY1 is connected to the input of flip-flop DFF1, while the input and output of dummy flip-flop DMY1 are left floating. The input of dummy flip-flop DMY2 is connected to the set input of flip-flop DFF1, while the set and output of dummy flip-flop DMY2 are left floating. By connecting the input and set input of flip-flop DFF1 to the set input of dummy flip-flop DMY1 and the input of dummy flip-flop DMY2 respectively, the input and set input of flip-flop DFF1 can be driven simultaneously, reducing the setup time of flip-flop DFF1 and improving the occurrence of the rising edge of the stop signal on the input signal DLL1. When the setup time is not met, triggers DFF1 and DFF2 may fail to meet the setup time requirements.
[0052] The input of flip-flop DFF2 is connected to the output of flip-flop DFF1, the set input is connected to the output of the first delay unit, and the output provides the output signal Q12. The input of the first delay unit is connected to the input signal DLL1. The first delay unit can be implemented using a flip-flop DFF4. In this case, the input terminal of the flip-flop DFF4 is connected to the power supply voltage VDD, and the set terminal serves as the input terminal of the first delay unit to receive the input signal DLL1. .
[0053] The input of flip-flop DFF3 is connected to the output of flip-flop DFF1, and the set input is connected to the output of the second delay unit. The output provides the output signal Q13. The input of the second delay unit receives the input signal DLL1 from the (i+1)th D flip-flop in the time-to-digital converter.<i+1> The second delay unit can be implemented using a flip-flop DFF5. In this case, the input of the flip-flop DFF5 is connected to the power supply voltage VDD, and the set terminal serves as the input of the second delay unit, receiving the input signal DLL1.<i+1> .
[0054] Furthermore, when i=1, the corresponding time margin extraction unit 200 is slightly different. At this time, the input terminal of the flip-flop DFF1 and the input terminal of the first delay unit are no longer connected to the input signal DLL1. Instead, it is connected to the power supply voltage VDD. When i=n, the corresponding time margin extraction unit 200 is slightly different. At this time, the input terminal of the second delay unit is no longer connected to the input signal DLL1.<i+1> Instead, it connects to the input signal DLL1. <1> .
[0055] OR gate OR1 has n inputs and one output. The n inputs are connected to the outputs of the flip-flops DFF2 of the n time margin extraction units 200, and the output provides the start signal Start1.
[0056] OR gate OR2 has n inputs and one output. The n inputs are connected to the outputs of the flip-flops DFF3 of the n time margin extraction units 200, and the output provides the stop signal Stop1.
[0057] In this embodiment of the invention, triggers DFF4 and DFF5 are preferably used as the first delay unit and the second delay unit, respectively, to completely eliminate the dead zone problem caused by trigger DFF1.
[0058] Of course, in other embodiments of the present invention, triggers DFF4 and DFF5 can also be replaced with, for example... Figure 1 The delay unit τ is shown, but the delay time is difficult to control. If the delay time is too long, the stop signal Stop1 will be sampled repeatedly. If the delay time is too short, the dead time caused by the transmission delay of the trigger DFF1 will still exist.
[0059] See Figure 5 Similarly, the rising edge of the stop signal appears on the input signal DLL1. <2> The rising edge appears, but the input signal DLL1 <3> Let's take the case where the rising edge does not appear as an example.
[0060] In input signal DLL1 <2> After a rising edge occurs, time t1 (t1 < t0) elapses, the stop signal rises, and the input signal DLL1... <2> The corresponding time margin extraction unit 200 provides a high-level output signal Q11 to the input of flip-flop DFF2 and the input of flip-flop DFF3 via flip-flop DFF1.
[0061] The set input of flip-flop DFF2 is connected to the input signal DLL1. <2> After a rising edge occurs, a new rising edge appears after a delay of t4 in the first delay unit. Then, when flip-flop DFF1 outputs a high-level output signal Q11, flip-flop DFF2 outputs a high-level input signal Q12, causing the start signal Start1 provided by OR gate OR1 to have a rising edge. When the delay time t4 equals the delay time of the flip-flops, the rising edge of the set input of flip-flop DFF2 has already arrived when the rising edge of the output signal Q11 reaches it. Therefore, ignoring the output delays of the flip-flops and OR gate, the time when the rising edge of the start signal Start1 appears can be considered synchronized with the time when the rising edge of the stop signal Stop1 appears.
[0062] The set input of flip-flop DFF3 is connected to the input signal DLL1. <3> After a rising edge occurs, a rising edge appears again after a delay of t4 in the second delay unit. Flip-flop DFF3 provides a high-level output signal Q13, and OR gate OR2 provides a rising edge for the stop signal Stop1. When the delay time t4 equals the delay time of the flip-flop, ignoring the output delays of the flip-flop and OR gate, the rising edge at the set input of flip-flop DFF3 occurs exactly t3 later than the rising edge at the input of flip-flop DFF2, where t3 = t0 - t1. Therefore, the time interval between the rising edge of the start signal Start and the rising edge of the stop signal Stop1 is the time margin that needs to be extracted.
[0063] When the delay time t4 is less than the delay time of the trigger, the dead time caused by the transmission delay of the trigger DFF1 still exists, and at this time, t3 < t0-t1, so the extracted time margin is not accurate.
[0064] When the delay time t4 is greater than the delay time of the flip-flop, the rising edge of the set terminal of the flip-flop DFF3 may appear after the rising edge of its input terminal, resulting in the sampling of the input terminal of the flip-flop DFF3 without the rising edge appearing, thus causing the stop signal Stop1 to be resampled.
[0065] The time margin extraction circuit for a time-to-digital converter provided in this embodiment of the invention includes multiple time margin extraction units 200 corresponding one-to-one with the D flip-flops of the time-to-digital converter. Each time margin extraction unit 200 includes a flip-flop DFF1, and flip-flops DFF2 and DFF3 whose input terminals are connected to the output terminals of flip-flop DFF1. The input and set terminals of flip-flop DFF1 are respectively connected to the set terminal of pseudo-flip-flop DMY1 and the input terminal of pseudo-flip-flop DMY2, which allows the input and set terminals of flip-flop DFF1 to be driven simultaneously, reducing the setup time of flip-flop DFF1 and improving the occurrence of the rising edge of the stop signal on the input signal DLL1. When the time is set, flip-flops DFF1 and DFF2 may fail to meet the setup time requirements. Furthermore, flip-flops DFF4 and DFF5 are used to delay the inputs of both flip-flops DFF2 and DFF3, improving the measurement accuracy of the time-to-digital converter and ensuring a dead-time-free time extraction circuit, thus enhancing the continuous measurement capability of the time-to-digital converter.
[0066] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents. < / n> < / n>
Claims
1. A time margin extraction circuit for a time-to-digital converter, the time-to-digital converter comprising a plurality of D flip-flops arranged sequentially, a first start signal providing a plurality of input signals to the input terminals of the plurality of D flip-flops via a delay chain, and a first stop signal being provided to the set terminals of the plurality of D flip-flops, the time margin extraction circuit comprising: Multiple time margin extraction units correspond one-to-one with multiple D flip-flops of the time-to-digital converter; The first OR gate has multiple input terminals and one output terminal. The multiple input terminals respectively receive the first output signals of the multiple time margin extraction units, and the output terminal provides a second start signal. The second OR gate has multiple input terminals and one output terminal. The multiple input terminals respectively receive the second output signals of the multiple time margin extraction units, and the output terminal provides a second termination signal. Each of the time margin extraction units includes: The first flip-flop receives a first input signal at its input terminal and a first stop signal at its set terminal. The second flip-flop has its input terminal connected to the output terminal of the first flip-flop, its set terminal connected to the first input signal delayed by the first delay unit, and its output terminal providing the first output signal. The third flip-flop has its input connected to the output of the first flip-flop, its set terminal connected to the second input signal delayed by the second delay unit, and its output terminal providing the second output signal. The first pseudo-flip-flop has its input and output terminals left floating, and its set terminal connected to the input terminal of the first flip-flop. The second pseudo-flip-flop has its set and output terminals left floating, while its input terminal is connected to the set terminal of the second flip-flop.
2. The time margin extraction circuit according to claim 1, wherein, The delay time of the first delay unit and the second delay unit are the same.
3. The time margin extraction circuit according to claim 2, wherein, The output delay times of the first to third flip-flops are the same, and the delay times of the first delay unit and the second delay unit are equal to the output delay time of the flip-flops.
4. The time margin extraction circuit according to claim 3, wherein, The first delay unit includes: The fourth flip-flop has its input terminal connected to the power supply voltage, its set terminal serving as the input terminal of the first delay unit connected to the first input signal, and its output terminal connected to the set terminal of the second flip-flop.
5. The time margin extraction circuit according to claim 3, wherein, The second delay unit includes: The fifth flip-flop has its input terminal connected to the power supply voltage, its set terminal serving as the input terminal of the second delay unit connected to the second input signal, and its output terminal connected to the set terminal of the third flip-flop.
6. The time margin extraction circuit according to claim 1, wherein, The first input signal of the time margin extraction unit corresponding to the first D flip-flop is the power supply voltage, and the first input signal of the remaining time margin extraction units is the input signal of their corresponding D flip-flops.
7. The time margin extraction circuit according to claim 1, wherein, The second input signal of the time margin extraction unit corresponding to the last D flip-flop is the input signal of the first D flip-flop, and the second input signal of the remaining time margin extraction units is the input signal of the next D flip-flop of its corresponding D flip-flop.
8. The time margin extraction circuit according to claim 1, wherein, The time interval between the second start signal and the second stop signal represents the time margin that is not quantized by the time-to-digital converter.
9. A time-to-digital converter, comprising: A series of D flip-flops are arranged in sequence. A first start signal is provided to the input terminals of the multiple D flip-flops via a delay chain, and a first stop signal is provided to the set terminals of the multiple D flip-flops. A thermometer code converter is used to convert the output signals of multiple D flip-flops into binary code. as well as The time margin extraction circuit as described in any one of claims 1-8 is used to extract the time margin that has not been converted by the thermometer code converter.
10. The time-to-digital converter according to claim 9, wherein, The time interval between the rising edges of the input signals of two adjacent D flip-flops is the same.