Array substrate manufacturing method, array substrate, display panel and display
By setting an etching protection layer on the silicon nitride layer and performing protective hole etching, the problems of poor etching quality and interface chamfer of the organic photoresist layer are solved, achieving more efficient etching and hole opening quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HKC CORP LTD
- Filing Date
- 2023-03-30
- Publication Date
- 2026-07-07
AI Technical Summary
Existing technologies result in poor etching quality of the organic photoresist layer and the formation of chamfers at the interface between the organic photoresist and silicon nitride during the etching process.
An etching protection layer is set on the silicon nitride layer, and etching protection holes are made on it. After etching the silicon nitride layer through the etching protection holes, the etching protection layer is removed. Then, a pixel layer is set on the silicon nitride layer, and holes are made on the organic photoresist layer.
It effectively avoids the interface chamfering problem during the etching of organic photoresist and silicon nitride, improving etching efficiency and hole quality.
Smart Images
Figure CN116525621B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a method for fabricating an array substrate, an array substrate, a display panel, and a display. Background Technology
[0002] With the development of science and technology and the progress of society, the use of displays has gradually become widespread in people's lives and work. In the manufacturing process of thin film transistor liquid crystal display (TFT-LCD), it is necessary to open holes in the stack of organic photoresist and silicon nitride to achieve the purpose of conduction. However, currently, the organic photoresist and silicon nitride are etched and opened at the same time. Since organic photoresist and silicon nitride are different types of materials, the etching process will lead to poor etching quality of the organic photoresist layer and the problem of interface chamfering between organic photoresist and silicon nitride.
[0003] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art.
[0004] Application content
[0005] The main objective of this application is to provide a method for fabricating an array substrate, an array substrate, a display panel, and a display, which aims to solve the technical problems of poor etching quality of organic photoresist layers and the formation of interface chamfers between organic photoresist and silicon nitride during the etching process in the prior art.
[0006] To achieve the above objectives, the array substrate fabrication method includes:
[0007] A substrate is provided, a silicon nitride layer is deposited on the substrate, and the via regions on the silicon nitride layer that require openings are defined;
[0008] An etching protection layer is formed on the silicon nitride layer, and etching protection holes are formed on the etching protection layer, the positions of the etching protection holes corresponding to the positions of the via areas;
[0009] The silicon nitride layer is etched based on the etched protective hole positions to create holes on the silicon nitride layer at positions corresponding to the via regions.
[0010] Remove the etched protective layer;
[0011] A pixel layer is disposed on a substrate including the silicon nitride layer;
[0012] An organic photoresist layer is disposed on a substrate including the pixel layer, and an opening is made on the organic photoresist layer at a position corresponding to the via region.
[0013] Optionally, the step of forming an etching protection layer on the silicon nitride layer and opening etching protection holes on the etching protection layer includes:
[0014] An etching protection layer is coated on the silicon nitride layer, and the etching protection layer is exposed and developed.
[0015] Etching is performed on the developed etch protection layer to create etch protection holes at positions corresponding to the via regions on the etch protection layer, the etch protection layer comprising photoresist.
[0016] Optionally, the step of forming a pixel layer on a substrate including the silicon nitride layer includes:
[0017] A pixel layer is formed on a substrate including the silicon nitride layer, and a hole is made on the pixel layer at a position corresponding to the via region.
[0018] Optionally, the step of forming a pixel layer on a substrate including the silicon nitride layer and opening a hole on the pixel layer at a position corresponding to the via region includes:
[0019] A pixel layer is formed on a substrate including the silicon nitride layer, and the pixel layer is exposed and developed.
[0020] Etching is performed on the developed pixel layer to create holes at locations corresponding to the via regions on the pixel layer.
[0021] Optionally, the step of forming an organic photoresist layer on a substrate including the pixel layer and making an opening in the organic photoresist layer at a position corresponding to the via region includes:
[0022] An organic photoresist layer is disposed on a substrate including the pixel layer, and the organic photoresist layer is exposed and developed.
[0023] Etching is performed on the developed organic photoresist layer to create holes at locations corresponding to the via regions on the organic photoresist layer.
[0024] Optionally, etching the silicon nitride layer based on the etched protective hole positions to create holes in the silicon nitride layer at positions corresponding to the via regions includes:
[0025] Based on the etching protection hole positions, the silicon nitride layer is dry etched with etching gas to create holes on the silicon nitride layer at positions corresponding to the via regions.
[0026] Optionally, the etching gas is a mixed gas, which includes fluorinated gas and chlorine gas;
[0027] The fluorinated gases include sulfur hexafluoride and nitrogen trifluoride.
[0028] In addition, to achieve the above objectives, this application also provides an array substrate, which is prepared according to the above-described array substrate preparation method.
[0029] In addition, to achieve the above objectives, this application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and the array substrate described above, wherein the liquid crystal layer is located between the color filter substrate and the array substrate.
[0030] In addition, to achieve the above objectives, this application also provides a display, which includes a backlight module and the aforementioned display panel. The backlight module is disposed on the back side of the display panel and is used to provide a backlight source to the display panel.
[0031] This application provides a method for fabricating an array substrate, the method comprising: providing a substrate; depositing a silicon nitride layer on the substrate and determining via regions on the silicon nitride layer for which vias are to be made; forming an etching protection layer on the silicon nitride layer and forming etching protection vias on the etching protection layer, the positions of the etching protection vias corresponding to the positions of the via regions; etching the silicon nitride layer based on the etching protection vias to create vias at the positions corresponding to the via regions on the silicon nitride layer; removing the etching protection layer; forming a pixel layer on the substrate including the silicon nitride layer; forming an organic photoresist layer on the substrate including the pixel layer; and forming vias on the organic photoresist layer at the positions corresponding to the via regions. The invention involves creating an etching protection layer on a silicon nitride layer and then creating etching protection holes at the corresponding via areas on the etching protection layer. The silicon nitride layer is then etched based on these etching protection holes. This allows for the creation of vias while protecting the silicon nitride film with an etching protection layer. After removing the etching protection layer, a pixel layer is formed on a substrate including the silicon nitride layer. An organic photoresist layer is then formed on the substrate including the pixel layer, and vias are created at the corresponding via areas on the organic photoresist layer. Because the invention etches the silicon nitride layer first and then creates the organic photoresist layer, it effectively avoids the chamfering problem that occurs when etching both silicon nitride and organic photoresist simultaneously, thus improving etching efficiency and via quality. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only the drawings corresponding to this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0033] Figure 1 This is a schematic flowchart of the array substrate fabrication method in the first embodiment of this application;
[0034] Figure 2 This is a schematic diagram of the first state of the array substrate during the fabrication process in the first embodiment of this application;
[0035] Figure 3 This is a schematic diagram of the second state of the array substrate during the fabrication process in the first embodiment of this application;
[0036] Figure 4 This is a schematic diagram of the third state of the array substrate during the fabrication process in the first embodiment of this application;
[0037] Figure 5 This is a schematic diagram of the fourth state of the array substrate during the fabrication process in the first embodiment of this application;
[0038] Figure 6 This is a schematic diagram of the fifth state of the array substrate during the fabrication process in the first embodiment of this application;
[0039] Figure 7 This is a schematic diagram of the sixth state of the array substrate during the fabrication process in the first embodiment of this application;
[0040] Figure 8 This is a schematic diagram showing the interface chamfer caused by the inconsistent aperture sizes between the silicon nitride layer and the organic photoresist layer in the first embodiment of this application;
[0041] Figure 9 This is a photograph of the chamfer caused by the inconsistent opening rates of the silicon nitride layer and the organic photoresist layer in the prior art of the first embodiment of this application.
[0042] Figure 10 This is a schematic diagram of the PFA layer and silicon nitride layer after the opening is completed in the first embodiment of this application;
[0043] Figure 11 This is a schematic diagram of the structure of the display panel embodiment of this application;
[0044] Figure 12 This is a schematic diagram of the structure of an embodiment of the display of this application.
[0045] Explanation of icon numbers:
[0046] label name label name 10 substrate 20 silicon nitride layer 30 Etching protective layer 40 Pixel layer 50 Organic photoresist layer 60 Array substrate 70 Liquid crystal layer 80 Color film substrate 90 Display panel 100 Backlight module 110 Interface chamfer
[0047] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0049] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.
[0050] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.
[0051] In the current TFT-LCD manufacturing process, the stack of organic photoresist and silicon nitride is dry etched simultaneously. It is very difficult to adjust the ratio and parameters of the dry etching gas when etching two different film layers at the same time, which makes the etching difficult and inefficient. Moreover, simultaneous etching will result in rough surface of the organic photoresist layer and chamfering problems at the interface between the organic photoresist layer and silicon nitride.
[0052] In view of this, this application proposes a method for fabricating an array substrate, wherein... Figure 1 This is a schematic flowchart of an array substrate fabrication method provided in this application.
[0053] The method for fabricating the array substrate includes:
[0054] Step S1: Provide a substrate, deposit a silicon nitride layer on the substrate, and determine the via areas on the silicon nitride layer that require openings;
[0055] Step S2: An etching protection layer is formed on the silicon nitride layer, and etching protection holes are formed on the etching protection layer. The positions of the etching protection holes correspond to the positions of the via areas.
[0056] Step S3: Etch the silicon nitride layer based on the etched protective hole position to create a hole on the silicon nitride layer at the position corresponding to the via area;
[0057] Step S4: Remove the etched protective layer;
[0058] Step S5: Form a pixel layer on a substrate including the silicon nitride layer;
[0059] Step S6: An organic photoresist layer is formed on the substrate including the pixel layer, and an opening is made on the organic photoresist layer at the position corresponding to the via region.
[0060] It should be noted that the substrate 10 can be a glass substrate 10. The aforementioned organic photoresist layer 50 can be PFA (acrylic resin & silicone resin). The aforementioned pixel layer 40 can be an RGB layer (i.e., red, green, and blue chromaticity layer). Silicon nitride acts as an insulating layer to isolate the sub-pixel layer 40 from the metal layer. In addition to its insulating function, PFA can also flatten the RGB terrain. The aforementioned etching protection layer 30 can be photoresist, which can be removed using a stripping solution through a photoresist process. The aforementioned via area can be the area where openings are required. The aforementioned etching protection hole positions can be holes made in the etching protection layer 30 to protect the silicon nitride openings.
[0061] It should be understood that, with reference Figures 2 to 7 , Figures 2 to 7 This is a schematic diagram illustrating the state during the fabrication process of the array substrate in this embodiment. This embodiment provides a substrate 10, on which silicon nitride is deposited to form the first state of the array substrate during the fabrication process. (Refer to...) Figure 2 , Figure 2 This is a schematic diagram of the first state of the array substrate during fabrication. The via regions on the silicon nitride layer that require openings are determined. After silicon nitride film deposition, an etching protection layer 30 is formed on the silicon nitride layer 20. Etching protection holes are formed on the etching protection layer 30 at the positions corresponding to the via regions to form the second state of the array substrate during fabrication. (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the second state of the array substrate during fabrication; openings are made in the silicon nitride through the etched protective holes to form the third state of the array substrate during fabrication, as shown in the diagram. Figure 4 , Figure 4 This is a schematic diagram of the third state of the array substrate during fabrication, effectively avoiding the problem of over-etching. The etch protection layer 30 is removed using a photoresist process to form the fourth state of the array substrate during fabrication, as shown in the diagram. Figure 5 , Figure 5This is a schematic diagram of the fourth state of the array substrate during fabrication; a pixel layer 40 is formed on the substrate 10 including the silicon nitride layer 20, and openings are made on the pixel layer 40 at positions corresponding to the via regions to form the fifth state of the array substrate during fabrication, as shown in the diagram. Figure 6 , Figure 6 This is a schematic diagram of the fifth state of the array substrate during fabrication; an organic photoresist layer 50 is disposed on the substrate 10 including the pixel layer 40, and openings are made in the organic photoresist layer 50 at positions corresponding to the via regions to form the sixth state of the array substrate during fabrication, as shown below. Figure 7 , Figure 7 This diagram illustrates the sixth state of the array substrate during its fabrication process. By optimizing the TFT-LCD manufacturing process and performing the opening processes for the organic photoresist film and silicon nitride film separately, the fabrication difficulty of the array substrate is reduced, and the problems of non-illumination of TFT-LCD panel areas and fragments caused by PFA surface roughness and interface chamfers are improved, thereby increasing the yield of TFT-LCD display panels.
[0062] It should be noted that, compared with the prior art, this embodiment can effectively avoid the problem of chamfering. The prior art involves simultaneously dry etching the silicon nitride layer and the organic photoresist layer using a mixed gas. Since silicon nitride and organic photoresist are completely different materials, simultaneous gas etching of both makes it impossible to accurately control their etching rates and to properly configure the gas composition and ratio in the etching mixed gas. This leads to significant etching difficulty due to the difficulty in configuring the mixed gas. Furthermore, the inconsistent etching rates of silicon nitride and organic photoresist result in inconsistent aperture sizes during etching, causing interface chamfering. (Refer to...) Figure 8 and Figure 9 , Figure 8 This diagram illustrates the interface chamfering that occurs when the etching rates of silicon nitride and organic photoresist differ, resulting in inconsistent aperture sizes. Figure 9 A real-life image showing the chamfer between the PFA layer and the silicon nitride layer, for reference. Figure 9 It is known that existing technologies simultaneously perform gas etching to create openings in both the PFA and silicon nitride layers, resulting in a significant chamfering problem between the PFA and silicon nitride layers, such as... Figure 9 The circled area represents the chamfer at the interface between the PFA and silicon nitride. In this embodiment, the silicon nitride layer is etched first to create openings, and then an organic photoresist layer is applied for openings. This allows for reasonable and effective control over the opening size and etching rate during opening, ensuring that the opening sizes on both the silicon nitride and organic photoresist layers are consistent. This effectively avoids the chamfering problem during the opening process. (Refer to...) Figure 10 , Figure 10This is a schematic diagram of the PFA layer and silicon nitride layer after the opening is completed in this embodiment. Figure 10 It is evident that in this embodiment, after creating holes in the PFA layer and silicon nitride layer respectively, no chamfer is formed between them, such as... Figure 10 The area circled in the image shows a natural transition between PFA and silicon nitride, with no chamfer at the interface.
[0063] Furthermore, in order to improve the etching efficiency of the etch protective layer and enhance the protection of the silicon nitride layer, step S2 may include:
[0064] Step S21: Coat an etching protective layer on the silicon nitride layer, and expose and develop the etching protective layer;
[0065] Step S22: Etch on the developed etch protection layer to create etch protection holes at the locations corresponding to the via areas on the etch protection layer, wherein the etch protection layer includes photoresist.
[0066] It should be noted that the etching protective layer can be a protective structure for silicon nitride image fabrication; for example, the etching protective layer can be a protective layer composed of photoresist. In this embodiment, after the silicon nitride layer 20 is formed, photoresist is coated on the silicon nitride layer 20 to protect the silicon nitride during etching and opening. Specifically, this includes exposing the photoresist and opening etching protective holes at the corresponding via areas on the developed photoresist layer, thereby achieving the etching protection effect on the silicon nitride layer 20, improving the subsequent hole opening efficiency and ensuring the hole opening quality.
[0067] It should be understood that, in order to accurately create openings in the silicon nitride layer and avoid etching of areas on the silicon nitride layer that do not require openings during the opening process, this embodiment applies an etching protection layer to the silicon nitride layer after the silicon nitride film is formed. The opening positions on the etching protection layer are determined based on the locations on the silicon nitride layer where openings are required. The etching protection layer is then exposed and developed based on the locations where openings are required. Specifically, this includes: exposing the opening positions; developing the opening positions with a developer after exposure; thereby creating etch protection holes on the etching protection layer; then performing gas etching to create openings at the locations of the via areas on the silicon nitride where openings are required through the etch protection holes; and finally, removing the photoresist using a stripper solution after the silicon nitride opening is completed. This achieves protection of the silicon nitride openings and effectively avoids the problem of inaccurate etching during the silicon nitride opening process.
[0068] Furthermore, in order to effectively set the pixel layer, step S5 above may include:
[0069] Step S51: Form a pixel layer on a substrate including the silicon nitride layer, and expose and develop the pixel layer;
[0070] Step S52: Etch on the developed pixel layer to create an opening at the location corresponding to the via region on the pixel layer 40.
[0071] It should be noted that pixel layer 40 can be an RGB layer (i.e., red, green and blue chromaticity layer), silicon nitride is an insulating layer that isolates sub-pixel layer 40 from the metal layer, and PFA can flatten the RGB terrain in addition to its insulating function.
[0072] It should be understood that after the pixel layer 40 is coated, different development capabilities will occur at the longitudinal position of the etching during vacuuming, soft baking, exposure and development, thus forming a slope. The angle between the pixel layer 40 and silicon nitride can be 30 to 60°, and the openings of the pixel layer 40 will be larger than those of silicon nitride.
[0073] In practice, the exposure environment requires a cleanliness level of less than 1000, the coating thickness of the pixel layer 40 can be 2.2um / 2.2um / 2.4um, the soft baking temperature of the pixel layer 40 can be 90-100℃, the exposure energy can be 30-50mj, and the development time can be 40-80s.
[0074] Furthermore, in order to improve the opening efficiency of the organic photoresist layer, step S6 above may include:
[0075] Step S61: An organic photoresist layer is disposed on a substrate including the pixel layer, and the organic photoresist layer is exposed and developed;
[0076] Step S62: Etch on the developed organic photoresist layer to create a hole at the location corresponding to the via region on the organic photoresist layer.
[0077] It should be noted that the organic photoresist layer 50 can be PFA (acrylic resin & silicone resin).
[0078] It should be understood that in this embodiment, by covering the pixel layer 40 with the organic photoresist layer 50, an insulating effect is achieved, and the RGB terrain can be flattened. The organic photoresist layer 50 is etched after vacuuming, soft baking, exposure, and development, so that while ensuring that the organic photoresist layer 50 can cover the pixel layer 40, holes can be opened at the positions corresponding to the via areas. Compared with the prior art, since the prior art uses dry etching gas to etch and open holes in PFA, the PFA (siloxane resin) reacts with oxygen (O2) in the dry etching gas to generate SiO2 (precipitate), resulting in a rough PFA surface. In this embodiment, the PFA is opened by exposure and development, thereby effectively avoiding the problem of precipitate generation during the opening process and improving the problem of PFA surface roughness.
[0079] In practice, the exposure environment requires a cleanliness level of less than 1000, the coating thickness of the pixel layer 40 can be 2.1µm, the soft baking temperature of the pixel layer 40 can be 95-110℃, the exposure energy can be 50-100mJ, and the development time can be 60-90s.
[0080] It should be noted that the developer used for developing organic photoresist layers is different from the developer used for developing pixel layers.
[0081] It should be understood that in this embodiment, an organic photoresist layer is coated on the pixel layer, and the via area is set as the exposure area. The corresponding position of the via area on the organic photoresist layer is exposed. After the via area on the PFA layer reacts with light, it can be dissolved in the developer (e.g., tetramethylammonium hydroxide). After the development process, the PFA can be washed with water to remove surface residues. Compared with the existing technology of opening holes in the PFA layer by gas dry etching, the method of opening holes in the PFA layer in this embodiment effectively avoids the problem of deposits in the PFA layer causing roughness on the PFA layer surface.
[0082] Furthermore, in order to improve the opening efficiency of the silicon nitride layer, step S3 above may include:
[0083] Step S31: Based on the etching protection hole position, dry etch the silicon nitride layer with etching gas to open a hole on the silicon nitride layer at the position corresponding to the via area.
[0084] It should be noted that the etching gas is a mixed gas, which includes fluorinated gas and chlorine; the fluorinated gas includes sulfur hexafluoride and nitrogen trifluoride.
[0085] It should be understood that during dry etching, the lateral and vertical etching power, etching time, and gas ratio can be controlled to control the opening of the vias; dry etching needs to be performed under vacuum. Since this embodiment creates vias at the corresponding via regions of the silicon nitride layer based on etch protection holes, the silicon nitride layer can be accurately opened by adjusting the position and size of the etch protection holes on the etch protection layer. By adjusting the composition and ratio of the etching gas, as well as the etching time and etching power, accurate opening of the silicon nitride layer can be achieved, avoiding problems of inaccurate hole size and position.
[0086] In specific implementations, the lateral etching power of dry etching can be 8000–12000W, the vertical etching power can be 5000–8000W, the etching time can be 70–105s, and the etching pressure can be 20–40mTorr. This embodiment controls the silicon nitride (Si) aperture size by controlling the dry etching time and the PFA (Plasma Acrylic Acid) aperture size by controlling the exposure and development parameters. Since this embodiment first performs gas etching to create apertures in the SiN layer and then performs exposure etching to create apertures in the PFA, ensuring that the SiN and PFA aperture sizes are consistent, the aperture sizes of SiN and PFA can be controlled separately. This effectively avoids the problem of inconsistent aperture rates between SiN and PFA caused by simultaneous aperture creation, which leads to an inability to accurately control their aperture sizes and prevents interface chamfering issues due to inconsistent aperture sizes. The etching gas may include 30% nitrogen trifluoride, 20% sulfur hexafluoride, and 50% chlorine. That is, the ratio of sulfur hexafluoride, nitrogen trifluoride, and chlorine in the mixed gas can be 2:3:5. Since the etching gas used in this embodiment during dry etching is mainly F-series gases such as SF6 and NF3, which do not contain O2; the etching component is silicon nitride without siloxane resin; and the process reaction does not generate SiO2 precipitates, the problem of rough silicon nitride surface is effectively avoided.
[0087] This embodiment provides a method for fabricating an array substrate. The method includes: providing a substrate; depositing a silicon nitride layer on the substrate and determining via regions on the silicon nitride layer where vias are required; setting an etching protection layer on the silicon nitride layer and forming etching protection vias on the etching protection layer, the positions of the etching protection vias corresponding to the positions of the via regions; etching the silicon nitride layer based on the etching protection vias to create vias at the positions corresponding to the via regions on the silicon nitride layer; removing the etching protection layer; forming a pixel layer on the substrate including the silicon nitride layer; forming an organic photoresist layer on the substrate including the pixel layer; and forming vias on the organic photoresist layer at the positions corresponding to the via regions. The method involves creating an etch protection layer on the silicon nitride layer and then creating etch protection holes at the corresponding via areas on the etch protection layer. The silicon nitride layer is then etched based on these etch protection holes. This allows for the creation of etched holes while protecting the silicon nitride film after deposition. The etch protection layer is then removed, and a pixel layer is formed on the substrate containing the silicon nitride layer. An organic photoresist layer is then formed on the substrate containing the pixel layer, and holes are created at the corresponding via areas on the organic photoresist layer. Because this embodiment etches the silicon nitride layer first and then creates holes on the organic photoresist layer, it effectively avoids the chamfering problem that occurs when etching both silicon nitride and organic photoresist simultaneously, thus improving etching efficiency and hole quality.
[0088] Furthermore, this application also proposes an array substrate 60, which is prepared according to the above-described array substrate preparation method.
[0089] Furthermore, this application also proposes a display panel 90, which is applied to the array substrate 60 of the above embodiments, referring to... Figure 11 , Figure 11 This is a schematic diagram of the structure of a display panel embodiment of the present application. The display panel includes an array substrate 60 as described above, a color filter substrate 80 disposed opposite to the array substrate 60, and a liquid crystal layer 70 sandwiched between the array substrate 60 and the color filter substrate 80.
[0090] Furthermore, embodiments of this application also propose a display, referring to... Figure 12 , Figure 12 This is a schematic diagram of the structure of a display embodiment of the present application. The display includes a display panel 90 as described in the above embodiment and a backlight module 100. The backlight module 100 is disposed on the back side of the display panel 90 and is used to provide a backlight source to the display panel 90 of the above embodiment.
[0091] Since this display adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.
[0092] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
[0093] Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.
[0094] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0095] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of a person skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, the user should consider such a combination of technical solutions to be non-existent and not within the scope of protection claimed in this application.
Claims
1. A method for fabricating an array substrate, characterized in that, The method for fabricating the array substrate includes: A substrate is provided, a silicon nitride layer is deposited on the substrate, and the via regions on the silicon nitride layer that require openings are defined; An etching protection layer is formed on the silicon nitride layer, and etching protection holes are formed on the etching protection layer, the positions of the etching protection holes corresponding to the positions of the via areas; The silicon nitride layer is etched based on the etched protective hole positions to create holes on the silicon nitride layer at positions corresponding to the via regions. Remove the etched protective layer; A pixel layer is formed on a substrate including the silicon nitride layer, and a hole is made on the pixel layer at a position corresponding to the via region; An organic photoresist layer is disposed on a substrate including the pixel layer, and an opening is made on the organic photoresist layer at a position corresponding to the via region.
2. The method for fabricating an array substrate as described in claim 1, characterized in that, The step of setting an etching protection layer on the silicon nitride layer and forming etching protection holes on the etching protection layer includes: An etching protection layer is coated on the silicon nitride layer, and the etching protection layer is exposed and developed. Etching is performed on the developed etch protection layer to create etch protection holes at positions corresponding to the via regions on the etch protection layer, the etch protection layer comprising photoresist.
3. The method for fabricating an array substrate as described in claim 1, characterized in that, The step of forming a pixel layer on a substrate including the silicon nitride layer and making holes on the pixel layer at positions corresponding to the via regions includes: A pixel layer is formed on a substrate including the silicon nitride layer, and the pixel layer is exposed and developed. Etching is performed on the developed pixel layer to create holes at locations corresponding to the via regions on the pixel layer.
4. The method for fabricating an array substrate as described in claim 1, characterized in that, The step of forming an organic photoresist layer on a substrate including the pixel layer, and making an opening in the organic photoresist layer at a position corresponding to the via region, includes: An organic photoresist layer is disposed on a substrate including the pixel layer, and the organic photoresist layer is exposed and developed. Etching is performed on the developed organic photoresist layer to create holes at locations corresponding to the via regions on the organic photoresist layer.
5. The method for fabricating an array substrate as described in claim 1, characterized in that, The etching of the silicon nitride layer based on the etched protective via locations to create vias at positions corresponding to the via regions on the silicon nitride layer includes: Based on the etching protection hole positions, the silicon nitride layer is dry etched with etching gas to create holes on the silicon nitride layer at positions corresponding to the via regions.
6. The method for fabricating an array substrate as described in claim 5, characterized in that, The etching gas is a mixed gas, which includes fluorinated gas and chlorine gas; The fluorinated gases include sulfur hexafluoride and nitrogen trifluoride.
7. An array substrate, characterized in that, The array substrate is prepared by the array substrate preparation method according to any one of claims 1 to 6.
8. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate as described in claim 7, wherein the liquid crystal layer is located between the color filter substrate and the array substrate.
9. A display, characterized in that, The display includes a backlight module and a display panel as described in claim 8. The backlight module is disposed on the back side of the display panel and is used to provide a backlight source to the display panel.