Fourth-order pulse amplitude modulation baud rate phase discrimination method, cdr circuit and receiver

Abstract

This invention discloses a fourth-order pulse amplitude modulation (PWM) baud rate phase detection method, a CDR circuit, and a receiver. The phase detection method includes: determining slope information based on three adjacent sampled data D(n-1), D(n), and D(n+1); determining three adjacent error types E(n-1), E(n), and E(n+1); if E(n) is a valid error type, then the phase detection result of the nth sampled data D(n) is obtained based on E(n) and the slope information; otherwise, the phase detection result of the nth sampled data D(n) is obtained based on E(n-1) or E(n+1) which is a valid error type, combined with the slope information. This invention can obtain phase information for all monotonic changes, achieve high BRPD gain, and enable the CDR circuit to have higher conversion density and lower jitter, and it is easily implemented using digital circuits.

Description

Technical Field

[0001] This invention relates to the field of high-speed serial data communication, specifically to a fourth-order pulse amplitude modulation (PAM4) baud rate phase detection method, a CDR circuit, and a receiver. Background Technology

[0002] Serializers / deserializers (SerDes) are one of the mainstream technologies for high-speed serial data communication. Due to their low cost, high speed, and strong anti-interference capabilities, they are widely used in applications such as Ethernet, fiber optic communication, and wireless communication. Clock and Data Recovery (CDR) circuits are an important component of SerDes. Their main function is to extract clock information from input data containing amplitude and phase noise, and then retime the data. Based on the sampling frequency, CDRs can be divided into baud rate sampling CDRs and oversampling CDRs. Baud rate sampling CDRs refer to CDRs where the sampling frequency is equal to the baud rate of the input data. It calculates the phase error between the local clock and the input data through subsequent digital processing. Oversampling CDRs refer to CDRs where the number of samples within a single unit (UI) is two or more.

[0003] Compared to traditional oversampling techniques, baud rate phase detectors require only one sampling clock cycle per unit interval, half the sampling clock rate, making them well-suited for high-speed CDR circuits based on ADC structures. In the CDR circuit structure, the gain of the fourth-order pulse amplitude modulation baud rate phase detector (PAM4 BRPD) (BRPD gain) is crucial for the PAM4 clock recovery loop; insufficient BRPD gain significantly weakens the performance of the PAM4 clock recovery loop. However, existing BRPDs suffer from two main problems: ① their gains are generally very small; ② there is a lack of linearization modeling for the PAM4 BRPD gain, resulting in a lack of intuitive analysis in the design of key parameters for the clock recovery loop. Therefore, effectively improving the PAM4 BRPD gain and establishing a PAM4 BRPD gain parameter model are critical technical issues that urgently need to be addressed. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a fourth-order pulse amplitude modulation baud rate phase detection method, a CDR circuit and a receiver, which can obtain phase information for all monotonic changes, achieve high BRPD gain, and enable the CDR circuit to have higher conversion density and lower jitter, and can be easily implemented with digital circuits.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A fourth-order pulse amplitude modulation baud rate phase detection method includes:

[0007] S101, determine the slope information based on three adjacent sampled data D(n-1), D(n), and D(n+1);

[0008] S102, based on the sampling point region of the sampled data, determine three adjacent error types E(n-1), E(n), and E(n+1). If E(n) is a valid error type, then obtain the phase detection result of the nth sampled data D(n) based on E(n) and the slope information. If E(n) is an invalid error type, and E(n-1) or E(n+1) is a valid error type, then obtain the phase detection result of the nth sampled data D(n) based on E(n-1) or E(n+1) which is a valid error type and the slope information.

[0009] Optionally, in step S102, when determining three adjacent error types E(n-1), E(n), and E(n+1) based on the sampling point region of the sampled data, the sampling point region is divided into continuously distributed regions I to VII according to the voltage in ascending order. If the sampling point region of the sampled data is located in region IV, the corresponding error type is the first error type. If the sampling point region of the sampled data is located in region I, region VII, region III, or region V, the corresponding error type is the second error type. If the sampling point region of the sampled data is located in region II or region VI, the corresponding error type is the third error type. The effective error type refers to the first and third error types, and the invalid error type refers to the second error type.

[0010] Optionally, the error type encoding includes three types: 00, 11, and 01, where 00 represents the first error type, 11 represents the third error type, and 01 represents the second error type.

[0011] Optionally, the slope information determined in step S102 is composed of the comparison results of the sampled data D(n-1) and D(n) and the comparison results of the sampled data D(n) and D(n+1).

[0012] Optionally, the phase discrimination result of phase lead or lag obtained according to E(n) and the combined slope information in step S102 includes: when the determined slope information is D(n-1) < D(n) ≤ D(n+1) or D(n-1) ≤ D(n) < D(n+1), and the nth error type E(n) is 00, if the value of the nth sampling data D(n) is +3, the phase discrimination result is no information; if the value of the nth sampling data D(n) is +1, the phase discrimination result is lead; if the value of the nth sampling data D(n) is -1, the phase discrimination result is lag; if the value of the nth sampling data D(n) is -3, the phase discrimination result is no information; when the determined slope information is D(n-1) < D(n) ≤ D(n+1) or D(n-1) ≤ D(n) < D(n+1), and the nth error type E(n) is 11, if the value of the nth sampling data D(n) is +3, the phase discrimination result is lead; if the value of the nth sampling data D(n) is +1, the phase discrimination result is lag; if the value of the nth sampling data D(n) is -1, the phase discrimination result is lead; if the value of the nth sampling data D(n) is -3, the phase discrimination result is lag; when the determined slope information is D(n-1) ≥ D(n) > D(n+1) or D(n-1) > D(n) ≥ D(n+1), and the nth error type E(n) is 00, if the value of the nth sampling data D(n) is +3, the phase discrimination result is no information; if the value of the nth sampling data D(n) is +1, the phase discrimination result is lag; if the value of the nth sampling data D(n) is -1, the phase discrimination result is lead; if the value of the nth sampling data D(n) is -3, the phase discrimination result is no information; when the determined slope information is D(n-1) ≥ D(n) > D(n+1) or D(n-1) > D(n) ≥ D(n+1), and the nth error type E(n) is 11, if the value of the nth sampling data D(n) is +3, the phase discrimination result is lag; if the value of the nth sampling data D(n) is +1, the phase discrimination result is lead; if the value of the nth sampling data D(n) is -1, the phase discrimination result is lag; if the value of the nth sampling data D(n) is -3, the phase discrimination result is lead.

[0013] Optionally, the phase discrimination result of obtaining the nth sampling data D(n) by combining E(n-1) or E(n+1) which is an effective error type in step S102 with the slope information includes: when the determined slope information is D(n-1) < D(n) ≤ D(n+1) and the nth error type E(n) is 01, if the (n-1)th error type E(n-1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lag; when the determined slope information is D(n-1) ≤ D(n) < D(n+1) and the nth error type E(n) is 01, if the (n+1)th error type E(n+1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lead; when the determined slope information is D(n-1) ≥ D(n) > D(n+1) and the nth error type E(n) is 01, if the (n+1)th error type E(n+1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lead; when the determined slope information is D(n-1) > D(n) ≥ D(n+1) and the nth error type E(n) is 01, if the (n-1)th error type E(n-1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lag.

[0014] In addition, the present invention also provides a CDR circuit for a high-speed serial interface, including an ADC sampler, a feed-forward equalizer FFE, a baud rate phase discriminator, a voter, a low-pass digital filter, and a phase interpolator. The ADC sampler, the feed-forward equalizer FFE, the baud rate phase discriminator, the voter, and the low-pass digital filter are connected in sequence. The phase interpolator is used to perform phase calibration on the externally input PPL clock according to the phase information output by the low-pass digital filter and then use it as the clock signal of the ADC sampler. The baud rate phase discriminator is programmed or configured to execute the above-mentioned fourth-order pulse amplitude modulation baud rate phase discrimination method.

[0015] Optionally, the low-pass digital filter is a second-order low-pass digital filter.

[0016] Optionally, the feed-forward equalizer FFE is a 4-tap feed-forward equalizer FFE.

[0017] Furthermore, the present invention also provides a SerDes receiver, including an analog front-end circuit (AFE), a phase-locked loop (PPL), a clock sampling data recovery circuit, and a sampling data channel. The clock sampling data recovery circuit is the CDR circuit used for high-speed serial interfaces. The sampling data output by the analog front-end circuit (AFE) is sent to the ADC sampler in the CDR circuit. The PPL clock output by the PPL is connected to the input of the phase interpolator in the CDR circuit. The sampling data channel includes a feedforward equalizer (FFE) and a decision feedback equalizer (DFE) connected in sequence. The output of the ADC sampler is connected to the input of the feedforward equalizer (FFE) in the sampling data channel, and the output of the decision feedback equalizer (DFE) serves as the sampling data output of the SerDes receiver.

[0018] Compared with the prior art, the present invention has the following main advantages:

[0019] 1. The fourth-order pulse amplitude modulation baud rate phase detection method of the present invention can obtain phase information for all monotonic changes through three adjacent data and three error types, realize the high BRPD gain of the fourth-order pulse amplitude modulation baud rate phase detector (PAM4BRPD), and enable the CDR circuit using the fourth-order pulse amplitude modulation baud rate phase detection method of the present invention to have higher conversion density and lower jitter compared with existing CDR circuits.

[0020] 2. The fourth-order pulse amplitude modulation baud rate phase detection method of the present invention is simple to implement and can be easily implemented using digital circuits. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of the error types and sampling areas in the PAM4 eye diagram in an embodiment of the present invention.

[0023] Figure 3 This is an analysis of the phase detection waveform and phase detection when E(n) is an effective error type in the embodiments of the present invention.

[0024] Figure 4 This is a phase detection analysis in an embodiment of the present invention when E(n) is an invalid error type.

[0025] Figure 5 This is a schematic diagram illustrating how Gaussian dithering smooths the phase detection characteristics in an embodiment of the present invention.

[0026] Figure 6 The gain simulation curve for adding Gaussian dithering phase detection with small phase difference in this embodiment of the invention is shown.

[0027] Figure 7This is a schematic diagram of the SerDes receiver and its CDR circuit in an embodiment of the present invention.

[0028] Figure 8 The results are simulation results of the performance of the PAM4 baud rate CDR circuit in the embodiments of the present invention. Detailed Implementation

[0029] like Figure 1 As shown, the fourth-order pulse amplitude modulation baud rate phase detection method in this embodiment includes:

[0030] S101, determine the slope information based on three adjacent sampled data D(n-1), D(n), and D(n+1);

[0031] S102, based on the sampling point region of the sampled data, determine three adjacent error types E(n-1), E(n), and E(n+1). If E(n) is a valid error type, then obtain the phase detection result of the nth sampled data D(n) based on E(n) and the slope information. If E(n) is an invalid error type, and E(n-1) or E(n+1) is a valid error type, then obtain the phase detection result of the nth sampled data D(n) based on E(n-1) or E(n+1) which is a valid error type and the slope information.

[0032] See Figure 2 In step S102 of this embodiment, when determining three adjacent error types E(n-1), E(n), and E(n+1) based on the sampling point region of the sampled data, the sampling point region is divided into continuously distributed regions I to VII according to the voltage in ascending order. If the sampling point region of the sampled data is located in region IV, the corresponding error type is the first error type. If the sampling point region of the sampled data is located in region I, VII, III, or V, the corresponding error type is the second error type. If the sampling point region of the sampled data is located in region II or VI, the corresponding error type is the third error type. The effective error type refers to the first and third error types, and the invalid error type refers to the second error type. The fourth-order pulse amplitude modulation signal has four levels, namely "+3, +1, -1, and -3", each of which can be determined by three data decision voltages, namely upper eye (UE), middle eye (ME), and lower eye (LE). Figure 2 As shown, they are located in the middle of the three eyes. The high and low levels within each eye can also be represented by two levels, therefore... Figure 2The six voltages shown on both sides of the three data decision voltages respectively represent the high and low levels of these three eyes, including the upper eye high level (UE_U), the upper eye low level (UE_L), the middle eye high level (ME_U), the middle eye low level (ME_L), the lower eye high level (LE_U), and the lower eye low level (LE_L). In this embodiment, these six voltages are defined as error decision voltages. Therefore, the vertical region of the eye diagram is divided into regions I to VII with a continuous distribution as shown in Figure 2 shown. For the convenience of calculation, as an optional implementation manner, the encoding of the error types in this embodiment includes three types: 00, 11, and 01. Among them, 00 represents the first error type, 11 represents the third error type, and 01 represents the second error type. 00 means the sampling point is in region IV, 11 means the sampling point is in regions II and VI, and 01 means the sampling point is in regions I, III, V, and VII, as shown in Figure 2 shown.

[0033] In this embodiment, the slope information determined in step S102 is composed of the combined results of the magnitude comparison results of the two sampling data D(n - 1) and D(n) and the magnitude comparison results of D(n) and D(n + 1). For example, combining "D(n - 1) < D(n)" and "D(n) ≤ D(n + 1)" forms "D(n - 1) < D(n) ≤ D(n + 1)". When determining the slope information based on three adjacent sampling data D(n - 1), D(n), and D(n + 1), there are 64 changes in the three adjacent signals, which can be divided into two types: monotonic and non - monotonic. Among them, 32 monotonic changes can be further divided into three types: pure monotonic, pre - monotonic, and post - monotonic. As shown in Figure 3 as shown in (a - 1) and (a - 2) of , pure monotonic means that the magnitude comparison results of the two sampling data D(n - 1) and D(n) and the magnitude comparison results of D(n) and D(n + 1) are the same. For example, in (a - 1), they are all upward slopes (D(n - 1) < D(n) and D(n) < D(n + 1)), and in (a - 2), they are all downward slopes (D(n - 1) > D(n) and D(n) > D(n + 1)). As shown in Figure 3 as shown in (b - 1) and (b - 2) of , pre - monotonic means that the magnitudes of the two sampling data D(n - 1) and D(n) are different, and the magnitudes of D(n) and D(n + 1) are the same. For example, in (b - 1), they are all upward slopes (D(n - 1) < D(n) and D(n) = D(n + 1)), and in (b - 2), they are all downward slopes (D(n - 1) > D(n) and D(n) = D(n + 1)). As shown in Figure 3As shown in (c-1) and (c-2), post-monotonicity refers to the fact that the sampled data D(n-1) and D(n) are of the same magnitude, while the sampled data D(n) and D(n+1) are of different magnitudes. For example, (c-1) is always upsloping (D(n-1) = D(n) and D(n) > D(n+1)), and (c-2) is always downsloping (D(n-1) = D(n) and D(n) > D(n+1)). All 32 monotonic variations can be used to extract phase information.

[0034] In this embodiment, after obtaining the slope information, lead / lag phase information is generated using three error types and D(n). When E(n) is 00 or 11 (effective error type), and the sampling point is located in region II, IV, or VI, the phase results under different D(n) conditions can be directly obtained. Table 1 shows the truth table of phase results when E(n) is an effective error type. For example, when the input three adjacent data are "-1, +1, +3", the slope information is monotonically increasing. Combined with D(n) = +1, if E(n) is 00 and the sampling point is located in region IV, the local clock phase leads the input data phase. However, if E(n) is 11 and the sampling point is located in region VI, the local clock phase lags the input data phase.

[0035] Table 1: Truth table of the algorithm when E(n) is an effective error type.

[0036]

[0037] Specifically, referring to Table 1, the phase discrimination results of being phase-advanced or phase-lagged obtained based on E(n) and the slope information include: when the determined slope information is D(n - 1) < D(n) ≤ D(n + 1) or D(n - 1) ≤ D(n) < D(n + 1), and the nth error type E(n) is 00, if the value of the nth sampling data D(n) is +3, the phase discrimination result is no information; if the value of the nth sampling data D(n) is +1, the phase discrimination result is phase-advanced; if the value of the nth sampling data D(n) is -1, the phase discrimination result is phase-lagged; if the value of the nth sampling data D(n) is -3, the phase discrimination result is no information; when the determined slope information is D(n - 1) < D(n) ≤ D(n + 1) or D(n - 1) ≤ D(n) < D(n + 1), and the nth error type E(n) is 11, if the value of the nth sampling data D(n) is +3, the phase discrimination result is phase-advanced; if the value of the nth sampling data D(n) is +1, the phase discrimination result is phase-lagged; if the value of the nth sampling data D(n) is -1, the phase discrimination result is phase-advanced; if the value of the nth sampling data D(n) is -3, the phase discrimination result is phase-lagged; when the determined slope information is D(n - 1) ≥ D(n) > D(n + 1) or D(n - 1) > D(n) ≥ D(n + 1), and the nth error type E(n) is 00, if the value of the nth sampling data D(n) is +3, the phase discrimination result is no information; if the value of the nth sampling data D(n) is +1, the phase discrimination result is phase-lagged; if the value of the nth sampling data D(n) is -1, the phase discrimination result is phase-advanced; if the value of the nth sampling data D(n) is -3, the phase discrimination result is no information; when the determined slope information is D(n - 1) ≥ D(n) > D(n + 1) or D(n - 1) > D(n) ≥ D(n + 1), and the nth error type E(n) is 11, if the value of the nth sampling data D(n) is +3, the phase discrimination result is phase-lagged; if the value of the nth sampling data D(n) is +1, the phase discrimination result is phase-advanced; if the value of the nth sampling data D(n) is -1, the phase discrimination result is phase-lagged; if the value of the nth sampling data D(n) is -3, the phase discrimination result is phase-advanced.

[0038] However, when E(n) is a valid error type, this method will still lose some phase information. For example, in (b - 1) and (b - 2) in Figure 3 , it can be seen from Table 1 that only the phase-advanced phase information can be extracted; similarly, in Figure 3In (c-1) and (c-2), only the lag phase information can be obtained. To further improve the gain of the fourth-order pulse amplitude modulation baud rate phase discrimination, when E(n) is not a valid error type, in this embodiment, the slope information and three adjacent error types E(n-1), E(n), and E(n+1) are used to provide additional phase information. After obtaining the slope information, if the current sampling point is in region I, III, V, or VII, it indicates that E(n) is an invalid error type, and if E(n-1) or E(n+1) is a valid error type, the phase identification result can still be obtained. That is, when E(n) is an invalid error type, the algorithm will obtain the phase information through E(n-1) or E(n+1), as Figure 4 shown. Table 2 is the truth table corresponding to this phase detection method.

[0039] SL[1:0] E(n) E(n-1) E(n+1) information D(n-1)<D(n)≤D(n+1) 01 ≠01 X Lag D(n-1)≤D(n) <D(n+1) 01 X ≠01 Advanced D(n-1)≥D(n)>D(n+1) 01 X ≠01 Advanced D(n-1)>D(n)≥D(n+1) 01 ≠01 X Lag

[0040] In Table 2, "X" indicates that it can take any value. Specifically, referring to Table 2, the phase discrimination result of the nth sampling data D(n) obtained by combining the slope information with E(n-1) or E(n+1) that is a valid error type in step S102 includes: when the determined slope information is D(n-1) < D(n) ≤ D(n+1) and the nth error type E(n) is 01, if the n-1th error type E(n-1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lag; when the determined slope information is D(n-1) ≤ D(n) < D(n+1) and the nth error type E(n) is 01, if the n+1th error type E(n+1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lead; when the determined slope information is D(n-1) ≥ D(n) > D(n+1) and the nth error type E(n) is 01, if the n+1th error type E(n+1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lead; when the determined slope information is D(n-1) > D(n) ≥ D(n+1) and the nth error type E(n) is 01, if the n-1th error type E(n-1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lag. It should be noted that if E(n-1), E(n), and E(n+1) are all invalid error types, the sampling point is close to the optimal sampling point, and at this time, the PAM4BRPD does not generate phase information. For example, if three adjacent data " +1, +3, +3" are input, the slope information is monotonically increasing before, and E(n) is 01. If E(n-1) is not 01 and the previous sampling point is not in region VI, the local clock phase lags behind the input data phase. If E(n-1) is 01 and the sampling point is in region V, it is close to the best sampling point, and at this time, the fourth-order pulse amplitude modulation baud rate phase discrimination does not generate phase information.

[0041] In summary, traditional fourth-order pulse amplitude modulation baud rate phase detection based on the Bang-Bang detection algorithm primarily determines the optimal sampling point for the input data through the crossover point of the reference potential (ME). However, this method significantly reduces the gain of the fourth-order pulse amplitude modulation baud rate phase detection and the tracking bandwidth of the clock data recovery circuit (CDR). In contrast, the fourth-order pulse amplitude modulation baud rate phase detection method in this embodiment can obtain phase information for all monotonic changes using three adjacent data points and three error types, and this method can be easily implemented using digital circuits.

[0042] To accurately calculate the gain of the fourth-order pulse amplitude modulation baud rate phase detector and describe the characteristics of the clock data recovery circuit CRD loop, this embodiment proposes a linear model for the fourth-order pulse amplitude modulation baud rate phase detector for the first time. It is assumed that the random phase error (the phase difference between the input data and the recovered clock) follows a Gaussian distribution with a mean of 0 and a standard deviation of σ. The inherent jitter of the input smooths the binary output characteristics of the fourth-order pulse amplitude modulation baud rate phase detector, such as... Figure 5 As shown. Combining the fourth-order pulse amplitude modulation baud rate phase detection process, we use "1" to represent phase delay and "-1" to represent phase lead. Then, we weight and sum the positive and negative samples according to their occurrence probabilities. Therefore, the average output u of the fourth-order pulse amplitude modulation baud rate phase detection is:

[0043] u=(1) r (|φ)+(-1) r (|), (1)

[0044] In the above formula, P r (|φ) is the hysteresis phase probability density, P r (|) represents the probability density of the leading phase, and φ represents the phase. Figure 5 In this context, φ represents the average phase error between the input data and the recovered clock. m This represents the drift bandwidth when no phase information is generated. In reality, since the drift bandwidth varies with different phases, we use the maximum drift bandwidth as an estimate. When the average phase error is φ, the drift bandwidth is 2. m The lag phase probability density is:

[0045]

[0046] In the above formula, σ is the standard deviation of the Gaussian distribution, φ is the average phase error between the input data and the recovered clock, and φ m This represents half the drift bandwidth when no phase information is generated, when the average phase error is φ and the drift bandwidth is 2. m The leading phase density function is:

[0047]

[0048] Substituting (2) and (3) into (1), we can deduce:

[0049]

[0050] Because equation (4) does not take into account the detector density of the fourth-order pulse amplitude modulation baud rate phase detector (1 / 2), the gain of the Gaussian jitter-based BRPD is 1 / (2*u). According to existing research and analysis results, the gain of the fourth-order pulse amplitude modulation baud rate phase detector is inversely proportional to the input jitter. The higher the jitter, the lower the gain.

[0051] To verify the correctness of the linear model for fourth-order pulse amplitude modulation baud rate phase detection, we added Gaussian jitter to the recovery clock and scanned the phase difference φ at the input. We then measured the average output of the fourth-order pulse amplitude modulation baud rate phase detector as a function of different φ values. Figure 6 As shown in (b), the curve for comparison was generated using a fourth-order pulse amplitude modulation baud rate phase detection linear model. It can be seen that the trajectories of the two curves are almost identical, thus verifying the correctness of the fourth-order pulse amplitude modulation baud rate phase detection linear model. The fourth-order pulse amplitude modulation baud rate phase detection gain can be calculated using the measured slope information or the slope information in the linear model. Figure 6 (a) in the figure depicts three average outputs obtained by three fourth-order pulse amplitude modulation baud rate phase detection algorithms under different φ. According to the simulation results, the fourth-order pulse amplitude modulation baud rate phase detection method in this embodiment has better performance than the existing methods [3](N.Qi et al., "A51Gb / s,320mW,PAM4 CDR with baud-ratesampling for high-speed optical interconnects", in 2017IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul,Korea (South), Nov. 2017, pp. 89-92.) and [9](Z.Zhang,G.Zhu,C.Wang,L.Wang,andCPYue, "A32-Gb / s 0.46-pJ / bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based MultiphaseClock Generator", IEEE Journal of Solid-State Circuits, vol.55, no.10, pp.2734-2746, 2020.) has higher gain.

[0052] like Figure 7 As shown, this embodiment also provides a CDR circuit for a high-speed serial interface, including an ADC sampler, a feedforward equalizer (FFE), a baud rate phase detector (PAM4 BRPD), a voter, a low-pass digital filter (LPDF), and a phase interpolator (PI). The ADC sampler, feedforward equalizer (FFE), baud rate phase detector, voter, and low-pass digital filter are connected in sequence. The phase interpolator is used to perform phase calibration on the externally input PPL clock based on the phase information output by the low-pass digital filter, and then uses it as the clock signal for the ADC sampler. The baud rate phase detector is programmed or configured to perform the fourth-order pulse amplitude modulation baud rate phase detection method described above. As an optional implementation, in this embodiment, the low-pass digital filter is a second-order low-pass digital filter, and the feedforward equalizer (FFE) is a 4-tap feedforward equalizer (FFE). The working process of the CDR circuit is as follows: ① The serial input data is first sampled by an 8-bit ADC sampler (analog-to-digital conversion) and converted into parallel data. ② Equalization is performed by a feedforward equalizer (FFE) to obtain equalized data, reducing crosstalk between paths. ③ The equalized data is compared into a decision voltage in the baud rate phase detector (PAM4 BRPD) to obtain the lead / lag phase decision result. ④ The phase decision result passes through a voter, a low-pass digital filter, and a phase interpolator. The ADC clock phase is calibrated by the CDR to ensure sampling accuracy. It should be noted that the improvement to the CDR circuit in this embodiment is only that the baud rate phase detector (PAM4 BRPD) is programmed or configured to perform the fourth-order pulse amplitude modulation baud rate phase detection method described above.

[0053] like Figure 7As shown, this embodiment also provides a SerDes receiver, including an analog front-end circuit (AFE), a phase-locked loop (PPL), a clock sampling data recovery circuit, and a sampling data channel. The clock sampling data recovery circuit is the CDR circuit used for high-speed serial interfaces. The sampling data output by the analog front-end circuit (AFE) is sent to the ADC sampler in the CDR circuit. The PPL clock output by the PPL is connected to the input of the phase interpolator in the CDR circuit. The sampling data channel includes a feedforward equalizer (FFE) and a decision feedback equalizer (DFE) connected in sequence. The output of the ADC sampler is connected to the input of the feedforward equalizer (FFE) in the sampling data channel, and the output of the decision feedback equalizer (DFE) serves as the sampling data output of the SerDes receiver. The analog front-end circuit (AFE) includes a T-coil, a linear equalizer (CTLE), and a variable gain amplifier (VGA). It should be noted that the improvement to the SerDes receiver in this embodiment is only in the CDR circuit; therefore, other related components will not be described in detail here.

[0054] As an optional implementation, this embodiment uses a 12nm CMOS process to design a SerDes receiver. The CDR circuit operates at a rate of 112Gb / s and employs PAM4 signal modulation. To reduce jitter and bit error rate, a jitter model is established using the fourth-order pulse amplitude modulation baud rate phase detector gain equation described earlier to accurately set parameters and thus reduce clock jitter. When the CDR circuit loop converges, the transistor-level simulation result for restoring clock jitter at 14GHz is 523fs. RMS and 2.95ps pp ,like Figure 8 As shown in (a) of the table. 10 -12 Simulation results of jitter tolerance at the order of magnitude of bit error rate are as follows: Figure 8 As shown in (b), the jitter tolerance fully meets the requirements of the CEI-112G-LR-PAM4 mask. Table 3 shows a performance comparison of the CDR circuit of the SerDes receiver in this embodiment with the CDR circuits of other fourth-order pulse amplitude modulation baud rate phase detection methods in recent years.

[0055] Table 3: Performance Comparison of Different CDR Circuits

[0056]

[0057] In Table 3, Silicon[3] is the existing CDR circuit described in the literature (N. Qi et al., "A 51Gb / s, 320mW, PAM4CDR with baud-rate sampling for high-speed optical interconnects", in 2017IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, Korea (South), Nov. 2017, pp. 89-92.), and Silicon

[10] is the existing CDR circuit described in the literature (B. Dehlaghi et al., "A 1.41-pJ / b 56-Gb / s PAM-4Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7-nm CMOS", IEEE Solid-State Circuits Conference). The existing CDR circuit described in Letters, vol.2, no.11, pp.248-251, 2019, is Silicon

[11] the existing CDR circuit described in the literature (P. Peng, J. Li, L. Chen, and J. Lee, "6.1A 56Gb / s PAM-4 / NRZ transceiver in 40nm CMOS", in 2017 IEEE International Solid-State Circuits Conference (ISSCC), pp.110-111, Feb. 2017.). As can be seen from Table 3, the CDR circuit of this embodiment has higher conversion density and lower jitter, thus improving the design efficiency of each parameter of the CDR ring and reducing clock recovery jitter. It can be applied to the high-speed digital clock recovery circuit of the ADC-based high-speed SerDes receiver in the fields of electrical communication and optical communication.

[0058] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A fourth-order pulse amplitude modulation baud rate phase detection method, characterized in that, include: S101, determine the slope information based on three adjacent sampled data D(n-1), D(n), and D(n+1); S102. Determine three adjacent error types E(n - 1), E(n), and E(n + 1) based on the sampling point region of the sampling data. If E(n) is a valid error type, obtain the phase discrimination result of the nth sampling data D(n) according to E(n) and combined with slope information: When the determined slope information is D(n 1) < D(n) ≤ D(n + 1) or D(n 1) ≤ D(n) < D(n + 1), and when the nth error type E(n) is 00, if the value of the nth sampling data D(n) is +3, the phase discrimination result is no information; if the value of the nth sampling data D(n) is +1, the phase discrimination result is leading; if the value of the nth sampling data D(n) is -1, the phase discrimination result is lagging; if the value of the nth sampling data D(n) is -3, the phase discrimination result is no information. When the determined slope information is D(n 1) < D(n) ≤ D(n + 1) or D(n 1) ≤ D(n) < D(n + 1), and when the nth error type E(n) is 11, if the value of the nth sampling data D(n) is +3, the phase discrimination result is leading; if the value of the nth sampling data D(n) is +1, the phase discrimination result is lagging; if the value of the nth sampling data D(n) is -1, the phase discrimination result is leading; if the value of the nth sampling data D(n) is -3, the phase discrimination result is lagging. When the determined slope information is D(n 1) ≥ D(n) > D(n + 1) or D(n 1) > D(n) ≥ D(n + 1), and when the nth error type E(n) is 00, if the value of the nth sampling data D(n) is +3, the phase discrimination result is no information; if the value of the nth sampling data D(n) is +1, the phase discrimination result is lagging; if the value of the nth sampling data D(n) is -1, the phase discrimination result is leading; if the value of the nth sampling data D(n) is -3, the phase discrimination result is no information. When the determined slope information is D(n 1) ≥ D(n) > D(n + 1) or D(n 1) When D(n) ≥ D(n+1) and the nth error type E(n) is 11, if the value of the nth sampling data D(n) is +3, the phase discrimination result is lag; if the value of the nth sampling data D(n) is +1, the phase discrimination result is lead; if the value of the nth sampling data D(n) is -1, the phase discrimination result is lag; if the value of the nth sampling data D(n) is -3, the phase discrimination result is lead. When E(n) is an invalid error type and E(n-1) or E(n+1) is a valid error type, the phase discrimination result of the nth sampling data D(n) is obtained by combining the valid error type of E(n-1) or E(n+1) with the slope information: when the determined slope information is D(n-1) < D(n) ≤ D(n+1) and the nth error type E(n) is 01, if the (n-1)th error type E(n-1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lag. 1) When D(n) ≤ D(n) < D(n+1) and the nth error type E(n) is 01, if the (n+1)th error type E(n+1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lead. When the determined slope information is D(n 1) ≥ D(n) > D(n+1) and the nth error type E(n) is 01, if the (n+1)th error type E(n+1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lead. When the determined slope information is D(n 1) > D(n) ≥ D(n+1) and the nth error type E(n) is 01, if the (n-1)th error type E(n-1) is not 01, when the value of the nth sampling data D(n) is +1, the phase discrimination result is lag.

2. The fourth-order pulse amplitude modulation baud rate phase detection method according to claim 1, characterized in that, In step S102, when determining three adjacent error types E(n-1), E(n), and E(n+1) based on the sampling point region of the sampled data, the sampling point region is divided into continuously distributed regions I to VII according to the voltage in ascending order. If the sampling point region of the sampled data is located in region IV, the corresponding error type is the first error type. If the sampling point region of the sampled data is located in region I, region VII, region III, or region V, the corresponding error type is the second error type. If the sampling point region of the sampled data is located in region II or region VI, the corresponding error type is the third error type. The effective error type refers to the first and third error types, and the invalid error type refers to the second error type.

3. The fourth-order pulse amplitude modulation baud rate phase detection method according to claim 2, characterized in that, The error type encoding includes three types: 00, 11, and 01. 00 represents the first error type, 11 represents the third error type, and 01 represents the second error type.

4. The fourth-order pulse amplitude modulation baud rate phase detection method according to claim 3, characterized in that, The slope information determined in step S102 is composed of the comparison results of the sampled data D(n-1) and D(n) and the comparison results of the sampled data D(n) and D(n+1).

5. A CDR circuit for a high-speed serial interface, characterized in that, The device includes an ADC sampler, a feedforward equalizer (FFE), a baud rate phase detector, a voter, a low-pass digital filter, and a phase interpolator. The ADC sampler, FFE, baud rate phase detector, voter, and low-pass digital filter are connected in sequence. The phase interpolator is used to perform phase calibration on an externally input PPL clock based on the phase information output by the low-pass digital filter, and then uses this calibration as the clock signal for the ADC sampler. The baud rate phase detector is programmed or configured to execute the fourth-order pulse amplitude modulation baud rate phase detection method according to any one of claims 1 to 4.

6. The CDR circuit for a high-speed serial interface according to claim 5, characterized in that, The low-pass digital filter is a second-order low-pass digital filter.

7. The CDR circuit for a high-speed serial interface according to claim 6, characterized in that, The feedforward equalizer FFE is a 4-tap feedforward equalizer FFE.

8. A SerDes receiver, comprising an analog front-end circuit (AFE), a phase-locked loop (PPL), a clock sampling data recovery circuit, and a sampling data channel, characterized in that, The clock sampling data recovery circuit is the CDR circuit for high-speed serial interface as described in any one of claims 5 to 7. The sampling data output by the analog front-end circuit AFE is sent to the ADC sampler in the CDR circuit. The PPL clock output by the phase-locked loop PPL is connected to the input terminal of the phase interpolator in the CDR circuit. The sampling data channel includes a feedforward equalizer FFE and a decision feedback equalizer DFE connected in sequence. The output terminal of the ADC sampler is connected to the input terminal of the feedforward equalizer FFE in the sampling data channel, and the output terminal of the decision feedback equalizer DFE serves as the sampling data output terminal of the SerDes receiver.

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