Optical node apparatus

Abstract

The plurality of pixels of the spatial light modulator of the optical node device each include first switching circuitry and first signal holding circuitry that sample and hold forward gray scale data or reverse gray scale data, and second switching circuitry and second signal holding circuitry that sample and hold the forward gray scale data or the reverse gray scale data held in the first signal holding circuitry for all of the plurality of pixels at a common timing for one subframe and apply the same to the reflective electrode. The spatial light modulator driving section applies an alternating voltage of positive and negative polarity to the liquid crystal by inverting the voltage of the common electrode of the liquid crystal display element, and provides a voltage of an amplitude different from the amplitude between the forward gray scale data and the reverse gray scale data to the common electrode.

Description

TECHNICAL FIELD

[0001] The present application relates to an optical node device. BACKGROUND

[0002] Optical networks are used to support the modern demand for fast and large-capacity electric communication. These networks generally use known technology as an optical wavelength division multiplexing system (WDM) to utilize as much of the optical spectrum as possible.

[0003] In many optical networks, an optical node device corresponding to a branching point of the optical network is used. Often, in the optical node device, a reconfigurable optical add-drop multiplexer (ROADM) device having a reconfigurable add-drop function is preferably used.

[0004] In order to realize a ROADM system, a wavelength selective switch (WSS) can also be used for routing of an arbitrary wavelength channel. In the WSS, an optical beam deflection device such as a spatial light modulator can also be used to select a wavelength in order to deflect to a desired output port. Currently, a WSS using a reflective spatial light modulator is used.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Patent No. 5733154 SUMMARY

[0008] In the above-described reflective spatial light modulator, in order to improve reliability, it is preferable to be able to suppress burn-in.

[0009] In view of the above-described problem, an object of the present embodiment is to provide an optical node device capable of improving reliability.

[0010] The optical node device according to one embodiment includes: an input-output section having an input port into which incident light is incident and an output port from which emergent light is emitted, the emergent light corresponding to each wavelength included in the incident light; a wavelength disperser that disperses light of each wavelength included in the incident light in space according to each wavelength and emits the emergent light toward the input-output section side; an optical coupler that condenses light of each wavelength dispersed by the wavelength disperser on a two-dimensional plane by each wavelength and emits reflected light of each wavelength toward the wavelength disperser side; a spatial light modulator disposed at a position of the two-dimensional plane, having a plurality of pixels, and reflecting light of each wavelength condensed by the optical coupler toward a direction determined by routing by representing a gray scale by the plurality of pixels; and a spatial light modulator drive section that drives the plurality of pixels of the spatial light modulator. A forward gray scale data is input to each of the plurality of pixels during one of a plurality of subframe periods into which one frame period is divided by the spatial light modulator drive section, and a reverse gray scale data is input during another one of the plurality of subframe periods to form the gray scale. Each of the plurality of pixels includes: a first switch circuit that samples the forward gray scale data or the reverse gray scale data from a data line; a first signal holding circuit that holds the forward gray scale data or the reverse gray scale data sampled by the first switch circuit; a second switch circuit that samples the forward gray scale data or the reverse gray scale data held in the first signal holding circuit at a common timing for all the plurality of pixels; and a second signal holding circuit that holds the forward gray scale data or the reverse gray scale data sampled by the second switch circuit for one subframe period and applies it to a reflection electrode of a liquid crystal display element. The spatial light modulator drive section applies an alternating voltage of positive and negative polarities to a liquid crystal of the liquid crystal display element by inverting a voltage of a common electrode of the liquid crystal display element at the timing, and supplies a voltage having an amplitude different from an amplitude between the forward gray scale data and the reverse gray scale data to the common electrode.

[0011] According to the present embodiment, it is possible to improve reliability. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 FIG. 1 is a diagram showing a structure of a wavelength selective switch array according to a first embodiment.

[0013] Figure 2 FIG. 1 is a diagram showing a structure of a wavelength selective switch array according to a first embodiment.

[0014] Figure 3 FIG. 1 is a diagram showing a structure of a wavelength selective switch array according to a first embodiment.

[0015] Figure 4 FIG. 2 is a diagram showing the structure of a reflective liquid crystal display device according to the second embodiment.

[0016] Figure 5 FIG. 3 is a diagram showing the structure of a pixel of the reflective liquid crystal display device according to the second embodiment.

[0017] Figure 6 FIG. 4 is a diagram showing the circuit structure of a pixel of the reflective liquid crystal display device according to the third embodiment.

[0018] Figure 7 FIG. 5 is a diagram showing the circuit structure of a CMOS inverter.

[0019] Figure 8 FIG. 6 is a diagram showing the magnitude relationship of driving forces between inverters.

[0020] Figure 9 FIG. 7 is a timing chart showing the operation of the reflective liquid crystal display device according to the third embodiment.

[0021] Figure 10 FIG. 8 is a diagram showing the relationship between the applied voltage of liquid crystal and the gray scale value.

[0022] Figure 11 FIG. 9 is a diagram showing the circuit structure of a pixel of the reflective liquid crystal display device according to the fourth embodiment.

[0023] Figure 12 FIG. 10 is a diagram showing the circuit structure of a pixel of the reflective liquid crystal display device according to the fifth embodiment.

[0024] Figure 13 FIG. 11 is a diagram showing the cross-sectional structure of a pixel of the reflective liquid crystal display device according to the fifth embodiment.

[0025] Figure 14 FIG. 12 is a diagram showing the circuit structure of a pixel of the reflective liquid crystal display device according to the sixth embodiment.

[0026] Figure 15 FIG. 13 is a diagram showing the cross-sectional structure of a pixel of the reflective liquid crystal display device according to the sixth embodiment.

[0027] Figure 16 FIG. 14 is a diagram showing the circuit structure of a pixel of the reflective liquid crystal display device according to the seventh embodiment.

[0028] Figure 17 FIG. 15 is a diagram showing the cross-sectional structure of a pixel of the reflective liquid crystal display device according to the seventh embodiment. DETAILED DESCRIPTION

[0029] The following describes the present embodiment in detail based on the drawings. Note that the present embodiment is not limited to the following description. Also, in the constituent elements in the following embodiments, elements that can be easily substituted by those skilled in the art, or substantially identical elements are included.

[0030] (First Embodiment)

[0031] Figure 1 and Figure 2 is a diagram showing the structure of a wavelength selective switch (WSS) array of the first embodiment. Figure 1 is a diagram of the WSS array 10 viewed from the direction opposite to the x-axis direction. Figure 2 is a diagram of the WSS array 10 viewed from the direction opposite to the y-axis direction.

[0032] The WSS array 10 corresponds to an example of the "optical node device" of the present application.

[0033] The WSS array 10 of the present application uses at least two WSSs in a single package. The WSS array 10 of the present application enables independent operation of each WSS within the WSS array 10 without the need for dedicated optical elements. Furthermore, many optical elements can be shared among the respective WSS devices, and thus cost reduction and downsizing can be achieved. Such a device is, for example, ideally suited for use as a reconfigurable optical add-drop multiplexer (ROADM) in modern communication networks. Furthermore, one or more arrays having two WSSs coupled together can be ideally suited as constituent elements within a branching node of a path and use selection (RS) architecture.

[0034] Referring to Figure 1 , the WSS array 10 includes two independent WSS devices WSS1 and WSS2 that can operate as respective independent WSS devices. In the present application, the term "independent" refers to the function of the WSS device WSS1 that independently processes one or more WDM signals regardless of the WSS device WSS2, and the same applies in the opposite direction. In the present application, the term "process" is used in a broad sense, and for example, includes modulating, attenuating, blocking, switching direction, and / or switching each wavelength channel that constitutes each WDM signal.

[0035] The WSS array 10 includes an input-output section 11 and an optical system 12. The optical system 12 is configured to perform beam shaping on each of the WDM signal light beams. In addition, the optical system 12 is configured to spectrally disperse (demultiplex) each of the WDM signals among the wavelength channels (or groups of wavelength channels) that make up the WDM signals. Further, the optical system 12 is configured to spectrally couple (multiplex) the dispersed wavelength channels (or groups of wavelength channels) into one or more WDM signals. In addition, the WSS array 10 includes a reflective liquid crystal display device 13. The reflective liquid crystal display device 13 is configured to, for example, optically process the dispersed wavelength channels in order to directionally switch each of the wavelength channels along a prescribed path within the WSS array 10.

[0036] The reflective liquid crystal display device 13 corresponds to an example of the "spatial light modulator" of the present application. The reflective liquid crystal display device 13 will be described in detail later in the second embodiment.

[0037] The WSS array 10 allows a single optical system 12 and reflective liquid crystal display device 13 to be shared among some of the WSS devices of the WSS array 10, in this example, among the WSS devices WSS1 and WSS2, by using an architecture that is symmetric about the symmetry axis 14. However, the WSS devices WSS1 and WSS2 can share many of the same optical components, while the architecture of the first embodiment allows the WSS devices WSS1 and WSS2 of the WSS array 10 to be independently controllable devices. Thus, the WSS array 10 of the first embodiment is reduced in size and optical complexity. In addition, the WSS array 10 provides a multi-WSS device that retains the independent processing capabilities inherent to devices having a larger size and cost.

[0038] In the present disclosure, the input-output section 11 can include a number of input ports and output ports for passing one or more optical WDM signals. For example, the devices can include a number of optical fibers, planar waveguides, etc., but they can all be assigned as input ports or output ports. In the first embodiment described below, the input ports or output ports are installed as optical fibers 15. However, any other kind of port can be used without departing from the scope of the present application.

[0039] The input-output section 11 includes an input-output section 11-1 for the WSS device WSS1. The input-output section 11-1 includes an input optical fiber 1 and a number of output optical fibers 1a, 1b,..., 1n. Here, n is a natural number. The input-output section 11 also includes an input-output section 11-2 for the WSS device WSS2. The input-output section 11-2 includes an input optical fiber 2 and a number of output optical fibers 2a, 2b,..., 2n. Here, n is a natural number. Thus, Figure 1An array of two 1×N WSS devices, including WSS devices WSS1 and WSS2, is shown as an example. In other words, the input / output section 11 of the WSS array 10 includes an array of input fiber 1, output fiber 1a, 1b, ..., 1n, input fiber 2, and output fiber 2a, 2b, ..., 2n arranged in a fiber stack along the y-axis direction.

[0040] The input / output section 11 also includes an array of collimating lenses 16 arranged in the form of a microlens array. The array of collimating lenses 16 is an array of corresponding optical power elements, for example, respectively disposed in front of the output section and / or input section of the optical fiber (in the z-direction). In this invention, the collimating lenses 16 include any optical element capable of guiding and / or changing the direction of the light beam and / or focusing a group of light rays. A first group including input optical fiber 1, output optical fibers 1a, 1b, ..., 1n, combined with a pair of collimating lenses 16, forms the input / output section 11-1 of the WSS device WSS1. A second group including input optical fiber 2, output optical fibers 2a, 2b, ..., 2n, combined with a pair of collimating lenses 16, forms the input / output section 11-2 of the WSS device WSS2. Figure 1 The diagram shows a WSS array 10 mounted as a microlens array, but other types of WSS arrays can also be used without departing from the scope of the invention.

[0041] In this disclosure, for example, the optical axis of the first set of optical fibers is displaced relative to the optical axis of the first set of collimating lenses 16. Through this offset in relative position between the array of input and output ports and the array of collimating lenses 16, the input and output beams of the first set are sent out into the optical system 12 (or out of the optical system 12) at an angle θ1 relative to the axis of symmetry 14. Thus, the set of input and output beams from the WSS device WSS1 is sent out along an angle θ1 in a direction of overall descent (opposite to the y-axis direction).

[0042] Similarly, the optical axis of the second set of optical fibers is displaced relative to the optical axis of the second set of collimating lenses 16. The input and output beams of the second set are sent out into the optical system 12 (or out of the optical system 12) at an angle θ2 relative to the axis of symmetry 14. Thus, the set of input and output beams from the WSS device WSS2 is sent out along an angle θ2 in the direction of overall upward movement (y-axis direction).

[0043] As mentioned above, Figure 1 The example shown is a WSS array 10 using two 1×N WSS devices, namely WSS devices WSS1 and WSS2. Therefore, in Figure 1In the example shown, the WSS device WSS1 includes an input fiber 1 for incident WDM signal beam 31 into the device, and an input fiber 2 for incident WDM signal beam 32 into the device. The input fiber / output fiber structure shown herein is merely illustrative and is not intended to limit the scope of the invention. Rather, any useful combination of input / output ports can be used without departing from the scope of the invention.

[0044] The WDM signal beam 31 is sent from the input fiber 1 to the device, and after passing through the collimating lens 16, it propagates through the optical system 12 at an angle θ1 in the yz plane. The WDM signal beam 31 is then incident on a lens 21 used to shape the WDM signal beam 31 in the x-direction. In one example, the lens 21 could also be a cylindrical lens with its cylindrical axis extending along the y-direction. Therefore, from the input fiber 1... Figure 1 When viewed from the viewpoint shown, lens 21 will not affect the WDM signal beam 31.

[0045] The WDM signal beam 31 passes through lens 21 and then enters lens 22. Figure 1 In the example shown, lens 22 can also be a cylindrical lens with its cylindrical axis extending along the x-direction. The function of lens 22 depends on the reflective liquid crystal display device 13 positioned at the focal plane of lens 22. Furthermore, the center (cylindrical axis) of lens 22 is located on the axis of symmetry 14. Since the reflective liquid crystal display device 13 is positioned at the focal plane of lens 22, any group of parallel light rays entering lens 22 converges to the same height on the reflective liquid crystal display device 13. Conversely, any group of light rays starting from the same height on the reflective liquid crystal display device 13 exits from lens 22 as a group of parallel light rays.

[0046] For example, such as Figure 1 As shown, an arbitrary incident light beam (e.g., WDM signal beam 31) traveling along angle θ1 is directed by lens 22 to a position LC1 in the y-axis direction on the reflective liquid crystal display device 13. Conversely, a group of light rays 41 starting from position LC1 on the reflective liquid crystal display device 13 is as follows: Figure 1 As shown, parallel light rays traveling at the same angle θ1 are emitted from lens 22. Similarly, any incident light beam traveling at an angle θ2 (e.g., WDM signal beam 32) is directed by lens 22 to position LC2 in the y-axis direction on the reflective liquid crystal display device 13. Conversely, groups of light rays 42 starting from position LC2 on the reflective liquid crystal display device 13 are as follows: Figure 1 As shown, parallel rays that advance at the same angle θ2 are emitted from lens 22.

[0047] When returning to the propagation of the WDM signal light beam 31 through the optical system 12, after passing through the lens 22, as shown in Figure 1 and Figure 2 shown, the WDM signal light beam 31 passes through the dispersion element 24 which disperses the wavelength channels of the WDM signal light beam 31. In the present disclosure, the dispersion element 24 can also be a transmission-type optical component such as a diffraction grating, a prism, or the like.

[0048] The dispersion element 24 corresponds to an example of the "wavelength disperser" of the present disclosure.

[0049] The dispersed wavelength channels, after passing through the dispersion element 24, as shown in Figure 1 and Figure 2 shown, pass through the lens 23 which focuses the dispersed wavelength channels on the surface of the reflective liquid crystal display device 13 per wavelength channel. In the present disclosure, the lens 23 can also be a cylindrical lens.

[0050] The lens 23 corresponds to an example of the "optical coupler" of the present disclosure.

[0051] The reflective liquid crystal display device 13 is a two-dimensional pixelated optical element such as a pixelated spatial light modulator. The two-dimensional pixelated optical element, as described in more detail below, can reflect one or more of the dispersed wavelength channels, or can perform a direction conversion, in a manner that the dispersed wavelength channel or channels are routed to any one of the output fibers.

[0052] With respect to the WSS device WSS1, according to the present disclosure, since the lens 22 is present, all the light rays from the position LC1 on the reflective liquid crystal display device 13 are output from the lens 22 along the angle θ1 as shown in Figure 1 However, all the light rays from the position LC1 on the reflective liquid crystal display device 13 are displaced with respect to each other by an amount corresponding to the deflection angle from the reflective liquid crystal display device 13. Therefore, in the case where the deflection angle is appropriately set, the reflected output light rays can be routed to any one of the output fibers 1a, 1b,..., 1n. Here, the reflected output light rays are, for example, reflected output light rays corresponding to the groups of the light rays 41 which can contain one or more wavelength channels of the WDM signal light beam 31, respectively. Further, in the present disclosure, the collimator lenses 16 are displaced by the same amount with respect to their corresponding output fibers, respectively, and thus the respective output light beams can be recoupled with the respective output fibers in a state where the efficiency is improved.

[0053] Similarly, with respect to the WSS device WSS2, according to the present disclosure, since the lens 22 is present, as shown in Figure 1All the light rays starting from the position LC2 on the reflective liquid crystal display device 13 are output from the lens 22 along the angle θ2. However, the light rays starting from the position LC2 on the reflective liquid crystal display device 13 are all displaced with respect to each other by an amount corresponding to the deflection angle from the reflective liquid crystal display device 13. Therefore, in the case where the deflection angle is properly set, the reflected output light rays can be routed to any of the output fibers 2a, 2b,..., 2n. Here, the reflected output light rays are, for example, the reflected output light rays corresponding to the groups of the light rays 42 each capable of containing one or more wavelength channels of the WDM signal light beam 32. Further, in the present disclosure, the collimating lenses 16 are each displaced by the same amount with respect to its corresponding output fiber, and thus each output light beam can be recoupled with each output fiber in a state where the efficiency is improved.

[0054] Therefore, the combination of the input-output section 11 and the lens 22 sends out a given group of beams along a given angle (for example, the angle θ1 in the case of the WSS device WSS1 and the angle θ2 in the case of the WSS device WSS2). Thereafter, the combination of the input-output section 11 and the lens 22 provides a WSS array device that orients these light beams in a manner that depends only on the positions (the positions LC1 and LC2) on the reflective liquid crystal display device 13. Therefore, the WSS array 10 enables two groups of the WDM signal light beams 31 and 32 from the WSS devices WSS1 and WSS2 or the light rays 41 and 42 to the WSS devices WSS1 and WSS2 to share the same optical system 12 and the reflective liquid crystal display device 13. On the other hand, the WSS array 10 retains the capability of the WSS array that processes each wavelength channel separately.

[0055] Reference Signs List Figure 2 The stack of the optical fibers and the microlenses constituting the input-output section 11 is viewed from the upper part of the fiber stack, and thus only the input fiber 1 is visible together with its corresponding collimating lens 16. The following description focuses on the WSS device WSS1, but the same description applies to the WSS device WSS2 in accordance with the symmetry of the system.

[0056] As described above, in the case of the WSS device WSS1, the WDM signal light beam 31 is incident on the system via the input fiber 1. The light beam 31 is collimated by the collimating lens 16 and is then focused by the lens 22 on the position LC1 on the reflective liquid crystal display device 13. Figure 2In this case, angle θ1 is not visible because it is the direction inside the paper. In this disclosure, the WDM signal beam 31 includes several wavelength channels, and these channels have a wavelength range from the longest wavelength λ1 to the shortest wavelength λn. In several examples, the number of wavelength channels can be large, for example, 96 wavelength channels spaced at 50 GHz or 100 GHz on a fixed grid. In another example, the device can, for example, use a frequency spacing of 12.5 GHz, enabling its use in adaptive grid systems with more than 97 wavelength channels, such as more than 130 wavelength channels.

[0057] The WDM signal beam 31 is first incident on lens 21. Lens 21 functions to expand the beam to a diameter suitable for achieving the desired beam size on dispersive element 24. For example, collimating lens 16 and lens 21 can also function as a beam-expanding telescope. In this disclosure, as Figure 2 As shown, the dispersive element 24 functions to angularly disperse the wavelength channels of the WDM signal beam 31 in the x-axis direction. After the wavelength channels 51 to 5n are angularly dispersed in the x-axis direction by the dispersive element 24, they are focused onto the surface of the reflective liquid crystal display device 13 by the lens 23. Thus, from the wavelength channels 51 to 5n, the wavelengths are spatially dispersed in the wavelength dispersion direction (x-axis direction) on the reflective liquid crystal display device 13 according to their wavelengths.

[0058] Figure 3 This is a diagram showing a reflective liquid crystal display device with a WSS array according to the first embodiment. Figure 3 This is a diagram of the reflective liquid crystal display device 13 viewed from the z-axis direction.

[0059] exist Figure 3 An example of the distribution of wavelength channels on the surface of the reflective liquid crystal display device 13 is shown more clearly. More generally, wavelength channels can be arranged as stripes or elliptical spots on the two-dimensional surface of the reflective liquid crystal display device 13. In short, the wavelength channels are processed as discrete wavelength signals that can be acted independently by the reflective liquid crystal display device 13. However, in this disclosure, the reflective liquid crystal display device 13 is not limited to acting on individual wavelength channels, but can also act on groups of wavelength channels. Furthermore, as Figure 3 As shown, the wavelength channel or group of wavelength channels does not need to have a fixed bandwidth. This is because the reflective liquid crystal display device 13 can be installed as a spatial light modulator capable of dynamic and complete reconfiguration. Therefore, this disclosure can be implemented in current fixed grid architectures and / or, current or future highly adaptable grid architectures.

[0060] Refer again Figure 2The reflective liquid crystal display device 13 selectively redirects one or more wavelength channels 51 to 5n in a certain direction. Furthermore, the reflective liquid crystal display device 13 is capable of orienting the selected one or more wavelength channels 51 to 5n towards one or more output ports (e.g., located at...). Figure 2 One or more output optical fibers on the inside of the paper (refer to) Figure 1 Change direction in the manner of )) . In Figure 2 In the case shown, the orientation conversion achieved by the reflective liquid crystal display device 13 is performed along an angle located in a plane orthogonal to the paper (yz plane). Wavelength channels 51 to 5n are, for example, referenced... Figure 1 The direction conversion is shown in more detail below, as described. After being reflected by the reflective liquid crystal display device 13, the direction-converted wavelength channels 51 to 5n are re-intruded into the lens 23 and further direction-converted in order to reach the dispersive element 24, where they are re-coupled. For example, these wavelength channels 51 to 5n, which have undergone direction conversion along the same angle, are re-coupled into a single beam, which is then direction-converted along the direction in which the processed signal can be output at one of the output ports.

[0061] For example, a WDM signal beam 31 containing three WDM channels with wavelengths λ1, λ2, and λ3 and channel bandwidths δλ1, δλ2, and δλ3 is studied. Figure 1 In the example shown, the WDM signal beam 31 enters the system at an angle θ1. Furthermore, the WDM signal beam 31, advancing at angle θ1, passes through the center of lens 22, deviating from angle θ1 without being deflected. The three wavelength channels of the WDM signal beam 31 undergo angular dispersion in an orthogonal plane (xz plane) after passing through the dispersive element 24; however, all channels after angular dispersion still advance at angle θ1. Then, as... Figure 3 As shown, these three dispersed wavelength channels are focused by lens 23 at different positions on the reflective liquid crystal display device 13.

[0062] Regarding the device's routing capabilities, several different routing combinations are possible. For example, the study aims to route all three wavelength channels to... Figure 1 The output fiber 1n is shown. The corresponding portion of the reflective liquid crystal display device 13 deflects the wavelength channels of wavelengths λ1, λ2, and λ3 respectively, so that the wavelength channels of wavelengths λ1, λ2, and λ3 respectively follow... Figure 1One of the light rays 41 is shown returning. The role of the dispersive element 24 with respect to the return paths of the wavelength channels is to recouple (multiplex) the individual wavelength channels in such a way that they become the same light beam that is currently propagating. This recoupled beam is then redirected by the lens 22 to have an angle θ1 and propagate along the output beam 31c that has now been shifted from the WDM signal beam 31. The role of the collimating lens 16 is to couple the recoupled and redirected output beam 31c with the output fiber ln. In this mode of operation, the WSS device WSS1 thus acts to pass all three wavelength channels of the WDM signal beam 31 from the input fiber 1 to the output fiber ln.

[0063] In another example, it can be desirable to route the several wavelength channels to different output fibers, respectively, depending on the situation. For example, depending on the situation, the reflective liquid crystal display device 13 deflects the wavelength channel of wavelength λ1 along the output beam 31a, the wavelength channel of wavelength λ2 along the output beam 31b, and the wavelength channel of wavelength λ3 along the output beam 31c. Here, the role of the dispersive element 24 is also to redirect these output beams. However, in this case, the dispersive element 24 does not recouple the output beams in such a way that they become a single beam, but rather generates three output beams that fan out and proceed. Furthermore, since the output beams each start from the same y-axis position LCI on the reflective liquid crystal display device 13, the output beams exit the lens 22 as a set of parallel light rays propagating along the same angle θ1 as the original WDM signal beam 31. However, since the output beams each impinge on the lens 22 at a different height (different y-axis position), the output beams are shifted with respect to each other. As a result, for example, the wavelength channel of wavelength λ1 propagates along the output beam 31a, the wavelength channel of wavelength λ2 propagates along the output beam 31b, and the wavelength channel of wavelength λ3 propagates along the output beam 31c. Thus, in this configuration, the WSS device WSS1 acts to route the wavelength channel of wavelength λ1 from the input fiber 1 to the output fiber la. In addition, the WSS device WSS1 acts to route the wavelength channel of wavelength λ2 from the input fiber 1 to the output fiber lb. Furthermore, the WSS device WSS1 acts to route the wavelength channel of wavelength λ3 from the input fiber 1 to the output fiber ln.

[0064] In view of the above, it is clear that in the WSS array 10 of the present disclosure, any wavelength channel of a WDM signal beam can be routed to any of the output fibers as desired. Furthermore, depending on the situation, the WSS array 10 can be configured to route the wavelength channels of the WDM signal beam 31 to the output fibers la, lb, and ln, respectively, or to route the wavelength channels of the WDM signal beam 32 to the output fibers la, lb, and ln, respectively. Figure 1 The symmetry of the system shown, the above description applies equally to the routing of the WDM signal beam 32 using the WSS device WSS2. This is because, as Figure 3As shown, the dispersed wavelength channels of the WSS devices WSS1 and WSS2 are finally condensed onto different parts of the reflective liquid crystal display device 13, respectively. Also, in the example shown, one input port and n output ports are used, but it is understood that the output ports can be reconfigured as input ports, and vice versa. Also, any number of input ports and output ports can be used without departing from the scope of the present application. Similarly, Figures 1 to 3 The example explicitly shown in FIG. 1 is a WSS array 10 using two WSS devices WSS1 and WSS2, but any number of WSS devices can be used without departing from the scope of the present application. For example, when the input-output section 11 is designed to use four separate transmission angles, the WSS array 10 can provide four independent WSS devices. Figures 1 to 3

[0065] (Second Embodiment)

[0066] Figure 4 FIG. 1 is a diagram showing the structure of a reflective liquid crystal display device according to the second embodiment.

[0067] The reflective liquid crystal display device 13 uses a subframe driving method as a halftone display method. In the subframe driving method, which is a kind of time-axis modulation method, a prescribed period (for example, one frame period in the case of a moving image, which is the display unit of one image) is divided into a plurality of subframe periods, and the pixels are driven by the combination of subframes corresponding to the gray scale to be displayed. The gray scale to be displayed is determined by the proportion of the driving period of the pixel in the prescribed period, which is determined by the combination of subframes.

[0068] The reflective liquid crystal display device 13 includes an image display section 61 in which a plurality of pixels Pix are regularly arranged, a timing generator 62, a vertical shift register 63, a data latch circuit 64, and a horizontal driver 65. The horizontal driver 65 includes a horizontal shift register 65a, a latch circuit 65b, and a level shifter / pixel driver 65c.

[0069] The timing generator 62, the vertical shift register 63, the data latch circuit 64, and the horizontal driver 65 correspond to an example of the "spatial light modulator driving section" of the present disclosure.

[0070] ​m (m is a natural number of 2 or more) row scanning lines gl to gm extend in the row direction (x direction), and one end of each is connected to the vertical shift register 63. In addition, there is a case where inverted row scanning lines gbl to gbm are provided in addition to the row scanning lines gl to gm. n (n is a natural number of 2 or more) column data lines dl to dn extend in the column direction (y direction), and one end of each is connected to the level shifter / pixel driver 65c. In addition, there is a case where inverted column data lines db 1 to dbn are provided in addition to the column data lines dl to dn.

[0071] The image display portion 61 has a plurality of pixels Pix provided at each of the intersections of the row scanning lines gl to gm and the column data lines dl to dn. That is, the plurality of pixels Pix are arranged in a two-dimensional matrix shape.

[0072] All of the pixels Pix in the image display portion 61 are commonly connected to a trigger line trig, and one end of the trigger line trig is connected to the timing generator 62. In addition, there is a case where an inverted trigger line trigb is provided in addition to the trigger line trig.

[0073] The forward (non-inverted) row scanning pulses transmitted from the row scanning lines gl to gm and the inverted row scanning pulses transmitted from the inverted row scanning lines gbl to gbm are always in a relationship of opposite logic values (complementary relationship).

[0074] In addition, the forward (non-inverted) data transmitted from the column data lines dl to dn and the inverted data transmitted from the inverted column data lines db 1 to dbn are always in a relationship of opposite logic values (complementary relationship).

[0075] In addition, the forward trigger pulse TRIG transmitted from the trigger line trig and the inverted trigger pulse TRIGB transmitted from the inverted trigger line trigb are always in a relationship of opposite logic values (complementary relationship).

[0076] The timing generator 62 receives, as input signals, external signals such as a vertical synchronization signal Vst, a horizontal synchronization signal Hst, and a basic clock signal CLK from the upper-level device 71. The timing generator 62 generates internal signals such as an alternating signal FR, a vertical start pulse VST, a horizontal start pulse HST, clock signals VCK and HCK, a latch pulse LT, a forward trigger pulse TRIG, and an inverted trigger pulse TRIGB on the basis of the external signals.

[0077] The alternating-current signal FR is a signal that is polarity-inverted per subfield, and is supplied as a common electrode voltage Vcom to the common electrode of the liquid crystal element in the pixel Pix that constitutes the image display portion 61. The vertical start pulse VST is a pulse signal that is output at the start timing of each subfield as described later, and the switching of the subfield is controlled by the vertical start pulse VST. The horizontal start pulse HST is a pulse signal that is output at the start timing of input to the horizontal shift register 65a. The clock signal VCK is a shift clock that defines one horizontal scanning period (1H) in the vertical shift register 63, and the vertical shift register 63 performs a shift operation at the timing of the clock signal VCK. The clock signal HCK is a shift clock in the horizontal shift register 65a, and is a signal for shifting data in 32-bit width.

[0078] The latch pulse LT is a pulse signal that is output at the timing at which the horizontal shift register 65a ends the shifting of the data of the number of pixels in one row in the horizontal direction. The timing generator 62 supplies the forward rotation trigger pulse TRIG via the trigger line trig and the backward rotation trigger pulse TRIGB via the backward rotation trigger line trigb to all of the pixels Pix in the image display portion 61. The forward rotation trigger pulse TRIG and the backward rotation trigger pulse TRIGB are sequentially written in the first signal holding circuit (described later) in each of the pixels Pix in the image display portion 61 during the subfield period, and are output immediately after the writing ends. The forward rotation trigger pulse TRIG and the backward rotation trigger pulse TRIGB are signals for transferring the data of the first signal holding circuit (described later) in all of the pixels Pix in the image display portion 61 to the second signal holding circuit (described later) in the same pixel Pix at a time during the output subfield period.

[0079] The vertical shift register 63 transfers the vertical start pulse VST that is supplied at the beginning of each subfield in accordance with the clock signal VCK. In addition, the vertical shift register 63 sequentially and exclusively supplies the forward rotation line scanning pulse in units of 1H with respect to the line scanning lines gl to gm and the backward rotation line scanning pulse in units of 1H with respect to the backward rotation line scanning lines gbl to gbm. The vertical shift register 63 supplies the forward rotation line scanning pulse from all of the line scanning lines gl to gm and the backward rotation line scanning pulse from all of the backward rotation line scanning lines gbl to gbm during one frame period. Thus, during one frame period, the line scanning lines g and the backward rotation line scanning lines gb are each sequentially selected in units of 1H from the line scanning line gl and the backward rotation line scanning line gbl that are located at the top in the image display portion 61 to the line scanning line gm and the backward rotation line scanning line gbm that are located at the bottom.

[0080] The data latch circuit 64 latches 32-bit width data supplied from an external circuit not shown in the figure, which is divided by each subframe, based on a basic clock signal CLK from the upper device 71. Thereafter, the data latch circuit 64 outputs the latched data to the horizontal shift register 65a in synchronization with the basic clock signal CLK. Here, in the second embodiment, the reflective liquid crystal display device 13 divides 1 frame of an image signal into a plurality of subframes having a display period shorter than that of 1 frame of the image signal, and performs gradation display by combination of the subframes. Therefore, the above-mentioned external circuit converts gradation data indicating the gradation of each pixel of the image signal into subframe data of 1 bit per subframe for displaying the gradation of each pixel in the entire above-mentioned plurality of subframes. Further, the above-mentioned external circuit further aggregates the above-mentioned subframe data of 32-pixel amount in the same subframe as the above-mentioned 32-bit width data, and supplies the data to the data latch circuit 64.

[0081] In the case of looking at the processing system from 1-bit serial data, the horizontal shift register 65a starts shifting by the horizontal start pulse HST of 1H initially supplied from the timing generator 62. Further, the horizontal shift register 65a shifts the 32-bit width data supplied from the data latch circuit 64 in synchronization with the clock signal HCK. The latch pulse LT is supplied from the timing generator 62 at the timing at which the horizontal shift register 65a ends shifting of n-bit amount data identical to the number n of pixels of 1 row amount of the image display section 61. The latch circuit 65b latches n-bit amount data (i.e., subframe data of n-pixel amount of the same row) supplied in parallel from the horizontal shift register 65a in accordance with the latch pulse LT, and outputs to the level shifter of the level shifter / pixel driver 65c. When the data transfer to the latch circuit 65b ends, the horizontal start pulse HST is output again from the timing generator 62, and the horizontal shift register 65a starts shifting of the 32-bit width data from the data latch circuit 64 again in accordance with the clock signal HCK.

[0082] The level shifter within the level shifter / pixel driver 65c level-shifts the signal level of n subframe data corresponding to n pixels of 1 row, which is latched and supplied by the latch circuit 65b, to reach the liquid crystal drive voltage amplitude. The pixel driver within the level shifter / pixel driver 65c outputs n subframe data corresponding to n pixels of 1 row in parallel to n column data lines dl to dn after level shifting.

[0083] The horizontal driver 65 performs the output of data for the pixel row to which data is written in 1H and the shifting of data related to the pixel row to which data is written in the next 1H in parallel within 1H. During a certain horizontal scan period, n subframe data of 1 row amount, which is latched, is output in parallel and all at once as a data signal from n column data lines dl to dn, respectively.

[0084] The n pixels Pix of the 1 line selected by the forward direction line scanning pulse from the vertical shift register 63 sample n subframe data of 1 line amount collectively output from the level shifter / pixel driver 65c via n column data lines dl to dn. Also, the n pixels Pix of the 1 line write the sampled n subframe data of 1 line amount into the first signal holding circuit (described later) in each pixel Pix, respectively.

[0085] Figure 5 FIG. 4 is a diagram showing a structure of a pixel of a reflective liquid crystal display device according to a second embodiment.

[0086] The pixel Pix is disposed at an intersection of the row scanning line g and the column data line d. The pixel Pix includes a first memory 81 and a second memory 82 which store 1 bit of gradation data (pixel data), respectively. The first memory 81 includes a switch 81a and a first signal holding circuit 81b. The second memory 82 includes a switch 82a and a second signal holding circuit 82b.

[0087] The pixel Pix includes a liquid crystal display element LC. The liquid crystal display element LC has a liquid crystal LCM interposed between a reflection electrode PE and a common electrode CE which are disposed to face each other. The common electrode CE is exemplified as being formed on the counter substrate of the reflective liquid crystal display device 13, but the present disclosure is not limited thereto.

[0088] The column data line d is connected with a horizontal driver 65 (refer to Figure 4 ). The horizontal driver 65 changes a driving timing to drive a specific column data line d. The row scanning line g is connected with a vertical shift register 63 (refer to Figure 4 ). The vertical shift register 63 changes a driving timing to drive a specific row scanning line g.

[0089] When a forward direction line scanning pulse is supplied to the row scanning line g, the switch 81a becomes an on state. At this time, the gradation data supplied from the column data line d is written into the first signal holding circuit 81b via the switch 81a. The switch 82a becomes an on state when a forward direction trigger pulse TRIG is supplied to the trigger line trig. At this time, the gradation data held in the first signal holding circuit 81b is transferred to the second signal holding circuit 82b via the switch 82a. The gradation data transferred to the second signal holding circuit 82b is supplied to the reflection electrode PE of the liquid crystal display element LC.

[0090] When the pixel Pix of the specific intersection is selected by the column data line d and the row scanning line g, 1-bit gradation data is written in the first memory 81 within the pixel Pix. This is repeated by shifting the timing with respect to all the pixels Pix, and thus 1-bit gradation data is written in all the pixels Pix. Then, by supplying the positive rotation trigger pulse TRIG to the trigger line trig commonly connected to all the pixels Pix, the gradation data held in the first memory 81 is transferred to the second memory 82 in all the pixels Pix. The second memory 82 is connected to the reflective electrode PE, and the gradation data held in the second memory 82 is applied to the liquid crystal display element LC.

[0091] When the transfer of the gradation data from the first memory 81 to the second memory 82 is completed, the supply of the positive rotation trigger pulse TRIG is completed, and thus the first memory 81 and the second memory 82 are not conducted. Then, 1-bit gradation data is written again in the first memory 81 of all the pixels Pix. During the writing of the gradation data in the first memory 81, the gradation data held in the second memory 82 is continuously applied to the liquid crystal display element LC.

[0092] The gradation data is described. First, the positive rotation subframe gradation data is written in all the pixels Pix, and the liquid crystal display element LC displays based on the positive rotation subframe gradation data. Next, the inversion gradation data is written in the first memory 81 of all the pixels Pix. At the time when the writing of the inversion gradation data in the first memory 81 is completed, the positive rotation trigger pulse TRIG is supplied, and the inversion gradation data is transferred at once to the second memory 82 of all the pixels Pix. Then, the liquid crystal display element LC displays based on the inversion gradation data. At this timing, the common electrode voltage Vcom supplied to the common electrode CE of the liquid crystal display element LC is inverted. The relationship of the voltage of the inversion gradation data and the common electrode voltage Vcom becomes the opposite side voltage compared with the case where the positive rotation subframe gradation data is applied to the liquid crystal display element LC. That is, by sequentially inputting the positive rotation subframe gradation data and the inversion gradation data to the pixel Pix, the liquid crystal display element LC can be AC driven positively and negatively. Thus, the liquid crystal display element LC does not burn, and a highly reliable reflective liquid crystal display device 13 can be achieved.

[0093] Based on the structure of the pixel Pix, it is possible to distinguish between the grayscale data writing time of the pixel Pix to the first memory 81 and the grayscale data application time to the reflective electrode PE of the liquid crystal display element LC. That is, the grayscale data written to the first memory 81 during the grayscale data writing time is not applied to the liquid crystal display element LC at the moment it is written to the first memory 81. Therefore, the voltage relationship between the voltage of the reflective electrode PE and the voltage of the common electrode Vcom is not disrupted during the grayscale data writing process. Therefore, it is not necessary to keep the reflective electrode PE and the common electrode CE at the same potential during the grayscale data writing time to keep the liquid crystal display element LC in an off state, as is the case in the past. In this way, the display loss time of the liquid crystal display element LC during the grayscale data writing time can be eliminated, thus providing a high-performance reflective liquid crystal display device 13 with good grayscale. In addition, there is no limitation that the liquid crystal display element LC cannot display during the grayscale data writing time. Therefore, even for devices with a large number of pixels such as FHD (1920×1080) and 4K2K, a high-performance reflective liquid crystal display device 13 can be achieved without sacrificing grayscale.

[0094] (Third Implementation)

[0095] Figure 6 This is a diagram showing the circuit structure of the pixels of the reflective liquid crystal display device according to the third embodiment.

[0096] One end of column data line d and the other end of the inverted column data line db are connected to the level shifter / pixel driver 65c (see reference). Figure 4 Connect and extend along the column direction (y direction). Column data line d and reverse column data line db are any one of the n pairs of column data lines, where column data line dj for forward rotor frame grayscale data and reverse column data line dbj for reverse grayscale data are set as a pair. Pixel Pix1 is located at the intersection of any one pair of column data lines d and reverse column data line db with any one row scan line g.

[0097] The pixel Pix1 includes a first memory 91, a second memory 92, and a liquid crystal display element LC.

[0098] The first memory 91 includes switches SW11a and SW11b and a first signal holding circuit SM11.

[0099] The second memory 92 includes switches SW12a and SW12b and a second signal holding circuit SM12.

[0100] In pixel Pix1, each of the first memory 91 and the second memory 92 includes static random access memory (SRAM).

[0101] The switches SW11a and SW11b correspond to an example of the "first switching circuit" of the present disclosure. The first signal holding circuit SM11 corresponds to an example of the "first signal holding circuit" of the present disclosure. The first memory 91 corresponds to an example of the "first static random access memory" of the present disclosure. The switches SW12a and SW12b correspond to an example of the "second switching circuit" of the present disclosure. The second signal holding circuit SM12 corresponds to an example of the "second signal holding circuit" of the present disclosure. The second memory 92 corresponds to an example of the "second static random access memory" of the present disclosure.

[0102] The switch SW11a includes an N-channel type MOS (Metal Oxide Semiconductor) transistor (hereinafter referred to as NMOS) transistor whose gate is connected to the row scan line g, whose drain is connected to the column data line d, and whose source is connected to the input terminal of one of the first signal holding circuits SM11. The switch SW11b includes an NMOS transistor whose gate is connected to the row scan line g, whose drain is connected to the inverted column data line db, and whose source is connected to the input terminal of the other of the first signal holding circuits SM11.

[0103] The first signal holding circuit SM11 is a self-holding type memory including two inverters INV1 and INV2 whose output terminal of one is connected to the input terminal of the other. The input terminal of the inverter INV1 is connected to the output terminal of the inverter INV2, the source of the NMOS transistor constituting the switch SW11a, and the switch SW12a. The input terminal of the inverter INV2 is connected to the output terminal of the inverter INV1, the source of the NMOS transistor constituting the switch SW11b, and the switch SW12b.

[0104] The switch SW12a includes an NMOS transistor whose gate is connected to the trigger line trig, whose drain is connected to the connection point of the first signal holding circuit SM11 and the switch SW11a, and whose source is connected to one input terminal of the second signal holding circuit SM12. The switch SW12b includes an NMOS transistor whose gate is connected to the trigger line trig, whose drain is connected to the connection point of the first signal holding circuit SM11 and the switch SW11b, and whose source is connected to the other input terminal of the second signal holding circuit SM12.

[0105] The second signal holding circuit SM12 is a self-holding memory including two inverters INV3 and INV4 whose output terminal is connected to the input terminal of the other. The input terminal of the inverter INV3 is connected to the output terminal of the inverter INV4, the source of the NMOS transistor constituting the switch SW12a, and the reflection electrode PE. The input terminal of the inverter INV4 is connected to the output terminal of the inverter INV3 and the source of the NMOS transistor constituting the switch SW12b.

[0106] The inverters INV1, INV2, INV3, and INV4 each exemplify the structure of a CMOS (Complementary Metal Oxide Semiconductor) inverter.

[0107] Figure 7 is a diagram showing the circuit structure of a CMOS inverter. The source of the PMOS transistor Ptr is connected to the power supply voltage VDD. The drain of the PMOS transistor Ptr is connected to the drain of the NMOS transistor Ntr. The source of the NMOS transistor Ntr is connected to the reference voltage GND. The gate of the PMOS transistor Ptr is connected to the gate of the NMOS transistor Ntr, which is the input terminal IN of the CMOS inverter. The drain of the PMOS transistor Ptr is connected to the drain of the NMOS transistor Ntr, which is the output terminal OUT of the CMOS inverter.

[0108] Referring again to Figure 6 , the writing of the gradation data to the first memory 91 is performed via two switches SW11a and SW11b that operate by the forward rotation row scanning pulse. The gradation data of mutually opposite polarities is supplied to the column data line d and the inverted column data line db. The two switches SW11a and SW11b include NMOS transistors. In the switches SW11a and SW11b, the drain of the NMOS transistor of one switch is supplied with the power supply voltage VDD, and the drain of the NMOS transistor of the other switch is supplied with the reference voltage GND. In the case where the power supply voltage VDD is supplied to the drain of one NMOS transistor, only a voltage lower than the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor is output from the source of the NMOS transistor. Also, at this voltage, since the NMOS transistor is driven in the vicinity of the threshold voltage Vth, almost no current flows. Therefore, the gradation data is written to the first memory 91 by the NMOS transistor supplied with the other reference voltage GND.

[0109] The writing of the gradation data to the second memory 92 is performed via two switches SW12a and SW12b which are operated by the positive rotation trigger pulse TRIG. The wiring m between the output terminal of the inverter INV2 and the switch SW12a, and the wiring mb between the output terminal of the inverter INVl and the switch SW12b are supplied with the gradation data of mutually opposite polarities. The two switches SW12a and SW12b include NMOS transistors. The drain of the NMOS transistor of one of the switches SW12a and SW12b is supplied with the power supply voltage VDD, and the drain of the NMOS transistor of the other switch is supplied with the reference voltage GND. In the case where the drain of the NMOS transistor is supplied with the power supply voltage VDD, only a voltage lower than the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor is output from the source of the NMOS transistor. Also, at this voltage, since the NMOS transistor is driven in the vicinity of the threshold voltage Vth, almost no current flows. Therefore, the gradation data is written to the second memory 92 by the NMOS transistor which is supplied with the other reference voltage GND.

[0110] In the case where the positive rotation trigger pulse TRIG is supplied, it is necessary to rewrite the gradation data of the second memory 92 with the gradation data of the first memory 91. That is, it is not possible to rewrite the gradation data of the first memory 91 with the gradation data of the second memory 92. Therefore, it is necessary to make the driving force of the inverters INV3 and INV4 which constitute the second memory 92 smaller than the driving force of the inverters INVl and INV2 which constitute the first memory 91. That is, in the case where the gradation data of the first memory 91 is different from the gradation data of the second memory 92, when the positive rotation trigger pulse TRIG is supplied, the output of the inverter INVl competes with the output of the inverter INV3. In order to be able to reliably rewrite the gradation data of the inverter INV4 with the gradation data of the inverter INVl, it is necessary to make the driving force of the inverter INVl larger than the driving force of the inverter INV3.

[0111] Likewise, in the competition between the inverter INV2 and the inverter INV4, it is necessary to be able to reliably rewrite the gradation data of the inverter INV3 with the gradation data of the inverter INV2. Therefore, the driving force of the inverter INV2 needs to be larger than the driving force of the inverter INV4.

[0112] Figure 8 is a diagram which shows the magnitude relationship of the driving forces between the inverters.

[0113] To simply explain the relationship between inverters INV1 and INV3, when the grayscale data of the first memory 91 in the wiring mb is at a "H" level, the PMOS transistor PT1 of inverter INV1 is turned on. Conversely, when the grayscale data on the mb side of the second memory 92 is at a "L" level, the NMOS transistor NT2 of inverter INV3 is turned on.

[0114] The following scenario is investigated: The NMOS transistor constituting switch SW12b is turned on by the "H" level of the forward trigger pulse TRIG, and the outputs of inverters INV1 and INV3 are interconnected. Current flows from the power supply voltage VDD through the PMOS transistor PT1 of inverter INV1 and the NMOS transistor NT2 of inverter INV3 to the reference voltage GND. At this time, the voltage across wiring mb is determined by the ratio of the on-resistance of the PMOS transistor PT1 of inverter INV1 and the NMOS transistor NT2 of inverter INV3.

[0115] Conversely, when the grayscale data of the first memory 91 in the wiring mb is at the "L" level, the NMOS transistor NT1 of the inverter INV1 is turned on. In contrast, when the grayscale data on the mb side of the second memory 92 is already at the "H" level, the PMOS transistor PT2 of the inverter INV3 is turned on.

[0116] The following scenario is investigated: The NMOS transistor constituting switch SW12b is turned on by the "H" level of the forward trigger pulse TRIG, and the outputs of inverters INV1 and INV3 are interconnected. Current flows from the power supply voltage VDD through the PMOS transistor PT2 of inverter INV3 and the NMOS transistor NT1 of inverter INV1 to the reference voltage GND. At this time, the voltage of wiring mb is determined by the ratio of the on-resistance of the PMOS transistor PT2 of inverter INV3 and the NMOS transistor NT1 of inverter INV1.

[0117] Additionally, an inverter INV4 is connected to the wiring mb (see reference). Figure 6). The inverter INV4 determines the output data to be an "L" level or an "H" level by the voltage level of the wire mb. That is, the output data of the second memory 92 is determined by the voltage level of the wire mb. Therefore, in order to rewrite the gradation data of the second memory 92 by the gradation data of the first memory 91, the on-resistance of the transistors of the inverters INV1 and INV2 needs to be lower than the on-resistance of the transistors of the inverters INV3 and INV4. The on-resistance of the transistors of the inverters INV1 and INV2 is lower than the on-resistance of the transistors of the inverters INV3 and INV4, whereby the gradation data of the first memory 91 is reliably written to the second memory 92 regardless of the gradation data level of the second memory 92.

[0118] The use of a transistor with low on-resistance can be achieved by using a transistor with high driving force, which can be achieved by reducing the gate length or increasing the gate width.

[0119] Referring again to Figure 6 When the gradation data stored in the first memory 91 is simultaneously transferred to the second memory 92 of all the pixels Pixl, the forward trigger pulse TRIG becomes an "L" level, and the switches SW12a and SW12b become an off state. Therefore, the second memory 92 can hold the transferred gradation data, and fix the potential of the reflecting electrode PE to the potential corresponding to the gradation data at any time (in this case, during one subframe).

[0120] Further, the switches SW11a, SW11b, SW12a, and SW12b can also include PMOS transistors. In this case, it can be considered that it is sufficient to be the opposite polarity to the above-described explanation, and thus the illustration and explanation are omitted.

[0121] In addition, the switches SW11a, SW11b, SW12a, and SW12b can also be transmission gates including PMOS transistors and NMOS transistors.

[0122] Figure 9 is a timing chart showing the operation of the reflective liquid crystal display device of the third embodiment.

[0123] As described above, in the reflective liquid crystal display device 13 (refer to Figure 4) in which one line of the row scanning lines g is selected in units of 1H from the row scanning line gl to the row scanning line gm by the forward rotation line scanning pulse output from the vertical shift register 63. By this, the plurality of pixels Pixl constituting the image display portion 61 performs the writing of the gradation data in units of 1 row of n pixels Pixl which are commonly connected to the selected line of the row scanning lines g. Then, after the writing to all of the plurality of pixels Pixl constituting the image display portion 61 is completed, the transfer of all of the pixels Pixl from the first memory 91 to the second memory 92 is performed at once by the forward rotation trigger pulse TRIG.

[0124] Figure 9 (A) of FIG. 8 schematically shows the writing period and the readout period of one pixel of the 1-bit subframe gradation data output from the horizontal driver 65 to the column data lines dl to dn. The oblique line slanted to the right and down indicates the writing period. Further, in (A) of FIG. 8, the bits BOb, Blb, and B2b are the inverted data of the gradation data of the bits B0, B1, and B2. Figure 9

[0125] Figure 9 (B) of FIG. 8 indicates the forward rotation trigger pulse TRIG output from the timing generator 62 to the trigger line trig. The forward rotation trigger pulse TRIG is output per one subframe.

[0126] Figure 9 (C) of FIG. 8 schematically shows the bits of the subframe gradation data applied to the reflective electrode PE. Figure 9 (D) of FIG. 8 indicates the common electrode voltage Vcom. Figure 9 (E) of FIG. 8 indicates the voltage applied to the liquid crystal LCM.

[0127] First, the plurality of pixels Pixl of 1 row selected by the forward rotation line scanning pulse output from the timing generator 62, the forward rotation subframe gradation data of the bit B0 (A) of FIG. 8) is sampled by the switch SWl la and is written to the first signal holding circuit SMl l. Hereinafter, similarly, the writing of the forward rotation subframe gradation data of the bit B0 to the first signal holding circuit SMl l of all of the pixels Pixl constituting the image display portion 61 is performed. At the timing Tl after the end of this writing operation, the forward rotation trigger pulse TRIG (B) of FIG. 8) of the "H" level is simultaneously supplied to all of the pixels Pixl constituting the image display portion 61. Figure 9 Figure 9

[0128] ​​​Therefore, the switches SW12a and SW12b of all the pixels Pixl become the on state. Therefore, the positive subframe gradation data of the bit B0 stored in the first signal holding circuit SMl l is simultaneously transferred and held in the second signal holding circuit SM12 via the switches SW12a and SW12b. At the same time, the positive subframe gradation data of the bit B0 is applied to the reflective electrode PE. The holding period of the second signal holding circuit SM12 of the positive subframe gradation data of the bit B0 is one subframe period from the timing Tl to the timing T2 at which the next "H" level positive rotation trigger pulse TRIG is input.

[0129] Here, in the case where the bit value of the subframe gradation data is "1", that is, the "H" level, the power supply voltage VDD (for example, 3.3 V) is applied to the reflective electrode PE. In the case where the bit value of the subframe gradation data is "0", that is, the "L" level, the reference voltage GND (for example, 0 V) is applied to the reflective electrode PE. On the other hand, for the common electrode CE, a voltage other than the reference voltage GND, the power supply voltage VDD, can be applied as the common electrode voltage Vcom. The common electrode voltage Vcom is switched to a prescribed voltage at the same timing as when the "H" level positive rotation trigger pulse TRIG is supplied. Here, the common electrode voltage Vcom is set to a voltage lower than 0 V by the threshold voltage Vtt of the liquid crystal during the subframe period in which the positive subframe gradation data is applied to the reflective electrode PE (for example, from the timing Tl to the timing T2), as shown in (D) of FIG. 6. Figure 9

[0130] The liquid crystal display element LC performs gradation display corresponding to the absolute value of the difference voltage between the applied voltage of the reflective electrode PE and the common electrode voltage Vcom, that is, the applied voltage of the liquid crystal LCM. During one subframe period from the timing Tl to the timing T2, the positive subframe gradation data of the bit B0 is applied to the reflective electrode PE. Therefore, as shown in (E) of FIG. 6, in the case where the bit value of the subframe gradation data is "1", the applied voltage of the liquid crystal LCM is 3.3 V + Vtt (= 3.3 V - (-Vtt)). On the other hand, in the case where the bit value of the subframe gradation data is "0", the applied voltage of the liquid crystal LCM is +Vtt (= 0 V - (-Vtt)). Figure 9

[0131] Figure 10 is a graph showing the relationship between the applied voltage (RMS (effective) voltage) of the liquid crystal and the gradation value.

[0132] As shown in (F) of FIG. 6, the applied voltage of the liquid crystal LCM is 3.3 V + Vtt (= 3.3 V - (-Vtt)) in the case where the bit value of the subframe gradation data is "1", and +Vtt (= 0 V - (-Vtt)) in the case where the bit value of the subframe gradation data is "0". Figure 10 ​​As shown, the gray scale value curve 101 moves to the high voltage side. Specifically, the black gray scale value corresponds to the RMS voltage of the threshold voltage Vtt of the liquid crystal LCM, and the white gray scale value corresponds to the RMS voltage of the saturation voltage Vsat (= 3.3 V + Vtt) of the liquid crystal LCM. The gray scale values can be made to coincide with the effective portion of the gray scale value curve 101. Thus, as described above, the liquid crystal display element LC displays white when the applied voltage of the liquid crystal LCM is (3.3 V + Vtt), and displays black when the applied voltage of the liquid crystal LCM is + Vtt.

[0133] Referring again to Figure 9 During the period of the subframe in which the forward subframe gray scale data of the bit B0 is displayed, the writing of the reverse subframe gray scale data of the bit BOb (refer to Figure 9 (A)) to the first signal holding circuit SM11 of the pixel Pixl is sequentially started. Then, the reverse subframe gray scale data of the bit BOb is written to the first signal holding circuit SM11 of all the pixels Pixl of the image display portion 61. At the timing T2 after this writing ends, the forward trigger pulse TRIG of the "H" level is simultaneously supplied to all the pixels Pixl constituting the image display portion 61.

[0134] Thus, the switches SW12a and SW12b of all the pixels Pixl become the on state. Therefore, the reverse subframe gray scale data of the bit BOb stored in the first signal holding circuit SM11 is transferred to the second signal holding circuit SM12 via the switches SW12a and SW21b and is held. At the same time, the reverse subframe gray scale data of the bit BOb is applied to the reflective electrode PE. The holding period of the second signal holding circuit SM12 of the reverse subframe gray scale data of the bit BOb is one subframe period from the timing T2 to the timing T3 at which the next "H" level forward trigger pulse TRIG is supplied. Here, the reverse subframe gray scale data of the bit BOb is always in the opposite logical value relationship with the forward subframe gray scale data of the bit B0. Therefore, the reverse subframe gray scale data of the bit BOb is "0" when the forward subframe gray scale data of the bit B0 is "1", and is "1" when the forward subframe gray scale data of the bit B0 is "0".

[0135] On the other hand, the common electrode voltage Vcom is set to a voltage higher than the threshold voltage Vtt of the liquid crystal LCM by 3.3 V during one subframe period from the timing T2 at which the reverse subframe gray scale data is applied to the reflective electrode PE to the timing T3, as shown in (D) of Figure 9 Thus, during one subframe period from the timing T2 to the timing T3, the voltage of the reflective electrode PE is higher than the threshold voltage Vtt of the liquid crystal LCM, as shown in (E) of Figure 9As shown in (E), when the bit value of the subframe grayscale data is "1", the applied voltage of the liquid crystal LCM is -Vtt (=3.3V-(3.3V+Vtt)). On the other hand, when the bit value of the subframe grayscale data is "0", the applied voltage of the liquid crystal LCM is -3.3V-Vtt (=0V-(3.3V+Vtt)).

[0136] When the bit value of the forward rotor frame grayscale data of bit B0 is "1", the bit value of the subsequent input bit B0b inverted subframe grayscale data is "0". Therefore, the applied voltage to the liquid crystal LCM is -(3.3V + Vtt), and the direction of the potential applied to the liquid crystal LCM is opposite to that of the forward rotor frame grayscale data of bit B0, but the absolute value is the same. Therefore, pixel Pix1 displays white in the same way as the forward rotor frame grayscale data of bit B0. Similarly, when the bit value of the forward rotor frame grayscale data of bit B0 is "0", the bit value of the subsequent input bit B0b inverted subframe grayscale data is "1". Therefore, the applied voltage to the liquid crystal LCM is -Vtt, and the direction of the potential applied to the liquid crystal LCM is opposite to that of the forward rotor frame grayscale data of bit B0, but the absolute value is the same. Therefore, pixel Pix1 displays black in the same way as the forward rotor frame grayscale data of bit B0.

[0137] Therefore, as Figure 9 As shown in (E), pixel Pix1 displays the same grayscale in bit B0 and bit B0b, which is the complementary bit of bit B0, during the two subframes from timing T1 to T3. Simultaneously, pixel Pix1 performs AC drive that reverses the voltage direction of the liquid crystal LCM in each subframe. Therefore, pixel Pix1 can prevent burn-in of the liquid crystal LCM.

[0138] Next, during the subframe period displaying the inverted subframe grayscale data of bit B0b, bit B1 (reference) Figure 9 The writing of the forward rotor frame grayscale data (A) to the first signal holding circuit SM11 of pixel Pix1 begins sequentially. Then, bit B1 of the forward rotor frame grayscale data is written to the first signal holding circuit SM11 of all pixels Pix1 of the image display unit 61. At time T3 after the writing is completed, a forward trigger pulse TRIG of the "H" level is simultaneously provided to all pixels Pix1 constituting the image display unit 61.

[0139] Therefore, switches SW12a and SW12b of all pixels Pix1 are turned on. Thus, the forward rotor frame grayscale data of bit B1 stored in the first signal holding circuit SM11 is transferred to the second signal holding circuit SM12 via switches SW12a and SW12b and held. Simultaneously, the forward rotor frame grayscale data of bit B1 is applied to the reflective electrode PE. The second memory 92 holds the forward rotor frame grayscale data of bit B1 for one subframe from timing T3 to timing T4, which provides the next "H" level forward trigger pulse TRIG.

[0140] On the other hand, during the subframe period when the common electrode voltage Vcom applies positive rotor frame grayscale data to the reflective electrode PE, such as Figure 9 As shown in (D), the threshold voltage Vtt of the liquid crystal LCM is set to be lower than 0V. During one subframe from timing T3 to timing T4, the positive rotor frame grayscale data of bit B1 is applied to the reflective electrode PE. Therefore, as Figure 9 As shown in (E), when the bit value of the subframe grayscale data is "1", the applied voltage of the liquid crystal LCM is 3.3V + Vtt (=3.3V-(-Vtt)). On the other hand, when the bit value of the subframe grayscale data is "0", the applied voltage of the liquid crystal LCM is +Vtt (=0V-(-Vtt)).

[0141] Next, during the subframe period displaying the grayscale data of the positive rotor frame containing bit B1, bits B1b are sequentially started (refer to...). Figure 9 The inverted subframe grayscale data of (A) is written to the first signal holding circuit SM11 of pixel Pix1. Then, the inverted subframe grayscale data of bit B1b is written to the first signal holding circuit SM11 of all pixels Pix1 of the image display unit 61. At time T4 after the writing is completed, a forward trigger pulse TRIG of the "H" level is simultaneously provided to all pixels Pix1 constituting the image display unit 61.

[0142] Therefore, switches SW12a and SW12b of all pixels Pix1 are turned on. Consequently, the inverted subframe grayscale data of bit B1b stored in the first signal holding circuit SM11 is transferred to the second signal holding circuit SM12 via switches SW12a and SW12b and held. Simultaneously, the inverted subframe grayscale data of bit B1b is applied to the reflective electrode PE. The holding period of the inverted subframe grayscale data of bit B1b by the second signal holding circuit SM12 is one subframe from timing T4 to timing T5, which provides the next "H" level forward trigger pulse TRIG. Here, the inverted subframe grayscale data of bit B1b and the forward frame grayscale data of bit B1b are always in opposite logic value relationships.

[0143] On the other hand, the common electrode voltage Vcom is set to a voltage higher than the threshold voltage Vtt of the liquid crystal LCM during a subframe in which the inverted subframe gradation data is applied to the reflective electrode PE, as shown in (D) of FIG. 6. During one subframe from timing T4 to timing T5, the inverted subframe gradation data of the bit Blb is applied to the reflective electrode PE. Therefore, as shown in (E) of FIG. 6, in a case where the bit value of the subframe gradation data is "1", the applied voltage of the liquid crystal LCM is -Vtt (= 3.3 V - (3.3 V + Vtt)). On the other hand, in a case where the bit value of the subframe gradation data is "0", the applied voltage of the liquid crystal LCM is -3.3 V - Vtt (= 0 V - (3.3 V + Vtt)). Figure 9 Figure 9

[0144] Therefore, as shown in (E) of FIG. 6, the pixel Pixl displays the same gradation in the bit Bl and the bit Blb which is the complementary bit of the bit Bl during two subframes from the timing T3 to T5. At the same time, the pixel Pixl performs the AC drive in which the potential direction of the liquid crystal LCM is inverted every subframe. Thus, the pixel Pixl can prevent the burn-in of the liquid crystal LCM. Figure 9

[0145] After that, the same operation as described above is repeated, and according to the reflective liquid crystal display device 13 including the pixel Pixl, it is possible to perform the gradation display by the combination of a plurality of subframes.

[0146] In addition, the display period length of the bit B0 and the display period length of the bit B0b which is the complementary bit are the same first subframe period length. In addition, the display period length of the bit Bl and the display period length of the bit Blb which is the complementary bit are the same second subframe period length. However, the first subframe period length and the second subframe period length are not necessarily the same. Here, as an example, the second subframe period length is set to be twice the first subframe period length. In addition, the third subframe period length of the display period length of the bit B2 and the display period length of the bit B2b which is the complementary bit is set to be twice the second subframe period length. The same applies to other subframe periods, and each subframe period length is determined to a prescribed length according to the system, and in addition, the number of subframes can be determined to an arbitrary number.

[0147] (Summary)

[0148] ​​​The gradation data written to the second memory 92 is the forward subframe gradation data and the reverse subframe gradation data switched per each subframe. On the other hand, the common electrode voltage Vcom is alternately switched to a prescribed potential per each subframe in synchronization with the writing. Thereby, the pixel Pixl is able to perform the positive and negative AC drive of the liquid crystal display element LC. Therefore, the reflective liquid crystal display device 13 is able to suppress the sintering of the liquid crystal display element LC, and thus is able to improve the reliability.

[0149] In addition, the pixel Pixl does not need to make the reflection electrode PE and the common electrode CE the same potential to make the liquid crystal display element LC the off state during the gradation data writing time. Therefore, the reflective liquid crystal display device 13 is able to eliminate the display loss time of the liquid crystal display element LC in the gradation data writing time, and thus is able to make the gradation good. In addition, the reflective liquid crystal display device 13 does not have the constraint that the liquid crystal display element LC cannot perform display in the gradation data writing time, and thus even for a liquid crystal display device with a large number of pixels such as FHD, 4K2K, the gradation is not sacrificed.

[0150] In addition, the pixel Pixl sets the driving force of the inverters INV1 and INV2 to be larger than the driving force of the inverters INV3 and INV4, and thus is able to perform stable and accurate gradation display.

[0151] In addition, the pixel Pixl is able to set the applied voltage of the liquid crystal display element LC to be higher, and is able to expand the dynamic range. Thereby, the reflective liquid crystal display device 13 is able to suppress the reduction of the contrast ratio, and is able to suppress the reduction of the brightness. In addition, the reflective liquid crystal display device 13 is able to increase the reflection angle of the reflected light.

[0152] When the reflective liquid crystal display device 13 of the third embodiment capable of suppressing the reduction of the contrast ratio and the reduction of the brightness is applied to the WSS array 10, the reduction of the contrast ratio from the output light beam 31a to the output light beam 31c (refer to FIG. 1) is suppressed, and the reduction of the brightness is suppressed. Thereby, the WSS array 10 is able to improve the S / N (signal / noise) ratio of the wavelength channels. Figure 1 Furthermore, when the reflective liquid crystal display device of the third embodiment capable of increasing the reflection angle of the reflected light is applied to the WSS array 10 of the first embodiment, the spatial interval of the output light beams 31a to 31c (refer to FIG. 1) is expanded. Thereby, the WSS array 10 is able to improve the S / N ratio of the wavelength channels. Alternatively, the WSS array 10 is able to output a new output light beam while maintaining the spatial interval of the output light beams 31a to 31c. Thereby, the WSS array 10 is able to increase the wavelength channels.

[0153] Figure 1

[0154] ​​Further, in the pixel Pixl, the first signal holding circuit SMl l and the second signal holding circuit SMl 2 are static random access memories. Therefore, the pixel Pixl can improve noise resistance.

[0155] (Fourth Embodiment)

[0156] Figure 11 Fig. 6 is a diagram showing a circuit structure of a pixel of a reflective liquid crystal display device according to the fourth embodiment.

[0157] Among the constituent elements of the pixel Pix2 of the reflective liquid crystal display device according to the fourth embodiment, the same reference numerals are attached to the same constituent elements as those of the pixel Pixl of the third embodiment, and the description thereof is omitted.

[0158] The pixel Pix2 is provided at an intersection of an arbitrary one of the column data lines d and an arbitrary one of the row scan lines g.

[0159] The pixel Pix2 includes a first memory 111 and a second memory 112, and a liquid crystal display element LC. The first memory 111 includes a switch SW13 and a first signal holding circuit SM13. The second memory 112 includes a switch SW14 and a second signal holding circuit SM14.

[0160] In the pixel Pix2, each of the first memory 111 and the second memory 112 includes an SRAM.

[0161] The switch SW13 corresponds to an example of the "first switch circuit" of the present disclosure. The first signal holding circuit SM13 corresponds to an example of the "first signal holding circuit" of the present disclosure. The first memory 111 corresponds to an example of the "first static random access memory" of the present disclosure. The switch SW14 corresponds to an example of the "second switch circuit" of the present disclosure. The second signal holding circuit SM14 corresponds to an example of the "second signal holding circuit" of the present disclosure. The second memory 112 corresponds to an example of the "second static random access memory" of the present disclosure.

[0162] The pixel Pix2 contains a 2-stage SRAM like the pixel Pixl (see Figure 6 ), but is characterized in that writing to the first signal holding circuit SM13 and the second signal holding circuit SM14 is performed via the switches SW13 and SW14.

[0163] The switch SW13 contains an NMOS transistor whose gate is connected to the row scan line g, whose drain is connected to the column data line d, and whose source is connected to one input terminal of the first signal holding circuit SM13.

[0164] The first signal holding circuit SM13 is a self-holding type memory including two inverters INV11 and INV12 whose output terminal of one is connected to the input terminal of the other. The input terminal of the inverter INV11 is connected to the output terminal of the inverter INV12 and the source of the NMOS transistor constituting the switch SW13. The input terminal of the inverter INV12 is connected to the output terminal of the inverter INV11 and the drain of the NMOS transistor constituting the switch SW14.

[0165] The switch SW14 includes the NMOS transistor whose gate is connected to the trigger line trig, whose drain is connected to the output terminal of the first signal holding circuit SM13, and whose source is connected to the input terminal of the second signal holding circuit SM14.

[0166] The second signal holding circuit SM14 is a self-holding type memory including two inverters INV13 and INV14 whose output terminal of one is connected to the input terminal of the other. The input terminal of the inverter INV13 is connected to the output terminal of the inverter INV14 and the reflection electrode PE. The input terminal of the inverter INV14 is connected to the output terminal of the inverter INV13 and the source of the NMOS transistor constituting the switch SW14.

[0167] The inverters INV11, INV12, INV13, and INV14 each exemplify the structure of the CMOS inverter (refer to Fig. 6). Figure 7 ) the structure of the CMOS inverter (refer to Fig. 6).

[0168] The pixel Pix2 performs the same action as that described with reference to the timing chart of Fig. 7 in the third embodiment. Figure 9

[0169] First, the plurality of pixels Pix2 of one line selected by the forward rotation line scanning pulse output from the timing generator 62 are switched to the on state by the forward rotation line scanning pulse. At this time, the forward rotation subframe gradation data output to the column data line d is sampled by the switch SW13 and written to the first signal holding circuit SM13. Hereinafter, similarly, the first signal holding circuit SM13 of all the pixels Pix2 constituting the image display portion 61 is subjected to the writing of the forward rotation subframe gradation data. At the timing after the end of this writing action, the forward rotation trigger pulse TRIG of the "H" level is simultaneously supplied to all the pixels Pix2 constituting the image display portion 61.

[0170] ​Thus, the switch SW14 of all the pixels Pix2 becomes the on state. Therefore, the inversion subframe gradation data stored in the first signal holding circuit SM13 is collectively transferred and held in the second signal holding circuit SM14 via the switch SW14. At the same time, the inversion subframe gradation data is applied to the reflection electrode PE. The holding period of the inversion subframe gradation data by the second signal holding circuit SM14 is one subframe period until the next positive rotation trigger pulse TRIG of the "H" level is supplied.

[0171] Next, each pixel Pix2 in the image display portion 61 is selected by the positive rotation line scanning pulse in units of lines as described above, and the inversion subframe gradation data of the opposite logic value to the immediately preceding positive rotation subframe gradation data is written to the first signal holding circuit SM13 for each pixel Pix2. When the writing of the inversion subframe gradation data to the first signal holding circuit SM13 of all the pixels Pix2 constituting the image display portion 61 is completed, the positive rotation trigger pulse TRIG of the "H" level is simultaneously supplied to all the pixels Pix2 constituting the image display portion 61.

[0172] Thus, the switch SW14 of all the pixels Pix2 becomes the on state. Therefore, the inversion subframe gradation data stored in the first signal holding circuit SM13 is collectively transferred and held in the second signal holding circuit SM14 via the switch SW14. At the same time, the inversion subframe gradation data is applied to the reflection electrode PE. The holding period of the inversion subframe gradation data by the second signal holding circuit SM14 is one subframe period until the next positive rotation trigger pulse TRIG of the "H" level is supplied.

[0173] The data writing to the first signal holding circuit SM13 is performed via one switch SW13 as described above. In this case, the transistor in the inverter INV11 on the input side as viewed from the switch SW13 uses a transistor having a larger driving force than the transistor in the inverter INV12 on the output side as viewed from the switch SW13. Also, the NMOS transistor constituting the switch SW13 uses a transistor having a larger driving force than the transistor constituting the inverter INV12.

[0174] This is related to the case of rewriting the gradation data of the first signal holding circuit SM13. This is because, particularly in the case where the voltage a on the side of the switch SW13 of the first signal holding circuit SM13 is the "L" level and the data of the column data line d is the "H" level, it is necessary to make the voltage a higher than the input voltage (threshold voltage) inverted by the inverter INV11.

[0175] That is, the voltage a in the case of the "H" level is determined by the ratio of the current of the NMOS transistor constituting the inverter INV12 to the current of the NMOS transistor constituting the switch SW13. The switch SW13 is an NMOS transistor. Therefore, in the case where the switch SW13 is in the on state, even if the power supply voltage VDD of the "H" level is input to the drain from the column data line d, the voltage output from the source is lower than the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor. That is, the voltage of the "H" level of the voltage a becomes a voltage lower than the power supply voltage VDD by the threshold voltage Vth. And, at this voltage, since the NMOS transistor of the switch SW13 operates near the threshold voltage Vth, the current hardly flows. That is, the higher the voltage a in which the switch SW13 is turned on, the less the current flowing in the switch SW13.

[0176] That is, in the case where the voltage a is the "H" level, in order to make the voltage a reach a voltage above which the NMOS transistor of the inverter INV11 inverts, it is necessary to make the current flowing through the switch SW13 greater than the current flowing through the NMOS transistor of the inverter INV12. Therefore, the NMOS transistor constituting the switch SW13 uses a transistor having a greater driving force than the NMOS transistor constituting the inverter INV12. In consideration of the magnitude relationship of the driving forces, it is necessary to determine the transistor size of the NMOS transistor constituting the switch SW13 and the transistor size of the NMOS transistor constituting the inverter INV12.

[0177] In addition, the data write to the second signal holding circuit SM14 is performed via one switch SW14. In this case, the transistor in the inverter INV14 on the input side as viewed from the switch SW14 uses a transistor having a greater driving force than the transistor in the inverter INV13 on the output side as viewed from the switch SW14.

[0178] The case where the positive rotation trigger pulse TRIG becomes the "H" level and the switch SW14 becomes the on state is investigated. In the case where the gradation data held by the first signal holding circuit SM13 is different from the gradation data held by the second signal holding circuit SM14, the output of the inverter INV11 competes with the output of the inverter INV13. However, the driving force of the inverter INV11 is greater than the driving force of the inverter INV13. Therefore, the gradation data of the first signal holding circuit SM13 is not overwritten by the gradation data of the second signal holding circuit SM14, and the gradation data of the second signal holding circuit SM14 is overwritten by the gradation data of the first signal holding circuit SM13.

[0179] Further, the NMOS transistor constituting the switch SW14 uses a transistor having a greater driving force than the NMOS transistor constituting the inverter INV13.

[0180] This is related to the case where the gray scale data of the second signal holding circuit SM14 is rewritten. This is because, particularly in the case where the voltage b on the side of the switch SW14 of the second signal holding circuit SM14 is the "L" level and the gray scale data of the first signal holding circuit SM13 is the "H" level, it is necessary to make the voltage b higher than the threshold voltage at which the inverter INV14 inverts.

[0181] That is, the voltage b in the case of the "H" level is determined by the ratio of the current of the NMOS transistor constituting the inverter INV13 to the current of the NMOS transistor constituting the switch SW14. The switch SW14 is an NMOS transistor. Therefore, in the case where the switch SW14 is in the on state, even if the power supply voltage VDD of the "H" level is input from the first signal holding circuit SM13 to the drain, the voltage output from the source becomes a voltage lower than the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor. That is, the voltage of the "H" level of the voltage b becomes a voltage lower than the power supply voltage VDD by the threshold voltage Vth. Also, at this voltage, since the NMOS transistor of the switch SW14 operates near the threshold voltage Vth, the current hardly flows. That is, the higher the voltage b at which the switch SW14 is turned on, the less the current flowing in the switch SW14.

[0182] That is, in the case where the voltage b is the "H" level, in order to make the voltage b reach a voltage above that at which the NMOS transistor of the inverter INV14 inverts, it is necessary to make the current flowing through the switch SW14 greater than the current flowing through the NMOS transistor of the inverter INV13. Therefore, the NMOS transistor constituting the switch SW14 uses a transistor having a greater driving force than the NMOS transistor constituting the inverter INV13. Considering the magnitude relationship of the driving forces, it is necessary to determine the transistor size of the NMOS transistor constituting the switch SW14 and the transistor size of the NMOS transistor constituting the inverter INV13.

[0183] When the gray scale data held in the first memory 111 is transferred to the second memory 112 of all the pixels Pix2 at once, the positive transition trigger pulse TRIG becomes the "L" level, and the switch SW14 becomes the off state. Therefore, the second memory 112 can hold the transferred gray scale data, and fix the potential of the reflecting electrode PE to the potential corresponding to the gray scale data at an arbitrary time (in this case, during one subfield).

[0184] In addition, the switches SW13 and SW14 can also include PMOS transistors. In this case, it can be considered that the polarity is opposite to the above-described explanation, and thus the illustration and explanation are omitted.

[0185] In addition, the switches SW13 and SW14 can also be transmission gates including PMOS transistors and NMOS transistors.

[0186] (SUMMARY)

[0187] The pixel Pix2 has the same effect as the pixel Pixl of the third embodiment.

[0188] Further, the pixel Pix2 has an effect of being able to be miniaturized. The reason is as follows. Each of the inverters INV11 to INV14 includes two transistors. Therefore, the pixel Pix2 includes a total of 10 transistors, and can include a smaller number of elements than the pixel Pixl (a total of 12 transistors).

[0189] (FIFTH EMBODIMENT)

[0190] The pixel Pixl of the third embodiment requires a total of 12 transistors. The pixel Pix2 of the fourth embodiment requires a total of 10 transistors.

[0191] In addition, the liquid crystal display element LC is required to be driven at 3 V to 5 V, and the transistors require a drive of 3.3 V or 5 V. Therefore, a transistor of high withstand voltage and large size is required to be used.

[0192] Further, in the pixels Pixl and Pix2 using two SRAMs, in order to reliably rewrite data, the design needs to be made considering the transistor sizes of the respective switches and SRAMs. A transistor required to increase the driving force needs to increase in size.

[0193] On the other hand, reflective liquid crystal display devices are being high-pixelated year by year, and there is a strong demand for miniaturization of pixels. In a small pixel pitch, it is required to configure a 2-stage memory with a small number of transistors. Figure 5

[0194] The pixel Pix3 of the fifth embodiment can satisfy the above-described requirements.

[0195] Figure 12 is a view showing a circuit structure of a pixel of a reflective liquid crystal display device of the fifth embodiment.

[0196] Among the constituent elements of the pixel Pix3 of the reflective liquid crystal display device of the fifth embodiment, the same reference numerals are attached to the same constituent elements as the pixel Pixl of the third embodiment or the pixel Pix2 of the fourth embodiment, and the description is omitted.

[0197] The pixel Pix3 is provided at an intersection of an arbitrary one of the column data lines d and an arbitrary one of the row scanning lines g.

[0198] The pixel Pix3 includes a first memory 111, a second memory 121, and a liquid crystal display element LC. The second memory 121 includes a switch SW21 and a second signal holding circuit DM21.

[0199] ​In the pixel Pix3, the first memory 111 includes an SRAM, and the second memory 121 includes a Dynamic Random Access Memory (DRAM).

[0200] The switch SW13 corresponds to an example of the "first switch circuit" of the present disclosure. The first signal holding circuit SM13 corresponds to an example of the "first signal holding circuit" of the present disclosure. The first memory 111 corresponds to an example of the "first static random access memory" of the present disclosure. The switch SW21 corresponds to an example of the "second switch circuit" of the present disclosure. The second signal holding circuit DM21 corresponds to an example of the "second signal holding circuit" of the present disclosure. The second memory 121 corresponds to an example of the "first dynamic random access memory" of the present disclosure.

[0201] The switch SW21 is a well-known transmission gate including an NMOS transistor Trl and a PMOS transistor Tr2 connected between the drains thereof and connected between the sources thereof. The gate of the NMOS transistor Trl is connected to the trigger line trig, and the gate of the PMOS transistor Tr2 is connected to the inverted trigger line trigb.

[0202] In addition, one terminal of the switch SW21 is connected to the first signal holding circuit SM13, and the other terminal is connected to the second signal holding circuit DM21 and the reflection electrode PE. Therefore, the switch SW21 becomes an on state in the case where the forward trigger pulse TRIG is an "H" level (in this case, the inverted trigger pulse TRIGB is an "L" level). Therefore, the switch SW21 reads out the gradation data of the first signal holding circuit SM13 and transmits to the second signal holding circuit DM21 and the reflection electrode PE. In addition, the switch SW21 becomes an off state in the case where the forward trigger pulse TRIG is an "L" level (in this case, the inverted trigger pulse TRIGB is an "H" level), and the reading out of the gradation data of the first signal holding circuit SM13 is not performed.

[0203] Switch SW21 is a known transmission gate comprising NMOS transistor Tr1 and PMOS transistor Tr2, thus enabling the switching of a voltage range from the reference voltage GND to the power supply voltage VDD. Specifically, when the signal applied to the gates of both NMOS transistor Tr1 and PMOS transistor Tr2 is the voltage at the reference voltage GND ("L" level), PMOS transistor Tr2 cannot conduct. Instead, NMOS transistor Tr1 can conduct with low resistance. Conversely, when the signal applied to the gates of both NMOS transistor Tr1 and PMOS transistor Tr2 is the voltage at the power supply voltage VDD ("H" level), NMOS transistor Tr1 cannot conduct. Instead, PMOS transistor Tr2 can conduct with low resistance. Therefore, the transmission gate constituting switch SW21 is controlled to turn on / off using a forward trigger pulse TRIG and a reverse trigger pulse TRIGB. Through this control, switch SW21 can switch the voltage range from the reference voltage GND to the power supply voltage VDD with low resistance and high resistance, respectively.

[0204] The second signal holding circuit DM21 includes a capacitor C1. Here, we examine the case where the grayscale data of the first signal holding circuit SM13 differs from the grayscale data of the second signal holding circuit DM21. When switch SW21 is in the ON state and the grayscale data of the first signal holding circuit SM13 is transmitted to the second signal holding circuit DM21, it is necessary to rewrite the grayscale data of the second signal holding circuit DM21 using the grayscale data of the first signal holding circuit SM13.

[0205] When the grayscale data of capacitor C1, which constitutes the second signal holding circuit DM21, is rewritten, this grayscale data changes through charging or discharging. The charging and discharging of capacitor C1 is driven by the output signal of inverter INV11.

[0206] When the grayscale data of capacitor C1 is changed from "L" level to "H" level by charging, the output signal of inverter INV11 is "H". At this time, the PMOS transistor constituting inverter INV11 (refer to...) Figure 7 The PMOS transistor (Ptr) is in the ON state, and the NMOS transistor (refer to) is in the ON state. Figure 7 The NMOS transistor (Ntr) is in the off state. Therefore, capacitor C1 is charged by the power supply voltage VDD connected to the source of the PMOS transistor of inverter INV11.

[0207] On the other hand, when the grayscale data of capacitor C1 is changed from "H" level to "L" level by discharging, the output signal of inverter INV11 is at "L" level. At this time, the NMOS transistor constituting inverter INV11 (refer to...) Figure 7the NMOS transistor Ntr of the inverter INV 11 is in an on state, and the PMOS transistor Ptr of the inverter INV 12 is in an off state. Thus, the charge of the capacitor Cl is discharged to the reference voltage GND via the NMOS transistor of the inverter INV 11. The switch SW21 is configured as an analog switch using a transmission gate, and thus can perform rapid charge and discharge of the capacitor Cl. Figure 7

[0208] Further, the driving force of the inverter INV 11 is set to be greater than the driving force of the inverter INV 12. Thus, the inverter INV 11 can rapidly perform charge and discharge of the capacitor Cl constituting the second signal holding circuit DM21.

[0209] Further, when the switch SW21 is on, the charge accumulated in the capacitor Cl can also affect the input gate of the inverter INV 12. However, since the driving force of the inverter INV 11 is set to be greater than the inverter INV 12, the inverter INV 11 is given priority in charge and discharge of the capacitor Cl over the data inversion of the inverter INV 12. Thus, the gradation data of the first signal holding circuit SM13 is not overwritten by the gradation data of the second signal holding circuit DM21.

[0210] The pixel Pix3 can transmit 1-bit gradation data from the first signal holding circuit SM13 to the second signal holding circuit DM21 with the amplitude of the reference voltage GND and the power supply voltage VDD. Thus, the pixel Pix3 can set the applied voltage of the liquid crystal display element LC to be higher in the case of driving with the same power supply voltage VDD, and can expand the dynamic range.

[0211] Further, the pixel Pix3 has the effect of being able to be miniaturized. The first reason is as follows. The inverters INV 11 and INV 12 each include two transistors. Thus, the pixel Pix3 includes a total of seven transistors and one capacitor Cl, and can include a smaller number of elements than the pixel Pixl (a total of 12 transistors) and the pixel Pix2 (a total of 10 transistors). The second reason is because, as described below, the first signal holding circuit SM13, the second signal holding circuit DM21, and the reflective electrode PE can be effectively arranged in the height direction of the elements.

[0212] Figure 13 FIG. 5 is a diagram showing the cross-sectional structure of a pixel of a reflective liquid crystal display device according to the fifth embodiment.

[0213] ​The capacitor Cl can use a MIM (Metal-Insulator-Metal) capacitor that forms a capacitor between lines, a Diffusion capacitor that forms a capacitor between a substrate and polysilicon, a PIP (Poly-Insulator-Poly) capacitor that forms a capacitor between two layers of polysilicon, or the like. Figure 13 A cross-sectional structure of a reflective liquid crystal display device is shown in a case where the capacitor Cl is composed of MIM.

[0214] In Figure 13 In the N well 201 formed in the silicon substrate 200, the PMOS transistor PTrll of the inverter INVl l and the PMOS transistor Tr2 of the switch SW21 are formed by sharing diffusion layers to connect the drains to each other. In the P well 202 formed in the silicon substrate 200, the NMOS transistor NTrll of the inverter INVl l and the NMOS transistor Trl of the switch SW21 are formed by sharing diffusion layers to connect the drains to each other. In the N well 203 formed in the silicon substrate 200, the PMOS transistor PTrl2 of the inverter INVl 2 and the PMOS transistor Tr3 of the switch SW22 are formed by sharing diffusion layers to connect the drains to each other. In the P well 204 formed in the silicon substrate 200, the NMOS transistor NTrl 2 of the inverter INVl 2 and the NMOS transistor Tr2 of the switch SW22 are formed by sharing diffusion layers to connect the drains to each other. Figure 13 In the N well 201 formed in the silicon substrate 200, the PMOS transistor PTrll of the inverter INVl l and the PMOS transistor Tr2 of the switch SW21 are formed by sharing diffusion layers to connect the drains to each other. In the P well 202 formed in the silicon substrate 200, the NMOS transistor NTrll of the inverter INVl l and the NMOS transistor Trl of the switch SW21 are formed by sharing diffusion layers to connect the drains to each other. In the N well 203 formed in the silicon substrate 200, the PMOS transistor PTrl2 of the inverter INVl 2 and the PMOS transistor Tr3 of the switch SW22 are formed by sharing diffusion layers to connect the drains to each other. In the P well 204 formed in the silicon substrate 200, the NMOS transistor NTrl 2 of the inverter INVl 2 and the NMOS transistor Tr2 of the switch SW22 are formed by sharing diffusion layers to connect the drains to each other.

[0215] Further, the first metal 206, the second metal 208, the third metal 210, the electrode 212, the fourth metal 214, and the fifth metal 216 are stacked above the PMOS transistors PTrll and Tr2 and the NMOS transistors Trl and NTrl 2, with the interlayer insulating film 205 interposed between the metals. The fifth metal 216 constitutes the reflective electrode PE formed for each pixel. For the NMOS transistor Trl and the PMOS transistor Tr2 constituting the switch SW21, two diffusion layers constituting the sources of the NMOS transistor Trl and the PMOS transistor Tr2, respectively, are electrically connected to the first metal 206 through two contact pieces 218, respectively. Further, the two diffusion layers are electrically connected to the second metal 208, the third metal 210, the fourth metal 214, and the fifth metal 216 via vias 219a, 219b, 219c, and 219e. That is, the sources of the NMOS transistor Trl and the PMOS transistor Tr2 constituting the switch SW21 are electrically connected to the reflective electrode PE.

[0216] Further, on the reflective electrode PE (fifth metal 216), a passivation film (PSV) 217 is formed as a protective film, and is disposed in opposition to the common electrode CE as a transparent electrode. The liquid crystal LCM is filled between these reflective electrode PE and the common electrode CE, and is sealed to constitute the liquid crystal display element LC.

[0217] Here, an electrode 212 is formed on the third metal 210 with an interlayer insulating film 205 in between. The electrode 212, the third metal 210, and the interlayer insulating film 205 between the electrode 212 and the third metal 210 constitute a capacitor C1.

[0218] When capacitor C1 is constructed using MIM, the first signal holding circuit SM13, switch SW13, and switch SW12 can include the transistor on silicon substrate 200 and the first metal 206 and second metal 208 layer 1 and 2 wirings. Additionally, the second signal holding circuit DM21 can include MIM wirings utilizing the third metal 210 above the transistor.

[0219] Electrode 212 is electrically connected to the fourth metal 214 via through-hole 219d. Furthermore, the fourth metal 214 is electrically connected to the reflective electrode PE via through-hole 219e. Therefore, capacitor C1 is electrically connected to the reflective electrode PE.

[0220] Light from a light source (not shown in the figure) passes through the common electrode CE and the liquid crystal LCM and is incident on the reflective electrode PE (fifth metal 216) and reflected. It travels in reverse along the original incident path and exits through the common electrode CE.

[0221] like Figure 13 As shown, by assigning the fifth metal 216 to the reflective electrode PE, the pixel Pix3 can effectively configure the first signal holding circuit SM13, the second signal holding circuit DM21, and the reflective electrode PE in the height direction. Therefore, the pixel Pix3 can achieve pixel miniaturization. Thus, the pixel Pix3 can, for example, be composed of transistors with a power supply voltage of 3.3V to form pixels with a pitch of less than 3μm. This 3μm pixel pitch enables a liquid crystal display panel with a diagonal length of 0.55 inches, a horizontal resolution of 4000 pixels, and a vertical resolution of 2000 pixels.

[0222] Pixel Pix3 execution and reference in the third embodiment Figure 9 The sequence diagram describes the same actions.

[0223] First, multiple pixels Pix3 in one row selected by the forward scan pulse output from the timing generator 62 are turned on by the forward scan pulse, and switch SW13 is turned on. At this time, the forward rotor frame grayscale data output to column data line d is sampled by switch SW13 and written to the first signal holding circuit SM13. Similarly, the forward rotor frame grayscale data is written to the first signal holding circuit SM13 of all pixels Pix3 constituting the image display unit 61. At the timing after this writing operation is completed, a forward trigger pulse TRIG at the "H" level and a reverse trigger pulse TRIGB at the "L" level are simultaneously provided to all pixels Pix3 constituting the image display unit 61.

[0224] Thus, the switches SW21 of all the pixels Pix3 become the on state. Therefore, the positive subframe gradation data stored in the first signal holding circuit SM13 are collectively transferred and held in the second signal holding circuit DM21 via the switches SW21. At the same time, the positive subframe gradation data are applied to the reflecting electrode PE. The holding period of the second signal holding circuit DM21 for the positive subframe gradation data is one subframe period until the next positive trigger pulse TRIG of the "H" level and the negative trigger pulse TRIGB of the "L" level are supplied.

[0225] Next, the pixels Pix3 in the image display portion 61 are selected by the positive subframe gradation data of the immediately preceding positive subframe gradation data are written to the first signal holding circuit SM13. When the writing of the negative subframe gradation data to the first signal holding circuit SM13 of all the pixels Pix3 in the image display portion 61 ends, the positive trigger pulse TRIG of the "H" level and the negative trigger pulse TRIGB of the "L" level are simultaneously supplied to all the pixels Pix3.

[0226] Thus, the switches SW21 of all the pixels Pix3 become the on state. Therefore, the negative subframe gradation data stored in the first signal holding circuit SM13 are collectively transferred and held in the second signal holding circuit DM21 via the switches SW21. At the same time, the negative subframe gradation data are applied to the reflecting electrode PE. The holding period of the second signal holding circuit DM21 for the negative subframe gradation data is one subframe period until the next positive trigger pulse TRIG of the "H" level and the negative trigger pulse TRIGB of the "L" level are supplied.

[0227] Further, the switch SW13 can also include a PMOS transistor. In this case, it can be considered that only the polarity opposite to the above-described explanation is necessary, and thus the illustration and explanation are omitted.

[0228] In addition, the switch SW13 can also be a transmission gate including a PMOS transistor and an NMOS transistor.

[0229] In addition, the switch SW21 can also be a PMOS transistor or an NMOS transistor.

[0230] (SUMMARY)

[0231] The pixel Pix3 has the same effects as the pixels Pixl and Pix2 of the third and fourth embodiments.

[0232] Further, the pixel Pix3 has the effect of being able to be miniaturized.

[0233] (Sixth Embodiment)

[0234] Figure 14 FIG. 6 is a diagram showing a circuit structure of a pixel of a reflective liquid crystal display device according to the sixth embodiment.

[0235] Among the constituent elements of the pixel Pix4 of the reflective liquid crystal display device according to the sixth embodiment, the same reference symbols are attached to the same constituent elements as the pixels Pix1 to Pix3 according to the third to fifth embodiments, and the description is omitted.

[0236] The pixel Pix4 is provided at the intersection of an arbitrary one of the column data lines d and an arbitrary one pair of the row scan lines g and the inverted row scan line gb.

[0237] The pixel Pix4 includes the first memory 131 and the second memory 132 and the liquid crystal display element LC. The first memory 131 includes the switch SW31 and the first signal holding circuit DM31. The second memory 132 includes the switch SW32 and the second signal holding circuit SM32.

[0238] In the pixel Pix4, the first memory 131 includes a DRAM, and the second memory 132 includes an SRAM.

[0239] The switch SW31 corresponds to an example of the "first switch circuit" of the present disclosure. The first signal holding circuit DM31 corresponds to an example of the "first signal holding circuit" of the present disclosure. The first memory 131 corresponds to an example of the "first dynamic random access memory" of the present disclosure. The switch SW32 corresponds to an example of the "second switch circuit" of the present disclosure. The second signal holding circuit SM32 corresponds to an example of the "second signal holding circuit" of the present disclosure. The second memory 132 corresponds to an example of the "first static random access memory" of the present disclosure.

[0240] The switch SW31 is a well-known transmission gate including an NMOS transistor Tr31 and a PMOS transistor Tr32 connected between the drains thereof and between the sources thereof, respectively. The gate of the NMOS transistor Tr31 is connected to the row scan line g, and the gate of the PMOS transistor Tr32 is connected to the inverted row scan line gb.

[0241] Further, one terminal of the switch SW31 is connected to the column data line d, and the other terminal is connected to the first signal holding circuit DM31. Therefore, the switch SW31 becomes an on state in the case where the forward rotation line scanning pulse is an "H" level (in this case, the reverse rotation line scanning pulse is an "L" level), and the gradation data of the column data line d is read out and transmitted to the first signal holding circuit DM31. Further, the switch SW31 becomes an off state in the case where the forward rotation line scanning pulse is an "L" level (in this case, the reverse rotation line scanning pulse is an "H" level), and the reading out of the gradation data of the column data line d is not performed.

[0242] The switch SW31 is a well-known transmission gate including an NMOS transistor Tr31 and a PMOS transistor Tr32, and thus can make the voltage in the range from the reference voltage GND to the power supply voltage VDD on or off. That is, in the case where the signal applied to the gates of the NMOS transistor Tr31 and the PMOS transistor Tr32 is a voltage on the reference voltage GND side ("L" level), the PMOS transistor Tr32 cannot be made on. Instead, the NMOS transistor Tr31 can be made on with low resistance. On the other hand, in the case where the signal applied to the gates of the NMOS transistor Tr31 and the PMOS transistor Tr32 is a voltage on the power supply voltage VDD side ("H" level), the NMOS transistor Tr31 cannot be made on. Instead, the PMOS transistor Tr32 can be made on with low resistance. Therefore, by performing on / off control of the transmission gate constituting the switch SW31 using the forward rotation line scanning pulse and the reverse rotation line scanning pulse, the voltage in the range from the reference voltage GND to the power supply voltage VDD can be switched with low resistance and high resistance.

[0243] The first signal holding circuit DM31 includes a capacitor C2. Here, a case where the gradation data of the column data line d is different from the gradation data of the first signal holding circuit DM31 is considered. In the case where the switch SW31 becomes an on state and the gradation data of the column data line d is transmitted to the first signal holding circuit DM31, it is necessary to rewrite the gradation data of the first signal holding circuit DM31 with the gradation data of the column data line d.

[0244] In the case where the gradation data of the capacitor C2 constituting the first signal holding circuit DM31 is rewritten, the gradation data is changed by charging or discharging. In the case where the gradation data of the column data line d is transmitted to the capacitor C2, the gradation data is written by charge transmission between the data line capacitance of the column data line d and the capacitor C2. Generally, the capacitance ratio of the data line capacitance of the column data line d to the capacitor C2 is as large as about 1000: 1. Therefore, the pixel Pix4 can reliably rewrite the gradation data of the capacitor C2.

[0245] The switch SW32 is a well-known transmission gate including an NMOS transistor Tr33 and a PMOS transistor Tr34 connected between the drains of each other and connected between the sources of each other. The gate of the NMOS transistor Tr33 is connected to the trigger line trig, and the gate of the PMOS transistor Tr34 is connected to the inverted trigger line trigb.

[0246] In addition, one terminal of the switch SW32 is connected to the first signal holding circuit DM31, and the other terminal is connected to the second signal holding circuit SM32. Therefore, the switch SW32 becomes an on state in the case where the forward trigger pulse TRIG is an "H" level (in this case, the inverted trigger pulse TRIGB is an "L" level), and the gradation data of the first signal holding circuit DM31 is read out and transferred to the second signal holding circuit SM32. Further, the switch SW32 becomes an off state in the case where the forward trigger pulse TRIG is an "L" level (in this case, the inverted trigger pulse TRIGB is an "H" level), and the reading out of the gradation data of the first signal holding circuit DM31 is not performed.

[0247] The second signal holding circuit SM32 is a self-holding type memory including two inverters INV33 and INV34 whose output terminal of one is connected to the input terminal of the other. The input terminal of the inverter INV33 is connected to the output terminal of the inverter INV34 and the reflection electrode PE. The input terminal of the inverter INV34 is connected to the output terminal of the inverter INV33 and the switch SW32.

[0248] The inverters INV33 and INV34 each exemplify the structure of a CMOS inverter (refer to Figure 7 ).

[0249] The data writing to the second signal holding circuit SM32 is performed via one switch SW32 as described above. In this case, the transistor in the inverter INV34 on the input side when viewed from the switch SW32 is compared with the transistor in the inverter INV33 on the output side when viewed from the switch SW32, and the transistor using a large driving force is used. Further, the transistor constituting the switch SW32 uses a transistor having a larger driving force than the transistor constituting the inverter INV33. Thereby, the second signal holding circuit SM32 easily inputs data from the capacitor C2, and it is difficult to input data from the liquid crystal display element LC.

[0250] When the switch SW32 becomes the on state, the electric charge accumulated in the capacitor C2 drives the input gate of the inverter INV34, and overwrites the gradation data of the second signal holding circuit SM32. Further, when the switch SW32 becomes the on state, the output of the inverter INV33 can affect the capacitor C2. However, the capacitance on the input side of the inverter INV33 is only the gate capacitance of the inverter INV33 and the liquid crystal capacitance of the liquid crystal display element LC, and is significantly less than the gate capacitance of the input of the inverter INV34 and the capacitor C2. In addition, the driving force of the inverter INV34 is set to be larger than that of the inverter INV33. Therefore, the capacitor C2 prioritizes the driving of the inverter INV34 over the output of the inverter INV33, and the gradation data of the capacitor C2 is not overwritten by the gradation data of the second signal holding circuit SM32.

[0251] In addition, the gradation data of the capacitor C2 is the transfer of electric charge from the column data line d. In addition, there is an influence of gate feedthrough and the like generated at the timing when the NMOS transistor and the PMOS transistor constituting the switch SW31 are turned off. Therefore, the capacitor C2 is determined in potential as the voltage that shifts in the direction in which the dynamic range of the reference voltage GND and the power supply voltage VDD becomes less. However, the voltage finally applied to the reflective electrode PE is shaped by the second signal holding circuit SM32, and a voltage that applies the correct reference voltage GND and power supply voltage VDD. Therefore, the pixel Pix4 can expand the dynamic range.

[0252] In addition, if light is irradiated to the diffusion electrode portion of the transistor constituting the switches SW31 and SW32 connected to the capacitor C2, a leakage current is generated, and the electric charge held in the capacitor C2 is reduced and a potential variation can occur.

[0253] However, the voltage held in the capacitor C2 is used to drive the second signal holding circuit SM32. Therefore, even if the voltage held in the capacitor C2 slightly varies, as long as the second signal holding circuit SM32 does not vary beyond the threshold value at which the gradation data can be held at the "L" level or the "H" level, it does not affect the voltage of the reflective electrode PE. At this time, the voltage applied to the reflective electrode PE of the liquid crystal display LCM is supplied by the second signal holding circuit SM32. In the case where the voltage of the reflective electrode PE is the "H" level, the PMOS transistor in the inverter INV34 constituting the second signal holding circuit SM32 is turned on, and the power supply voltage VDD is applied to the reflective electrode PE. In the case where the voltage of the reflective electrode PE is the "L" level, the NMOS transistor in the inverter INV34 constituting the second signal holding circuit SM32 is turned on, and the reference voltage GND is applied. Therefore, the voltage of the reflective electrode PE is not affected by the leakage current caused by light, and the reflective electrode PE can apply a stable voltage to the liquid crystal LCM.

[0254] Further, as explained above, even if the voltage of the capacitor C2 is slightly varied due to charge transfer, gate feedthrough, light leakage, etc., there is no problem as long as the gradation data of the second signal holding circuit SM32 can be rewritten.

[0255] Therefore, the switch SW31 constituting the first memory 131 and the switch SW32 constituting the second memory 132 can not be complementary switches using NMOS transistors and PMOS transistors.

[0256] For example, a case where the switch SW31 and the switch SW32 are constituted only by NMOS transistors is studied. In this case, the switch SW31 and the switch SW32 can pass only the voltage of the "H" level of the input signal to VDD-Vth including the substrate effect. That is, in the case where the switch SW31 is constituted only by NMOS transistors, even if a voltage of 3.3 V is supplied to the column data line d, the voltage a of the connection point of the switch SW31 and the capacitor C2 is VDD-Vth or less, for example, 2.5 V. Therefore, the voltage of 2.5 V is accumulated in the capacitor C2. Next, the switch SW32 is turned on to rewrite the gradation data of the second signal holding circuit SM32. In the case where the switch SW32 is also constituted only by NMOS transistors, the voltage b of the connection point of the switch SW32 and the second signal holding circuit SM32 is also 2.5 V like the voltage a. However, if the voltage b is 1.65 V or more of VDD / 2, the "H" level can be input to the second signal holding circuit SM32 (the "L" level is applied to the reflection electrode PE of the output). Therefore, the second signal holding circuit SM32 can write either one of the gradation data of the "H" level and the gradation data of the "L" level.

[0257] In the case where the switch SW31 and the switch SW32 are constituted only by PMOS transistors, the range of the voltage not input is opposite to the above.

[0258] In this way, the switch SW31 and the switch SW32 can not be complementary switches but switches using one MOS transistor. In this case, the number of transistors constituting one pixel is reduced, and therefore the pixel Pix4 functions to enable further miniaturization.

[0259] Further, the voltage logically inverted from the voltage of the capacitor C2 is applied to the reflection electrode PE. Therefore, the gradation data written to the pixel Pix4 needs to input inverted data of the data (voltage) intended to be applied to the reflection electrode PE.

[0260] The pixel Pix4 has an effect of enabling miniaturization of the pixel. The first reason is as follows. The inverters INV33 and INV34 each include two transistors. Therefore, the pixel Pix4 includes a total of eight transistors and one capacitor, and can include a smaller number of elements than the pixel Pixl (a total of twelve transistors) and the pixel Pix2 (a total of ten transistors). Further, in addition to the first reason, the second reason is that, as described below, the first signal holding circuit DM31, the second signal holding circuit SM32, and the reflective electrode PE can be effectively arranged in the height direction of the elements.

[0261] Figure 15 FIG. 6 is a diagram showing a cross-sectional structure of a pixel of a reflective liquid crystal display device according to the sixth embodiment.

[0262] The capacitor C2 can use an MIM capacitor, a Diffusion capacitor, a PIP capacitor, or the like. Figure 15 FIG. 7 is a diagram showing a cross-sectional structure of a reflective liquid crystal display device in a case where the capacitor C2 is constituted by an MIM.

[0263] In the Figure 15 In the Figure 15 In the

[0264] Further, over the PMOS transistor Tr2 and PTrll and the NMOS transistor NTrll and Trl, the first metal 206, the second metal 208, the third metal 210, the electrode 212, the fourth metal 214, and the fifth metal 216 are stacked with the interlayer insulating film 205 interposed therebetween. The fifth metal 216 constitutes a reflection electrode PE formed per pixel. The NMOS transistor constituting an inverter INV34 not shown in the drawing and each diffusion layer constituting a drain of the PMOS transistor, the gate electrode of the NMOS transistor NTrll, and the gate electrode of the PMOS transistor PTrll are electrically connected to the first metal 206 via a contact not shown in the drawing, respectively. Further, the above diffusion layers and the above gate electrodes are electrically connected to the second metal 208, the third metal 210, the fourth metal 214, and the fifth metal 216 via vias 219a, 219b, 219c, and 219e. That is, the NMOS transistor constituting the inverter INV34 not shown in the drawing and the drains of the PMOS transistor are electrically connected to the reflection electrode PE.

[0265] Further, over the reflection electrode PE (fifth metal 216), a passivation film (PSV) 217 is formed as a protective film, and is disposed in opposition to the common electrode CE as a transparent electrode. The liquid crystal LCM is filled between these reflection electrode PE and the common electrode CE, and is sealed to constitute a liquid crystal display element LC.

[0266] Here, the electrode 212 is formed over the third metal 210 with the interlayer insulating film 205 interposed therebetween. The electrode 212, the third metal 210, and the interlayer insulating film 205 between the electrode 212 and the third metal 210 constitute a capacitor C2.

[0267] When the capacitor C2 is constituted by MIM, the second signal holding circuit SM32, the switch SW31, and the switch SW32 can include the 1, 2 layer wiring of the transistor and the first metal 206 and the second metal 208 on the silicon substrate 200. In addition, the first signal holding circuit DM31 can include the MIM wiring using the third metal 210 on the upper portion of the transistor.

[0268] The electrode 212 is electrically connected to the fourth metal 214 via a via 219d. Further, the fourth metal 214 is electrically connected to the switches SW31 and SW32 at a position not shown in the drawing.

[0269] Light from a light source not shown in the drawing is transmitted through the common electrode CE and the liquid crystal LCM, is incident on the reflection electrode PE (fifth metal 216), is reflected, is retroacted on the original incident path, and is emitted through the common electrode CE.

[0270] As Figure 15As shown, the pixel Pix4 can effectively arrange the first signal holding circuit DM31, the second signal holding circuit SM32, and the reflective electrode PE in the height direction by assigning the fifth metal 216 to the reflective electrode PE. Therefore, the pixel Pix4 can achieve pixel miniaturization. Thus, the pixel Pix4 can be configured by a transistor of a power supply voltage of 3.3 V to be a pixel of a pitch of 3 μm or less. The pixel of the pitch of 3 μm can achieve a liquid crystal display panel of a diagonal length of 0.55 inches, 4000 pixels in the horizontal direction, and 2000 pixels in the vertical direction.

[0271] The pixel Pix4 performs the same operation as that described with reference to the timing chart in the third embodiment. Figure 9

[0272] First, the plurality of pixels Pix4 of one row selected by the forward and reverse row scanning pulses output from the timing generator 62 are switched by the forward and reverse row scanning pulses to be in the on state. At this time, the forward subframe gradation data output to the column data line d is sampled by the switch SW31 and written to the first signal holding circuit DM31. Hereinafter, similarly, the first signal holding circuit DM31 of all the pixels Pix4 configuring the image display portion 61 is written with the forward subframe gradation data. At the timing after this writing operation, the forward trigger pulse TRIG of the "H" level and the reverse trigger pulse TRIGB of the "L" level are simultaneously supplied to all the pixels Pix4 configuring the image display portion 61.

[0273] Thus, the switch SW32 of all the pixels Pix4 is in the on state. Therefore, the forward subframe gradation data stored in the first signal holding circuit DM31 is collectively transferred via the switch SW32 and held in the second signal holding circuit SM32. At the same time, the forward subframe gradation data is applied to the reflective electrode PE. The holding period of the second signal holding circuit SM32 of the forward subframe gradation data is one subframe period until the next forward trigger pulse TRIG of the "H" level and the reverse trigger pulse TRIGB of the "L" level are input.

[0274] Next, each of the pixels Pix4 in the image display portion 61 is selected by the forward and reverse row scanning pulses in units of rows as described above. Then, the reverse subframe gradation data having the opposite logic value from the immediately preceding forward subframe gradation data is written to the first signal holding circuit DM31. When the writing of the reverse subframe gradation data to the first signal holding circuit DM31 of all the pixels Pix4 in the image display portion 61 is completed, the forward trigger pulse TRIG of the "H" level and the reverse trigger pulse TRIGB of the "L" level are simultaneously supplied to all the pixels Pix4.

[0275] ​Thus, the switch SW32 of all the pixels Pix4 becomes the on state. Therefore, the inversion subframe gradation data stored in the first signal holding circuit DM31 is transmitted all at once and held in the second signal holding circuit SM32 via the switch SW32. At the same time, the inversion subframe gradation data is applied to the reflective electrode PE. The holding period of the second signal holding circuit SM32 of the inversion subframe gradation data is one subframe period until the next "H" level positive rotation trigger pulse TRIG and the "L" level inversion trigger pulse TRIGB are supplied.

[0276] (SUMMARY)

[0277] The pixel Pix4 has the same effect as the pixels Pix1 to Pix3 of the third to sixth embodiments.

[0278] Further, the pixel Pix4 has the effect of being able to be miniaturized.

[0279] (SEVENTH EMBODIMENT)

[0280] Figure 16 FIG. 7 is a view showing a circuit structure of a pixel of a reflective liquid crystal display device of a seventh embodiment.

[0281] Among the constituent elements of the pixel Pix5 of the reflective liquid crystal display device of the seventh embodiment, the same constituent elements as the pixels Pix1 to Pix4 of the third to sixth embodiments are denoted by the same reference numerals, and the description thereof is omitted.

[0282] The pixel Pix5 is provided at an intersection of an arbitrary one of the column data lines d and an arbitrary one of the row scanning lines g.

[0283] The pixel Pix5 includes a first memory 141 and a second memory 142 and a liquid crystal display element LC. The first memory 141 includes a switch SW41 and a first signal holding circuit DM41. The second memory 142 includes a switch SW42 and a second signal holding circuit DM42.

[0284] In the pixel Pix5, the first memory 141 and the second memory 142 include DRAMs.

[0285] The switch SW41 corresponds to an example of the "first switching circuit" of the present disclosure. The first signal holding circuit DM41 corresponds to an example of the "first signal holding circuit" of the present disclosure. The first memory 141 corresponds to an example of the "first dynamic random access memory" of the present disclosure. The switch SW42 corresponds to an example of the "second switching circuit" of the present disclosure. The second signal holding circuit DM42 corresponds to an example of the "second signal holding circuit" of the present disclosure. The second memory 142 corresponds to an example of the "second dynamic random access memory" of the present disclosure.

[0286] The switch SW41 includes an NMOS transistor whose gate is connected to the row scanning line g, whose drain is connected to the column data line d, and whose source is connected to the first signal holding circuit DM11.

[0287] The first signal holding circuit DM41 includes a capacitor C3. Here, a case where the gradation data of the column data line d is different from the gradation data of the first signal holding circuit DM41 is studied. In a case where the switch SW41 is in the on state and the gradation data of the column data line d is transferred to the first signal holding circuit DM41, the gradation data of the first signal holding circuit DM41 needs to be rewritten with the gradation data of the column data line d.

[0288] In a case where the gradation data of the capacitor C3 constituting the first signal holding circuit DM41 is rewritten, the gradation data is changed by charging or discharging. In a case where the gradation data of the column data line d is transferred to the capacitor C3, the gradation data is written by charge transfer between the data line capacitance of the column data line d and the capacitor C3. Normally, the capacitance ratio of the data line capacitance of the column data line d to the capacitor C3 is as large as about 1000: 1. Therefore, the pixel Pix5 can reliably rewrite the gradation data of the capacitor C3.

[0289] The switch SW42 includes an NMOS transistor whose gate is connected to the trigger line trig, whose drain is connected to the first signal holding circuit DM41, whose source is connected to the second signal holding circuit DM42, and whose back gate is connected to the back gate electrode PE.

[0290] The second signal holding circuit DM42 includes a capacitor C4. Here, a case where the gradation data of the first signal holding circuit DM41 is different from the gradation data of the second signal holding circuit DM42 is studied. In a case where the switch SW42 is in the on state and the capacitor C3 is connected to the capacitor C4, the gradation data of the second signal holding circuit DM42 needs to be rewritten with the gradation data of the first signal holding circuit DM41.

[0291] In a case where the charge level of the capacitor C3 (the gradation data of the first signal holding circuit DM41) is different from the charge level of the capacitor C4 (the gradation data of the second signal holding circuit DM42), neutralization of charges occurs. Therefore, in the present application, the capacitor C3 is made larger than the capacitor C4. That is, C3 > C4 is provided. For example, in a case where the gradation data of "H" level is held in the capacitor C3 and the gradation data of "L" level is held in the capacitor C4, neutralization of charges occurs. However, by providing C3 > C4, even if neutralization of charges occurs, the voltage after the neutralization can be made higher than the threshold voltage. That is, the gradation data of "H" level can be written to the capacitor C4. Thus, the pixel Pix5 can reliably rewrite the gradation data of the capacitor C4 with the gradation data of the capacitor C3.

[0292] Alternatively, switches SW41 and SW42 may also include PMOS transistors. In this case, it can be assumed that the polarity is opposite to that described above, therefore, the illustrations and descriptions are omitted.

[0293] Alternatively, switches SW41 and SW42 can also be transmission gates that include PMOS transistors and NMOS transistors.

[0294] Pixel Pix5 offers the advantage of miniaturization. The first reason is as follows: Pixel Pix5 includes a total of two transistors and two capacitors, C3 and C4. That is, pixel Pix5 can include fewer components than pixel Pix1 (12 transistors), pixel Pix2 (10 transistors), pixel Pix3 (7 transistors and one capacitor), and pixel Pix4 (8 transistors and one capacitor). The second reason is that, as explained below, the first signal holding circuit DM41, the second signal holding circuit DM42, and the reflective electrode PE can be effectively arranged in the height direction of the components.

[0295] Figure 17 This is a diagram showing the cross-sectional structure of the pixels of the reflective liquid crystal display device according to the seventh embodiment.

[0296] Capacitors C3 and C4 can be MIM capacitors, Diffusion capacitors, PIP capacitors, etc. Figure 17 The cross-sectional structure of a reflective liquid crystal display device in which capacitors C3 and C4 are constructed using MIM is shown.

[0297] exist Figure 17 In this configuration, an NMOS transistor with switch SW41 is formed on a P-well 202 formed on a silicon substrate 200. The drain of the NMOS transistor with switch SW41 is electrically connected to the column data line d (not shown in the figure) via a contact 218a and a first metal 206.

[0298] Additionally, an NMOS transistor for switch SW42 is formed on the P-well 203 formed on the silicon substrate 200. The drain of the NMOS transistor for switch SW42 is electrically connected to the source of the NMOS transistor for switch SW41 via contact 218b and first metal 206.

[0299] Furthermore, above the NMOS transistors of switch SW41 and switch SW42, an interlayer insulating film 205 is placed between the metals, and a first metal 206, a second metal 208, a third metal 210, an electrode 212, a fourth metal 214, and a fifth metal 216 are stacked. The fifth metal 216 constitutes a reflective electrode PE formed for each pixel.

[0300] Further, on the reflective electrode PE (fifth metal 216), a passivation film (PSV) 217 is formed as a protective film, and is disposed in opposition to the common electrode CE as a transparent electrode. The liquid crystal LCM is filled between these reflective electrode PE and common electrode CE, and is sealed to constitute a liquid crystal display element LC.

[0301] Here, on the third metal 210, electrodes 212a and 212b are formed through the interlayer insulating film 205. The electrode 212a, the third metal 210, and the interlayer insulating film 205 between the electrode 212a and the third metal 210 constitute a capacitor C3. The electrode 212b, the third metal 210, and the interlayer insulating film 205 between the electrode 212b and the third metal 210 constitute a capacitor C4.

[0302] Here, the electrode 212a is larger than the electrode 212b. Thus, the capacitor C3 becomes larger than the capacitor C4. That is, C3 > C4.

[0303] When the capacitors C3 and C4 are constituted by MIM, the switches SW41 and SW42 can include the transistor and the 1, 2 layer wiring of the first metal 206 and the second metal 208 on the silicon substrate 200. Further, the first signal holding circuit DM41 and the second signal holding circuit DM42 can include the MIM wiring using the third metal 210 on the transistor upper portion.

[0304] The source of the NMOS transistor of the switch SW41 is electrically connected to the electrode 212a via the contact 218c, the vias 219d, 219e, 219f, and 219g. The third metal 210 in opposition to the electrode 212a is electrically connected to a reference potential (ground potential) via the via 219h.

[0305] The source of the NMOS transistor of the switch SW42 is electrically connected to the electrode 212b via the contact 218d, the vias 219j, 219k, 219l, and 219m. The third metal 210 in opposition to the electrode 212b is electrically connected to a reference potential (ground potential) via the via 219n. The electrode 212b is electrically connected to the reflective electrode PE via the vias 219m and 219o.

[0306] Light from a light source not shown in the figure is transmitted through the common electrode CE and the liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 216) and is reflected, is retroacted on the original incident path, and is emitted through the common electrode CE.

[0307] As Figure 17As shown, the pixel Pix5 is able to effectively arrange the first signal holding circuit DM41 and the second signal holding circuit DM42 and the reflective electrode PE in the height direction by assigning the fifth metal 216 to the reflective electrode PE. Therefore, the pixel Pix5 is able to realize pixel miniaturization. Thus, the pixel Pix5 is able to constitute a pixel of a pitch of 3 μm or less by a transistor of a power supply voltage of 3.3 V, for example. The pixel of the 3 μm pitch is able to realize a liquid crystal display panel of a diagonal length of 0.55 inches, 4000 pixels in the horizontal direction, and 2000 pixels in the vertical direction.

[0308] The pixel Pix5 performs the same operation as that described with reference to the timing chart in the third embodiment. Figure 9

[0309] First, the plurality of pixels Pix5 of one line selected by the forward rotation line scanning pulse output from the timing generator 62 are brought into the on state by the forward rotation line scanning pulse. At this time, the forward rotation subframe gradation data output to the column data line d is sampled by the switch SW41 and written to the first signal holding circuit DM41. Hereinafter, the same is performed for the first signal holding circuit DM41 of all the pixels Pix5 constituting the image display portion 61 with respect to the writing of the forward rotation subframe gradation data. At the timing after the end of this writing operation, the forward rotation trigger pulse TRIG of the "H" level is simultaneously supplied to all the pixels Pix5 constituting the image display portion 61.

[0310] Thus, the switch SW42 of all the pixels Pix5 is brought into the on state. Therefore, the forward rotation subframe gradation data stored in the first signal holding circuit DM41 is transmitted and held in the second signal holding circuit DM42 via the switch SW42. At the same time, the forward rotation subframe gradation data is applied to the reflective electrode PE. The holding period of the forward rotation subframe gradation data by the second signal holding circuit DM42 is one subframe period until the next forward rotation trigger pulse TRIG of the "H" level is input.

[0311] Next, the pixels Pix5 in the image display portion 61 are selected by the forward rotation line scanning pulse in units of lines as described above, and the reverse rotation subframe gradation data of the opposite logic value to the immediately preceding forward rotation subframe gradation data is written to the first signal holding circuit DM41 for each pixel Pix5. When the writing of the reverse rotation subframe gradation data to the first signal holding circuit DM41 of all the pixels Pix5 constituting the image display portion 61 ends, the forward rotation trigger pulse TRIG of the "H" level is simultaneously supplied to all the pixels Pix5 constituting the image display portion 61.

[0312] ​Thus, the switch SW42 of all the pixels Pix5 becomes the on state. Therefore, the inversion subframe gradation data stored in the first signal holding circuit DM41 is transmitted all at once and held in the second signal holding circuit DM42 via the switch SW42. At the same time, the inversion subframe gradation data is applied to the reflection electrode PE. The holding period of the second signal holding circuit DM42 of the inversion subframe gradation data is until the next "H" level positive rotation trigger pulse TRIG is supplied, which is one subframe period.

[0313] (SUMMARY)

[0314] The pixel Pix5 has the same effect as the pixels Pixl to Pix4 of the third to sixth embodiments.

[0315] Further, the pixel Pix5 has the effect of being able to be miniaturized. The pixel Pix5 is able to generate the neutralization of the above-described charges, and although the noise resistance is low compared to the SRAM, compared to the pixels Pixl to Pix4, further miniaturization can be achieved. Therefore, which one of the pixels Pixl to Pix5 to employ is determined in accordance with the specifications required of the reflection type liquid crystal display device 13 (for example, miniaturization priority, noise resistance priority, and the like).

[0316] (POSTSCRIPT)

[0317] Figure 3 The pixels of the portion 13a of the reflection type liquid crystal display device 13 shown, to which the diffused plurality of wavelength channels are incident, are inverted during each subframe. However, the pixels of the portion (frame portion) 13b to which the diffused plurality of wavelength channels are not incident do not need to be inverted per subframe. From the viewpoint of power consumption, the number of inversions can be reduced.

[0318] Therefore, the common electrode CE can also be divided into the portion 13a and the portion 13b, and driven separately, and the number of inversions can be reduced in the portion 13b. In this case, inversion is performed per subframe in the portion 13a, but inversion for a prescribed number of frames (in other words, inversion per prescribed number of frames) can be performed in the portion 13b.

[0319] In this case, in the case of the structure in which the pixels of the portion 13b are the pixels Pix3 (refer to Figure 12 ), when there is leakage of the charges of the capacitor Cl, the potential of the reflection electrode PE drops. Therefore, it is preferable to turn on the positive rotation trigger pulse TRIG and the inversion trigger pulse TRIGB every certain time, and perform the re-writing operation to the capacitor Cl. Alternatively, the prescribed number of frames to inversion can be reduced compared to other pixel circuit structures.

[0320] Further, the writing of the partial 13b to the first memory is preferably performed as soon as possible before the inversion. This is because, when the contents of the first memory 111 and the second memory 121 are inverted, a leakage current is generated by the switch SW21, and the power consumption increases.

[0321] Further, in the structure of the pixel Pixl (refer to Figure 6 ), since the writing to the first memory 91 can be performed earliest, the contents of the first memory 91 are preferably rewritten immediately before.

[0322] The technical scope of the present embodiment is not limited to the above-described embodiments, and appropriate modifications can be made within the scope of the gist of the present embodiment.

[0323] Industrial Applicability

[0324] The optical node device of the present embodiment can be used, for example, for an optical network.

[0325] Explanation of Symbols

[0326] 10 WSS array

[0327] 11 Input / output section

[0328] 12 Optical system

[0329] 13 Reflective liquid crystal display device

[0330] 16 Collimating lens

[0331] 21, 22, 23 Lenses

[0332] 24 Dispersion element

[0333] 61 Image display section

[0334] 62 Timing generator

[0335] 63 Vertical shift register

[0336] 64 Data latch circuit

[0337] 65 Horizontal driver

[0338] 65a Horizontal shift register

[0339] 65b Latch circuit

[0340] 65c Level shifter / pixel driver

[0341] 81, 91, 111, 131, 141 First memory

[0342] 81a, 82a, SW11a, SW11b, SW12a, SW12b, SW13, SW14, SW21, SW31, SW32, SW41, SW42 switches

[0343] 81b, SM11, SM13, DM31, DM41 first signal holding circuit

[0344] 82, 92, 112, 121, 132, 142 second memory

[0345] 82b, SM12, SM14, DM21, SM32, DM42 second signal holding circuit

[0346] INV1, INV2, INV3, INV4, INV11, INV12, INV13, INV14, INV33, INV34 inverters

[0347] Pix, Pix1, Pix2, Pix3, Pix4, Pix5 pixels

[0348] PT1, PT2

[0349] PMOS transistor

[0350] NT1, NT2 NMOS transistor

[0351] C1, C2, C3, C4 capacitors

[0352] LC liquid crystal display element

[0353] LCM liquid crystal

[0354] PE reflective electrode

[0355] CE common electrode

Claims

1. An optical node device comprising: an input-output section having an input port for inputting incident light and an output port for outputting emergent light corresponding to each wavelength included in the incident light; a wavelength disperser for dispersing light of each wavelength included in the incident light in space according to each wavelength and for outputting the emergent light toward the input-output section side; an optical coupler for condensing light of each wavelength dispersed by the wavelength disperser on a two-dimensional plane by each wavelength and for outputting the reflected light of each wavelength toward the wavelength disperser side; a spatial light modulator disposed at a position of the two-dimensional plane, having a plurality of pixels, and reflecting light of each wavelength condensed by the optical coupler by each wavelength toward a direction determined by routing by representing a gradation by the plurality of pixels; a spatial light modulator drive section for driving the plurality of pixels of the spatial light modulator; and a common electrode divided into a first common electrode of a first region where light is incident and a second common electrode of a second region where light is not incident, a gradation is formed by inputting forward gradation data to each of the plurality of pixels during one of a plurality of subframe periods obtained by dividing one frame period and inputting reverse gradation data during another of the plurality of subframe periods by the spatial light modulator drive section, each of the plurality of pixels includes: a first switch circuit for sampling the forward gradation data or the reverse gradation data from a data line; a first signal holding circuit for holding the forward gradation data or the reverse gradation data sampled by the first switch circuit; a second switch circuit for sampling the forward gradation data or the reverse gradation data held in the first signal holding circuit at a common timing for all of the plurality of pixels; and a second signal holding circuit for holding the forward gradation data or the reverse gradation data sampled by the second switch circuit for one subframe period and applying the same to a reflection electrode of a liquid crystal display element, the spatial light modulator drive section in the first region, by inverting a voltage of the first common electrode of the liquid crystal display element by each subframe at the timing, an alternating voltage of positive and negative polarities is applied to liquid crystal of the liquid crystal display element and a voltage having an amplitude different from an amplitude between the forward gradation data and the reverse gradation data is supplied to the first common electrode, in the second region, a voltage of the reflection electrode and the second common electrode is inverted for every prescribed plurality of subframes.

2. The optical node device according to claim 1, wherein the first switch circuit and the first signal holding circuit constitute a first static random access memory, the second switch circuit and the second signal holding circuit constitute a second static random access memory, a driving force of a transistor constituting the first signal holding circuit is greater than a driving force of a transistor constituting the second signal holding circuit.

3. The optical node device according to claim 1, wherein the first switch circuit and the first signal holding circuit constitute a first static random access memory, the second switch circuit and the second signal holding circuit constitute a second static random access memory, the first switch circuit and the second switch circuit each include one transistor, the first signal holding circuit includes a first inverter and a second inverter whose output terminal and input terminal are connected, the second signal holding circuit includes a third inverter and a fourth inverter whose output terminal and input terminal are connected, a driving force of the transistor constituting the first inverter which is an input side when viewed from the first switch circuit side is greater than a driving force of the transistor constituting the second inverter which is an output side when viewed from the first switch circuit side, a driving force of the transistor constituting the third inverter which is an input side when viewed from the second switch circuit side is greater than a driving force of the transistor constituting the fourth inverter which is an output side when viewed from the second switch circuit.

4. The optical node device according to claim 3, wherein a driving force of the transistor constituting the first switch circuit is greater than a driving force of the transistor constituting the second inverter, and a driving force of the transistor constituting the second switch circuit is greater than a driving force of the transistor constituting the fourth inverter.

5. The optical node device according to claim 1, wherein the first switch circuit and the first signal holding circuit constitute a first static random access memory, the second switch circuit and the second signal holding circuit constitute a first dynamic random access memory, the second signal holding circuit includes a capacitor.

6. The optical node device according to claim 5, wherein the second switch circuit is a complementary switch circuit including a P-channel transistor and an N-channel transistor.

7. The optical node device according to claim 5, wherein the first signal holding circuit includes a first inverter and a second inverter whose output terminal and input terminal are connected, a driving force of the transistor constituting the first inverter which is an input side when viewed from the first switch circuit side is greater than a driving force of the transistor constituting the second inverter which is an output side when viewed from the first switch circuit.

8. The optical node device according to claim 7, wherein the first switch circuit includes one transistor, a driving force of the transistor constituting the first switch circuit is greater than a driving force of the transistor constituting the second inverter.

9. The optical node device according to claim 1, wherein the first switch circuit and the first signal holding circuit constitute a first dynamic random access memory, the second switch circuit and the second signal holding circuit constitute a first static random access memory, the first signal holding circuit includes a capacitor.

10. The optical node device according to claim 9, wherein the first switch circuit is a complementary switch circuit including a P-channel transistor and an N-channel transistor.

11. The optical node device according to claim 9, wherein the first switch circuit includes one transistor.

12. The optical node device according to claim 9, wherein The second signal holding circuit includes a first inverter and a second inverter whose output terminal and input terminal are connected, The driving force of the transistor constituting the first inverter, which is the input side when viewed from the second switching circuit side, is greater than the driving force of the transistor constituting the second inverter, which is the output side when viewed from the second switching circuit side.

13. The optical node apparatus according to claim 9, wherein The second switching circuit is a complementary switching circuit including a P-channel transistor and an N-channel transistor.

14. The optical node apparatus according to claim 9, wherein The second switching circuit includes one transistor.

15. The optical node apparatus according to claim 1, wherein The first switching circuit and the first signal holding circuit constitute a first dynamic random access memory, The second switching circuit and the second signal holding circuit constitute a second dynamic random access memory, The first signal holding circuit and the second signal holding circuit each include a capacitor.

16. The optical node apparatus according to claim 15, wherein The first switching circuit includes one transistor.

17. The optical node apparatus according to claim 15, wherein The first switching circuit is a complementary switching circuit including a P-channel transistor and an N-channel transistor.

18. The optical node apparatus according to claim 15, wherein The second switching circuit includes one transistor.

19. The optical node apparatus according to claim 15, wherein The second switching circuit is a complementary switching circuit including a P-channel transistor and an N-channel transistor.

20. The optical node apparatus according to claim 1, wherein The writing to the first signal holding circuit of the second region is performed immediately before the voltage reversal timing between the reflection electrode and the second common electrode.

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