Techniques for fast correction of waveforms after quantum system calibration

Abstract

Techniques to facilitate fast waveform correction after calibration of a quantum system. In one example, a system can include a processor that executes computer executable components stored in memory. The computer executable components include a calibration component and a regeneration component. The calibration component can identify parameters of a directed graph that are changed by a calibration of a quantum system that occurs after the directed graph is generated. The regeneration component can correct the directed graph based on the identified parameters to generate an updated directed graph.

Description

Technical Field

[0001] This disclosure relates to quantum computing, and more specifically to techniques for facilitating rapid waveform correction after calibration of quantum systems. Background Technology

[0002] Some quantum computers receive quantum circuits or programs in a specialized language of waves and pulses. Significant abstraction has been achieved, allowing such quantum circuits to be submitted by entities to computing services as a high-level language rather than as the specialized language of waves and pulses received by some quantum computers. The computing services can then translate the quantum circuits or programs submitted by entities in a higher-level language into a waveform and pulse schedule that the quantum computer can interpret via waveform generation. In some respects, the waveform generation process can be interpreted as analogous to an assembler implementing instructions for implementation by a classical computer. The waveform generation process is typically performed based on calibration data from the most recently calibrated quantum system that will execute the given quantum circuit. This waveform generation process usually consumes a non-negligible amount of time and computational resources before the quantum circuit can be executed or run by the quantum system.

[0003] The control parameters of a quantum system deviate from their calibration state over time, introducing noise and other error sources into the results obtained from executing a quantum circuit on the quantum system. For example, a quantum circuit may include one or more gates. Calibration can define these gates as defined pulses. During waveform generation, these defined pulses can be converted into a directed graph of pulses. The header of the directed graph of pulses can be the very end of a defined sequence of pulses, with each edge pointing in the direction of the previous pulse. Those pulses can then be arranged, and a rigorous time representation can be received when these pulses are being emitted into the quantum system and when they are about to cease emission. Any deviation from the calibration state can negatively affect those rigorous time representations, which in turn introduces noise and other error sources.

[0004] Mitigating this noise and other sources of error typically involves calibrating the quantum system to return the control parameters to a calibrated state. When calibration occurs, any waveforms previously generated based on earlier calibration data become invalid or outdated. Completely reconstructing or regenerating invalid waveforms performed on this recalibrated quantum system usually involves using the new calibration data to reshape each step of the waveform generation process to generate an updated waveform. Given that waveform generation processes typically consume a non-negligible amount of time and computational resources, correcting invalid waveforms without repeating each step of the waveform generation process reduces error and improves computational efficiency. Summary of the Invention

[0005] The following overview is presented to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, systems, apparatuses, computer-implemented methods, and / or computer program products are described to facilitate rapid waveform correction after quantum system calibration.

[0006] According to an embodiment, the system may include a processor that executes computer-executable components stored in memory. The computer-executable components include a calibration component and a regeneration component. The calibration component can identify parameters of the directed graph that have been altered by calibration of the quantum system after the directed graph is generated. The regeneration component can correct the directed graph based on the identified parameters to generate an updated directed graph.

[0007] According to another embodiment, a computer-implemented method may include: having the system identify parameters of the directed graph that have been altered by calibration of the quantum system occurring after the directed graph is generated. The computer-implemented method may further include having the system correct the directed graph based on the identified parameters to generate an updated directed graph.

[0008] According to another embodiment, a computer program product may have a computer-readable storage medium containing program instructions therein. The program instructions are executable by a processor to cause the processor to perform operations. These operations may include identifying parameters of the directed graph that have been altered by calibration of the quantum system after the directed graph is generated. The operations may further include correcting the directed graph based on the identified parameters to generate an updated directed graph.

[0009] According to another embodiment, a computer-implemented method may include having the system identify multiple parameters of the directed graph that have been altered by calibration of the quantum system occurring after the directed graph is generated. The computer-implemented method may further include having the system correct the directed graph based on the multiple parameters identified at one time to generate an updated directed graph.

[0010] According to another embodiment, a computer-implemented method may include having the system detect calibrations of a quantum system that invalidate the directed graph after its generation. The computer-implemented method may further include having the system identify parameters of the directed graph altered by the calibrations of the quantum system. The computer-implemented method may further include having the system correct the directed graph based on the identified parameters to generate an updated directed graph. Attached Figure Description

[0011] Figure 1A block diagram of an exemplary, non-limiting system that can facilitate rapid waveform correction after quantum system calibration, according to one or more embodiments described herein, is shown.

[0012] Figure 2 Exemplary, non-limiting quantum circuits suitable for implementing aspects of one or more embodiments described herein are shown.

[0013] Figure 3 Exemplary, non-limiting circuit diagrams are shown according to one or more embodiments described herein.

[0014] Figure 4 Exemplary, non-limiting pulse time diagrams according to one or more embodiments described herein are shown.

[0015] Figure 5 An exemplary, non-limiting, updated pulse-time plot is shown according to one or more embodiments described herein.

[0016] Figure 6 Another exemplary, non-limiting, updated pulse timing diagram is shown according to one or more embodiments described herein.

[0017] Figure 7 Another exemplary, non-limiting, updated pulse timing diagram is shown according to one or more embodiments described herein.

[0018] Figure 8 Another exemplary, non-limiting, updated pulse timing diagram is shown according to one or more embodiments described herein.

[0019] Figure 9 A flowchart illustrating an exemplary, non-limiting computer-implemented method for facilitating rapid waveform correction after calibration of a quantum system according to one or more embodiments described herein is shown.

[0020] Figure 10 A flowchart is shown of another exemplary, non-limiting computer implementation of a method for facilitating rapid waveform correction after quantum system calibration, according to one or more embodiments described herein.

[0021] Figure 11 A flowchart is shown of another exemplary, non-limiting computer-implemented method for facilitating rapid waveform correction after quantum system calibration, according to one or more embodiments described herein.

[0022] Figure 12 A block diagram is shown illustrating an exemplary, non-limiting operating environment that may facilitate one or more embodiments described herein. Detailed Implementation

[0023] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, no explicit or implicit information constraints are intended to be presented in the preceding background or overview or detailed description sections.

[0024] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various circumstances.

[0025] Classical computers operate on binary digits (or bits) that store or represent information as binary states to perform computation and information processing functions. In contrast, quantum computing devices operate on qubits (or quantum bits), which store or represent information as binary states and superpositions of binary states. To do this, quantum computing devices utilize quantum mechanical phenomena such as entanglement and interference.

[0026] Quantum computing uses qubits instead of classical computing bits as its basic unit. A qubit (e.g., a quantum binary digit) is a quantum mechanical simulation of that classical bit. While a classical bit can only exist in one of two fundamental states (e.g., 0 or 1), a qubit can exist in a superposition of these fundamental states (e.g., α|0>+β|1>, where α and β are complex scalars such that |α| 2 +|β| 2=1) is used, thus allowing multiple qubits to theoretically retain more information exponentially than the same number of classical bits. Therefore, quantum computers (e.g., computers that use qubits instead of just classical bits) can theoretically solve problems that might be extremely difficult for classical computers very quickly. A bit in a classical computer is simply a binary digit with a value of 0 or 1. Almost any device with two distinct states can be used to represent a classical bit: switches, valves, magnets, coins, etc. A qubit involved in the mystery of quantum mechanics can occupy a superposition of 0 and 1 states. The qubit may not have an intermediate value, such as 0.63; when the state of the qubit is measured, the result is either 0 or 1. However, during computation, the qubit can act as a mixture of states, for example: 63% 0 and 37% 1. General quantum programs require coordination between the quantum and classical parts of the computation. One way to think about general quantum programs is to identify the processes and abstractions involved in specifying a quantum algorithm, converting that algorithm into an executable form, running experiments or simulations, and analyzing those results. The concept throughout these processes is the use of intermediate representations. The intermediate representation (IR) of a computation is neither its source language description nor the target machine instructions, but something in between. A compiler can use several IRs during the translation and optimization process. The input is source code describing the quantum algorithm and one or more compile-time parameters. The output is a quantum / classical program expressed using high-level IRs. The difference between a quantum and a classical computer is that the quantum computer is probabilistic, so a measurement of the algorithm's output provides an appropriate solution within an algorithm-specific confidence interval. This computation is then repeated until a potentially deterministic solution that satisfactorily satisfies the problem can be achieved.

[0027] By using the laws of quantum mechanics to process information, quantum computers offer new ways to perform computational tasks such as molecular computing, financial risk calculation, optimization, and more.

[0028] As discussed above, the control parameters of a quantum system deviate from their calibration state over time, introducing noise and other error sources into the results obtained from executing quantum circuits on the quantum system. Mitigating this noise and other error sources typically involves calibrating the quantum system to return the control parameters to their calibration state. When calibration occurs, any waveforms previously generated based on previously calibrated data become invalid or outdated. Completely reconstructing or regenerating invalid waveforms executed on this recalibrated quantum system typically involves using the new calibration data to reshape each step of the waveform generation process to generate an updated waveform.

[0029] Embodiments of this disclosure describe techniques for modifying waveforms (or compiled quantum programs) based on new calibration data without repeating each step of the waveform generation process to generate an updated waveform. According to one or more embodiments described herein, existing waveforms can be corrected based on the new calibration data using fewer computational resources than would be involved in repeating each step of the waveform generation process to generate an updated waveform. For example, calibration of a quantum system can increase or decrease the amount of time used to emit waves for implementing a particular gate on that quantum system. As described in more detail below, existing waveforms or pulse scheduling can be corrected by editing pulse durations using embodiments of this disclosure to generate updated waveforms instead of repeating each step of the waveform generation process. Therefore, embodiments of this disclosure provide computationally efficient techniques that facilitate rapid waveform correction after quantum system calibration.

[0030] Figure 1 A block diagram of an exemplary, non-limiting system 100, according to one or more embodiments described herein, is shown that can facilitate rapid waveform correction after quantum system calibration. System 100 includes a memory 110 for storing computer-executable components and one or more processors 120 operatively coupled to the memory 110 via one or more communication buses 130 for executing the computer-executable components stored in the memory 110. Figure 1 As shown, the computer-executable components include: a calibration component 140 and a regeneration component 150.

[0031] The calibration component 140 can identify parameters of the directed graph that have been altered by calibration of the quantum system after the directed graph is generated. In embodiments, parameters include: pulse phase; pulse duration; pulse frequency; pulse amplitude; gate definition; or combinations thereof. In one embodiment, the calibration component can identify parameters using metadata associated with multiple named pulses comprising the directed graph. In another embodiment, the calibration component can interrupt the quantum system's job queue comprising the directed graph.

[0032] The regeneration component 150 can modify the directed graph based on the identified parameters to generate an updated directed graph. In one embodiment, the regeneration component 150 can modify the directed graph by modifying the corresponding pulse frequencies of the pulses and associated pulses. In another embodiment, the regeneration component 150 can modify the corresponding pulse frequencies using a list traversal of the pulses and associated pulses or a corresponding hash table. In yet another embodiment, the regeneration component 150 can modify the directed graph by inserting or removing placeholder pulses to maintain synchronization within the updated directed graph. In yet another embodiment, the regeneration component 150 can modify the directed graph by modifying the corresponding pulse amplitudes of the pulses and associated pulses. In yet another embodiment, subsets of the directed graph can remain unchanged in the updated directed graph.

[0033] In one embodiment, system 100 may use a model to evaluate the computational cost associated with correcting the directed graph based on identified parameters before regeneration component 150 corrects the directed graph. In another embodiment, the model may be implemented using one or more machine learning models trained to determine the computational cost associated with reconstructing and / or correcting the directed graph. Any known artificial intelligence, machine learning, knowledge-based, or rule-based mechanism may be used to train one or more machine learning models using training data. Examples of such mechanisms include support vector machines, neural networks, expert systems, Bayesian belief networks, fuzzy logic, data fusion engines, classifiers, etc. Training data may be obtained from datasets including historical calibration data, historical computational cost data, or combinations thereof. In another embodiment, system 100 may reconstruct the directed graph to generate a new directed graph in response to an evaluation indicating that the computational cost associated with correcting the directed graph exceeds the computational cost associated with reconstruction.

[0034] In an embodiment, the computer-executable component stored in memory 110 may further include a tracking component 160. The tracking component 160 can monitor calibration data to detect changes that invalidate the directed graph. The functionality of the computer-executable component utilized in the embodiment will be covered in more detail below.

[0035] Figure 2 An exemplary, non-limiting quantum circuit 200 suitable for implementing one or more embodiments described herein is shown. Figure 2 As shown, the quantum circuit 200 includes a U1 gate 230 applied to a first qubit 210 and a U3 gate 240 applied to a second qubit 220. In an embodiment, the U1 gate 230 can realize single-qubit rotation about the Z-axis, and the U3 gate 240 can realize single-qubit rotation about three rotation axes (e.g., the X-axis, Y-axis, and Z-axis). The quantum circuit 200 also includes a barrier operation 250 applied to the first qubit 210 and the second qubit 220 after the U1 gate 230 and the U3 gate 240 are applied to the first qubit 210 and the second qubit 220, respectively. In an embodiment, the barrier operation 250 helps maintain separation between the different gates or operations of the quantum circuit 200.

[0036] After applying the barrier operation 250, the quantum circuit 220 includes a U1 gate 235 applied to the second qubit 220. Figure 2The quantum circuit 200 further includes a controlled X-gate 260, which is applied to the first qubit 210 and the second qubit 220 after a barrier operation 250 and a U1 gate 235 are applied, respectively. In an embodiment, if the control qubit (e.g., the first qubit 210) is in the |1> state, the controlled X-gate 260 can flip the state of the target qubit (e.g., the second qubit 220). The quantum circuit 200 also includes a U3 gate 245 applied to the first qubit 210 after the controlled X-gate 260 is applied. In the quantum circuit 200, a measurement operation 270 is applied to the first qubit 210 after the U3 gate 245 is applied, and a measurement operation 275 is applied to the second qubit 220 after the controlled X-gate 260 is applied.

[0037] In some implementations, quantum circuits (e.g., Figure 2 A quantum circuit (200) can be converted into a waveform for input to a quantum system that physically implements or executes the quantum circuit via waveform generation. The waveform can be a directed graph of named pulses (or pulses) with associated metadata and a mapping of these named pulses to a signal that a driving source applies to the quantum system to execute the quantum circuit. Waveform generation can include three steps. One of those steps can include converting high-level information defining the quantum circuit into a directed graph of named pulses with directed edges pointing to future pulses. The directed graph generated from this conversion can be referred to as a circuit diagram, which is referenced below. Figure 3 To describe in more detail.

[0038] Another step in waveform generation may include adding clock information to the circuit diagram based on calibration data from a recent calibration performed on the quantum system. Adding such clock information can help to fit (or align) the named pulses of the circuit diagram with the time slots of the signals from the driving source applied to the quantum system to perform the quantum circuitry. In an embodiment, each time slot defines an equal time partition. When this clock information is added, the circuit diagram is transformed into a diagram that may be referred to as a pulse-time diagram, as shown below. Figure 4 A more detailed description follows. Generally, a pulse time graph can be a directed graph with vertices that include metadata. Examples of such metadata include: start time st, end time et, parent gate pg, named pulse p, data for associated pulse p', and combinations thereof. In embodiments, a quantum system may include multiple qubits that process the pulse time graph in parallel to perform a quantum circuit.

[0039] Another step in waveform generation may include adding frequency, amplitude, and / or shape information to the pulse-time diagram to facilitate waveform generation. In an embodiment, the waveform may be implemented as a set of two elements {P, T}, where P is a time-pulse diagram and T is a lookup table from named pulses p to actual waves. The lookup table T may include the frequency f, amplitude a, and / or shape of each actual wave. In an embodiment, the lookup table T may be a mapping of named pulses, including the associated pulse-time diagram P, to signals applied to the quantum system by a driving source to perform quantum circuitry. In an embodiment, the set of two elements {P, T} including the waveform may facilitate a sequence of instructions for controlling electronic devices to drive the hardware to implement quantum circuitry.

[0040] Figure 3 An exemplary, non-limiting circuit diagram 300 is shown according to one or more embodiments described herein. In the embodiments, definitions can be transformed. Figure 2 The high-level information of the quantum circuit 200 is used to generate the circuit diagram 300. For example... Figure 3 As shown, circuit diagram 300 includes multiple pulses, each pulse corresponding to one or more named pulses used to implement a specific gate or operation of quantum circuit 200. In circuit diagram 300, pulses 302 and 304 correspond to C0 and C2 pulses, respectively, which can be applied to the first qubit 210 to implement gate 230 of quantum circuit 200. Pulses 316 and 318 correspond to C1 and C0 pulses, respectively, which can be applied to the second qubit 220 to implement gate 240 of quantum circuit 200. Pulses 306 and 320 can be applied to the first qubit 210 and the second qubit 220, respectively, to implement barrier operation 250 of quantum circuit 200.

[0041] In circuit diagram 300, pulses 322 and 324 correspond to C0 and C2 pulses, respectively, which can be applied to the second qubit 220 to implement the U1 gate 235 of the quantum circuit 200. Pulses 308 and 310 correspond to two C1 pulses, which can be applied to the first qubit 210 to implement the controlled X gate 260 relative to the first qubit 210. Pulses 326, 328, and 330 correspond to C1, C3, and C0 pulses, respectively, which can be applied to the second qubit 220 to implement the controlled X gate 260 relative to the second qubit 220. Pulses 312 and 314 correspond to C1 and C0 pulses, which can be applied to the first qubit 210 to implement the U3 gate 245 of the quantum circuit 200.

[0042] Figure 4An exemplary, non-limiting pulse time map 400 is illustrated according to one or more embodiments described herein. In embodiments, the pulse time map 400 can be generated based on calibration data from a recent calibration performed on a quantum system. Figure 3 Clock information is added to circuit diagram 300 to implement or execute quantum circuit 200. Adding clock information to circuit diagram 300 may involve allocating or scheduling time slots for pulses in circuit diagram 300 using pulse durations of corresponding named pulses determined or set based on calibration data. For example, based on calibration data from a recent calibration, pulses C0, C1, and C3 may each be determined to have a pulse duration of 1 time unit; and pulse C2 may be determined to have a pulse duration of 2 time units. Time slots can be allocated to pulses in circuit diagram 300 using those pulse durations to generate pulse timing diagram 400.

[0043] like Figure 4 The bidirectional arrows with indicator p' shown in the pulse timing diagram 400 indicate that some pulses have associated pulses. In allocating or scheduling these time slots, pulses with associated pulses can be assigned such that the associated pulses are scheduled to be input into the quantum system at the same (or substantially the same) time. For example, Figure 4 Pulses 306 and 320 are described as associated pulses. Therefore, both pulses 306 and 320 can be assigned to the time slot defined by the start time t3 (st) and end time t4 (et). As another example, Figure 4 Pulses 308 and 326 are also described as associated pulses. As associated pulses, both pulses 308 and 326 can be assigned to the time slot defined by the start time st of t7 and the end time et of t8.

[0044] Identity (or placeholder) pulses may be added or inserted into pulse timing diagram 400 to resolve any time intervals arising from the assignment of associated pulses. For example, identity pulse 460 may be added to pulse timing diagram 400 to resolve the time interval between pulses 318 and 320 arising from the assignment of associated pulses 306 and 320. Figure 4 As shown, the pulse timing diagram 400 also includes identity pulses 440, 450 and 470, which are also added to resolve similar time intervals.

[0045] In an embodiment, adding or inserting an identity pulse may involve a qubit q. i When a pulse p is encountered, this pulse has a value in another qubit q. j The associated pulse p' on the qubit. In response, a pulse p' can be proposed for the qubit q. i The start time t of the upper scheduling pulse p i When the quantum bit q jWhen a related pulse p' is encountered, a start time t can be proposed for scheduling the related pulse p'. j Pulse p and its associated pulse p' can be suggested at a later start time (e.g., t) in the pulse time diagram. i or t j The pulse is scheduled. A pulse with a duration |t can be inserted in the pulse time diagram before a pulse corresponding to a suggested start time that occurs earlier in time (e.g., pulse p or associated pulse p'). i -t j |Identity pulse.

[0046] For example, the first qubit 210 may encounter pulse 308 and the associated pulse (i.e., pulse 326) on the second qubit 220. In response, a start time t4 may be suggested for scheduling pulse 308 on the first qubit 210. When the second qubit 220 encounters pulse 326, a start time t7 may be suggested for scheduling pulse 326 to assist in scheduling pulses 322 and 324. Pulses 308 and 326 may be scheduled to occur later in time at suggested start times (i.e., t7) in the pulse time diagram 400. An identity pulse 440 with a pulse duration of 3 time units (i.e., |t4-t7|) may be inserted in the pulse time diagram 400 before pulse 308.

[0047] By adding clock information Figure 3 When circuit diagram 300 generates pulse time diagram 400, pulse time diagram 400 can be added to the job queue of a quantum system storing existing directed graphs. After generating pulse time diagram 400, calibration of the quantum system can invalidate existing waveforms or directed graphs (such as those stored in the job queue). One or more parameters of pulse time diagram 400 can be changed through calibration of the quantum system.

[0048] For example, the calibration of this quantum system can change the pulse frequencies associated with the C1 and C2 pulses of pulse time map 400. Based on the calibration data available when generating pulse time map 400, the pulse frequencies associated with both C1 and C2 pulses are set to 2 Hz. However, based on new calibration data from a calibration that invalidates pulse time map 400, the pulse frequencies associated with C1 and C2 pulses should each be set to 3 Hz. Instead of repeating each step of the waveform generation process discussed above, pulse time map 400 can be modified based on the new calibration data to generate... Figure 5The updated pulse time map 500. In the embodiment, pulses associated with parameters (e.g., pulse frequencies) of invalid pulse time maps that have been altered by calibration of the quantum system after the generation of the directed graph can be located for correction using a list traversal of those pulses (e.g., using a lookup table T) or a hash table.

[0049] Figure 4 and Figure 5 The comparison shows that each pulse in the time pulse map 400 corresponding to the C1 or C2 pulse has been corrected to include a 3Hz pulse frequency. For example, the pulse time map 400 includes pulses 308, 310, 312, 316, and 326, each corresponding to a C1 pulse with a 2Hz pulse frequency; and pulses 304 and 324, each corresponding to a C2 pulse with a 2Hz pulse frequency. The pulse frequency of each of those pulses corresponding to the C1 or C2 pulse has been corrected from 2Hz to 3Hz to generate the updated pulse time map 500. Figure 5 As shown, a subset of pulse timing map 400 (e.g., pulses 302, 314, 320, and 328) remains unchanged in the updated pulse timing map 500. In the updated pulse timing map 500, only the pulses corresponding to C1 pulses (e.g., pulses 508, 510, 512, 516, and 526) or C2 pulses (e.g., pulses 504 and 524) have changed.

[0050] As another example, the calibration of a quantum system can alter the pulse amplitude associated with C0 and the identity (or placeholder) pulse of pulse time map 400. Based on the calibration data available when generating pulse time map 400, the pulse amplitudes associated with C0 and the identity pulse are each set to 0.1 volts (V). However, based on new calibration data from a calibration that invalidates pulse time map 400, the pulse amplitudes associated with C0 and the identity pulse should each be set to 0.2V. Instead of repeating each step of the waveform generation process discussed above, pulse time map 400 can be modified based on the new calibration data to generate... Figure 6 The updated pulse time graph 600.

[0051] Figure 4 and Figure 6The comparison shows that each pulse in the time pulse map 400 corresponding to the C0 or identity pulse has been corrected to include a 0.2V pulse amplitude. For example, the pulse time map 400 includes pulses 302, 314, 318, 322, and 330, each corresponding to a C0 pulse with a pulse amplitude of 0.1V; and pulses 440, 450, 460, and 470, each corresponding to an identity pulse with a pulse amplitude of 0.1V. The pulse amplitude of each of those pulses in the time pulse map 400 corresponding to the C0 or identity pulse has been modified from 0.1V to 0.2V to generate the updated time pulse map 600. Figure 6 As shown, a subset of pulse timing map 400 (e.g., pulses 304, 310, 320, and 326) remains unchanged in the updated pulse timing map 600. In the updated pulse timing map 600, only the pulses corresponding to C0 pulses (e.g., pulses 602, 614, 618, 622, and 630) or identity pulses (e.g., pulses 640, 650, 660, and 670) are changed.

[0052] As another example, the calibration of this quantum system can alter the pulse duration associated with the C2 pulse in pulse time map 400. Based on the calibration data available when generating pulse time map 400, the pulse duration associated with the C2 pulse is initially set to two time units. However, based on new calibration data from a calibration that invalidates pulse time map 400, the pulse duration associated with the C2 pulse should be set to one time unit. Instead of repeating each step of the waveform generation process discussed above, pulse time map 400 can be modified based on the new calibration data to generate... Figure 7 The updated pulse timing diagram 700.

[0053] To generate the updated pulse time map 700, each identity pulse inserted into the pulse time map 400 can be removed. Therefore, identity pulses 440, 450, 460, and 470 can each be removed from the pulse time map 400 to generate the updated pulse time map 700. When removing an inserted identity pulse, the first time (e.g., t) that a C2 pulse is encountered at a particular qubit is considered. i The end time of the C2 pulse (e.g., t) i+1The start time is set to one time unit after the corresponding start time. For example, pulse 304 first encounters the C2 pulse on the first qubit 210 at t1. The end time of pulse 304 in pulse time plot 400 is set to t3. In the updated pulse time plot 700, the start time of pulse 704 corresponding to the C2 pulse remains t1; however, the end time of pulse 704 has been corrected from t3 to t2 to reflect the updated one-time-unit pulse duration of the C2 pulse. Similarly, pulse 324 in pulse time plot 400 first encounters the C2 pulse on the second qubit 220. In the updated pulse time plot 700, the end time of pulse 724 has been similarly corrected to reflect the updated one-time-unit pulse duration of the C2 pulse.

[0054] The downstream portion of the pulse timing diagram 400 is rescheduled based on the corresponding end times of pulses 704 and 724. This downstream portion includes each future gate or operation scheduled after a C2 pulse for the first qubit 210 (e.g., pulses 308, 310, 312, and 314) or for the second qubit 220 (e.g., pulses 326, 328, and 330). These future gates or operations can be rescheduled while ensuring that the associated pulses remain scheduled to be input to the quantum system at the same (or substantially the same) time, such as... Figure 7 As shown. After rescheduling these future gates or operations, identity (or placeholder) pulses can be added or inserted into the updated pulse timing diagram 700, as described above regarding... Figure 4 The discussion focuses on resolving any time intervals arising from the allocation of associated pulses. Figure 7 In the updated pulse timing diagram 700, such identity pulses include pulses 740, 750, and 770. The aforementioned disclosure regarding changes in pulse duration caused by calibration of the quantum system has been discussed in relation to a decrease in pulse duration. However, those skilled in the art will recognize that the disclosed techniques can be similarly applied to an increase in pulse duration caused by calibration of the quantum system.

[0055] As another example, the calibration of this quantum system can be altered by changing the pulses implemented for each U1 gate (e.g., pulse timing diagram 400). Figure 2The gate definitions for UI gates 230 and 235 are as follows. Based on the calibration data available when generating pulse timing diagram 400, the gate definition for implementing the U1 gate involves applying a pulse sequence including a C0 pulse followed by a C2 pulse to the qubit used to implement the U1 gate. However, based on new calibration data from a calibration that invalidates pulse timing diagram 400, the gate definition for implementing the U1 gate involves applying a C0 pulse to the qubit used to implement the U1 gate. Instead of repeating each step of the waveform generation process discussed above, pulse timing diagram 400 can be modified based on the new calibration data to generate... Figure 8 The updated pulse time graph 800.

[0056] To generate the updated pulse time map 800, each identity pulse inserted into the pulse time map 400 can be removed. Therefore, identity pulses 440, 450, 460, and 470 can each be removed from the pulse time map 400 to generate the updated pulse time map 800. When removing the inserted identity pulses, each pulse in the pulse time map 400 implementing the U1 gate is identified. In an embodiment, each pulse in an invalid pulse time map implementing a gate associated with a changed gate definition can be located and corrected using list traversal (e.g., utilizing a lookup table T) or a hash table of those pulses. Each pulse in the pulse time map 400 implementing the U1 gate (e.g., pulses 302 and 304 for implementing U1 gate 230; and pulses 322 and 324 for implementing U1 gate 235) can be removed and replaced with pulses conforming to the new gate definition (e.g., pulse 802 for implementing U1 gate 230 and pulse 822 for implementing U1 gate 235).

[0057] The downstream portion of pulse timing graph 400 is rescheduled based on the corresponding end times of pulses 802 and 822. This downstream portion includes each future gate or operation scheduled after the U1 gate of the first qubit 210 (e.g., pulses 306, 308, 310, 312, and 314) or the second qubit 220 (e.g., pulses 326, 328, and 330). Those future gates or operations can be rescheduled while ensuring that the associated pulses remain scheduled to be input to the quantum system at the same (or substantially the same) time, such as... Figure 8 As shown. After these future gates or operations are rescheduled, identity (or placeholder) pulses can be added or inserted into the updated pulse timing diagram 800, as described above regarding... Figure 4 The discussion focuses on resolving any time intervals arising from the allocation of associated pulses. Figure 8 In the updated pulse timing diagram 800, the identity pulses inserted include pulses 840, 850, 870, and 880.

[0058] Figure 9A flowchart of an exemplary, non-limiting computer-implemented method 900 for facilitating rapid waveform correction after calibration of a quantum system, according to one or more embodiments described herein, is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0059] At 910, the computer-implemented method 900 may include a system (e.g., utilizing...) Figure 1 The calibration component 140 identifies parameters of the directed graph altered by calibration of the quantum system that occurs after the directed graph is generated. In an embodiment, parameters include: pulse phase; pulse duration; pulse frequency; pulse amplitude; gate definition; or combinations thereof. In an embodiment, the system may use metadata associated with multiple named pulses comprising the directed graph to identify the parameters.

[0060] At 920, the computer-implemented method 900 may include a system (e.g., utilizing...) Figure 1 The regeneration component 150 modifies the directed graph based on the identified parameters to generate an updated directed graph. In one embodiment, the system can modify the directed graph by adjusting the pulse frequency of the pulses. In another embodiment, the system can modify the pulse frequency using a list traversal of the pulses or a hash table. In yet another embodiment, the system can modify the directed graph by inserting or removing placeholder pulses to maintain synchronization within the updated directed graph. Finally, in another embodiment, the system can modify the directed graph by adjusting the pulse amplitude of the pulses.

[0061] In an embodiment, the computer-implemented method 900 may further include: by a system (e.g., utilizing...) Figure 1 The tracking component 160 monitors calibration data to detect changes that invalidate the directed graph. In an embodiment, the computer-implemented method 900 may further include: interrupting the quantum system's work queue, including the directed graph, by the system (e.g., using the calibration component 140).

[0062] Figure 10 A flowchart of an exemplary, non-limiting computer-implemented method 1000 for facilitating rapid waveform correction after quantum system calibration, according to one or more embodiments described herein, is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. At 1010, the computer-implemented method 1000 may include a system (e.g., utilizing...) Figure 1The calibration component 140 identifies multiple parameters of the directed graph that have been altered by calibration of the quantum system after the directed graph is generated. For example, the system can identify the pulse phase and pulse duration associated with the directed graph, which are altered by calibration of the quantum system after the directed graph is generated. As another example, the system can identify the pulse amplitude and pulse frequency associated with the directed graph, which are altered by calibration of the quantum system after the directed graph is generated. At 1020, the computer-implemented method 1000 may include parameters obtained by the system (e.g., utilizing...) Figure 1 The regeneration component 150 modifies the directed graph based on multiple parameters identified at once to generate an updated directed graph. In an embodiment, a subset of the directed graph remains unchanged in the updated directed graph.

[0063] Figure 11 A flowchart illustrating an exemplary, non-limiting computer implementation method 1100 for facilitating rapid waveform correction after quantum system calibration according to one or more embodiments described herein is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. At 1110, the computer implementation method 1100 may include a system (e.g., utilizing...) Figure 1 The tracking component 160) detects the calibration of the quantum system that invalidates the directed graph after it has been generated.

[0064] At 1120, the computer-implemented method 1100 may include the system (e.g., utilizing...) Figure 1 The calibration component 140 identifies parameters of the directed graph altered by the calibration of the quantum system that occurs after the directed graph is generated. In an embodiment, the system may use metadata associated with multiple named pulses including the directed graph to identify the parameters. At 1130, the computer-implemented method 1100 may further include the system (e.g., utilizing...) Figure 1 The regeneration component 150 modifies the directed graph based on the identified parameters to generate an updated directed graph. In an embodiment, a subset of the directed graph remains unchanged in the updated directed graph.

[0065] In one embodiment, the computer-implemented method 1100 may further include the system using a model based on identified parameters to evaluate the computational cost associated with the correction of the directed graph before correcting it. In another embodiment, the computer-implemented method 1100 may further include the system reconstructing the directed graph to generate a new directed graph in response to the evaluation, the evaluation indicating that the computational cost associated with the correction of the directed graph exceeds the computational cost associated with the reconstruction.

[0066] In order to provide context for the various aspects of the disclosed subject, Figure 12The following discussion is intended to provide a general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized. Figure 12 The suitable operating environment 1200 shown for implementing various aspects of this disclosure may also include a computer 1212. The computer 1212 may further include a processing unit 1214, system memory 1216, and a system bus 1218. The system bus 1218 couples system components, including but not limited to system memory 2816, to the processing unit 1214. The processing unit 1214 may be any of the various available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 1214. The system bus 1218 may be any of several types of bus architectures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of the various available bus architectures, including (but not limited to) Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1094), and Small Computer System Interface (SCSI). System memory 1216 may also include volatile memory 1220 and non-volatile memory 1222. The Basic Input / Output System (BIOS) is stored in the non-volatile memory 1222. The BIOS includes basic routines for transferring information between components within the computer 1212, such as during startup. By way of example and not limitation, non-volatile memory 1222 may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory 1220 may also include random access memory (RAM) that acts as an external cache memory. By way of illustration and not limitation, RAM can be obtained in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM.

[0067] Computer 1212 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 12Disk storage 1224 is shown. Disk storage 1224 may also include, but is not limited to, devices such as disk drives, floppy disk drives, magnetic tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or Memory Sticks. Disk storage 1224 may also include storage media, alone or in combination with other storage media, including but not limited to optical disc drives, such as high-density disk ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives), or digitally usable disk ROM drives (DVD-ROM). To facilitate connection of disk storage 1224 to system bus 1218, removable or non-removable interfaces, such as interface 1226, are typically used. Figure 12 Software acting as an intermediary between the user and the basic computer resources described in the suitable operating environment 1200 is also described. Such software may also include, for example, an operating system 1228. The operating system 1228, which may be stored on disk storage 1224, is used to control and allocate the resources of computer 1212. System application 1230 utilizes the operating system 1228 to manage resources through program modules 1232 and program data 1234, for example, stored in system memory 1216 or on disk storage 1224. It should be understood that this disclosure may be implemented using different operating systems or combinations of operating systems. The user inputs commands or information into computer 1212 through one or more input devices 1236. Input devices 1236 include, but are not limited to, pointing devices such as a mouse, trackball, pen, touchpad, keyboard, microphone, joystick, gamepad, disc satellite dish, scanner, TV tuner card, digital camera, digital camcorder, webcam, etc. These and other input devices are connected to processing unit 1214 via system bus 1218 through one or more interface ports 1238. One or more interface ports 1238 include, for example, serial ports, parallel ports, gaming ports, and Universal Serial Bus (USB). One or more output devices 1240 use some of the same type of ports as one or more input devices 1236. Thus, for example, a USB port can be used to provide input to computer 1212 and to output information from computer 1212 to one or more output devices 1240. Output adapter 1242 is provided to illustrate that, in addition to other output devices 1240 that require dedicated adapters, there are some output devices 1240 such as monitors, speakers, and printers. By way of illustration and not limitation, output adapter 1242 includes video and sound cards that provide a means of connection between output devices 1240 and system bus 1218. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 1244.

[0068] Computer 1212 can operate in a networked environment using a logical connection to one or more remote computers (such as one or more remote computers 1244). Remote computer 1244 may be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer-to-peer device, or other common network node, and may typically include many elements or components described relative to computer 1212. For simplicity, memory storage device 1246 is described using only remote computer 1244 as an example. Remote computer 1244 is logically connected to computer 1212 via network interface 1248 and then physically connected via communication connection 1250. Network interface 1248 includes wired and / or wireless communication networks, such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN)) and its variants, packet-switched networks, and Digital Subscriber Line (DSL). Communication connection 1250 refers to the hardware / software used to connect network interface 1248 to system bus 1218. Although communication connection 1250 is shown inside computer 912 for clarity, it may also be external to computer 1212. For illustrative purposes only, the hardware / software used to connect to network interface 1248 may also include internal and external technologies such as modems, including conventional telephone-grade modems, cable modems and DSL modems, ISDN adapters and Ethernet cards.

[0069] This invention can be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. The computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in slots having instructions recorded thereon, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0070] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). Computer-readable program instructions may execute entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may be personalized to execute computer-readable program instructions by utilizing state information of the computer-readable program instructions in order to perform aspects of the present invention.

[0071] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operations to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0072] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions marked in the blocks may occur in a non-linear order. For example, depending on the function involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or performs a combination of dedicated hardware and computer instructions.

[0073] While the subject matter has been described above in the general context of computer-executable instructions running on a computer and / or a computer program product on a computer, those skilled in the art will recognize that this disclosure may also be implemented in combination with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will recognize that the computer implementation methods of the present invention can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumables or industrial electronic products, etc. The aspects shown can also be practiced in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of the invention can be practiced on a standalone computer. In a distributed computing environment, program modules may reside in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components may be executed from memory that may include or consist of one or more distributed memory cells. As used herein, the terms “memory” and “memory cell” are interchangeable. Furthermore, one or more embodiments described herein are capable of executing code from computer executable components in a distributed manner, for example, multiple processors working together or cooperating to execute code from one or more distributed memory units. As used herein, the term "memory" may include a single memory or memory unit at one location or multiple memories or memory units at one or more locations.

[0074] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. As an illustration, both an application running on a server and the server itself can be components. One or more components may reside within a process and / or a thread of execution, and components may be located on one computer and / or distributed across two or more computers. In another instance, a corresponding component may be executed from a different computer-readable medium having different data structures stored thereon. Components may communicate via local and / or remote processes, such as according to a signal having one or more data packets (e.g., data from a component interacting with another component in a local system, a distributed system, and / or data from a component interacting with other systems across a network such as the Internet via that signal). As another example, a component may be a device having specific functions provided by mechanical components operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As another example, the component can be a means of providing a specific function through electronic components without mechanical parts, wherein the electronic components can include a processor or other means for performing software or firmware that at least partially imparts the functionality to the electronic components. In one aspect, the component can be emulated via a virtual machine, for example, within a cloud computing system.

[0075] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clearly apparent from the context, "X adopts A or B" is intended to mean any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing cases. Additionally, the articles "a" and "an" as used in this specification and accompanying drawings should generally be interpreted as meaning "one or more" unless otherwise specified or clearly apparent from the context as referring to the singular form. As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, illustration, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Furthermore, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as superior to or advantageous over other aspects or designs, nor does it imply the exclusion of equivalent exemplary structures and techniques known to those skilled in the art.

[0076] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, "processor" can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user devices. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "memory," "storage device," "data storage device," "data storage," "database," and substantially any other information storage component, as used in relation to the operation and function of a component, are used to refer to a "memory component," an entity implemented in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein can be volatile or non-volatile memory, or may include both volatile and non-volatile memory. By way of example and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include, for example, RAM that can serve as an external cache memory. By way of illustration and not limitation, RAM can be obtained in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Furthermore, the memory components of the systems or computer-implemented methods disclosed herein are intended to include (but are not limited to) these and any other suitable types of memory.

[0077] The above description includes only examples of systems and computer-implemented methods. Of course, for the purposes of describing this disclosure, it is impossible to describe every conceivable combination of components or computer-implemented method; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, the use of terms such as “comprising,” “having,” “possessing,” etc., in the detailed description, claims, appendices, and drawings is intended to be inclusive, similar to the way “comprising” is interpreted as the term “comprising” when used as a transitional word in a claim.

[0078] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer system comprising: a processor that executes the following computer-executable components stored in memory: a calibration component that identifies a parameter of a directed graph of named pulses changed by a calibration of a quantum system that occurs after the directed graph of named pulses is generated, wherein high-level information defining a quantum circuit is converted into the directed graph of named pulses having directed edges pointing to named pulses, the directed graph of named pulses including vertices of named pulses having associated metadata and directed edges pointing to vertices of named pulses; and a regeneration component that revises the directed graph of named pulses based on the identified parameter to generate an updated directed graph of named pulses.

2. The system of claim 1, wherein, the parameter includes: a pulse phase, a pulse duration; a pulse frequency; a pulse amplitude; a gate definition; or a combination thereof.

3. The system of claim 1, wherein, the calibration component uses metadata associated with a plurality of named pulses including the directed graph of named pulses to identify the parameter.

4. The system of claim 1, wherein, the regeneration component revises the directed graph of named pulses by modifying a pulse frequency of a pulse.

5. The system of claim 4, wherein, the regeneration component uses a list traversal or hash table of the pulses to modify the pulse frequency.

6. The system of any one of claims 1-5, wherein, the regeneration component revises the directed graph of named pulses by inserting or removing a placeholder pulse to maintain synchronization within the updated directed graph of named pulses.

7. The system of any one of claims 1-5, wherein, the regeneration component revises the directed graph of named pulses by modifying a pulse amplitude of a pulse.

8. The system of any of claims 1-5, further comprising: a tracking component that monitors calibration data to detect changes that invalidate the directed graph of named pulses.

9. The system of any one of claims 1-5, wherein, the calibration component interrupts a job queue of the quantum system including the directed graph of named pulses.

10. A computer-implemented method comprising: identifying, by a system, a parameter of a directed graph of named pulses changed by a calibration of a quantum system that occurs after the directed graph of named pulses is generated, wherein high-level information defining a quantum circuit is converted into the directed graph of named pulses having directed edges pointing to named pulses, the directed graph of named pulses including vertices of named pulses having associated metadata and directed edges pointing to vertices of named pulses; and revising, by the system, the directed graph of named pulses based on the identified parameter to generate an updated directed graph of named pulses.

11. The computer-implemented method of claim 10, wherein, the parameter includes: a pulse phase; a pulse duration; a pulse frequency; a pulse amplitude; a gate definition; or a combination thereof.

12. The computer-implemented method of claim 10, wherein, the system uses metadata associated with a plurality of named pulses including the directed graph of named pulses to identify the parameter.

13. The computer-implemented method of claim 10, wherein, the system revises the directed graph of named pulses by modifying a pulse frequency of a pulse.

14. The computer-implemented method of claim 13, wherein, the system uses a list traversal or hash table of the pulses to modify the pulse frequency.

15. The computer-implemented method of any one of claims 10 to 14, wherein, the system revises the directed graph of named pulses by inserting or removing a placeholder pulse to maintain synchronization within the updated directed graph of named pulses.

16. The computer-implemented method of any one of claims 10 to 14, wherein, the system revises the directed graph of named pulses by modifying a pulse amplitude of a pulse.

17. The computer-implemented method of any of claims 10 to 14, further comprising: Calibration data is monitored by the system to detect changes that invalidate the directed graph of named pulses.

18. The computer-implemented method of any one of claims 10 to 14, further comprising: interrupting, by the system, a work queue of the quantum system that includes the directed graph of named pulses.

19. A computer program product comprising program instructions executable by a processor to cause the processor to: identifying parameters of the directed graph of named pulses that are changed by a calibration of the quantum system that occurs after the directed graph of named pulses is generated, wherein convert high-level information defining a quantum circuit into a directed graph of named pulses having directed edges pointing to named pulses, the directed graph of named pulses including vertices of named pulses having associated metadata and directed edges pointing to vertices of named pulses; and correct the directed graph of named pulses based on the identified parameters to generate an updated directed graph of named pulses.

20. The computer program product of claim 19, wherein, The parameters include: pulse phases; pulse durations; pulse frequencies; pulse amplitudes; gate definitions; or combinations thereof.

21. A computer-implemented method comprising: identifying, by a system, a plurality of parameters of a directed graph of named pulses that are changed by a calibration of a quantum system that occurs after the directed graph of named pulses is generated, wherein high-level information defining a quantum circuit is converted into the directed graph of named pulses having directed edges pointing to named pulses, the directed graph of named pulses including vertices of named pulses having associated metadata and directed edges pointing to vertices of named pulses; and correcting, by the system, the directed graph of named pulses based on the plurality of identified parameters at a time to generate an updated directed graph of named pulses.

22. The computer-implemented method of claim 21, wherein, A subset of the directed graph of named pulses remains unchanged in the updated directed graph of named pulses.

23. A computer-implemented method comprising: detecting, by a system, a calibration of a quantum system that invalidates a directed graph of named pulses after the directed graph of named pulses is generated, wherein high-level information defining a quantum circuit is converted into the directed graph of named pulses having directed edges pointing to named pulses, the directed graph of named pulses including vertices of named pulses having associated metadata and directed edges pointing to vertices of named pulses; identifying, by the system, parameters of the directed graph of named pulses that are changed by the calibration of the quantum system; and correcting, by the system, the directed graph of named pulses based on the identified parameters to generate an updated directed graph of named pulses.

24. The computer-implemented method of claim 23, wherein, The system identifies the parameters using metadata associated with a plurality of named pulses that include the directed graph of named pulses.

25. The computer-implemented method of any one of claims 23 to 24, further comprising: prior to correcting the directed graph of named pulses, evaluating, by the system, a computational cost associated with correcting the directed graph of named pulses based on the identified parameters using a model; and in response to an evaluation indicating that the computational cost associated with correcting the directed graph of named pulses exceeds a computational cost associated with rebuilding the directed graph of named pulses, rebuilding, by the system, the directed graph of named pulses to generate a new directed graph of named pulses.

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