LCD display device

Abstract

A liquid crystal display device is realized that can suppress the increase of the bezel area and obtain a sufficient aperture ratio. Multiple pixel electrodes are disposed inside the display area (10). Multiple pixel transistors (30), each corresponding to one of the multiple pixel electrodes, are disposed in the area outside the display area (10). Each pixel transistor (30) is connected to the pixel electrode via its corresponding pixel wiring (11). An input pad group (20) for inputting drive signal groups for driving the multiple pixel transistors (30) is disposed on the TFT substrate (5). Here, the multiple pixel transistors (30) are disposed only in the area outside the area between the input pad group (20) and the display area (10) on the TFT substrate (5).

Description

Technical Field

[0001] The following disclosure relates to a liquid crystal display device, and more particularly to a liquid crystal display device that drives pixels in a display area independently. Background Technology

[0002] Liquid crystal display (LCD) devices can be broadly classified into transmissive LCD devices that utilize emitted light from a backlight located on the back of the display unit, and reflective LCD devices that utilize reflected light from external light. Additionally, transmissive LCD devices utilizing both emitted light from a backlight and reflected light from external light are also known. Reflective LCD devices do not require a backlight, thus allowing for easier reduction in power consumption and thinner designs compared to transmissive LCD devices. Furthermore, in recent years, dual-layer display devices (hereinafter referred to as "dual-layer displays") with an organic EL display device on the back of such a reflective LCD device have also been developed. Dual-layer displays are typically used in watches, for example, displaying images based on an organic EL display device for high-resolution displays and images based on a reflective LCD device for simpler displays such as text information.

[0003] However, in reflective liquid crystal display devices, since they utilize reflected light from external light, sufficient display quality cannot be obtained if the aperture ratio of the display area is low. Therefore, it is preferable to maximize the aperture ratio. Consequently, International Publication No. 2011 / 027600 discloses a pixel circuit configuration that achieves low power consumption without reducing the aperture ratio.

[0004] Furthermore, in recent years, to reduce power consumption, liquid crystal display devices with memory circuits integrated within the pixel circuits have been developed. In this regard, International Publication No. 2020 / 255536 discloses a liquid crystal display device that, by setting a structure that outputs a control polarity signal using a system control circuit, can stop the operation of the image signal control circuit in memory mode (a driving mode using signals recorded in the memory circuit). According to this liquid crystal display device, the operation of the image signal control circuit can be stopped in memory mode, thus achieving significant power reduction. Summary of the Invention

[0005] The technical problem to be solved by the present invention

[0006] However, according to the structure disclosed in International Publication No. 2011 / 027600, sufficient aperture ratio cannot be obtained because pixel transistors and storage circuits are present in the display area. In this regard, it is considered to place a portion of the components located within the display area outside the display area, but there are concerns about widening the bezel area. In recent years, especially with wearable devices such as watches, there has been a strong demand for miniaturization, therefore increasing the bezel area is not preferable.

[0007] Furthermore, according to the configuration disclosed in International Publication No. 2020 / 255536, a drive circuit (image signal output unit) is provided between the input pad group and the display area (refer to International Publication No. 2020 / 255536). Figure 1 as well as Figure 2 Therefore, based on the display area, the border area on the input pad group side will inevitably become larger.

[0008] Therefore, the purpose of the following disclosure is to realize a liquid crystal display device that can suppress the increase of the bezel area and obtain a sufficient aperture ratio.

[0009] Technical solutions for solving technical problems

[0010] (1) The liquid crystal display device of several embodiments of the present invention has a panel substrate, the panel substrate being provided with a display area including a plurality of pixel electrodes, the liquid crystal display device including: a plurality of pixel transistors disposed in a region outside the display area corresponding one-to-one with the plurality of pixel electrodes; a plurality of pixel wirings respectively connecting the plurality of pixel electrodes and the plurality of pixel transistors; and an input pad group disposed on the panel substrate and inputting a group of driving signals for driving the plurality of pixel transistors, wherein the plurality of pixel transistors are disposed only in the region on the panel substrate other than the region between the input pad group and the display area.

[0011] (2) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (1) above, wherein the panel substrate has a rectangular shape formed by a first side, a second side, a third side and a fourth side, the second side is opposite to the first side, the third side connects one end of the first side and one end of the second side, the fourth side connects the other end of the first side and the other end of the second side, the input pad group is disposed on the panel substrate in a border area along the first side, and the plurality of pixel transistors are not disposed in the border area along the first side, but are disposed in at least one of the border areas along the second side, the border areas along the third side and the border areas along the fourth side.

[0012] (3) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (2) above, wherein the plurality of pixel transistors are configured such that the direction of extension from the pixel transistor to the pixel electrode is the same for all of the plurality of pixel wirings.

[0013] (4) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (3) above, wherein the plurality of pixel transistors are disposed only in the border area along the second side.

[0014] (5) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (3) above, wherein the plurality of pixel transistors are disposed only in either the border region along the third side or the border region along the fourth side.

[0015] (6) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (2) above, wherein the plurality of pixel transistors are disposed in the border region along the third side and the border region along the fourth side, the plurality of pixel wirings are composed of a plurality of first type pixel wirings and a plurality of second type pixel wirings, the plurality of first type pixel wirings connect the pixel transistors disposed in the border region along the third side and their corresponding pixel electrodes, and the plurality of second type pixel wirings connect the pixel transistors disposed in the border region along the fourth side and their corresponding pixel electrodes.

[0016] (7) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (1) above. The panel substrate has a circular shape. Based on the second virtual line, the plurality of pixel transistors are disposed only in the border area on the side where the display area exists. The second virtual line is a virtual line that passes through the connection point of the first virtual line and the display area and is orthogonal to the first virtual line. The first virtual line is the virtual line that is the shortest virtual line connecting the display area and the input pad group.

[0017] (8) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (7) above, wherein the plurality of pixel transistors are configured such that the direction of extension from the pixel transistor to the pixel electrode is the same for all of the plurality of pixel wirings.

[0018] (9) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (8) above, with the third virtual line as a reference, and the plurality of pixel transistors are provided only in the border area on the side where the input pad group does not exist, wherein the third virtual line is a virtual line that passes through the center of the display area and is parallel to the second virtual line.

[0019] (10) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (8) above, with the fourth virtual line as a reference, and the plurality of pixel transistors are provided only in the border area on one side, wherein the fourth virtual line is a virtual line through the connection point between the first virtual line and the display area and the center of the display area.

[0020] (11) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (7) above. The plurality of pixel transistors are disposed on both sides of a border area on one side and a border area on the other side, with reference to a virtual line, namely a fourth virtual line, which is a connection point between the first virtual line and the display area and the center of the display area. The plurality of pixel wirings include a plurality of first-type pixel wirings and a plurality of second-type pixel wirings. The plurality of first-type pixel wirings connect the pixel transistors disposed on one side of the border area with reference to the fourth virtual line and their corresponding pixel electrodes. The plurality of second-type pixel wirings connect the pixel transistors disposed on the other side of the border area with reference to the fourth virtual line and their corresponding pixel electrodes.

[0021] (12) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (6) or (11) above, wherein the number of the plurality of first type pixel wirings is the same as the number of the plurality of second type pixel wirings.

[0022] (13) Furthermore, based on any one of the above-described (1) to (12) configurations, the liquid crystal display device of several embodiments of the present invention includes: a driving circuit that drives the plurality of pixel transistors based on the driving signal group, the driving circuit being disposed in a region on the panel substrate other than the input pad group and the display area, such that the plurality of pixel transistors are disposed in the region between the driving circuit and the display area.

[0023] (14) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (13) above. The driving circuit includes a shift register composed of a plurality of unit circuits connected in series. The plurality of unit circuits output a plurality of output signals that are activated in sequence as a plurality of timing signals, and the plurality of data signals contained in the driving signal group are acquired based on the plurality of timing signals.

[0024] (15) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (13) above. The driving circuit includes a decoding circuit. The decoding circuit has multiple output units. The multiple output units output multiple decoding signals that are activated sequentially as multiple timing signals. Based on the multiple timing signals, multiple data signals contained in the driving signal group are acquired.

[0025] (16) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration described in (14) or (15) above, where M is an integer greater than 2, the driving circuit includes M latch circuits for each timing signal, and the M latch circuits take in M ​​data signals based on the corresponding timing signal and output the taken in M ​​data signals.

[0026] (17) Furthermore, based on the configuration described in (16) above, the liquid crystal display device of several embodiments of the present invention includes a polarity switching circuit, which includes a plurality of pixel transistors. The polarity switching circuit is used to switch the polarity of the voltage applied to the plurality of pixel electrodes at predetermined intervals. The polarity switching circuit is composed of a plurality of polarity control units corresponding to the plurality of pixel wirings. Each polarity control unit includes a first pixel transistor and a second pixel transistor. The first pixel transistor and the second pixel transistor change their on / off states in opposite directions based on data signals output from the corresponding latch circuits. In each polarity control unit, between the first level and the second level, a first voltage and a second voltage that change in opposite directions at each predetermined interval are supplied. When the first pixel transistor is in the on state, the first voltage is applied to the corresponding pixel electrode via the corresponding pixel wiring. When the second pixel transistor is in the on state, the second voltage is applied to the corresponding pixel electrode via the corresponding pixel wiring.

[0027] (18) Furthermore, based on the configuration described in (14) or (15) above, the liquid crystal display device of several embodiments of the present invention includes a sampling circuit, which includes the plurality of pixel transistors. The plurality of pixel transistors are grouped in such a way that K pixel transistors form a group in which K is an integer greater than or equal to 2. Each pixel transistor has a control terminal to which a corresponding timing signal is supplied, a first conduction terminal to which a corresponding data signal is supplied, and a second conduction terminal connected to the corresponding pixel wiring. The same timing signal is supplied to the control terminals of the K pixel transistors forming the same group, and different data signals are supplied to the first conduction terminals of the K pixel transistors forming the same group.

[0028] (19) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration of any one of (1) to (12) above, each pixel transistor having: a control terminal to which a switch control signal included in the drive signal group is supplied; a first conduction terminal to which a data signal included in the drive signal group is supplied; and a second conduction terminal to which it is connected to a corresponding pixel wiring, the same switch control signal is supplied to the control terminal of the plurality of pixel transistors, and different data signals are supplied to the first conduction terminal of the plurality of pixel transistors.

[0029] (20) Furthermore, the liquid crystal display device of several embodiments of the present invention includes the configuration of any one of (1) to (12) above, wherein the plurality of pixel transistors are grouped in such a way that Z is an integer greater than or equal to 2, and each pixel transistor has: a control terminal, which is supplied with a switch control signal included in the drive signal group; a first conduction terminal, which is supplied with a data signal included in the drive signal group; and a second conduction terminal, which is connected to a corresponding pixel wiring, wherein different signals are supplied to the control terminals of the Z pixel transistors forming the same group as the switch control signals, and a data signal is supplied to the first conduction terminal of the Z pixel transistors forming the same group in a time-division manner.

[0030] Beneficial effects

[0031] According to several embodiments of the liquid crystal display device of the present invention, pixel transistors are disposed in a region outside the display area. That is, pixel transistors are not present in the display area. This results in a sufficient aperture ratio in the display area. Furthermore, pixel transistors are disposed only in the region on the panel substrate other than between the input pad group and the display area. Therefore, compared to a configuration where pixel transistors are disposed between the input pad group and the display area, the size of the entire bezel area can be reduced. Thus, a liquid crystal display device is realized that can suppress the increase of the bezel area and obtain a sufficient aperture ratio. Attached Figure Description

[0032] Figure 1 This is a first example schematic diagram showing the configuration of the constituent elements on the TFT substrate for all embodiments.

[0033] Figure 2 This is a diagram illustrating the general configuration of a display device (dual-layer display) for all embodiments.

[0034] Figure 3 This is a second example diagram showing the configuration of the various components on the TFT substrate for all embodiments.

[0035] Figure 4 This is a diagram illustrating a third example of the configuration of the constituent elements on a TFT substrate for all embodiments.

[0036] Figure 5 This is a diagram used to illustrate the details of the third example described above regarding all implementation methods.

[0037] Figure 6 This is a fourth example diagram showing the configuration of the constituent elements on the TFT substrate for all embodiments.

[0038] Figure 7This is a fifth example diagram showing the configuration of the various components on the TFT substrate for all embodiments.

[0039] Figure 8 This is a sixth example diagram showing the arrangement of the constituent elements on the TFT substrate for all embodiments.

[0040] Figure 9 This is a seventh example diagram showing the arrangement of the constituent elements on the TFT substrate in all embodiments.

[0041] Figure 10 This is a diagram used to illustrate the general structure of the display area in all implementation methods.

[0042] Figure 11 This is a schematic diagram used to illustrate the structure of pixels in all implementation methods.

[0043] Figure 12 This is a diagram used to illustrate the effects of all the implementation methods.

[0044] Figure 13 This is a diagram used to illustrate the effects of all the implementation methods.

[0045] Figure 14 This is a diagram used to illustrate the effects of all the implementation methods.

[0046] Figure 15 This is a functional block diagram used to illustrate the configuration related to the driving of pixel wiring in the first embodiment.

[0047] Figure 16 This is a block diagram illustrating the configuration of the shift register in the first embodiment described above.

[0048] Figure 17 This is a signal waveform diagram used to illustrate the operation of the shift register in the first embodiment described above.

[0049] Figure 18 This is a block diagram illustrating the configuration of the latching unit in the first embodiment described above.

[0050] Figure 19 This is a schematic diagram illustrating a latch circuit in the first embodiment described above.

[0051] Figure 20 This is a circuit diagram showing the detailed configuration of a latch circuit in the first embodiment described above.

[0052] Figure 21 This is a block diagram showing the general configuration of the polarity switching circuit in the first embodiment described above.

[0053] Figure 22This is a circuit diagram showing the general configuration of the polarity control unit in the first embodiment described above.

[0054] Figure 23 This is a circuit diagram showing the detailed configuration of the polarity control unit using a single-channel switch in the first embodiment described above.

[0055] Figure 24 This is a circuit diagram showing the detailed configuration of the polarity control unit using a CMOS switch in the first embodiment described above.

[0056] Figure 25 This is a signal waveform diagram used to illustrate the switching of the polarity of the voltage applied to the liquid crystal in the first embodiment described above.

[0057] Figure 26 This is a functional block diagram used to illustrate the configuration related to the driving of pixel wiring in the second embodiment.

[0058] Figure 27 This is a block diagram showing the general configuration of the sampling circuit in the second embodiment described above.

[0059] Figure 28 This is a circuit diagram showing the detailed configuration of the unit sampling section in the second embodiment described above.

[0060] Figure 29 This is a functional block diagram used to illustrate the configuration related to the driving of pixel wiring in the third embodiment.

[0061] Figure 30 This is a circuit diagram showing the detailed configuration of the decoder in the third embodiment described above. Figure 31 This is a circuit diagram showing the detailed configuration of one output quantity of the decoder in the third embodiment described above.

[0062] Figure 32 This is a diagram illustrating the blocks used for address setting in the third embodiment described above.

[0063] Figure 33 This is a diagram illustrating an example of address mapping in the third embodiment described above.

[0064] Figure 34 This is a diagram illustrating an example of address mapping in the third embodiment described above.

[0065] Figure 35 This is a diagram illustrating an example of address mapping in the third embodiment described above.

[0066] Figure 36 This is a diagram illustrating an example of address mapping in the third embodiment described above.

[0067] Figure 37 This is a block diagram illustrating the configuration of the latching unit in the third embodiment described above.

[0068] Figure 38 This is a functional block diagram used to illustrate the configuration related to the driving of pixel wiring in the fourth embodiment.

[0069] Figure 39 This is a circuit diagram showing the configuration of the sampling circuit in the fifth embodiment.

[0070] Figure 40 This is a signal waveform diagram used to illustrate the operation of the sampling circuit in the fifth embodiment described above.

[0071] Figure 41 This is a circuit diagram showing the configuration of the sampling circuit in the sixth embodiment.

[0072] Figure 42 This is a signal waveform diagram used to illustrate the operation of the sampling circuit in the sixth embodiment described above.

[0073] Figure 43 This diagram illustrates the configuration of the drive circuitry and pixel transistors near the input pad group. Detailed Implementation

[0074] <0. Matters related to all implementation methods>

[0075] First, matters related to all implementation methods will be explained.

[0076] <0.1 Overview of the Display Device>

[0077] Figure 2 This is a schematic diagram illustrating the general configuration of the display device 100 in all embodiments. Furthermore, this display device 100 is a dual-layer display with two display panels. Figure 2 As shown, the display device 100 comprises a polarizing plate 140, a phase retardation plate 130, a liquid crystal display device 120, and an organic EL display device 110. Figure 2 As shown, these components are arranged from the viewer's side in the following order: polarizing plate 140, retardation plate 130, liquid crystal display device 120, and organic EL display device 110. The polarizing plate 140 can be either an absorptive or reflective type. The liquid crystal display device 120 is a reflective liquid crystal display device, and its cell thickness is approximately half that of a typical transmissive liquid crystal display device. The organic EL display device 110 has a reflective layer. Furthermore, the retardation plate 130 is provided for optical compensation or to expand the viewing angle; however, a configuration without the retardation plate 130 is also possible.

[0078] In the configuration described above, when performing high-resolution display, all pixels of the liquid crystal display device 120 are set to a transmissive state to perform image display based on the organic EL display device 110. On the other hand, when performing simple displays such as displaying text information, the liquid crystal display device 120 performs image display using reflected light from external light caused by the reflective layer of the organic EL display device 110.

[0079] Furthermore, as described above, the object of this disclosure is to realize a liquid crystal display device that suppresses the increase of the bezel area and obtains a sufficient aperture ratio. Therefore, the following description only relates to the liquid crystal display device 120.

[0080] <0.2 TFT substrate configuration>

[0081] The liquid crystal display device 120 is composed of two substrates (a TFT substrate and an opposing substrate) facing each other. Pixel electrodes, pixel wiring, pixel transistors, etc., are formed on the TFT substrate. On the opposing substrate, a common electrode is formed for all pixels. The structure of the TFT substrate will be described in detail below.

[0082] Regarding the configuration on the TFT substrate (the arrangement of each component), before describing the configurations that can be used in each embodiment, the configuration used as a reference example (see reference) will be discussed. Figure 43 The following description will be provided. In the configuration of the reference example, the display area 910 on the TFT substrate 95 is divided into a plurality of unit display areas 919. Pixel electrodes are formed in the display area 910 corresponding to each unit display area 919, and pixel transistors 930 corresponding to each pixel electrode are disposed on the outer side of the display area 910. More specifically, a plurality of pixel transistors 930 are disposed on the TFT substrate 95 along one of the four sides forming the display area 910. Furthermore, pixel wiring 911 connecting the pixel transistors 930 and their corresponding pixel electrodes is formed on the TFT substrate 95. With the above configuration, the pixels within the display area 910 are driven independently. Here, a drive circuit 940 for driving these pixel transistors 930 is formed near the plurality of pixel transistors 930. Furthermore, an input pad group 920 for inputting drive signal groups for driving the plurality of pixel transistors 930 is disposed near the drive circuit 940. Furthermore, a signal wiring group 951 is formed on the TFT substrate 95 for transmitting drive signal groups input to the input pad group 920 to the drive circuit 940. Additionally, in Figure 43 In the figure, an input pad is labeled with reference numeral 921.

[0083] As described above, according to the configuration of the reference example, a driving circuit 940 and a pixel transistor 930 are provided between the input pad group 920 and the display area 910. Therefore, similar to the configuration disclosed in International Publication No. 2020 / 255536, the bezel area on the input pad group 920 side necessarily becomes larger, based on the display area 910. Therefore, the configuration (arrangement of each component on the TFT substrate 95) that can be adopted in the embodiments described below will be explained below.

[0084] <0.2.1 First Example>

[0085] Figure 1 This is a diagram illustrating a first example related to the arrangement of the constituent elements on the TFT substrate 5. (See diagram for example.) Figure 1 As shown, the TFT substrate 5 has a rectangular shape. In the first example, similar to the reference example, the display area 10 on the TFT substrate 5 is divided into multiple unit display areas 19, and pixel electrodes are formed in the display areas 10 in a manner corresponding to each unit display area 19 (the same applies to the second to seventh examples described later). Furthermore, similar to the reference example, pixel wiring 11 connecting the pixel electrodes and the pixel transistors 30 is formed on the TFT substrate 5. With this configuration, the pixels within the display area 10 are driven independently.

[0086] In the first example, unlike the reference example, the pixel transistor 30 and driving circuit 40, along with the input pad group 20, are positioned on opposite sides of the bezel area, sandwiching the display area 10. Hereinafter, regarding the TFT substrate 5, for ease of explanation, the accompanying drawings will be provided. Figure 1 The edge located at the bottom of the image (e.g., the edge above the image, opposite to the first edge) is called the "second edge," the edge located to the left of the image (the edge connecting one end of the first edge and one end of the second edge) is called the "third edge," and the edge located to the right of the image (the edge connecting the other end of the first edge and the other end of the second edge) is called the "fourth edge." Thus, in the first example, the input pad group 20 is located in the border region along the first edge, and the pixel transistor 30 and the driving circuit 40 are only located in the border region along the second edge. Focusing on the border region along the second edge, the pixel transistor 30 is located in the area between the driving circuit 40 and the display area 10.

[0087] In addition, Figure 1 In the figure, the signal routing group used to transmit the drive signal group input to the input pad group 20 to the drive circuit 40 is marked with reference numeral 51, and one input pad included in the input pad group 20 is marked with reference numeral 21. Figures 3-9 (The same applies).

[0088] However, in the first example, the multiple pixel transistors 30 and the multiple pixel wirings 11 are configured in a manner known as "single-sided driving". In other words, the multiple pixel transistors 30 are configured such that all the multiple pixel wirings 11 extend in the same direction from the pixel transistors 30 to the pixel electrodes.

[0089] <0.2.2 Second Example>

[0090] Figure 3 This is a diagram illustrating a second example related to the arrangement of the constituent elements on the TFT substrate 5. (See diagram for example.) Figure 3 As shown, the TFT substrate 5 has a rectangular shape. In the second example, the input pad group 20 is disposed in the border region along the first side, and the pixel transistor 30 and driving circuit 40 are disposed only in the border region along the fourth side. Focusing on the border region along the fourth side, the pixel transistor 30 is disposed in the area between the driving circuit 40 and the display area 10. Alternatively, the pixel transistor 30 and driving circuit 40 may be disposed only in the border region along the third side. Similar to the first example, multiple pixel transistors 30 and multiple pixel wirings 11 are configured in a manner known as "single-sided driving".

[0091] <0.2.3 Third Example>

[0092] Figure 4 This is a diagram illustrating a third example related to the arrangement of the constituent elements on the TFT substrate 5. (See diagram for example.) Figure 4 As shown, unlike the first and second examples, the TFT substrate 5 has a circular shape. In the third example, the input pad group 20 is set... Figure 4 Below the display area 10, the pixel transistor 30 and the driving circuit 40 are located Figure 4 The right side of display area 10 in the image. When focusing on... Figure 4 When the pixel transistor 30 is located to the right of the display area 10, it is positioned in the area between the driving circuit 40 and the display area 10. Similar to the first and second examples, multiple pixel transistors 30 and multiple pixel wirings 11 are configured in a manner known as "single-sided driving." Alternatively, the pixel transistors 30 and the driving circuit 40 can also be positioned... Figure 4 The left side of display area 10 in the middle.

[0093] Reference Figure 5The positional relationship between the input pad group 20 and the pixel transistor 30 will be explained in more detail. Here, the shortest virtual line connecting the display area 10 and the input pad group 20 is referred to as the "first virtual line". Reference numeral 53 is used to label the first virtual line. Reference numeral 54 is used to label the connection point between the first virtual line 53 and the display area 10. Furthermore, a virtual line passing through the connection point 54 of the first virtual line 53 and the display area 10 and orthogonal to the first virtual line 53 (the tangent line through the aforementioned connection point 54) is referred to as the "second virtual line". Reference numeral 55 is used to label the second virtual line. Based on the second virtual line 55, the pixel transistor 30 is provided only in the border area on the side where the display area 10 is located.

[0094] <0.2.4 Fourth Example>

[0095] Figure 6 This is a diagram illustrating a fourth example related to the arrangement of the constituent elements on the TFT substrate 5. (See diagram for example.) Figure 6 As shown, the TFT substrate 5 has a circular shape. In the fourth example, the input pad group 20 is set... Figure 6 Below the display area 10, the pixel transistor 30 and the driving circuit 40 are located Figure 6 Above the display area 10. Specifically, if a virtual line passing through the center of the display area 10 and parallel to the second virtual line 55 is designated as a "third virtual line" (the third virtual line is labeled with reference numeral 56), then based on the third virtual line 56, only in the border area on the side where the input pad group 20 does not exist ( Figure 6 Pixel transistors 30 are disposed within the border area marked with reference numeral 57 in the attached drawing. Additionally, in this fourth example, pixel transistors 30 are also disposed in the area between the driving circuit 40 and the display area 10. Furthermore, multiple pixel transistors 30 and multiple pixel wirings 11 are configured in a manner known as "single-sided driving".

[0096] <0.2.5 Fifth Example>

[0097] Figure 7 This is a diagram illustrating a fifth example related to the arrangement of the constituent elements on the TFT substrate 5. (See diagram for example.) Figure 7As shown, the TFT substrate 5 has a rectangular shape. In the fifth example, unlike the first to fourth examples, multiple pixel transistors 30 and multiple pixel wirings 11 are configured in a manner known as "side-drive". The input pad group 20 is disposed in the border region along the first side, and the pixel transistors 30 and the drive circuit 40 are disposed in the border regions along the third side and the border regions along the fourth side. For example, half of all the pixel transistors 30 are disposed in the border region along the third side, and the remaining pixel transistors 30 are disposed in the border region along the fourth side. Thus, with the pixel transistors 30 disposed in the border regions along the third side and the border regions along the fourth side, there are pixel wirings 11 extending from the pixel electrode to the border region along the third side and pixel wirings 11 extending from the pixel electrode to the border region along the fourth side. These pixel wirings 11 are formed, for example, in a comb-like shape.

[0098] In the fifth example, to achieve a drive referred to as "side-drive," multiple pixel wirings 11 connected to multiple pixel electrodes within the display area 10 include: multiple first-type pixel wirings that connect pixel transistors 30 disposed along the border region of the third side and their corresponding pixel electrodes; and multiple second-type pixel wirings that connect pixel transistors 30 disposed along the border region of the fourth side and their corresponding pixel electrodes. Pixel transistors 30 connected to the multiple first-type pixel wirings are only disposed along the border region of the third side, and pixel transistors 30 connected to the multiple second-type pixel wirings are only disposed along the border region of the fourth side.

[0099] <0.2.6 Sixth Example>

[0100] Figure 8 This is a sixth example diagram showing the arrangement of the constituent elements on the TFT substrate 5. (See diagram for example.) Figure 8 As shown, the TFT substrate 5 has a circular shape. In the sixth example, similar to the fifth example, multiple pixel transistors 30 and multiple pixel wirings 11 are configured for a driving method known as "side-drive". The input pad group 20 is set at... Figure 8 Below the display area 10, the pixel transistor 30 and the driving circuit 40 are located Figure 8The display area 10 is located on both the left and right sides. For example, half of all the pixel transistors 30 are located in the left border region of the display area 10, and the remaining pixel transistors 30 are located in the right border region of the display area 10. Thus, with the pixel transistors 30 located in both the left and right border regions of the display area 10, there are pixel wirings 11 extending from the pixel electrodes to the left border region of the display area 10 and pixel wirings 11 extending from the pixel electrodes to the right border region of the display area 10. These pixel wirings 11 are, for example, formed in a comb-like shape.

[0101] Furthermore, similar to the third example, pixel transistors 30 are provided only in the border area on the side where the display area 10 exists, based on the second virtual line 55 described above. Here, if the connection point 54 between the first virtual line 53 and the display area 10 (refer to...) is... Figure 5 The virtual line at the center of the display area 10 is designated as the "fourth virtual line" (the fourth virtual line is labeled with reference numeral 58). In the third example, based on the fourth virtual line 58, pixel transistors 30 are set only in one side of the area (see reference 58). Figure 4 In contrast, in this sixth example, with the fourth virtual line 58 as a reference, pixel transistors 30 are provided on both the border area on one side and the border area on the other side.

[0102] In the sixth example, to achieve a drive referred to as "side-drive," multiple pixel wirings 11 connected to multiple pixel electrodes within the display area 10 include: multiple first-type pixel wirings, which, based on a fourth virtual line 58, connect pixel transistors 30 disposed on one side of the bezel area and their corresponding pixel electrodes; and multiple second-type pixel wirings, which, based on the fourth virtual line 58, connect pixel transistors 30 disposed on the other side of the bezel area and their corresponding pixel electrodes. The pixel transistors 30 connected to the multiple first-type pixel wirings are disposed only on one side of the bezel area, based on the fourth virtual line 58, and the pixel transistors 30 connected to the multiple second-type pixel wirings are disposed only on the other side of the bezel area, based on the fourth virtual line 58.

[0103] <0.2.7 Seventh Example>

[0104] In the first to sixth examples, a driving circuit 40 for driving the pixel transistor 30 is formed on the TFT substrate 5. However, this is not a limitation; the driving circuit may also be provided on a substrate (a substrate other than the TFT substrate 5) connected to the input pad group 20. Therefore, as a seventh example, a configuration in which the driving circuit 40 for driving the pixel transistor 30 is not provided on the TFT substrate 5 will be described (see [reference]). Figure 9In the seventh example, the input pad group 20 is located in the border region along the first side, and the sampling circuit 60 containing the pixel transistor 30 is located in the border region along the second side. Additionally, Figure 9 The configuration shown is for the first example where the pixel transistor 30 and the driving circuit 40 are replaced with a sampling circuit 60 including the pixel transistor 30. However, for the second to sixth examples, the configuration where the pixel transistor 30 and the driving circuit 40 are replaced with a sampling circuit 60 including the pixel transistor 30 can also be adopted.

[0105] <0.2.8 Summary>

[0106] As described above, in any of the first to seventh examples, an input pad group 20 with a drive signal group is disposed at one end of the TFT substrate (panel substrate) 5. The drive signal group is used to drive a plurality of pixel transistors 30 corresponding to a plurality of pixel electrodes in the display area 10. The plurality of pixel transistors 30 are disposed only in the area of ​​the TFT substrate 5 (panel substrate) other than between the input pad group 20 and the display area 10.

[0107] <0.3 Composition of the display area>

[0108] Next, refer to Figure 10 The general configuration of the display area 10 in all embodiments will be described below. In the display area 10, a plurality of pixel electrodes 12 are formed in a manner corresponding one-to-one with the aforementioned plurality of unit display areas 19. Furthermore, in the following embodiments, it is assumed that 960 pixel electrodes 12 (32 rows × 30 columns of pixel electrodes 12) are formed in the display area 10: see [reference missing] Figure 10 ).

[0109] In typical liquid crystal display devices, pixel transistors are disposed within the display area. However, in all the embodiments of the liquid crystal display device described herein, the pixel transistors 30 are not disposed within the display area 10, but rather outside the display area 10. For example... Figure 10 As shown, 960 pixel wirings 11 are arranged on the TFT substrate 5, which connect 960 pixel transistors 30 disposed on the outer side of the display area 10 and 960 pixel electrodes 12 formed in the display area 10.

[0110] Figure 11 This is a schematic diagram showing the structure of pixels in all implementation methods. For example... Figure 11As shown, the pixel electrode 12 formed on the TFT substrate 5 and the common electrode 13 formed on the opposing substrate are opposed to each other, and the liquid crystal layer 14 is disposed in such a way that it is sandwiched between the pixel electrode 12 and the common electrode 13. The common electrode 13 is an electrode shared by all pixels. In order to suppress the degradation of the liquid crystal, a common electrode drive signal VCOM is supplied to the common electrode 13, and the voltage level varies between high and low levels at predetermined intervals.

[0111] <0.4 effect>

[0112] According to the above configuration, the multiple pixel transistors 30 corresponding to the multiple pixel electrodes 12 in the display area 10 are only disposed in the area outside the input pad group 20 and the display area 10 in the region of the TFT substrate 5.

[0113] For example, in the first example, the input pad group 20 is located in the border area along the first side, and the pixel transistor 30 and the driving circuit 40 are located only in the border area along the second side (see reference). Figure 1 Comparison of the structure of the reference example (see) Figure 43 The composition of the first example, such as Figure 12 As shown, regarding the width of the border region along the second side (the length in the vertical direction in the attached drawing), one side of the first example is only W1 longer than the reference example, but regarding the width of the border region along the first side (the length in the vertical direction in the attached drawing), one side of the first example is only W2 shorter than the reference example. Here, W2 is longer than W1. Therefore, according to the first example, it is possible to make the size of the entire border region smaller than that of the reference example. Regarding the fourth example (refer to...) Figure 6 The same applies.

[0114] Furthermore, for example, in the second example, the input pad group 20 is located in the border region along the first side, while the pixel transistor 30 and the driving circuit 40 are only located in the border region along the fourth side (see reference). Figure 3 Compare the structure of the reference example with the structure of the second example, such as... Figure 13 As shown, regarding the width of the border region along the fourth side (the length in the left-right direction in the attached diagram), one side of the second example is only W3 longer than the reference example, but as... Figure 14 As shown, regarding the width of the border region along the first side (the length in the vertical direction in the attached figure), the second example is only W4 shorter than the reference example. Here, W4 is longer than W3. Therefore, according to the second example, the overall size of the border region can be made smaller than that of the reference example. Regarding the third example (refer to...) Figure 4 Fifth example (refer to) Figure 7 ) and the sixth example (see Figure 8 The same applies.

[0115] Furthermore, according to the seventh example (see...) Figure 9 Since the driving circuit 40 for driving the pixel transistor 30 is not disposed on the TFT substrate 5, the size of the bezel area can be made significantly smaller than that of the reference example.

[0116] As described above, regarding the configuration of providing the pixel transistor 30 on the outer side of the display area 10, any of the first to seventh examples can reduce the size of the bezel area compared to the reference example. Furthermore, since there is no pixel transistor 30 within the display area 10, a sufficient aperture ratio can be obtained. In all the above embodiments, a liquid crystal display device is realized that can suppress the increase of the bezel area and obtain a sufficient aperture ratio.

[0117] <1. First Implementation Method>

[0118] The first embodiment will be described. In this embodiment, as in the first to sixth examples described above, a plurality of pixel transistors 30 are provided in the area between the display area 10 and the driving circuit 40.

[0119] <1.1 Components related to pixel wiring drive>

[0120] Reference Figure 15 The configuration related to the driving of pixel wiring 11 will be explained. For example... Figure 15 As shown, a driving circuit 40 and a polarity switching circuit 70 are provided in the area outside the display area 10 as components related to driving the pixel wiring 11. The driving circuit 40 is composed of a shift register 41 and a latch unit 42. Furthermore, the pixel transistor 30 is included in the polarity switching circuit 70.

[0121] The shift register 41 is supplied with control clock signals BCK, BCKB, start pulse signal BSP, and initialization signal INI via signal wiring group 51. The internal state of the shift register 41 is initialized based on the initialization signal INI. The shift register 41 performs shift operations based on the control clock signals BCK, BCKB, and BSP. Then, based on this shift operation, the output signals from each unit circuit described later are output as timing signals indicating the input timing of data signals.

[0122] The data signal BDAT<0:7>, representing binary data, is supplied to the latch unit 42 via the signal wiring group 51. Furthermore, the data signal BDAT<0:7> is 8 bits of data. The latch unit 42 includes multiple latch circuits, each of which fetches the corresponding data signal based on a corresponding timing signal (a timing signal output from the shift register 41) and outputs the fetched data signal.

[0123] A white display voltage VA and a black display voltage VB are supplied to the polarity switching circuit 70 via the signal wiring group 51. The voltage levels of the white display voltage VA and the black display voltage VB change in opposite directions between a high level (first level) and a low level (second level) at predetermined intervals. The polarity switching circuit includes multiple polarity control units corresponding to multiple pixel wirings 11 within the display area 10. Each polarity control unit applies either the white display voltage VA or the black display voltage VB to the corresponding pixel wiring based on a data signal output from the corresponding latch circuit. Furthermore, in this embodiment, the first voltage is implemented using the white display voltage VA, and the second voltage is implemented using the black display voltage VB.

[0124] As described above, a voltage (VA for white display or VB for black display) corresponding to the data signal BDAT<0:7> is applied to each pixel electrode 12, thereby displaying the desired image in the display area 10.

[0125] <1.2 Detailed Composition of the Drive Circuit>

[0126] Figure 16 This is a circuit diagram showing the detailed configuration of shift register 41. For example... Figure 16 As shown, the shift register 41 consists of 120 unit circuits 411(1) to 411(120) connected in series, a reset signal generation circuit 412, and multiple buffers 413. Each unit circuit 411 is a bistable circuit. As described above, a control clock signal BCK, a control clock signal BCKB, a start pulse signal BSP, and an initialization signal INI are supplied to the shift register 41. The states of the unit circuits 411(1) to 411(120) are initialized based on the initialization signal INI. The output signal Q from the previous unit circuit 411 is supplied to each unit circuit 411 as a set signal SB, and the output signal Q from the next unit circuit 411 is supplied to each unit circuit 411 as a reset signal R. However, for the first-level unit circuit 411(1), the start pulse signal BSP is supplied as the set signal SB, and for the 120th-level unit circuit 411(120), the signal generated by the reset signal generation circuit 412 is supplied as the reset signal R. In each unit circuit 411, after the set signal SB becomes high, the output signal Q becomes high (i.e., output shift pulse) based on the control clock signals BCK and BCKB. Furthermore, the output signal Q becomes low when the reset signal R becomes high.

[0127] Since the unit circuit 411 operates in the manner described above, after the pulse of the start pulse signal BSP is generated, the output signal Q from the unit circuit 411 successively becomes high level based on the control clock signals BCK and BCKB. That is, the high-level output signal Q from each unit circuit 411 is transmitted as a shift pulse from the 1st stage to the 120th stage. In addition, the output signal Q from each unit circuit 411 is supplied not only to the next stage and the previous stage unit circuit 411, but also to the latch circuit as a timing signal SR. As described above, Figure 17 As shown, after the pulse of the start pulse signal BSP is generated, based on the control clock signals BCK and BCKB, the timing signals are made to be high (active) in each specified period in the order of "timing signal SR(1), timing signal SR(2), ..., timing signal SR(119), timing signal SR(120)".

[0128] Figure 18 This is a block diagram showing the configuration of the latch unit 42. For example... Figure 18 As shown, the latch unit 42 is composed of 120 latch circuit groups 421(1) to 421(120). Each latch circuit group 421 includes 8 latch circuits. Therefore, a total of 960 latch circuits are provided. Each latch circuit group 421 is supplied with the data signal BDAT<0:7> and the timing signal SR output from the shift register 41. When the input timing signal SR changes from low level to high level, each latch circuit group 421 takes in the data signal BDAT<0:7> and outputs the taken data signal. In addition, the data signal output from the latch circuit is marked with the reference numeral BOUT. As described above, the timing signal becomes high level in the order of "timing signal SR(1), timing signal SR(2), ..., timing signal SR(119), timing signal SR(120)" (see reference). Figure 17 The data signal BDAT<0:7> in the latch circuit group is retrieved in the order of "latch circuit group 421(1), latch circuit group 421(2), ..., latch circuit group 421(119), latch circuit group 421(120)".

[0129] As described above, after the generation of the start pulse signal BSP, the data signal BDAT<0:7> of the latch circuit group 421 is fetched whenever the logic levels of the control clock signal BCK and the control signal BCKB reverse. That is, when the logic levels of the control clock signal BCK and the control signal BCKB reverse once, 8 bits of data are fetched into the latch circuit group 421. Therefore, after the generation of the start pulse signal BSP, the fetching of the data corresponding to all pixel electrodes 12 ends when the logic levels of the control clock signal BCK and the control signal BCKB reverse 120 times.

[0130] Figure 19 This is a schematic diagram illustrating a latch circuit (a latch circuit corresponding to 1 bit of data) 422. The 1-bit data signal BDAT is supplied to the latch circuit 422 as the input signal IN, and the timing signal SR output from the shift register 41 is supplied to the latch circuit 422 as the enable signal EN. Then, the output signal OUT from the latch circuit 422 is supplied to the polarity switching circuit 70 as the data signal BOUT.

[0131] Figure 20 This is a circuit diagram showing the detailed configuration of a latch circuit 422. Furthermore, the configuration shown here is an example and is not limited to this. The latch circuit 422 consists of an inverter 481, a CMOS switch 450 composed of n-channel and p-channel transistors, a clock inverter 460 composed of p-channel transistors 461, 462, n-channel transistors 463 and 464, a CMOS inverter 470 composed of p-channel transistors 471 and n-channel transistors 472, and an inverter 482.

[0132] The enable signal EN input to the latch circuit 422 is supplied to the gate terminal of the n-channel transistor constituting the CMOS switch 450. Furthermore, as... Figure 20 As shown, by configuring inverter 481, the inverter enable signal ENB is supplied to the gate terminal of the p-channel transistor constituting CMOS switch 450. As described above, if the enable signal EN is high, CMOS switch 450 is in the ON state, and therefore, the input signal IN is supplied to clock inverter 460. On the other hand, if the enable signal EN is low, CMOS switch 450 is in the OFF state, and therefore, the input signal IN is not supplied to clock inverter 460.

[0133] For clock inverter 460, the input terminal is connected to node 484, and the output terminal is connected to node 483. For CMOS inverter 470, the input terminal is connected to node 483, and the output terminal is connected to node 484. Furthermore, if the enable signal EN is low, both p-channel transistor 461 and n-channel transistor 464 are turned on; if the enable signal EN is high, both p-channel transistor 461 and n-channel transistor 464 are turned off. As described above, the value of the input signal IN input to the latch circuit 422 when the enable signal EN becomes high is held by clock inverter 460 and CMOS inverter 470 until the next time the enable signal EN becomes high. However, if the input signal IN is high, the potential of node 483 becomes high, and the output signal OUT also becomes high. Conversely, if the input signal IN is low, the potential of node 483 becomes low, and the output signal OUT also becomes low.

[0134] Furthermore, as described above, in this embodiment, each latch circuit group 421 includes eight latch circuits 422. That is, each timing signal is provided with eight latch circuits 422. However, it is not limited to this; it is also possible to use an integer M greater than 2, where the drive circuit 40 includes M latch circuits 422 for each timing signal. In this case, these M latch circuits 422 take in M ​​data signals (M bits of data) based on the corresponding timing signal SR and output the taken in M ​​data signals.

[0135] <1.3 Detailed Structure of Polarity Switching Circuit>

[0136] Figure 21 This is a block diagram showing a rough configuration of the polarity switching circuit 70. (Example) Figure 21 As shown, the polarity switching circuit 70 is composed of 960 polarity control units 71, each corresponding to one of the 960 pixel wirings 11. Each polarity control unit 71 outputs either the white display voltage VA or the black display voltage VB as a data signal SL applied to the pixel wirings 11 based on the data signal BOUT.

[0137] Figure 22 This is a diagram showing the general configuration of the polarity control unit 71. (See diagram below.) Figure 22As shown, the polarity control unit 71 includes two switches 711 and 712 that control the on / off state based on the data signal BOUT. The on / off states of switches 711 and 712 change in opposite directions. These two switches 711 and 712 function as pixel transistors 30. For example, when the data signal BOUT is high, switch 711 is off and switch 712 is on; when the data signal BOUT is low, switch 711 is on and switch 712 is off. Thus, when the data signal BOUT is high, the black display voltage VB is applied to the pixel wiring 11 as the data signal SL, and when the data signal BOUT is low, the white display voltage VA is applied to the pixel wiring 11 as the data signal SL. Hereinafter, two examples relating to a more detailed configuration of the polarity control unit 71 will be described.

[0138] Figure 23 This is a circuit diagram showing the detailed configuration of the polarity control unit 71 using a single-channel switch. (For example...) Figure 23 As shown, the polarity control unit 71 is composed of an n-channel transistor 713, an n-channel transistor 714, and an inverter 715. The n-channel transistors 713 and 714 function as pixel transistors 30. A data signal BOUT is supplied to the input terminal of the inverter 715, and the output terminal of the inverter 715 is connected to the control terminal of the n-channel transistor 713. A data signal BOUT is supplied to the control terminal of the n-channel transistor 714. A white display voltage VA is applied to the first conducting terminal of the n-channel transistor 713, and the second conducting terminal of the n-channel transistor 713 is connected to the pixel wiring 11. A black display voltage VB is applied to the first conducting terminal of the n-channel transistor 714, and the second conducting terminal of the n-channel transistor 714 is connected to the pixel wiring 11.

[0139] Based on the above configuration, when the data signal BOUT is high, n-channel transistor 713 is off and n-channel transistor 714 is on, so the black display voltage VB is supplied to the pixel wiring 11 as the data signal SL. On the other hand, when the data signal BOUT is low, n-channel transistor 713 is on and n-channel transistor 714 is off, so the white display voltage VA is supplied to the pixel wiring 11 as the data signal SL.

[0140] In addition, in Figure 23 In the example shown, the first pixel transistor is implemented by an n-channel transistor 713, and the second pixel transistor is implemented by an n-channel transistor 714.

[0141] Figure 24This is a circuit diagram showing the detailed configuration of the polarity control unit 71 using a CMOS switch. (For example...) Figure 24 As shown, the polarity control unit 71 is composed of a CMOS switch 716, a CMOS switch 717, and an inverter 718. The CMOS switches 716 and 717 function as pixel transistors 30. A data signal BOUT is supplied to the input terminal of the inverter 718, and the output terminal of the inverter 718 is connected to the control terminal of the n-channel transistor constituting the CMOS switch 716 and the control terminal of the p-channel transistor constituting the CMOS switch 717. A white display voltage VA is supplied to the input terminal of the CMOS switch 716, and the output terminal of the CMOS switch 716 is connected to the pixel wiring 11. A black display voltage VB is supplied to the input terminal of the CMOS switch 717, and the output terminal of the CMOS switch 717 is connected to the pixel wiring 11.

[0142] Based on the above configuration, when the data signal BOUT is high, CMOS switch 716 is in the off state and CMOS switch 717 is in the on state, so the black display voltage VB is applied to the pixel wiring 11 as the data signal SL. On the other hand, when the data signal BOUT is low, CMOS switch 716 is in the on state and CMOS switch 717 is in the off state, so the white display voltage VA is applied to the pixel wiring 11 as the data signal SL.

[0143] In addition, in Figure 24 In the example shown, the first pixel transistor is implemented by the n-channel transistor and the p-channel transistor constituting the CMOS switch 716, and the second pixel transistor is implemented by the n-channel transistor and the p-channel transistor constituting the CMOS switch 717.

[0144] Figure 25 This is a signal waveform diagram used to illustrate the switching of the polarity of the voltage applied to the liquid crystal (the voltage applied to the liquid crystal layer 14). For example... Figure 25As shown, the voltage levels of the white display voltage VA and the black display voltage VB change in opposite directions between high and low levels at predetermined intervals. Furthermore, the voltage level of the common electrode drive signal VCOM applied to the common electrode 13 also changes between high and low levels at predetermined intervals. Here, a positive voltage is applied to the liquid crystal layer 14 during periods when the voltage level of the common electrode drive signal VCOM is low. On the other hand, a negative voltage is applied to the liquid crystal layer 14 during periods when the voltage level of the common electrode drive signal VCOM is high. As described above, the polarity of the voltage applied to the liquid crystal reverses at predetermined intervals, thus suppressing liquid crystal degradation.

[0145] <1.4 Effects>

[0146] According to this embodiment, a polarity switching circuit 70 is provided as a component related to driving the pixel wiring 11. Therefore, even when a data signal is input to the input pad group 20 without considering the polarity of the liquid crystal applied voltage, the polarity of the liquid crystal applied voltage is reversed at predetermined intervals, thereby suppressing liquid crystal degradation. Furthermore, by arranging the components on the TFT substrate 5 as described in the first to sixth examples above, it is possible to suppress the increase of the bezel area and obtain a sufficient aperture ratio. Based on the above, according to this embodiment, a liquid crystal display device capable of suppressing liquid crystal degradation and bezel area increase while obtaining a sufficient aperture ratio is realized.

[0147] <2. Second Implementation Method>

[0148] The second embodiment will now be described. In this embodiment, as in the first to sixth examples described above, a plurality of pixel transistors 30 are also provided in the area between the display area 10 and the driving circuit 40. Furthermore, the following mainly describes the differences from the first embodiment.

[0149] <2.1 Related Components of Pixel Wiring Driving>

[0150] Reference Figure 26 This explains the configuration related to the driving of pixel wiring 11. For example... Figure 26 As shown, a driving circuit 40 and a sampling circuit 80 are provided in the region outside the display area 10 as components related to driving the pixel wiring 11. In the first embodiment, the driving circuit 40 is composed of a shift register 41 and a latch unit 42, but in this embodiment, the driving circuit 40 only includes the shift register 41. In addition, the pixel transistor 30 is included in the sampling circuit 80.

[0151] Similar to the first embodiment, a timing signal representing the input timing of the data signal is output from the shift register 41. The data signal BDAT<0:7> is supplied to the sampling circuit 80. In the sampling circuit 80, the data signal BDAT<0:7> is sampled based on the timing signal output from the shift register 41. Then, each data signal sampled by the sampling circuit 80 is applied to the corresponding pixel wiring 11. Thus, a data signal is applied to each pixel electrode 12, and the desired image is displayed in the display area 10.

[0152] <2.2 Sampling Circuit Structure>

[0153] Figure 27 This is a block diagram illustrating the configuration of the sampling circuit 80. (Example:) Figure 27 As shown, the sampling circuit 80 consists of 120 unit sampling units 81(1) to 81(120). Each unit sampling unit 81 corresponds to 8 pixel wirings 11 and includes 8 pixel transistors 30. A data signal BDAT<0:7> and a timing signal SR output from the shift register 41 are supplied to each unit sampling unit 81. Each unit sampling unit 81 samples the data signal BDAT<0:7> when the input timing signal SR changes from low to high. Figure 17 As shown, the timing signal SR becomes high level in the order of "timing signal SR(1), timing signal SR(2), ..., timing signal SR(119), timing signal SR(120)", and therefore the data signal BDAT<0:7> is sampled in the order of "unit sampling section 81(1), unit sampling section 81(2), ..., unit sampling section 81(119), unit sampling section 81(120)".

[0154] Based on the above, after the generation of the start pulse signal BSP, sampling of the data signal BDAT<0:7> based on the unit sampling unit 81 is performed whenever the logic levels of the control clock signal BCK and the control signal BCKB are reversed. That is, if the logic levels of the control clock signal BCK and the control signal BCKB are reversed once, 8 bits of data are sampled. Therefore, after the generation of the start pulse signal BSP, sampling of the data corresponding to all pixel electrodes 12 ends at the moment when the logic levels of the control clock signal BCK and the control signal BCKB have been reversed 120 times.

[0155] Furthermore, in this embodiment, the 960 pixel transistors 30 are grouped in such a way that each group consists of 8 pixel transistors 30. Therefore, a total of 120 groups are formed. Let p be an integer greater than or equal to 0 and less than or equal to 7, and q be an integer greater than or equal to 1 and less than or equal to 120. Figure 27In the figure, the data signal corresponding to the p-th pixel transistor 30 of the q-th group (the data signal applied to the pixel wiring 11) is marked with the reference numeral SLp(q).

[0156] Figure 28 This is a circuit diagram showing the detailed configuration of the unit sampling section 81. Additionally, Figure 28 The unit sampling unit 81 shown is the unit sampling unit 81 corresponding to the nth group (n is an integer greater than or equal to 1 and less than 120). For example... Figure 28 As shown, the unit sampling section 81 includes eight pixel transistors 30(0) to 30(7). For each pixel transistor 30, a timing signal SR(n) is supplied to the control terminal, a corresponding data signal BDAT (1 bit) is supplied to the first conduction terminal, and the second conduction terminal is connected to the corresponding pixel wiring 11. Figure 28 It can be seen that the same timing signal SR is supplied to the control terminals of the eight pixel transistors 30(0) to 30(7) that form the same group, and different data signals BDAT are supplied to the first conduction terminals of the eight pixel transistors 30(0) to 30(7) that form the same group.

[0157] In the above configuration, when the timing signal SR(n) changes from low level to high level, the eight pixel transistors 30(0) to 30(7) become on, and the data signals BDAT(0) to BDAT(7) are applied to the pixel wiring 11(0) to 11(7) as data signals SL0(n) to SL7(n).

[0158] In addition, in this embodiment, the groups are formed by a group of 8 pixel transistors 30, but K can also be set to an integer greater than 2, and the groups can be formed by a group of K pixel transistors 30.

[0159] <2.3 Effects>

[0160] According to this embodiment, since the sampling circuit 80 is provided only in the area between the shift register 41 constituting the driving circuit 40 and the display area 10, the size of the border area can be reduced compared to the first embodiment.

[0161] <3. Third Implementation Method>

[0162] The third embodiment will be described. In this embodiment, as in the first to sixth examples described above, a plurality of pixel transistors 30 are also provided in the area between the display area 10 and the driving circuit 40.

[0163] <3.1 Components related to pixel wiring drive>

[0164] Reference Figure 29The configuration related to the driving of pixel wiring 11 will be explained. For example... Figure 29 As shown, a driving circuit 40 and a polarity switching circuit 70 are provided in the area outside the display area 10 as components related to driving the pixel wiring 11. In the first embodiment, the driving circuit 40 is composed of a shift register 41 and a latch unit 42, but in this embodiment, the driving circuit 40 is composed of a decoder (decoding circuit) 43 and a latch unit 42. In addition, the pixel transistor 30 is included in the polarity switching circuit 70.

[0165] A first address selection signal GEN<1:2> and a second address selection signal GSEL<0:11> are supplied to the decoder 43 via signal wiring group 51. The first address selection signal GEN<1:2> is 2 bits of data, and the second address selection signal GSEL<0:11> is 12 bits of data. The decoder 43 receives the first address selection signal GEN<1:2> and the second address selection signal GSEL<0:11> as encoded data and decodes the data. The decoded data (decoded signal) is output from the decoder 43 as a timing signal, which indicates the timing of the data signal BDAT<0:7> fetched from each latch circuit 422 included in the latch unit 42. The configuration and operation of the latch unit 42 and the polarity switching circuit 70 are the same as in the first embodiment.

[0166] As described above, based on the timing signal output from the decoder 43, the latch unit 42 retrieves the data signal BDAT<0:7>. Then, through the polarity switching circuit 70, a voltage (white display voltage VA or black display voltage VB) corresponding to the data signal BDAT<0:7> retrieved by the latch unit 42 is applied to each pixel electrode 12. As a result, the desired image is displayed in the display area 10.

[0167] <3.2 Decoder (Decoding Circuit)>

[0168] Figure 30 This is a circuit diagram showing the detailed configuration of decoder 43. Figure 31 This is a circuit diagram showing the detailed configuration of one output quantity of decoder 43. For example... Figure 30 As shown, the decoder 43 is supplied with a first address selection signal GEN<1:2> and a first address selection signal GSEL<0:11>. In the decoder 43, for an output quantity, such as... Figure 31 As shown, it includes NAND circuit 431, inverter 432, NOR circuit 433, NAND circuit 434, inverter 435, and output terminal (output section) 440. (About...) Figure 31Node 436 is supplied with the first address selection signal GEN. <1> ~GEN <2> In any one of them, node 437 is supplied with the second address selection signal GSEL. <0> ~GSEL <3> In any one of them, node 438 is supplied with a second address selection signal GSEL. <4> ~GSEL <7> In either of these, node 439 is supplied with a second address selection signal GSEL. <8> ~GSEL <11> Any one of them. The decoded signal is output as a timing signal DEC from output terminal 440.

[0169] according to Figure 31 In the configuration shown, when the first address selection signal GEN supplied to node 436 is low, since the output from NAND circuit 434 is high, the timing signal DEC output from output terminal 440 is low, regardless of the second address selection signals GSEL supplied to nodes 437-439. When the first address selection signal GEN supplied to node 436 is high, the following actions are performed based on the second address selection signals GSEL supplied to nodes 437-439. If all the second address selection signals GSEL supplied to nodes 437-439 are high, the output from NAND circuit 431 is low and the output from inverter 432 is low, therefore the output from NOR circuit 433 is high. Consequently, since the output from NAND circuit 434 is low, the timing signal DEC output from output terminal 440 is high. If at least one of the second address selection signals GSEL supplied to nodes 437-439 is low, then at least one of the outputs from NAND circuit 431 and inverter 432 is high, and therefore the output from NOR circuit 433 is low. Consequently, since the output from NAND circuit 434 is high, the timing signal DEC output from output terminal 440 is low.

[0170] However, in this embodiment, 960 pixel electrodes 12 (32 rows × 30 columns of pixel electrodes 12) are provided in the display area 10, and 120 timing signals DEC are sent from the decoder 43 to the latch unit 42 so that the data fetched by the latch unit 42 is performed in 8-bit increments each time. These 120 timing signals DEC need to be sequentially high at predetermined intervals at different timings. Therefore, in this embodiment, an address mapping for setting 120 addresses is used. This will be explained below.

[0171] Indicative, as Figure 32As shown, the 32 vertical rows are combined into 8 rows for address setting. Therefore, 8 consecutive pixel electrodes 12 in the vertical direction correspond to one address. Furthermore, one output of the decoder 43 corresponds to one address, and the connection relationships within the decoder 43 are determined based on the settings in this address mapping.

[0172] Figures 33-36 This is a diagram illustrating an example of address mapping. The X-address value is labeled in the section indicated by the arrow marked 494. Furthermore, X-address values ​​range from 0 to 31, but values ​​from 1 to 30 are actually used. The first address selection signal GEN is shown in the section indicated by the arrow marked 491. <1> The value of the first address selection signal GEN <2> The value. According to... Figures 33-36 When the first address selection signal GEN <n>The value is H (high) and the first address selection signal GEN <2> When the value is L (low), the address selected is an address with an X-address value from 1 to 15, when the first address selection signal GEN... <1> The value is L and the first address selection signal GEN <2> When the value is H, the address with an X-address value of 16 to 30 is selected. In the section indicated by the arrow marked with reference numeral 492, each address corresponds to the second address selection signal GSEL. <8> ~GSEL <11> Which one, in the section indicated by the arrow marked with reference numeral 493, records that each address corresponds to the second address selection signal GSEL. <4> ~GSEL <7> Which one of them. Furthermore, in the section indicated by the arrow marked with reference numeral 495, it is recorded that each address corresponds to the second address selection signal GSEL. <0> ~GSEL <3> Which one?

[0173] For example, focusing on Figure 33 The address portion indicated by the arrow marked with reference numeral 497 in the attached diagram. The decoder corresponding to this address portion (1 output: refer to...) Figure 31 In this context, a first address selection signal GEN and a second address selection signal GSEL are supplied as shown below. The first address selection signal GEN is supplied to node 436. <1> The second address selection signal GSEL is supplied to node 437. <2> The second address selection signal GSEL is supplied to node 438. <5> The second address selection signal GSEL is supplied to node 439. <9> .

[0174] Considering the address mapping described above, by changing the values ​​of the first address selection signal GEN<1:2> and the second address selection signal GSEL<0:11> supplied to the input pad group 20, 120 high-level (activated) decoding signals are sequentially output as 120 timing signals DEC from the 120 output terminals 440 contained in the decoder 43 at predetermined intervals.

[0175] <3.3 Structure of the latching section>

[0176] Figure 37 This is a block diagram showing the configuration of the latch unit 42. As described above, the latch unit 42 in this embodiment has the same configuration as the latch unit 42 in the first embodiment. However, in the first embodiment, the timing signal SR output from the shift register 41 is supplied to the latch unit 42, while in this embodiment, the timing signal DEC output from the decoder 43 is supplied to the latch unit 42.

[0177] like Figure 37 As shown, the latch unit 42 is composed of 120 latch circuit groups 421(1) to 421(120). Each latch circuit group 421 includes 8 latch circuits 422. Therefore, a total of 960 latch circuits 422 are provided. Each latch circuit group 421 is supplied with a data signal BDAT<0:7> and a timing signal DEC output from the decoder 43. When the input timing signal DEC changes from low level to high level, each latch circuit group 421 takes in the data signal BDAT<0:7> and outputs the taken data signal. As the 120 timing signals DEC sequentially become high level at predetermined intervals, the data signal BDAT<0:7> is sequentially taken in by the 120 latch circuit groups 421.

[0178] Furthermore, the configuration and operation of the latch circuit 422 included in the latch circuit group 421 are the same as those in the first embodiment (see reference). Figure 19 as well as Figure 20 ).

[0179] <3.4 Effects>

[0180] According to this embodiment, similar to the first embodiment, a liquid crystal display device is realized that can suppress the deterioration of the liquid crystal and the increase of the bezel area and obtain a sufficient aperture ratio.

[0181] <4. Fourth Implementation Method>

[0182] The fourth embodiment will be described. In this embodiment, as in the first to sixth examples described above, a plurality of pixel transistors 30 are also provided in the area between the display area 10 and the driving circuit 40.

[0183] <4.1 Components related to pixel wiring drive>

[0184] Reference Figure 38 The configuration related to the driving of pixel wiring 11 will be explained. For example... Figure 38 As shown, a driving circuit 40 and a sampling circuit 80 are provided in the area outside the display area 10 as components related to driving the pixel wiring 11. The driving circuit 40 includes a decoder 43. (See from...) Figure 26 and Figure 38 As understood, the configuration in this embodiment is the replacement of the shift register 41 in the second embodiment with the decoder 43. Furthermore, the pixel transistor 30 is included in the sampling circuit 80.

[0185] The configuration and operation of the decoder 43 are the same as in the third embodiment, and the configuration and operation of the sampling circuit 80 are the same as in the second embodiment. Therefore, in the sampling circuit 80, the data signal BDAT<0:7> is sampled based on the timing signal DEC output from the decoder 43. Then, each data signal sampled by the sampling circuit 80 is applied to the corresponding pixel wiring 11. As a result, a data signal is applied to each pixel electrode 12, and the desired image is displayed in the display area 10.

[0186] <4.2 Effects>

[0187] According to this embodiment, since only the sampling circuit 80 is provided in the area between the decoder 43 constituting the driving circuit 40 and the display area 10, the size of the border area can be reduced compared to the third embodiment.

[0188] <5. Fifth Implementation Method>

[0189] The fifth embodiment will be described. In this embodiment, unlike the first to fourth embodiments, the driving circuit 40 for driving the pixel transistors 30 is not formed on the TFT substrate 5. In this embodiment, as in the seventh example described above, a sampling circuit 60 containing a plurality of pixel transistors 30 is formed on the TFT substrate 5 as a component related to driving the pixel wiring 11 (see reference). Figure 9 ).

[0190] <5.1 Composition of the Sampling Circuit>

[0191] Figure 39 This is a circuit diagram showing the configuration of the sampling circuit 60 in this embodiment. A switch control signal ASW and data signals DATA(1) to DATA(960) are supplied to the sampling circuit 60 via signal wiring group 51. Figure 39 As shown, the sampling circuit 60 includes 960 pixel transistors 30(1) to 30(960). For each pixel transistor 30, a switch control signal ASW is supplied to the control terminal, a corresponding data signal DATA is supplied to the first on terminal, and the second on terminal is connected to the corresponding pixel wiring 11. Figure 39 It can be seen that the same switch control signal ASW is supplied to the control terminals of the 960 pixel transistors 30(1) to 30(960), and different data signals DATA(1) to DATA(960) are supplied to the first conduction terminals of the 960 pixel transistors 30(1) to 30(960).

[0192] In the configuration described above, such as Figure 40 As shown, if the switch control signal SW changes from low to high at time t01, then the 960 pixel transistors 30(1) to 30(960) change from the off state to the on state. Furthermore, at... Figure 40 During the period marked with reference numeral T1, data signals DATA(1) to DATA(960) are sampled, and the sampled data signals DATA(1) to DATA(960) are applied to pixel wirings 11(1) to 11(960) as data signals SL(1) to SL(960), respectively. In this embodiment, data signals SL are supplied to all pixel electrodes 12 within the display area 10 together.

[0193] <5.2 Effects>

[0194] According to this embodiment, only the sampling circuit 60 is formed on the TFT substrate 5 as a component related to driving the pixel wiring 11. Therefore, compared with the first to fourth embodiments, the size of the bezel area can be significantly reduced.

[0195] <6. Sixth Implementation Method>

[0196] The sixth embodiment will be described. In this embodiment, similar to the fifth embodiment, the driving circuit 40 for driving the pixel transistors 30 is not formed on the TFT substrate 5. That is, as in the seventh example described above, a sampling circuit 60 containing a plurality of pixel transistors 30 is formed on the TFT substrate 5 as a component related to driving the pixel wiring 11 (see reference). Figure 9 ).

[0197] <6.1 Composition of the Sampling Circuit>

[0198] Figure 41 This is a circuit diagram showing the configuration of the sampling circuit 60 in this embodiment. Switch control signals ASW1-ASW3 and data signals DATA(1)-DATA(320) are supplied to the sampling circuit 60 via signal wiring group 51. Figure 41 As shown, the sampling circuit 60 includes 960 pixel transistors 30(1) to 30(960). (As shown by...) Figure 41 As can be seen, in this embodiment, the 960 pixel transistors 30(1) to 30(960) are grouped in groups of three. Setting m to an integer greater than or equal to 1 and less than 320, a switch control signal ASW1 is supplied to the control terminal of pixel transistor 30(3m-2), a switch control signal ASW2 is supplied to the control terminal of pixel transistor 30(3m-1), and a switch control signal ASW3 is supplied to the control terminal of pixel transistor 30(3m). Thus, different signals are supplied as switch control signals to the control terminals of the three pixel transistors 30 forming the same group. Furthermore, for each pixel transistor 30, a corresponding data signal DATA is supplied to its first conduction terminal, and its second conduction terminal is connected to the corresponding pixel wiring 11. However, for the first conduction terminals of the three pixel transistors 30 forming the same group, a single data signal DATA is supplied in a time-division manner. In addition, while in this embodiment, the grouping is done in groups of three pixel transistors 30, it is also possible to set Z to an integer greater than or equal to 2, and group the pixel transistors 30 in groups of Z.

[0199] In the configuration described above, such as Figure 42 As shown, the three switch control signals ASW1 to SWS3 sequentially become high at predetermined intervals. First, when switch control signal ASW1 changes from low to high at time t11, the 320 pixel transistors 30(3m-2) change from the off state to the on state. Then, at... Figure 42 During the period marked T21, data signals DATA(1) to DATA(320) are sampled, and the sampled data signals DATA(1) to DATA(320) are applied as data signals SL(1), SL(4), ..., SL(955) and SL(958) to pixel wirings 11(1), 11(4), ..., 11(955) and 11(958), respectively. Then, if at time tl2, the switch control signal ASW2 changes from low to high, the 320 pixel transistors 30(3m-1) change from the off state to the on state. Then, in... Figure 42 During the period marked T22, data signals DATA(1) to DATA(320) are sampled, and the sampled data signals DATA(1) to DATA(320) are applied as data signals SL(2), SL(5), ..., SL(956), SL(959) to pixel wirings 11(2), 11(5), ..., 11(956), 11(959), respectively. Finally, if at time t13, the switch control signal ASW3 changes from low to high, the 320 pixel transistors 30(3m) change from the off state to the on state. Then, in Figure 42 During the period marked with reference numeral T23, data signals DATA(1) to DATA(320) are sampled, and the sampled data signals DATA(1) to DATA(320) are applied to pixel wirings 11(3), 11(6), ..., 11(957) and 11(960) as data signals SL(3), SL(6), ..., SL(957) and SL(960), respectively.

[0200] <6.2 Effects>

[0201] According to this embodiment, similar to the fifth embodiment, only the sampling circuit 60 is formed on the TFT substrate 5 as a component related to driving the pixel wiring 11. Therefore, compared to the first to fourth embodiments, the size of the bezel area can be significantly reduced. Furthermore, since the sampling of the data signal DATA applied to the pixel wiring 11 is performed in a time-division manner, the number of signal wirings required for transmitting the data signal DATA is less than in the fifth embodiment. Therefore, the size of the bezel area used for signal wiring can be reduced.

[0202] <7. Other>

[0203] The present invention has been described in detail above, but the description is illustrative in all respects and is not restrictive. It will be understood that many other modifications and variations can be conceived without departing from the scope of the invention. For example, in the above description, a liquid crystal display device included in a dual-layer display has been used as an example, but the present invention is also applicable to other liquid crystal display devices.

[0204] Explanation of reference numerals in the attached figures

[0205] 5…TFT substrate

[0206] 10… Display area

[0207] 11…pixel wiring;

[0208] 12…pixel electrodes

[0209] 20… Input pad group

[0210] 21… Input pad

[0211] 30… pixel transistors

[0212] 40…Driver Circuit

[0213] 41… Shift Register

[0214] 42…Latch section

[0215] 43…Decoder (Decoding Circuit)

[0216] 51…Signal cabling group

[0217] 60, 80… sampling circuit

[0218] 70…Polarity switching circuit

[0219] 71… Polarity Control Department

[0220] 81…Unit sampling section

[0221] 100… Display device (dual-layer display)

[0222] 110… Organic EL Display Device

[0223] 120… LCD display device

[0224] 130… Phase Difference Plate

[0225] 140…Polarizing plate

[0226] 422…Latch circuit< / n>

Claims

1. A liquid crystal display device comprising a panel substrate, the panel substrate having a display area including a plurality of pixel electrodes, characterized in that the liquid crystal display device includes: Multiple pixel transistors are disposed in regions outside the display area that correspond one-to-one with the multiple pixel electrodes; Multiple pixel wirings, which respectively connect the multiple pixel electrodes and the multiple pixel transistors; An input pad group is provided on the panel substrate, and a group of drive signals for driving the plurality of pixel transistors is input. as well as A driving circuit that drives the plurality of pixel transistors based on the driving signal group. The plurality of pixel transistors are disposed only in the area on the panel substrate, outside the area between the input pad group and the display area. The driving circuit is disposed in a region on the panel substrate other than between the input pad group and the display area, such that the plurality of pixel transistors are disposed in the region between the driving circuit and the display area. The driving circuit includes a decoding circuit, which has multiple output sections. The multiple output units will output the multiple decoded signals that are activated sequentially as multiple timing signals. The driving signal group is used to acquire multiple data signals based on the multiple timing signals.

2. The liquid crystal display device according to claim 1, characterized in that, The panel substrate has a rectangular shape formed by a first side, a second side, a third side, and a fourth side. The second side is opposite to the first side, the third side connects one end of the first side and one end of the second side, and the fourth side connects the other end of the first side and the other end of the second side. The input pad group is disposed on the panel substrate in a border area along the first side. The plurality of pixel transistors are not disposed in the border region along the first side, but are disposed in at least one of the border regions along the second side, the border region along the third side, and the border region along the fourth side.

3. The liquid crystal display device according to claim 2, characterized in that, The plurality of pixel transistors are configured such that, for all of the plurality of pixel wirings, the direction of extension from the pixel transistor to the pixel electrode is the same.

4. The liquid crystal display device according to claim 3, characterized in that, The plurality of pixel transistors are disposed only in the border area along the second side.

5. The liquid crystal display device according to claim 3, characterized in that, The plurality of pixel transistors are disposed only in one of the border regions along the third side or along the border region along the fourth side.

6. The liquid crystal display device according to claim 2, characterized in that, The plurality of pixel transistors are disposed in the border region along the third side and the border region along the fourth side. The multiple pixel wirings consist of multiple first-type pixel wirings and multiple second-type pixel wirings. The multiple first-type pixel wirings connect the pixel transistors and their corresponding pixel electrodes located in the border area along the third side. The multiple second-type pixel wirings connect the pixel transistors and their corresponding pixel electrodes located in the border area along the fourth side.

7. The liquid crystal display device according to claim 1, characterized in that, The panel substrate has a circular shape. Based on the second virtual line, the plurality of pixel transistors are set only in the border area on the side where the display area exists. The second virtual line is a virtual line that passes through the connection point of the first virtual line and the display area and is orthogonal to the first virtual line. The first virtual line is the shortest virtual line connecting the display area and the input pad group.

8. The liquid crystal display device according to claim 7, characterized in that, The plurality of pixel transistors are configured such that, for all of the plurality of pixel wirings, the direction of extension from the pixel transistor to the pixel electrode is the same.

9. The liquid crystal display device according to claim 8, characterized in that, Based on the third virtual line, the plurality of pixel transistors are provided only in the border area on the side where the input pad group does not exist. The third virtual line is a virtual line that passes through the center of the display area and is parallel to the second virtual line.

10. The liquid crystal display device according to claim 8, characterized in that, Based on the fourth virtual line, the plurality of pixel transistors are provided only in the border area on one side. The fourth virtual line is a virtual line connecting the first virtual line and the display area to the center of the display area.

11. The liquid crystal display device according to claim 7, characterized in that, The plurality of pixel transistors are disposed on both sides of the border area on one side and the border area on the other side, with reference to the fourth virtual line, which is a virtual line passing through the connection point of the first virtual line and the display area and the center of the display area. The multiple pixel wirings include multiple first-type pixel wirings and multiple second-type pixel wirings. The multiple first-type pixel wirings connect pixel transistors and their corresponding pixel electrodes in the border area on one side, with the fourth virtual line as a reference. The multiple second-type pixel wirings connect pixel transistors and their corresponding pixel electrodes in the border area on the other side, with the fourth virtual line as a reference.

12. The liquid crystal display device according to claim 6 or 11, characterized in that, The number of the plurality of first-type pixel wirings is the same as the number of the plurality of second-type pixel wirings.

13. The liquid crystal display device according to claim 1, characterized in that, M is an integer greater than or equal to 2, and the driving circuit contains M latch circuits for each timing signal. The M latch circuits take in M ​​data signals based on the corresponding timing signals and output the taken in M ​​data signals.

14. The liquid crystal display device according to claim 13, characterized in that, The liquid crystal display device includes a polarity switching circuit comprising a plurality of pixel transistors. The polarity switching circuit is used to switch the polarity of the voltage applied to the plurality of pixel electrodes at predetermined intervals. The polarity switching circuit is composed of multiple polarity control units, each corresponding to one of the multiple pixel wirings. Each polarity control unit includes a first pixel transistor and a second pixel transistor, whose on / off states change in opposite directions based on data signals output from corresponding latch circuits. In each polarity control unit, between the first level and the second level, a first voltage and a second voltage whose voltage levels change in opposite directions during each specified period are supplied. When the first pixel transistor is in the ON state, the first voltage is applied to the corresponding pixel electrode via the corresponding pixel wiring. When the second pixel transistor is in the on state, the second voltage is applied to the corresponding pixel electrode via the corresponding pixel wiring.

15. The liquid crystal display device according to claim 1, characterized in that, The liquid crystal display device includes a sampling circuit, which includes the plurality of pixel transistors. The plurality of pixel transistors are grouped in such a way that K pixel transistors form a group, where K is an integer greater than or equal to 2. Each pixel transistor has a control terminal that receives a corresponding timing signal, a first conduction terminal that receives a corresponding data signal, and a second conduction terminal that is connected to the corresponding pixel wiring. The same timing signal is supplied to the control terminals of the K pixel transistors that form the same group. Different data signals are supplied to the first conducting terminals of K pixel transistors that form the same group.

16. A liquid crystal display device comprising a panel substrate having a display area including a plurality of pixel electrodes, characterized in that the liquid crystal display device includes: Multiple pixel transistors are disposed in regions outside the display area that correspond one-to-one with the multiple pixel electrodes; Multiple pixel wirings, which respectively connect the multiple pixel electrodes and the multiple pixel transistors; An input pad group is provided on the panel substrate, and a group of drive signals for driving the plurality of pixel transistors is input. as well as A driving circuit that drives the plurality of pixel transistors based on the driving signal group. The plurality of pixel transistors are disposed only in the area on the panel substrate, outside the area between the input pad group and the display area. The driving circuit is disposed in a region on the panel substrate other than between the input pad group and the display area, such that the plurality of pixel transistors are disposed in the region between the driving circuit and the display area. The driving circuit includes a shift register composed of multiple unit circuits connected in series. The multiple unit circuits will sequentially activate multiple output signals and output them as multiple timing signals. Based on the multiple timing signals, the multiple data signals contained in the drive signal group are acquired. M is an integer greater than or equal to 2, and the driving circuit contains M latch circuits for each timing signal. The M latch circuits take in M ​​data signals based on the corresponding timing signals and output the taken in M ​​data signals.

17. The liquid crystal display device according to claim 16, characterized in that, The liquid crystal display device includes a polarity switching circuit comprising a plurality of pixel transistors. The polarity switching circuit is used to switch the polarity of the voltage applied to the plurality of pixel electrodes at predetermined intervals. The polarity switching circuit is composed of multiple polarity control units, each corresponding to one of the multiple pixel wirings. Each polarity control unit includes a first pixel transistor and a second pixel transistor, whose on / off states change in opposite directions based on data signals output from corresponding latch circuits. In each polarity control unit, between the first level and the second level, a first voltage and a second voltage whose voltage levels change in opposite directions during each specified period are supplied. When the first pixel transistor is in the ON state, the first voltage is applied to the corresponding pixel electrode via the corresponding pixel wiring. When the second pixel transistor is in the on state, the second voltage is applied to the corresponding pixel electrode via the corresponding pixel wiring.

18. A liquid crystal display device comprising a panel substrate having a display area including a plurality of pixel electrodes, characterized in that the liquid crystal display device includes: Multiple pixel transistors are disposed in regions outside the display area that correspond one-to-one with the multiple pixel electrodes; Multiple pixel wirings, which respectively connect the multiple pixel electrodes and the multiple pixel transistors; An input pad group is provided on the panel substrate, and a group of drive signals for driving the plurality of pixel transistors is input. A driving circuit that drives the plurality of pixel transistors based on the driving signal group; as well as The sampling circuit includes the plurality of pixel transistors. The plurality of pixel transistors are disposed only in the area on the panel substrate, outside the area between the input pad group and the display area. The driving circuit is disposed in a region on the panel substrate other than between the input pad group and the display area, such that the plurality of pixel transistors are disposed in the region between the driving circuit and the display area. The driving circuit includes a shift register composed of multiple unit circuits connected in series. The multiple unit circuits will sequentially activate multiple output signals and output them as multiple timing signals. Based on the multiple timing signals, the multiple data signals contained in the drive signal group are acquired. The plurality of pixel transistors are grouped in such a way that K pixel transistors form a group, where K is an integer greater than or equal to 2. Each pixel transistor has a control terminal that receives a corresponding timing signal, a first conduction terminal that receives a corresponding data signal, and a second conduction terminal that is connected to the corresponding pixel wiring. The same timing signal is supplied to the control terminals of the K pixel transistors that form the same group. Different data signals are supplied to the first conducting terminals of K pixel transistors that form the same group.

Images