Integral modulation circuit

Abstract

This application provides an integral modulation circuit for use in a summation-integration analog-to-digital conversion circuit, including a signal input terminal, a chopper clock circuit, a cascaded multi-stage integral operational amplifier circuit, and a chopper circuit. The signal input terminal is used to input a sampled signal. The chopper clock circuit generates a multi-order chopper clock signal. The first-stage integral operational amplifier circuit at the beginning of the multi-stage integral operational amplifier circuit receives the sampled signal. The chopper circuit includes a first chopper circuit and a second chopper circuit, which are respectively connected to the input and output terminals of the first-stage integral operational amplifier circuit and are both connected to the chopper clock circuit. Under the action of the first chopper circuit, the second chopper circuit, and the chopper clock signal, the signal transmission path of the sampled signal input to the first-stage integral operational amplifier circuit is changed in the multi-stage integral operational amplifier circuit. This eliminates or reduces the DC offset of the integral operational amplifier circuit, thereby improving the signal-to-noise ratio of the entire integral modulation circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an integral modulation circuit. Background Technology

[0002] In addition to quantization noise and thermal noise, summation-integral analog-to-digital converter circuits also suffer from non-ideal factors such as DC offset of the operational amplifier circuit and low-frequency 1 / f noise. The signal-to-noise ratio of the integral modulation circuit decreases due to the presence of DC offset of the operational amplifier circuit and low-frequency 1 / f noise. Summary of the Invention

[0003] This application provides an integral modulation circuit that can eliminate DC offset of an integral operational amplifier circuit.

[0004] This application provides an integral modulation circuit for use in a summation-integration analog-to-digital conversion circuit, comprising:

[0005] The signal input terminal is used to input the sampling signal;

[0006] Chopper clock circuit, used to generate multi-stage chopper clock signals;

[0007] A cascaded multi-stage integrating operational amplifier circuit, wherein the first-stage integrating operational amplifier circuit at the beginning of the multi-stage integrating operational amplifier circuit is connected to the signal input terminal and the chopper clock circuit; the first-stage integrating operational amplifier circuit is used to receive the sampled signal; and

[0008] The chopper circuit includes a first chopper circuit and a second chopper circuit. The first chopper circuit and the second chopper circuit are respectively connected to the input terminal and the output terminal of the first-stage integrating operational amplifier circuit, and both are connected to the chopper clock circuit. Under the action of the first chopper circuit, the second chopper circuit and the chopper clock signal, the signal transmission path of the sampling signal input to the first-stage integrating operational amplifier circuit is changed in the multi-stage integrating operational amplifier circuit.

[0009] Optionally, the number of orders of the chopping clock signal is greater than or equal to the number of stages of the integrating operational amplifier circuit; or

[0010] The number of orders of the chopper clock signal is equal to the number of stages of the integrating operational amplifier circuit.

[0011] Optionally, the first chopper circuit includes a first chopper switch, and the second chopper circuit includes a second chopper switch; the integral modulation circuit further includes a master clock circuit for generating a master clock signal; the first chopper switch and the second chopper switch switch are switched under the action of the master clock signal, and under the action of the chopper clock signal, the sampling signal transmits at least a plurality of cycles of the master clock signal in the multi-stage integral operational amplifier circuit.

[0012] Optionally, the chopper clock circuit is used to generate at least m-order chopper clock signals, and the sampling signal at the input of the first-stage integrating operational amplifier circuit transmits at least N cycles of the master clock signal in the multi-stage integrating operational amplifier circuit; where m is greater than or equal to 4, and N / 2m is an integer.

[0013] Optionally, the signal input terminal includes a non-inverting sampling input terminal and an inverting sampling input terminal; the integral modulation circuit further includes a sampling circuit, including a sampling switching switch; the sampling switching switch includes a first sampling switching switch and a second sampling switching switch, the first sampling switching switch being connected between the non-inverting sampling input terminal and the first input terminal of the first chopper circuit and between the inverting sampling input terminal and the second input terminal of the first chopper circuit; the second sampling switching switch being connected between the inverting sampling input terminal and the first input terminal of the first chopper circuit and between the non-inverting sampling input terminal and the second input terminal of the first chopper circuit.

[0014] The chopper clock signal includes a first chopper clock signal and a second chopper clock signal; the chopper clock circuit is used to generate the first chopper clock signal synchronized with the switching signal of the first sampling switch at the rising edge of each master clock signal; and to generate the second chopper clock signal synchronized with the switching signal of the second sampling switch when each master clock signal switches from rising edge to falling edge.

[0015] Optionally, the chopper clock circuit includes a first clock output terminal and a second clock output terminal. The first clock output terminal is connected between the first output terminal of the first chopper circuit and the non-inverting input terminal of the first-stage integrating operational amplifier circuit, and is also connected to the first output terminal of the second chopper circuit. The second clock output terminal is connected between the second output terminal of the first chopper circuit and the inverting input terminal of the first-stage integrating operational amplifier circuit, and is also connected to the second output terminal of the second chopper circuit.

[0016] When the first sampling switch is turned on, the first chopper clock signal generated by the chopper clock circuit is at a high level, and this high level is output through the first clock output terminal; when the second sampling switch is turned off, the second chopper clock signal generated by the chopper clock circuit is at a low level, and this low level is output through the second clock output terminal; or

[0017] When the first sampling switch is off, the first chopper clock signal generated by the chopper clock circuit is at a low level, and this low level is output through the second clock output terminal; when the second sampling switch is on, the second chopper clock signal generated by the chopper clock circuit is at a high level, and this high level is output through the first clock output terminal.

[0018] Optionally, the signal input terminal includes a non-inverting sampling input terminal and an inverting sampling input terminal; the integral modulation circuit further includes a sampling circuit, including a sampling switching switch, a sampling capacitor, and a sampling phase switch. The sampling switching switch is connected to the non-inverting sampling input terminal, the inverting sampling input terminal, and the sampling capacitor, and the sampling phase switch is connected to the sampling capacitor. The sampling switching switch and the sampling phase switch are switched under the action of the master clock signal, so that the sampling capacitor alternately integrates and samples the sampling signals input to the non-inverting sampling input terminal and the inverting sampling input terminal.

[0019] Optionally, the sampling switching switch includes a first sampling switching switch and a second sampling switching switch; the sampling phase switch includes a first sampling phase switch and a second sampling phase switch;

[0020] Within one cycle of the master clock signal, the second sampling switching switch and the first sampling phase switch are synchronously turned on or off; or

[0021] Within one cycle of the master clock signal, the first sampling switching switch and the second sampling phase switch are synchronously turned on or off.

[0022] Optionally, the sampling switching switch includes a first sampling switching switch and a second sampling switching switch, and the sampling capacitor includes a first sampling capacitor and a second sampling capacitor; the first sampling switching switch is connected between the non-inverting sampling input terminal and the first sampling capacitor and between the inverting sampling input terminal and the second sampling capacitor; the second sampling switching switch is connected between the inverting sampling input terminal and the first sampling capacitor and between the non-inverting sampling input terminal and the second sampling capacitor; within one cycle of the master clock signal, one of the first sampling switching switch and the second sampling switching switch is turned on, and the other is turned off.

[0023] Optionally, the integral modulation circuit includes a reset node; the sampling phase switch includes a first sampling phase switch and a second sampling phase switch; the first sampling phase switch is connected between the first sampling capacitor and the reset node and between the second sampling capacitor and the reset node; the second sampling phase switch is connected between the first sampling capacitor and the first input terminal of the first chopper circuit and between the second sampling capacitor and the second input terminal of the first chopper circuit; within one cycle of the master clock signal, one of the first sampling phase switch and the second sampling phase switch is turned on, and the other is turned off.

[0024] Optionally, the integral modulation circuit further includes an integrating capacitor connected to the first-stage integral operational amplifier circuit; the signal input terminal further includes a positive feedback input terminal and an inverting feedback input terminal; the integral modulation circuit further includes a feedback circuit connected to the positive feedback input terminal and the inverting feedback input terminal, the feedback circuit including a feedback switching switch, a feedback capacitor and a feedback synchronization switch, the feedback switching switch being connected to the positive feedback input terminal, the inverting feedback input terminal and the feedback capacitor, the feedback capacitor being connected to the feedback synchronization switch, and the feedback synchronization switch being connected to the integrating capacitor; the feedback switching switch and the feedback synchronization switch are switched under the action of the master clock signal, so that the feedback capacitor alternately integrates and feeds back the feedback signals input to the positive feedback input terminal and the inverting feedback input terminal.

[0025] Optionally, the sampling phase switch includes a first sampling phase switch and a second sampling phase switch; the feedback switching switch includes a first feedback switching switch and a second feedback switching switch;

[0026] Within one cycle of the master clock signal, the first feedback switching switch is turned on or off relative to the first sampling phase switch after a preset time delay; or

[0027] Within one cycle of the master clock signal, the second feedback switching switch is either turned off or turned on relative to the second sampling phase switch after a preset time period.

[0028] Optionally, the sampling phase switch includes a first sampling phase switch; the feedback synchronization switch includes a first feedback synchronization switch and a second feedback synchronization switch; the chopper clock circuit includes a first clock output terminal and a second clock output terminal; the integral modulation circuit further includes a quantizer connected to the second chopper circuit and the integral capacitor, and the first input terminal of the quantizer is connected to the first clock output terminal, and the second input terminal of the quantizer is connected to the second clock output terminal.

[0029] The first feedback synchronization switch is turned on or off under the OR-NOT logic action of the output signal at the first output terminal of the quantizer and the switching signal of the first sampling phase switch; or

[0030] The second feedback synchronization switch is turned on or off under the AND-NOT logic action of the output signal at the second output terminal of the quantizer and the switching signal of the first sampling phase switch.

[0031] Optionally, the feedback switching switch includes a first feedback switching switch and a second feedback switching switch, and the feedback capacitor includes a first feedback capacitor and a second feedback capacitor; the first feedback switching switch is connected between the positive feedback input terminal and the first feedback capacitor and between the negative feedback input terminal and the second feedback capacitor; the second feedback switching switch is connected between the negative feedback input terminal and the first feedback capacitor and between the positive feedback input terminal and the second feedback capacitor; within one cycle of the master clock signal, one of the first feedback switching switch and the second feedback switching switch is turned on, and the other is turned off.

[0032] Optionally, the integrating capacitor includes a first integrating capacitor and a second integrating capacitor; the feedback synchronization switch includes a first feedback synchronization switch and a second feedback synchronization switch; the first feedback synchronization switch is connected between the first feedback capacitor and the first integrating capacitor and between the second feedback capacitor and the second integrating capacitor; the second feedback synchronization switch is connected between the first feedback capacitor and the second integrating capacitor and between the second feedback capacitor and the first integrating capacitor; within one cycle of the master clock signal, one of the first feedback synchronization switch and the second feedback synchronization switch is turned on, and the other is turned off.

[0033] The integral modulation circuit of this application embodiment is applied to a summation integral analog-to-digital conversion circuit. By setting up a chopper clock circuit, a chopper circuit, and a cascaded multi-stage integral operational amplifier circuit, the first and second chopper circuits of the chopper circuit are respectively connected to the input and output terminals of the first-stage integral operational amplifier circuit located at the beginning of the multi-stage integral operational amplifier circuit, and both are connected to the chopper clock circuit. Under the action of the first chopper circuit, the second chopper circuit, and the chopper clock signal, the signal transmission path of the sampling signal input to the first-stage integral operational amplifier circuit is changed in the multi-stage integral operational amplifier circuit, so as to eliminate or reduce the DC offset of the integral operational amplifier circuit, thereby improving the signal-to-noise ratio of the entire integral modulation circuit.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0036] Figure 1 The diagram shown is a schematic block diagram of one embodiment of the integral modulation circuit of this application.

[0037] Figure 2 As shown Figure 1 The circuit diagram of the integral modulation circuit shown is shown.

[0038] Figure 3 As shown Figure 2 The diagram shows the principle of eliminating offset using chopping technology in the integral modulation circuit.

[0039] Figure 4 As shown Figure 2 The timing diagram of the master clock signal of the master clock circuit of the integral modulation circuit and the fourth-order chopper clock signal of the chopper clock circuit is shown.

[0040] Figure 5 As shown Figure 2 The timing diagram of the sampling switching switch, sampling phase switch, and fourth-order chopper clock signal of the sampling circuit of the integral modulation circuit shown is presented.

[0041] Figure 6 As shown Figure 2 The timing diagrams shown are for the sampling phase switch of the sampling circuit of the integral modulation circuit, the feedback switching switch of the feedback circuit, the fourth-order chopper clock signal of the chopper clock circuit, and the master clock signal of the master clock circuit. Detailed Implementation

[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0043] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in this application should be understood in their ordinary sense by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "a" or "one," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and / or "upper," etc., are for ease of description only and are not limited to a location or spatial orientation. The terms "comprising" or "including," etc., mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The terms "connected," "linked," etc., are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0044] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0045] This application provides an integral modulation circuit for use in a summation-integration analog-to-digital conversion circuit. The integral modulation circuit includes a signal input terminal, a chopper clock circuit, a cascaded multi-stage integral operational amplifier circuit, and a chopper circuit. The signal input terminal is used to input a sampled signal. The chopper clock circuit is used to generate a multi-order chopper clock signal. The first-stage integral operational amplifier circuit at the beginning of the multi-stage integral operational amplifier circuit is connected to the signal input terminal and the chopper clock circuit; the first-stage integral operational amplifier circuit is used to receive the sampled signal. The chopper circuit includes a first chopper circuit and a second chopper circuit, which are respectively connected to the input and output terminals of the first-stage integral operational amplifier circuit, and both are connected to the chopper clock circuit; under the action of the first chopper circuit, the second chopper circuit, and the chopper clock signal, the signal transmission path of the sampled signal input to the first-stage integral operational amplifier circuit is changed in the multi-stage integral operational amplifier circuit.

[0046] The integral modulation circuit of this application embodiment is applied to a summation integral analog-to-digital conversion circuit. By setting up a chopper clock circuit, a chopper circuit, and a cascaded multi-stage integral operational amplifier circuit, the first and second chopper circuits of the chopper circuit are respectively connected to the input and output terminals of the first-stage integral operational amplifier circuit located at the beginning of the multi-stage integral operational amplifier circuit, and both are connected to the chopper clock circuit. Under the action of the first chopper circuit, the second chopper circuit, and the chopper clock signal, the signal transmission path of the sampling signal input to the first-stage integral operational amplifier circuit is changed in the multi-stage integral operational amplifier circuit, so as to eliminate or reduce the DC offset of the integral operational amplifier circuit, thereby improving the signal-to-noise ratio of the entire integral modulation circuit.

[0047] This application provides an integral modulation circuit capable of eliminating DC offset in an integrating operational amplifier circuit and improving the signal-to-noise ratio of the entire integral modulation circuit. The integral modulation circuit of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0048] The integral modulation circuit is used in the summation-integral analog-to-digital converter (ADC). The summation-integral ADC is mainly used to achieve high-precision analog-to-digital conversion of DC or low-speed signals, and its applications include instruments, meters, and sensor readout circuits. The summation-integral ADC can have first-order, second-order, or higher-order structures. In terms of circuit structure, the summation-integral ADC also includes a reset operation; that is, the integral modulation circuit is reset to zero before converting each sampled signal. Therefore, the existence of a periodic reset operation is one of the main characteristics of the summation-integral ADC. In this embodiment, the summation-integral ADC can be a Sigma-delta ADC.

[0049] Figure 1 The diagram shown is a schematic block diagram of one embodiment of the integral modulation circuit 1 of this application. Figure 1As shown, the integral modulation circuit 1 includes a signal input terminal 11, a chopper clock circuit 12, a cascaded multi-stage integral operational amplifier circuit 13, and a chopper circuit 14. The signal input terminal 11 is used to input the sampling signal. The chopper clock circuit 12 is used to generate a multi-stage chopper clock signal. The first-stage integral operational amplifier circuit 131, located at the beginning of the multi-stage integral operational amplifier circuit 13, is connected to the signal input terminal 11 and the chopper clock circuit 12. The first-stage integral operational amplifier circuit 131 is used to receive the sampling signal. The chopper circuit 14 includes a first chopper circuit 141 and a second chopper circuit 142, which are respectively connected to the input and output terminals of the first-stage integral operational amplifier circuit 131, and both are connected to the chopper clock circuit 12. Under the action of the first chopper circuit 141, the second chopper circuit 142, and the chopper clock signal, the signal transmission path of the sampling signal input to the first-stage integral operational amplifier circuit 131 is changed within the multi-stage integral operational amplifier circuit 13.

[0050] The multi-stage integrating operational amplifier circuit 13 includes two or more stages of integrating operational amplifier circuits. In this embodiment, the multi-stage integrating operational amplifier circuit 13 includes four cascaded integrating operational amplifier circuits. The multi-stage integrating operational amplifier circuit 13 includes a first-stage integrating operational amplifier circuit 131 located at the beginning. In addition, the multi-stage integrating operational amplifier circuit 13 also includes a second-stage integrating operational amplifier circuit (not shown in the figure), a third-stage integrating operational amplifier circuit (not shown in the figure), and a fourth-stage integrating operational amplifier circuit (not shown in the figure), which are cascaded sequentially after the first-stage integrating operational amplifier circuit 131. In some other embodiments, the multi-stage integrating operational amplifier circuit 13 also includes four or more stages of integrating operational amplifier circuits 13, which is not limited in this application.

[0051] Since the noise of the first-stage integrating operational amplifier circuit 131 has the greatest impact on the performance of the integrating modulation circuit 1, it is necessary to improve the first-stage integrating operational amplifier circuit 131 to mitigate the impact of low-frequency noise on the signal-to-noise ratio. In this embodiment, after the signal input terminal 11 receives the sampling signal, the sampling signal first passes through the first chopper circuit 141 and is transmitted from the first-stage integrating operational amplifier circuit 131. Then it passes through the second chopper circuit 142, and is subsequently transmitted in the second-stage, third-stage, and fourth-stage integrating operational amplifier circuits. During the above transmission process, under the combined action of the first chopper circuit 141, the second chopper circuit 142, and the chopper clock signal, the signal transmission path of the sampling signal in the first-stage integrating operational amplifier circuit 131 is changed. Similarly, when the sampling signal is transmitted in the second-stage, third-stage, and fourth-stage integrating operational amplifier circuits cascaded after the second chopper circuit 142, its signal transmission path is also changed synchronously.

[0052] With this configuration, the first chopper circuit 141 and the second chopper circuit 142 are respectively located at the input and output terminals of the first-stage integrating operational amplifier circuit 131, and a chopper clock circuit 12 is set to generate a chopper clock signal. Under the combined action of the first chopper circuit 141, the second chopper circuit 142, and the chopper clock signal, the sampling signal input to the signal input terminal 11 changes the signal transmission path in the multi-stage integrating operational amplifier circuit 13. This eliminates or reduces the DC offset of the integrating operational amplifier circuit 13, balances the input and output signals of the multi-stage integrating operational amplifier circuit 13, and improves the signal-to-noise ratio of the entire integrating modulation circuit 1.

[0053] In some embodiments, the chopper clock circuit 12 generates at least two or more chopper clock signals. In some embodiments, the number of orders of the chopper clock signals is greater than or equal to the number of stages of the integrating operational amplifier circuit. This configuration ensures that the sampling signal input to the signal input terminal 11, under the combined action of the multi-order chopper clock signals generated by the first chopper circuit 141, the second chopper circuit 142, and the chopper clock circuit 12, can change the signal transmission path in all the integrating operational amplifier circuits 13 in the multi-stage integrating operational amplifier circuit 13. This can better eliminate or reduce the DC offset of the integrating operational amplifier circuit 13, and even more thoroughly eliminate the DC offset of the integrating operational amplifier circuit 13. This avoids the problem that the signal transmission path in some of the integrating operational amplifier circuits 13 is not changed due to the small number of orders of the chopper clock signals, and avoids the problem that the elimination or reduction of the DC offset of the integrating operational amplifier circuit 13 is not effective or not thorough enough.

[0054] In this embodiment, the number of orders of the chopping clock signal is equal to the number of stages of the integrating operational amplifier circuit. With this configuration, the sampling signal input to the signal input terminal 11, under the combined action of the multi-order chopping clock signals generated by the first chopping circuit 141, the second chopping circuit 142, and the chopping clock circuit 12, alters the signal transmission paths in all the integrating operational amplifier circuits 13 within the multi-stage integrating operational amplifier circuit. This improves or even more thoroughly the elimination or reduction of DC offset in the integrating operational amplifier circuit 13, achieving a balance between the input and output signals of the multi-stage integrating operational amplifier circuit 13, thereby improving the signal-to-noise ratio of the entire integrating modulation circuit 1. Furthermore, the circuit structure is compact and non-redundant.

[0055] Ideally, the voltages at both input terminals of the integrating operational amplifier circuit 13 should be 0V, and therefore the voltage at its output terminal should also be 0V. However, in practical applications, there is always some voltage at the output terminal of the integrating operational amplifier circuit 13; this voltage is the DC offset voltage VOS. Dividing the DC offset voltage at the output terminal of the integrating operational amplifier circuit 13 by the noise gain in the circuit yields the input offset voltage or the input reference offset voltage. The DC offset voltage VOS is equivalent to a voltage source connected in series with the inverting input terminal of the integrating operational amplifier circuit 13. Therefore, in this embodiment, a differential voltage is applied to the two input terminals of the first-stage integrating operational amplifier circuit 131 to generate a 0V output.

[0056] To overcome the influence of DC offset voltage, this embodiment sets up a first chopper circuit 141 and a second chopper circuit 142 at the input and output terminals of the integrating operational amplifier circuit 13, respectively. A chopper clock circuit 12 generates a chopper clock signal. By continuously switching the differential input of the integrating operational amplifier circuit 13 using chopping technology, the positive and negative polarities of the DC offset voltage VOS are dynamically switched at the input terminals of the integrating operational amplifier circuit 13. This can be understood as the voltage at the input terminal of the integrating operational amplifier circuit 13 switching between VIN+VOS and VIN-VOS, thus forming a differential voltage. By setting up the chopper clock circuit 12, the first chopper circuit 141, and the second chopper circuit 142, and using the chopper clock signal generated by the chopper clock circuit 12, the differential signal is transmitted under the combined action of the first chopper circuit 141, the second chopper circuit 142, and the chopper clock signal. This balances the input and output voltages of the integrating operational amplifier circuit 13, eliminating the DC offset of the integrating operational amplifier circuit 13 and thereby improving the signal-to-noise ratio of the entire integrating modulation circuit. In addition to setting the first chopper circuit 141 and the second chopper circuit 142 at the input and output terminals of the integrating operational amplifier circuit 13, this embodiment only requires setting the chopper clock circuit 12, which can reduce the circuit design, avoid increasing the area of ​​the processor or detector, and also reduce the input voltage of the integrating operational amplifier circuit 13 and reduce the input impedance of the integrating operational amplifier circuit 13.

[0057] Figure 2 As shown Figure 1 The circuit diagram of the integral modulation circuit 1 shown is shown. Figure 3 As shown Figure 2 The schematic diagram shown is a schematic diagram of the chopping technique used by the integral modulation circuit 1 to eliminate offset. Figure 4 As shown Figure 2 The timing diagram shown is of the master clock signal of the master clock circuit 20 of the integral modulation circuit 1 and the fourth-order chopper clock signal of the chopper clock circuit 12. Combined with... Figures 1 to 4As shown, the first chopper circuit 141 includes a first chopper switch (not shown). The second chopper circuit 142 includes a second chopper switch (not shown). The integral modulation circuit 1 also includes a master clock circuit 20 for generating a master clock signal CLK. The first and second chopper switches switch under the action of the master clock signal, and under the action of the chopper clock signal, the sampled signal is transmitted in the multi-stage integral operational amplifier circuit 13 for at least a number of master clock signal cycles. Under the action of the master clock signal, the sampled signal is transmitted in the multi-stage integral operational amplifier circuit 13, and after the sampled signal has transmitted in the multi-stage integral operational amplifier circuit 13 for at least a number of master clock signal cycles, the DC offset of the integral operational amplifier circuit 13 can be completely eliminated or reduced, so that the input signal and output signal of the multi-stage integral operational amplifier circuit 13 are balanced, thereby improving the signal-to-noise ratio of the entire integral modulation circuit 1.

[0058] In some embodiments, the chopper clock circuit 12 is used to generate at least an m-order chopper clock signal, and the sampled signal at the input of the first-stage integrating operational amplifier circuit 131 transmits at least N cycles of the main clock signal in the multi-stage integrating operational amplifier circuit 13; where m is greater than or equal to 4 and N / 2 m The value is an integer. In this embodiment, the chopper clock circuit 12 is used to generate at least a fourth-order chopper clock signal. The sampling signal at the input of the first-stage integrating operational amplifier circuit 131 is transmitted through the multi-stage integrating operational amplifier circuit 13 for at least four cycles of the master clock signal. After the sampling signal is transmitted through the multi-stage integrating operational amplifier circuit 13 for four or more cycles of the master clock signal, the DC offset of the integrating operational amplifier circuit 13 can be completely eliminated or reduced.

[0059] The DC offset voltage of the integrating operational amplifier circuit 13 in the integrating modulation circuit 1 is eliminated by the chopper switches in the first chopper circuit 141 and the second chopper circuit 142, which are set at the input and output terminals of the integrating operational amplifier circuit 13, operating according to the timing pattern of the fourth-order chopper clock signal. Chopping technology works by modulating low-frequency noise and offset voltage to a high frequency, demodulating the signal back to the fundamental frequency, and then filtering to eliminate the influence of low-frequency noise and offset voltage. Figures 1 to 3 As shown, the provided sampling signal is a square wave signal with a 50% duty cycle, and its Fourier expression is:

[0060]

[0061] Where the coefficient

[0062] The chopping process to eliminate misalignment includes: modulating the input Vin with a square wave M1(t), which in the time domain is the product of the two, i.e., only at f chopThere are components at odd harmonic frequencies. The modulated signal Vin·M1(t), low-frequency noise VN, and offset voltage Vos are then used together as the input signal to the first-stage integrating operational amplifier circuit 131 and amplified. The amplified output signal VA is then multiplied by M2(t) and demodulated. Therefore, the amplified Vin·M1(t) signal is demodulated to carry only f chop The even-numbered harmonic frequency components, while VN and Vos, are shifted to carry only f since they are modulated only once. chop The high-frequency components at odd harmonic frequencies. The output signal Vout is then passed through a low-pass filter with a bandwidth slightly larger than the input signal cutoff frequency fT to obtain the amplified initial signal Vin.

[0063] The output offset of each stage of the four-stage cascaded integrating operational amplifier circuit 13 is eliminated by using a fourth-order chopper clock signal with a fixed period. This application can also be applied to integrating operational amplifier circuits 13 with more than four stages. The DC offset voltage of the integrating operational amplifier circuit 13 is precisely corrected and eliminated by using a first chopper circuit 141 and a second chopper circuit 142 in conjunction with the timing of the fourth-order chopper clock signal. Compared with related technologies, which can only eliminate the DC offset of a single-stage integrating operational amplifier circuit 13, this embodiment uses chopper circuit 14 (first chopper circuit 141 and second chopper circuit 142) and a chopper clock signal to eliminate the DC offset voltage of the entire multi-stage integrating operational amplifier circuit 13 using multi-order chopping technology. This also reduces low-frequency noise by shifting it to higher frequencies, which are then filtered out by a low-pass filter, significantly reducing noise components falling within the signal bandwidth and thus improving the system signal-to-noise ratio.

[0064] Combination Figures 1 to 4 As shown, the chopper clock circuit 12 in this embodiment is used to generate at least a fourth-order chopper clock signal. The expression for the at least fourth-order chopper clock signal is: The first-order chopper clock signal is represented as: S1 = (+-); the second-order chopper clock signal is represented as: Similarly, the third-order chopper clock signal is represented as: S3 = (+--+)(-++-); the fourth-order chopper clock signal is represented as: S4 = (+--+-++-)(-++-+--+). Here, "+" and "-" represent the high and low levels of the chopper clock signal, respectively, indicating the closing and opening of the corresponding switches. ±1 is used to represent the polarity (or direction) of the chopper clock signal's timing; +1 represents the forward propagation direction of the DC offset, and -1 represents the opposite direction of the DC offset, which is complementary to the forward propagation direction, i.e., the reverse propagation direction.

[0065] Taking the fully differential first-stage integrating operational amplifier circuit 131 as an example, if +1 represents the DC offset being transmitted from the non-inverting input terminal to the non-inverting output terminal of the first-stage integrating operational amplifier circuit 131, then -1 represents the DC offset being transmitted from the inverting input terminal to the non-inverting output terminal of the first-stage integrating operational amplifier circuit 131. By setting the first chopper circuit 141, the second chopper circuit 142, and the chopper clock circuit 12, the polarity of the input and output terminals of the first-stage integrating operational amplifier circuit 131 is exchanged. The DC offset voltage VOS executed in the integrating operational amplifier circuit 13 is reversed in the signal transmission path, but the integration direction of the signal remains unchanged. It can be proven that as long as N / 2 m If the offset propagation polarity of the m integral modulation circuits 1 is determined in the order Sm, then after N cycles of the main clock signal required for the conversion, the DC offset at the output of all integral operational amplifier circuits 13 will be eliminated. For m-stage cascaded integral operational amplifier circuits 13, when the main clock signal K = 2 m When the sequence is 2K, the DC offset is completely eliminated, meaning that the DC offset of the integrating operational amplifier circuit 13 is zero after the 2Kth master clock signal period, and the period of any master clock signal that is an integer multiple of 2K can be eliminated. Therefore, in this embodiment, the fourth-order chopping technique is applied to the loop structure of the first-stage operational amplifier circuit 131 of the integrating modulation circuit 1 to eliminate the DC offset voltage in the loop of the integrating operational amplifier circuit 13. This ensures that after the sampling signal has transmitted for 16 master clock signal periods in the multi-stage integrating operational amplifier circuit 13, the DC offset of the integrating operational amplifier circuit 13 can be completely eliminated or reduced, so that the input signal and output signal of the multi-stage integrating operational amplifier circuit 13 are balanced, thereby improving the signal-to-noise ratio of the entire integrating modulation circuit 1.

[0066] Figure 5 As shown Figure 2 The timing diagram shows the sampling switching switch 151 and sampling phase switch 153 of the sampling circuit 15 of the integral modulation circuit 1, and the fourth-order chopper clock signal of the chopper clock circuit 12. (Combined with...) Figure 2 and Figure 5 As shown, the signal input terminal 11 includes a sampling signal input terminal 111. The sampling signal input terminal 111 includes a non-inverting sampling input terminal VINP and an inverting sampling input terminal VINN. The integral modulation circuit 1 also includes a sampling circuit 15, which is connected to the non-inverting sampling input terminal VINP and the inverting sampling input terminal VINN. The sampling circuit 15 receives the non-inverting sampling signal and the inverting sampling signal through the non-inverting sampling input terminal VINP and the inverting sampling input terminal VINN, respectively.

[0067] exist Figure 2In the illustrated embodiment, the sampling circuit 15 includes a sampling switching switch 151, a sampling capacitor 152, and a sampling phase switch 153. The sampling switching switch 151 is connected to the non-inverting sampling input terminal VINP, the inverting sampling input terminal VINN, and the sampling capacitor 152. The sampling phase switch 153 is connected to the sampling capacitor 152. The sampling switching switch 151 and the sampling phase switch 153 switch under the action of the master clock signal, causing the sampling capacitor 152 to alternately integrate and sample the sampling signals input to the non-inverting sampling input terminal VINP and the inverting sampling input terminal VINN. This embodiment utilizes dual sampling and bilinear integration techniques to eliminate the capacitance mismatch of the sampling capacitor 152, improving the system signal-to-noise ratio, i.e., improving the system accuracy.

[0068] exist Figure 2 In the illustrated embodiment, the sampling switch 151 includes a first sampling switch S1 and a second sampling switch S2. The sampling capacitor 152 includes a first sampling capacitor CSP and a second sampling capacitor CSN. The first sampling switch S1 is connected between the non-inverting sampling input terminal VINP and the first sampling capacitor CSP, and between the inverting sampling input terminal VINN and the second sampling capacitor CSN. The second sampling switch S2 is connected between the inverting sampling input terminal VINN and the first sampling capacitor CSP, and between the non-inverting sampling input terminal VINP and the second sampling capacitor CSN. During one cycle of a master clock signal, one of the first sampling switch S1 and the second sampling switch S2 is turned on, while the other is turned off. Figure 2 and Figure 5 As shown, within one cycle of the master clock signal, the first sampling switch S1 and the second sampling switch S2 are a pair of complementary switches. During sampling, when the first sampling switch S1 is on, the second sampling switch S2 is off. When the first sampling switch S1 is off, the second sampling switch S2 is on. Figure 5 In the illustrated embodiment, during one cycle of the master clock signal CLK, when the level corresponding to the first sampling switch S1 is low and the level corresponding to the second sampling switch S2 is high, it indicates that the first sampling switch S1 is off and the second sampling switch S2 is on. Conversely, during one cycle of the master clock signal CLK, when the level corresponding to the first sampling switch S1 is high and the level corresponding to the second sampling switch S2 is low, it indicates that the first sampling switch S1 is on and the second sampling switch S2 is off. Figure 5In the illustrated embodiment, within one cycle of the master clock signal CLK, if the level corresponding to the first sampling switch S1 changes from low to high, it indicates that the first sampling switch S1 has switched from off to on. Within one cycle of the master clock signal CLK, if the level corresponding to the second sampling switch S2 changes from high to low, it indicates that the second sampling switch S2 has switched from on to off. In this embodiment, two first sampling switches S1 and two second sampling switches S2 are respectively set, and non-overlapping switching is performed within the cycle of the master clock signal.

[0069] exist Figure 2 In the illustrated embodiment, the integral modulation circuit 1 includes a reset node VCM. The sampling phase switch 153 includes a first sampling phase switch φ1 and a second sampling phase switch φ2. The first sampling phase switch φ1 is connected between the first sampling capacitor CSP and the reset node VCM, and between the second sampling capacitor CSN and the reset node VCM. The second sampling phase switch φ2 is connected between the first sampling capacitor CSP and the first input terminal 141a of the first chopper circuit 141, and between the second sampling capacitor CSN and the second input terminal 141b of the first chopper circuit 141. During one cycle of the master clock signal CLK, one of the first sampling phase switch φ1 and the second sampling phase switch φ2 is turned on, and the other is turned off. Figure 2 and Figure 5 As shown, within one cycle of the master clock signal, the first sampling phase switch φ1 and the second sampling phase switch φ2 are a pair of complementary switches. During sampling, when the first sampling phase switch φ1 is on, the second sampling phase switch φ2 is off. When the first sampling phase switch φ1 is off, the second sampling phase switch φ2 is on. Figure 5 In the illustrated embodiment, during one cycle of the master clock signal CLK, when the level corresponding to the first sampling phase switch φ1 is high and the level corresponding to the second sampling phase switch φ2 is low, it indicates that the first sampling phase switch φ1 is on and the second sampling phase switch φ2 is off. Conversely, during one cycle of the master clock signal CLK, when the level corresponding to the first sampling phase switch φ1 is low and the level corresponding to the second sampling phase switch φ2 is high, it indicates that the first sampling phase switch φ1 is off and the second sampling phase switch φ2 is on. Figure 5 In the illustrated embodiment, within one cycle of the master clock signal CLK, if the level corresponding to the first sampling phase switch φ1 changes from high to low, it indicates that the first sampling phase switch φ1 has switched from being on to being off. Within one cycle of the master clock signal CLK, if the level corresponding to the second sampling phase switch φ2 changes from low to high, it indicates that the second sampling phase switch φ2 has switched from being off to being on. In this embodiment, two first sampling phase switches φ1 and two second sampling phase switches φ2 are respectively set, and non-overlapping switching is performed within the cycle of the master clock signal.

[0070] exist Figure 5 In the illustrated embodiment, within one cycle of the master clock signal CLK, the second sampling switch S2 and the first sampling phase switch φ1 are synchronously turned on or off. Within one cycle of the master clock signal, the second sampling switch S2 and the first sampling phase switch φ1 are synchronously turned on. The second sampling switch S2 and the first sampling phase switch φ1 are synchronously turned off. Figure 5 In the illustrated embodiment, within one cycle of the master clock signal, the first sampling switching switch S1 and the second sampling phase switch φ2 are synchronously turned on or off. Within one cycle of the master clock signal, the first sampling switching switch S1 and the second sampling phase switch φ2 are synchronously turned on. The first sampling switching switch S1 and the second sampling phase switch φ2 are synchronously turned off.

[0071] exist Figure 2 and Figure 5 In the illustrated embodiment, the first sampling switch S1 is connected between the non-inverting sampling input terminal VINP and the first input terminal 141a of the first chopper circuit 141, and between the inverting sampling input terminal VINN and the second input terminal 141b of the first chopper circuit 141. The second sampling switch S2 is connected between the inverting sampling input terminal VINN and the first input terminal 141a of the first chopper circuit 141, and between the non-inverting sampling input terminal VINP and the second input terminal 141b of the first chopper circuit 141. The chopper clock signal includes a first chopper clock signal chop+ and a second chopper clock signal chop-.

[0072] exist Figure 5 In the illustrated embodiment, the chopper clock circuit 12 is used at the rising edge of each master clock signal CLK ( Figure 5 When the arrow points upwards, a first chopper clock signal Chop+ is generated, synchronized with the switching signal of the first sampling switch S1. And when each master clock signal CLK moves from its rising edge to its falling edge... Figure 5 When switching (in the downward direction indicated by the middle arrow), a second chopper clock signal, Chop-, is generated, synchronized with the switching signal of the second sampling switch S2. During the above switching process, the first chopper clock signal Chop+ and the second chopper clock signal Chop- are a complementary pair of signals. Combined with... Figure 2 and Figure 5As shown, the first clock output terminal 121 is used to output the first chop clock signal chop+ of the chopper clock circuit 12. The second clock output terminal 122 is used to output the second chop clock signal chop- of the chopper clock circuit 12. chop+ indicates that the node of the first chopper circuit 141 is connected to the non-inverting input terminal 131a of the first-stage integrating operational amplifier circuit 131; and indicates that the node of the first output terminal 142a of the second chopper circuit 142 is connected. chop- indicates that the node of the first chopper circuit 141 is connected to the inverting input terminal 131b of the first-stage integrating operational amplifier circuit 131; and indicates that the node of the second output terminal 142b of the second chopper circuit 142 is connected.

[0073] exist Figure 2 In the illustrated embodiment, the chopper clock circuit 12 includes a first clock output terminal 121 and a second clock output terminal 122. The first clock output terminal 121 is connected between the first output terminal 141a of the first chopper circuit 141 and the non-inverting input terminal 131a of the first-stage integrating operational amplifier circuit 131, and is also connected to the first output terminal 142a of the second chopper circuit 142. The second clock output terminal 122 is connected between the second output terminal 141b of the first chopper circuit 141 and the inverting input terminal 131b of the first-stage integrating operational amplifier circuit 131, and is also connected to the second output terminal 142b of the second chopper circuit 142. Figure 2 and Figure 5 In the illustrated embodiment, when the first sampling switch S1 is turned on, the first chopper clock signal Chop+ generated by the chopper clock circuit 12 is at a high level, and this high level is output through the first clock output terminal 121. When the second sampling switch S2 is turned off, the second chopper clock signal Chop- generated by the chopper clock circuit 12 is at a low level, and this low level is output through the second clock output terminal 122. Figure 2 and Figure 5 In the illustrated embodiment, when the first sampling switch S1 is open, the first chopper clock signal Chop+ generated by the chopper clock circuit 12 is at a low level, and this low level is output through the second clock output terminal 122. When the second sampling switch S2 is on, the second chopper clock signal Chop- generated by the chopper clock circuit 12 is at a high level, and this high level is output through the first clock output terminal 121. With this configuration, the two first sampling switches S1 and the two second sampling switches S2 in this embodiment conform to the aforementioned timing pattern and cycle periodically with the first chopper clock signal Chop+ and the second chopper clock signal Chop- generated by the chopper clock circuit 12, thereby eliminating capacitor mismatch and DC voltage imbalance.

[0074] In this embodiment, sampling and integration are performed separately, for example, sampling first and then integration. By setting a sampling switching switch 151 and a sampling phase switch 153, this embodiment separates the sampling and integration processes, which can reduce the performance requirements of the operational amplifier and thus reduce the design difficulty of the integrating operational amplifier.

[0075] Combination Figure 2 and Figure 5 In the illustrated embodiment, the operation of the sampling circuit 15 includes: when the first sampling phase switch φ1 is closed, the second sampling switching switch S2 is closed, and the first sampling switching switch S1 is open. The right plates of the first sampling capacitor CIP and the second sampling capacitor CIN are both reset to the reset node VCM, where the voltage is a stable voltage. The left plates of the first sampling capacitor CIP and the second sampling capacitor CIN are connected to the positive sampling input terminal VINP and the negative sampling input terminal VINN, respectively. When the second sampling phase switch φ2 is closed, the second sampling switching switch S2 is open, and the first sampling switching switch S1 is closed. The voltages of the left plates of the first sampling capacitor CIP and the second sampling capacitor CIN are swapped with the voltages when the first sampling phase switch φ1 is closed. Thus, the voltage sampled by the sampling circuit 15 each time is VINP + VINN, resulting in a sampled voltage of ±(VINP + VINN). Therefore, the dual-sampling structure and bilinear integral of this embodiment can double the sampling voltage.

[0076] In the above scheme, the switching timing of the chopper switches of the first chopper circuit 141 and the second chopper circuit 142, together with the sampling switching switch 151 and the phase switch 153 in the sampling circuit 15, cooperate with each other under the action of the main clock signal and the chopper clock signal. The timing of the fourth-order chopper clock signal is used to eliminate the output offset and low-frequency noise in the first-stage integrating operational amplifier circuit 131. Furthermore, the sampling capacitor 152 of the sampling circuit 15 in this embodiment doubles the amplitude of the input signal through a double sampling structure, thereby increasing the signal power accordingly. Under the condition of obtaining the same signal-to-noise ratio, the requirement for system noise floor can be greatly reduced. Assume that the main limiting noise floor is the thermal noise generated by the sampling switching switch 151, i.e., KT / C noise. According to the signal-to-noise ratio = signal power / noise power, reducing the noise requirement means that KT (constant) / C noise can be increased while obtaining the same signal-to-noise ratio. That is, the sampling capacitor C can be reduced. Reducing the sampling capacitor can reduce circuit power consumption and circuit area.

[0077] exist Figure 2In the illustrated embodiment, the integral modulation circuit 1 further includes an integrating capacitor 16 connected to the first-stage integral operational amplifier circuit 131. The signal input terminal 11 also includes a feedback signal input terminal 112. The feedback signal input terminal 112 includes a positive feedback input terminal VREFP and an inverting feedback input terminal VREFN. The integral modulation circuit 1 also includes a feedback circuit 17 connected to the positive feedback input terminal VREFP and the inverting feedback input terminal VREFN. The feedback circuit 17 includes a feedback switching switch 171, a feedback capacitor 172, and a feedback synchronization switch 173. The feedback switching switch 171 is connected to the positive feedback input terminal VREFP, the inverting feedback input terminal VREFN, and the feedback capacitor 172. The feedback capacitor 172 is connected to the feedback synchronization switch 173, and the feedback synchronization switch 173 is connected to the integrating capacitor 16. The feedback switching switch 171 and the feedback synchronization switch 173 switch under the action of the master clock signal, causing the feedback capacitor 172 to alternately integrate and feedback the feedback signals input to the positive feedback input terminal VREFP and the inverting feedback input terminal VREFN. This embodiment utilizes dual feedback and bilinear integration techniques to eliminate the capacitor mismatch of feedback capacitor 172, thereby improving the system signal-to-noise ratio and thus enhancing the system's accuracy.

[0078] exist Figure 2 In the illustrated embodiment, the feedback switching switch 171 includes a first feedback switching switch S3 and a second feedback switching switch S4, and the feedback capacitor 172 includes a first feedback capacitor CFBP and a second feedback capacitor CFBN. The first feedback switching switch S3 is connected between the positive feedback input terminal VREFP and the first feedback capacitor CFBP, and between the negative feedback input terminal VREFN and the second feedback capacitor CFBN. The second feedback switching switch S4 is connected between the negative feedback input terminal VREFN and the first feedback capacitor CFBP, and between the positive feedback input terminal VREFP and the second feedback capacitor CFBN. During one cycle of the master clock signal, one of the first feedback switching switch S3 and the second feedback switching switch S4 is turned on, while the other is turned off.

[0079] Figure 6 As shown Figure 2 The timing diagram shows the sampling phase switch 153 of the sampling circuit 15 of the integral modulation circuit 1, the feedback switching switch 171 of the feedback circuit 17, the fourth-order chopper clock signal of the chopper clock circuit 12, and the main clock signal of the main clock circuit 20. Combined with... Figure 2 and Figure 6 As shown, within one cycle of the master clock signal, the first feedback switching switch S3 and the second feedback switching switch S4 are a pair of complementary switches. During feedback, when the first feedback switching switch S3 is on, the second feedback switching switch S4 is off. When the first feedback switching switch S3 is off, the second feedback switching switch S4 is on. Figure 6In the illustrated embodiment, during one cycle of the master clock signal CLK, when the level corresponding to the first feedback switching switch S3 is low and the level corresponding to the second feedback switching switch S4 is high, it indicates that the first feedback switching switch S3 is off and the second feedback switching switch S4 is on. When the level corresponding to the first feedback switching switch S3 is high and the level corresponding to the second feedback switching switch S4 is low, it indicates that the first feedback switching switch S3 is on and the second feedback switching switch S4 is off. Figure 6 In the illustrated embodiment, within one cycle of the master clock signal CLK, if the level corresponding to the first feedback switching switch S3 changes from low to high, it indicates that the first feedback switching switch S3 has switched from off to on. Within one cycle of the master clock signal CLK, if the level corresponding to the second feedback switching switch S4 changes from high to low, it indicates that the second feedback switching switch S4 has switched from on to off. In this embodiment, two first feedback switching switches S3 and two second feedback switching switches S4 are respectively set, and non-overlapping switching is performed within the cycle of the master clock signal.

[0080] exist Figure 2 In the illustrated embodiment, the integrating capacitor 16 includes a first integrating capacitor CIP and a second integrating capacitor CIN. The feedback synchronization switch 173 includes a first feedback synchronization switch RP and a second feedback synchronization switch LN. The first feedback synchronization switch RP is connected between the first feedback capacitor CFBP and the first integrating capacitor CIP, and between the second feedback capacitor CFBN and the second integrating capacitor CIN. The second feedback synchronization switch LN is connected between the first feedback capacitor CFBP and the second integrating capacitor CIN, and between the second feedback capacitor CFBN and the first integrating capacitor CIP. During one cycle of the master clock signal, one of the first feedback synchronization switch RP and the second feedback synchronization switch LN is turned on, and the other is turned off. During one cycle of the master clock signal, the first feedback synchronization switch RP and the second feedback synchronization switch LN are a pair of complementary switches. When feedback is performed, when the first feedback synchronization switch RP is turned on, the second feedback synchronization switch LN is turned off. When the first feedback synchronization switch RP is turned off, the second feedback synchronization switch LN is turned on. In this embodiment, two first feedback synchronization switches RP and two second feedback synchronization switches LN are respectively set for non-overlapping switching.

[0081] exist Figure 6In the illustrated embodiment, within one cycle of the master clock signal, the first feedback switching switch S3 is turned on or off relative to the first sampling phase switch φ1 after a preset time delay. Within one cycle of the master clock signal, when the first sampling phase switch φ1 is on, the first feedback switching switch S3 is turned on relative to the first sampling phase switch φ1 after a preset time delay. Within one cycle of the master clock signal, when the first sampling phase switch φ1 is off, the first feedback switching switch S3 is turned off relative to the first sampling phase switch φ1 after a preset time delay. Figure 6 In the illustrated embodiment, the duration of a master clock signal is 31.25 ns. The first sampling phase switch φ1 turns on 2.5 ns after the rising edge of the master clock signal CLK, and the first feedback switching switch S3 turns on 3 ns after the rising edge of the master clock signal CLK. Therefore, in this embodiment, the preset time period is set to at least 0.5 ns. Within one cycle of the master clock signal, when the first sampling phase switch φ1 is on, the first feedback switching switch S3 turns on with a delay of 0.5 ns relative to the first sampling phase switch φ1. When the first sampling phase switch φ1 is off, the first feedback switching switch S3 turns off with a delay of 0.5 ns relative to the first sampling phase switch φ1. By setting the preset time period, feedback can be ensured after sampling is completed, resulting in better signal stability.

[0082] In some embodiments, the integral modulation circuit 1 further includes a quantizer 18, connected to the second chopper circuit 142 and the integrating capacitor 16. The first input terminal 18a of the quantizer 18 is connected to the first clock output terminal 121, and the second input terminal 18b of the quantizer 18 is connected to the second clock output terminal 122. The first feedback synchronization switch RP is turned on or off under the NOR logic of the output signal of the first output terminal DN of the quantizer 18 and the switching signal of the first sampling phase switch φ1. The second feedback synchronization switch LN is turned on or off under the NAND logic of the output signal of the second output terminal DH of the quantizer 18 and the switching signal of the first sampling phase switch φ1. In this embodiment, the timing of the first feedback synchronization switch RP is obtained by performing a NOR logic operation between the output signal of the first output terminal DN of the quantizer 18 and the complementary clock of the first sampling phase switch φ1. The timing of the second feedback synchronization switch LN is obtained by performing a NAND logic operation between the second output terminal DH of the quantizer 18 and the complementary clock of the first sampling phase switch φ1. Figure 2 and Figure 6 In the illustrated embodiment, the timing of the first feedback switching switch S3, the second feedback switching switch S4, the first feedback synchronization switch RP, the second feedback synchronization switch LN, and the first sampling phase switch φ1 of the feedback circuit 17 conforms to... Figure 6The timing pattern shown is cyclical. The output of quantizer 18, through a logic operation with the timing of the first sampling phase switch φ1, controls the opening or closing of the first feedback synchronization switch RP and the second feedback synchronization switch LN of the feedback synchronization switch 173 in the feedback circuit 17 to select the value of the feedback voltage. This causes the voltages on the left plates of the first feedback capacitor CFBP and the second feedback capacitor CFBN to be interchanged with the voltages when the second sampling phase switch φ2 is closed. Thus, the voltage fed back by the feedback circuit 17 each time is VREFP+VREFN, and the reference voltage for the feedback is ±(VREFP+VREFN). Therefore, this embodiment utilizes a dual-sampling structure, which can double the reference voltage and improve the dynamic range of the integral modulation circuit 1.

[0083] exist Figure 2 In the illustrated embodiment, the reset circuit 19 includes a first reset circuit 191 and a second reset circuit 192. The first reset circuit 191 is connected in parallel with the first integrating capacitor CIP, and the second reset circuit 192 is connected in parallel with the first integrating capacitor CIN. In this embodiment, the reset circuit 19 is used to reset once after acquiring a certain number of pulse signals. By setting the reset circuit 19, a reset operation is performed after each quantization, so that sampling between adjacent samplings will not interfere with each other. This structure is applicable to applications where multiple channels reuse the same analog-to-digital converter circuit.

[0084] This application combines dual sampling technology, bilinear integration technology, and fourth-order chopping technology to achieve a high integration dynamic range, eliminate capacitor mismatch in the sampling capacitors, and reduce the DC offset voltage of the integrating operational amplifier circuit 13. It is suitable for high-precision summation integration analog-to-digital converter circuits. It can also be extended to integrating operational amplifier circuits 13 with four or more stages. The sampling capacitor mismatch is eliminated by using the switching switches 151 (first sampling switching switch S1, second sampling switching switch S2) in the sampling circuit 15, and the first chopping circuit 141 and second chopping circuit 142 before and after the first-stage integrating operational amplifier circuit 131. This is achieved by alternately sampling the input signal Vin+ or Vin- according to the timing pattern of the fourth-order chopping clock signal. That is, the sampling pattern conforms to the timing pattern of the chopping clock signal and cycles periodically, thereby eliminating the DC offset of the integrating operational amplifier circuit 13 and improving the signal-to-noise ratio of the entire integrating modulation circuit. In addition, in this embodiment, multiple stages of the integral operational amplifier circuit 13 can be connected in series between the two output terminals of the integral operational amplifier circuit 13 and the quantizer 18 to form a multi-stage cascaded operational amplifier circuit 13, which is not limited in this application.

[0085] It should be noted that all switches in the above scheme are electrically controlled switches, which are controlled to be turned on or off by a controller (not shown). The quantizer 18 can also be a comparator. The reset node VCM connected to the two first sampling phase switches φ1, the reset node VCM connected to the second sampling phase switch φ2, and the reset node VCM connected to the first sampling capacitor CIP and the second sampling capacitor CIN can have the same or different voltages. In this embodiment, the voltages of the above reset node VCMs are all the same, and their voltages are all 0V, which is not limited in this application.

[0086] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims. It should be understood that this application is not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An integral modulation circuit, applied to a summation integral analog-to-digital converter circuit, characterized in that, include: The signal input terminal is used to input the sampling signal; Chopper clock circuit, used to generate multi-stage chopper clock signals; A cascaded multi-stage integrating operational amplifier circuit, wherein the first stage of the multi-stage integrating operational amplifier circuit located at the beginning is connected to the signal input terminal and the chopper clock circuit; The first-stage integrating operational amplifier circuit is used to receive the sampled signal; and The chopper circuit includes a first chopper circuit and a second chopper circuit. The first chopper circuit and the second chopper circuit are respectively connected to the input terminal and the output terminal of the first-stage integrating operational amplifier circuit, and both are connected to the chopper clock circuit. Under the action of the first chopper circuit, the second chopper circuit and the chopper clock signal, the signal transmission path of the sampling signal input to the first-stage integrating operational amplifier circuit is changed in the multi-stage integrating operational amplifier circuit. The integral modulation circuit further includes a master clock circuit for generating a master clock signal; the integral modulation circuit includes a sampling capacitor and a sampling phase switch, the sampling capacitor including a first sampling capacitor and a second sampling capacitor; the integral modulation circuit includes a reset node; the sampling phase switch includes a first sampling phase switch and a second sampling phase switch; the first sampling phase switch is connected between the first sampling capacitor and the reset node and between the second sampling capacitor and the reset node; the second sampling phase switch is connected between the first sampling capacitor and the first input terminal of the first chopper circuit and between the second sampling capacitor and the second input terminal of the first chopper circuit; within one cycle of the master clock signal, one of the first sampling phase switch and the second sampling phase switch is turned on, and the other is turned off.

2. The integral modulation circuit according to claim 1, characterized in that, The number of orders of the chopper clock signal is greater than or equal to the number of stages of the integrating operational amplifier circuit; or The number of orders of the chopper clock signal is equal to the number of stages of the integrating operational amplifier circuit.

3. The integral modulation circuit according to claim 2, characterized in that, The first chopper circuit includes a first chopper switch, and the second chopper circuit includes a second chopper switch; the first chopper switch and the second chopper switch switch are switched under the action of the master clock signal, and under the action of the chopper clock signal, the sampling signal transmits at least a plurality of cycles of the master clock signal in the multi-stage integrating operational amplifier circuit.

4. The integral modulation circuit according to claim 3, characterized in that, The chopper clock circuit is used to generate at least m-order chopper clock signals, and the sampled signal at the input of the first-stage integrating operational amplifier circuit is transmitted for at least N cycles of the master clock signal in the multi-stage integrating operational amplifier circuit; where m is greater than or equal to 4 and N / 2 m It is an integer.

5. The integral modulation circuit according to claim 4, characterized in that, The signal input terminal includes a non-inverting sampling input terminal and an inverting sampling input terminal; the integral modulation circuit further includes a sampling circuit, including a sampling switching switch; the sampling switching switch includes a first sampling switching switch and a second sampling switching switch, the first sampling switching switch being connected between the non-inverting sampling input terminal and the first input terminal of the first chopper circuit and between the inverting sampling input terminal and the second input terminal of the first chopper circuit; the second sampling switching switch being connected between the inverting sampling input terminal and the first input terminal of the first chopper circuit and between the non-inverting sampling input terminal and the second input terminal of the first chopper circuit; The chopper clock signal includes a first chopper clock signal and a second chopper clock signal; the chopper clock circuit is used to generate the first chopper clock signal synchronized with the switching signal of the first sampling switch at the rising edge of each master clock signal; and to generate the second chopper clock signal synchronized with the switching signal of the second sampling switch when each master clock signal switches from rising edge to falling edge.

6. The integral modulation circuit according to claim 5, characterized in that, The chopper clock circuit includes a first clock output terminal and a second clock output terminal. The first clock output terminal is connected between the first output terminal of the first chopper circuit and the non-inverting input terminal of the first-stage integrating operational amplifier circuit, and is also connected to the first output terminal of the second chopper circuit. The second clock output terminal is connected between the second output terminal of the first chopper circuit and the inverting input terminal of the first-stage integrating operational amplifier circuit, and is also connected to the second output terminal of the second chopper circuit. When the first sampling switch is turned on, the first chopper clock signal generated by the chopper clock circuit is at a high level, and this high level is output through the first clock output terminal; when the second sampling switch is turned off, the second chopper clock signal generated by the chopper clock circuit is at a low level, and this low level is output through the second clock output terminal. or When the first sampling switch is off, the first chopper clock signal generated by the chopper clock circuit is at a low level, and this low level is output through the second clock output terminal; when the second sampling switch is on, the second chopper clock signal generated by the chopper clock circuit is at a high level, and this high level is output through the first clock output terminal.

7. The integral modulation circuit according to claim 4, characterized in that, The signal input terminal includes a non-inverting sampling input terminal and an inverting sampling input terminal; the integral modulation circuit further includes a sampling circuit, including a sampling switching switch, which is connected to the non-inverting sampling input terminal, the inverting sampling input terminal and the sampling capacitor, and the sampling phase switch is connected to the sampling capacitor; the sampling switching switch and the sampling phase switch are switched under the action of the master clock signal, so that the sampling capacitor alternately integrates and samples the sampling signals input to the non-inverting sampling input terminal and the inverting sampling input terminal.

8. The integral modulation circuit according to claim 7, characterized in that, The sampling switching switch includes a first sampling switching switch and a second sampling switching switch; the sampling phase switch includes a first sampling phase switch and a second sampling phase switch; Within one cycle of the master clock signal, the second sampling switching switch and the first sampling phase switch are synchronously turned on or off; or Within one cycle of the master clock signal, the first sampling switching switch and the second sampling phase switch are synchronously turned on or off.

9. The integral modulation circuit according to claim 7, characterized in that, The sampling switching switch includes a first sampling switching switch and a second sampling switching switch; the first sampling switching switch is connected between the non-inverting sampling input terminal and the first sampling capacitor and between the inverting sampling input terminal and the second sampling capacitor, respectively; the second sampling switching switch is connected between the inverting sampling input terminal and the first sampling capacitor and between the non-inverting sampling input terminal and the second sampling capacitor, respectively; within one cycle of the master clock signal, one of the first sampling switching switch and the second sampling switching switch is turned on, and the other is turned off.

10. The integral modulation circuit according to claim 7, characterized in that, The integral modulation circuit further includes an integrating capacitor connected to the first-stage integral operational amplifier circuit; the signal input terminal further includes a positive feedback input terminal and an inverting feedback input terminal; the integral modulation circuit further includes a feedback circuit connected to the positive feedback input terminal and the inverting feedback input terminal, the feedback circuit including a feedback switching switch, a feedback capacitor and a feedback synchronization switch, the feedback switching switch being connected to the positive feedback input terminal, the inverting feedback input terminal and the feedback capacitor, the feedback capacitor being connected to the feedback synchronization switch, and the feedback synchronization switch being connected to the integrating capacitor; the feedback switching switch and the feedback synchronization switch are switched under the action of the master clock signal, so that the feedback capacitor alternately integrates and feeds back the feedback signals input to the positive feedback input terminal and the inverting feedback input terminal.

11. The integral modulation circuit according to claim 10, characterized in that, The sampling phase switch includes a first sampling phase switch and a second sampling phase switch; the feedback switching switch includes a first feedback switching switch and a second feedback switching switch; Within one cycle of the master clock signal, the first feedback switching switch is turned on or off relative to the first sampling phase switch after a preset time period; or Within one cycle of the master clock signal, the second feedback switching switch is either turned off or turned on relative to the second sampling phase switch after a preset time period.

12. The integral modulation circuit according to claim 10, characterized in that, The sampling phase switch includes a first sampling phase switch; the feedback synchronization switch includes a first feedback synchronization switch and a second feedback synchronization switch; the chopper clock circuit includes a first clock output terminal and a second clock output terminal; the integral modulation circuit further includes a quantizer, which is connected to the second chopper circuit and the integral capacitor, and the first input terminal of the quantizer is connected to the first clock output terminal, and the second input terminal of the quantizer is connected to the second clock output terminal. The first feedback synchronization switch is turned on or off under the OR-NOT logic action of the output signal at the first output terminal of the quantizer and the switching signal of the first sampling phase switch; or The second feedback synchronization switch is turned on or off under the AND-NOT logic action of the output signal at the second output terminal of the quantizer and the switching signal of the first sampling phase switch.

13. The integral modulation circuit according to claim 10, characterized in that, The feedback switching switch includes a first feedback switching switch and a second feedback switching switch, and the feedback capacitor includes a first feedback capacitor and a second feedback capacitor; the first feedback switching switch is connected between the positive feedback input terminal and the first feedback capacitor and between the negative feedback input terminal and the second feedback capacitor; the second feedback switching switch is connected between the negative feedback input terminal and the first feedback capacitor and between the positive feedback input terminal and the second feedback capacitor; within one cycle of the master clock signal, one of the first feedback switching switch and the second feedback switching switch is turned on, and the other is turned off; and / or The integrating capacitor includes a first integrating capacitor and a second integrating capacitor; the feedback synchronization switch includes a first feedback synchronization switch and a second feedback synchronization switch. The first feedback synchronization switch is connected between the first feedback capacitor and the first integrating capacitor, and between the second feedback capacitor and the second integrating capacitor; the second feedback synchronization switch is connected between the first feedback capacitor and the second integrating capacitor, and between the second feedback capacitor and the first integrating capacitor; within one cycle of the master clock signal, one of the first feedback synchronization switch and the second feedback synchronization switch is turned on, and the other is turned off.

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