Source driving circuit, source driving method, display device and display driving method

Abstract

A source driver circuit (100) comprises a logic control subcircuit (10), a latch subcircuit (20) and an output subcircuit (30). The logic control subcircuit (10) is configured to convert a source data signal into a data signal; and output a first latch signal, a second latch signal, a first enable signal and a second enable signal. The latch subcircuit (20) is configured to receive a data signal; and latch odd-row data of the data signal in an odd frame, and latch even-row data of the data signal in an even frame. The output subcircuit (30) is configured to receive odd-row data in an odd frame and output the odd-row data according to a first set time length, wherein the first set time length is greater than the charging time of the even-row subpixels and less than or equal to twice the charging time of the even-row subpixels; and receive even-row data in an even frame and output the even-row data according to a second set time length, wherein the second set time length is greater than the charging time of the odd-row subpixels and less than or equal to twice the charging time of the odd-row subpixels.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a source driving circuit, a source driving method, a display device, and a display driving method. Background Art

[0002] With the continuous development of display technology, consumers' requirements for the performance of display devices are gradually increasing. In order to increase the product competitiveness of display devices, improving the resolution and frame rate of display devices have become two effective ways.

[0003] However, as resolution and frame rate increase, the time for the driver chip in the display device to provide voltage to the data line is shortened, the charging time of each row of sub-pixels is shortened, and there is a difference between the grayscale displayed by the sub-pixels and the target grayscale, thereby reducing the display effect of the display device. Summary of the Invention

[0004] In one aspect, a source driver circuit is provided, comprising a logic control subcircuit, a latch subcircuit, and an output subcircuit.

[0005] A logic control subcircuit is coupled to a source data signal terminal, a gate start signal terminal, a mode switch signal terminal, an initial latch enable signal terminal, and a source output enable signal terminal; the logic control subcircuit is configured to receive a source data signal from the source data signal terminal and convert the source data signal into a data signal; and output a first latch signal, a second latch signal, a first enable signal, and a second enable signal according to a gate start signal from the gate start signal terminal, a first mode switch signal from the mode switch signal terminal, an initial latch enable signal from the initial latch enable signal terminal, and a source output enable signal from the source output enable signal terminal.

[0006] A latch subcircuit is coupled to the logic control subcircuit; the latch subcircuit is configured to receive a data signal from the logic control subcircuit; and, under the control of the first latch signal, latch the odd-numbered row data of the data signal in an odd frame, and under the control of the second latch signal, latch the even-numbered row data of the data signal in an even frame.

[0007] An output subcircuit is coupled to the latch subcircuit and the logic circuit subcircuit; the output subcircuit is configured to receive the odd-row data in an odd frame and, under the control of the first enable signal, output the odd-row data for a first set duration, wherein the first set duration is greater than the charging time of the even-row sub-pixels and less than or equal to twice the charging time of the even-row sub-pixels; and, to receive the even-row data in an even frame and, under the control of the second enable signal, output the even-row data for a second set duration, wherein the second set duration is greater than the charging time of the odd-row sub-pixels and less than or equal to twice the charging time of the odd-row sub-pixels.

[0008] In some embodiments, in odd frames, the first set duration is twice the charging time of sub-pixels in even rows; and / or, in even frames, the second set duration is twice the charging time of sub-pixels in odd rows.

[0009] In some embodiments, the logic control subcircuit includes: a shielding signal generating module, a latch signal generating module, and an enable signal generating module.

[0010] A shielding signal generating module is coupled to the gate start signal terminal and the mode switching signal terminal; the shielding signal generating module is configured to generate a first shielding signal and a second shielding signal according to the gate start signal and the first mode switching signal.

[0011] A latch signal generating module is coupled to the shielding signal generating module and the initial latch enable signal terminal; the latch signal generating module is configured to generate a first latch signal according to the first shielding signal and the initial latch enable signal; and to generate a second latch signal according to the second shielding signal and the initial latch enable signal.

[0012] An enable signal generating module is coupled to the shielding signal generating module and the source output enable signal terminal; the enable signal generating module is configured to generate a first enable signal according to the first shielding signal and the source output enable signal; and to generate a second enable signal according to the second shielding signal and the source output enable signal.

[0013] In some embodiments, the shielding signal generating module includes a distinguishing unit and a generating unit.

[0014] A distinguishing unit is coupled to the pulse signal terminal, the gate start signal terminal and the mode switching signal terminal; the distinguishing unit is configured to output a row characterization signal pair and a frame characterization signal pair according to the pulse signal from the pulse signal terminal, the gate start signal and the first mode switching signal; the row characterization signal pair represents odd rows and even rows, and the frame characterization signal pair represents odd frames and even frames.

[0015] A generating unit is coupled to the distinguishing unit; the generating unit is configured to generate a first shielding signal and a second shielding signal according to the row characterizing signal pair, the frame characterizing signal pair and the inverted delayed signal of the source output enable signal.

[0016] In some embodiments, the distinguishing unit includes a NAND gate, a first NOT gate, a first flip-flop, a first AND gate, and a second flip-flop.

[0017] A NAND gate, wherein a first input terminal of the NAND gate is coupled to the pulse signal terminal, and a second input terminal of the NAND gate is coupled to the gate start signal terminal.

[0018] A first NOT gate, wherein an input terminal of the first NOT gate is coupled to an output terminal of the NAND gate.

[0019] A first trigger, an enable terminal of the first trigger is coupled to the output terminal of the first NOT gate, a reset terminal of the first trigger is coupled to the mode switching signal terminal, a first output terminal and a second output terminal of the first trigger are coupled to the generating unit, an input terminal of the first trigger is coupled to the first output terminal of the first trigger; the first output terminal of the first trigger is configured to output a first frame characterization signal, and the second output terminal of the first trigger is configured to output a second frame characterization signal, the first frame characterization signal and the second frame characterization signal are inverted to form a frame characterization signal pair.

[0020] A first AND gate, wherein a first input terminal of the first AND gate is coupled to the output terminal of the NAND gate, and a second input terminal of the first AND gate is coupled to the mode switching signal terminal.

[0021] A second trigger, an enable terminal of the second trigger is coupled to the pulse signal terminal, a reset terminal of the second trigger is coupled to the output terminal of the first AND gate, a first output terminal and a second output terminal of the second trigger are coupled to the generation unit, and an input terminal of the second trigger is coupled to the first output terminal of the second trigger; the first output terminal of the second trigger is configured to output a first row characterization signal, and the second output terminal of the first trigger is configured to output a second row characterization signal, the first row characterization signal and the second row characterization signal are inverted to form a row characterization signal pair.

[0022] In some embodiments, the generating unit includes a multiplier and a third flip-flop.

[0023] a multiplier; a first input terminal and a second input terminal of the multiplier are coupled to the distinguishing unit and configured to receive the row characterizing signal pair; a third input terminal and a fourth input terminal of the multiplier are coupled to the distinguishing unit and configured to receive the frame characterizing signal pair.

[0024] a third trigger, wherein the input terminal of the third trigger is coupled to the output terminal of the multiplier, the enable terminal of the third trigger is configured to receive an inverted delayed signal of the source output enable signal, and the output terminal of the third trigger is configured to output a first shielding signal and a second shielding signal.

[0025] In some embodiments, the latch signal generating module includes a second NOT gate and a second AND gate.

[0026] A second NOT gate, wherein an input end of the second NOT gate is coupled to the shielding signal generating module.

[0027] A second AND gate, wherein the first input terminal of the second AND gate is coupled to the output terminal of the second NOT gate, and the second input terminal of the second AND gate is coupled to the initial latch enable signal terminal; the output terminal of the second AND gate is configured to output the first latch signal or the second latch signal.

[0028] In some embodiments, the enable signal generation module includes a signal generator.

[0029] A signal generator; an input terminal of the signal generator is coupled to the source output enable signal terminal, and an enable terminal of the signal generator is coupled to the shielding signal generating module; an output terminal of the signal generator is configured to output the first enable signal and the second enable signal.

[0030] In some embodiments, the logic control subcircuit is further configured to receive and output the initial latch enable signal and the source output enable signal according to the gate start signal and the second mode switching signal from the mode switching signal terminal.

[0031] The latch module is further configured to latch odd-numbered row data and even-numbered row data of the data signal in each frame under the control of the initial latch enable signal.

[0032] The output module is further configured to output odd-numbered row data and even-numbered row data in each frame under the control of the source output enable signal; the charging time of the odd-numbered row sub-pixels and the even-numbered row sub-pixels is equal.

[0033] In some embodiments, the source driver circuit further includes a level conversion and a digital-to-analog conversion sub-circuit.

[0034] A level conversion and digital-to-analog conversion sub-circuit is coupled to the latch sub-circuit and the output sub-circuit; the level conversion and digital-to-analog conversion sub-circuit is configured to receive the odd-numbered row data in an odd frame and perform level conversion and digital-to-analog conversion on the odd-numbered row data; and to receive the even-numbered row data in an even frame and perform level conversion and digital-to-analog conversion on the even-numbered row data.

[0035] In some embodiments, the source driver circuit further includes an output buffer.

[0036] An output buffer is coupled to the latch sub-circuit and the output sub-circuit; the output buffer is configured to receive the odd-numbered row data in an odd frame and temporarily store the odd-numbered row data; and to receive the even-numbered row data in an even frame and temporarily store the even-numbered row data.

[0037] In some embodiments, the first set duration is equal to the second set duration.

[0038] On the other hand, a source driving method is provided. The source driving method comprises:

[0039] In each frame, a source data signal is received and converted into a data signal.

[0040] In odd frames:

[0041] A first latch signal and a first enable signal are generated according to a gate start signal, a first mode switching signal, an initial latch enable signal, and a source output enable signal.

[0042] Under the control of the first latch signal, odd-numbered row data of the data signal is latched.

[0043] Under the control of the first enable signal, odd-numbered row data is output according to a first set duration; the first set duration is greater than the charging time of even-numbered row sub-pixels and less than or equal to twice the charging time of even-numbered row sub-pixels.

[0044] In even frames:

[0045] A second latch signal and a second enable signal are generated according to the gate start signal, the first mode switching signal, the initial latch enable signal, and the source output enable signal.

[0046] Under the control of the second latch signal, latching the even-numbered row data of the data signal;

[0047] Under the control of the second enable signal, even row data is output according to a second set time length; the second set time length is greater than the charging time of the odd row sub-pixels and less than or equal to twice the charging time of the odd row sub-pixels.

[0048] In some embodiments, in odd frames, the first set duration is twice the charging time of sub-pixels in even rows; and / or, in even frames, the second set duration is twice the charging time of sub-pixels in odd rows.

[0049] In some embodiments, generating the first latch signal and the first enable signal according to the gate start signal, the first mode switching signal, the initial latch enable signal, and the source output enable signal includes:

[0050] A first shielding signal is generated according to the gate start signal and the first mode switching signal.

[0051] A first latch signal is generated according to the first shielding signal and the initial latch enable signal.

[0052] A first enable signal is generated according to the first shielding signal and the source output enable signal.

[0053] The generating of a second latch signal and a second enable signal according to the gate start signal, the first mode switching signal, the initial latch enable signal and the source output enable signal comprises:

[0054] A second shielding signal is generated according to the gate start signal and the first mode switching signal.

[0055] A second latch signal is generated according to the second masking signal and the initial latch enable signal.

[0056] A second enable signal is generated according to the second shielding signal and the source output enable signal.

[0057] In some embodiments, generating a first shielding signal according to the gate start signal and the first mode switching signal includes:

[0058] A pulse signal is received, and a row characterization signal pair and a frame characterization signal pair are generated according to the pulse signal, the gate start signal and the first mode switching signal; the row characterization signal pair includes a first row characterization signal and a second row characterization signal that are mutually inverted, and the frame characterization signal pair includes a first frame characterization signal and a second frame characterization signal that are mutually inverted.

[0059] A first shielding signal is generated according to the pair of row characterizing signals, the pair of frame characterizing signals, and an inverted delayed signal of the source output enable signal.

[0060] Generating a second shielding signal according to the gate start signal and the first mode switching signal includes:

[0061] A pulse signal is received, and a row characterization signal pair and a frame characterization signal pair are generated according to the pulse signal, the gate start signal and the first mode switching signal; the row characterization signal pair includes a first row characterization signal and a second row characterization signal that are mutually inverted, and the frame characterization signal pair includes a first frame characterization signal and a second frame characterization signal that are mutually inverted.

[0062] A second shielding signal is generated according to the pair of row characterizing signals, the pair of frame characterizing signals, and an inverted delayed signal of the source output enable signal.

[0063] Among them, the first row characterization signal is a low level within the odd row time and a high level within the even row time; the first frame characterization signal is a low level within the odd frame time and a high level within the even frame time; or, the first row characterization signal is a high level within the odd row time and a low level within the even row time; the first frame characterization signal is a high level within the odd frame time and a low level within the even frame time.

[0064] On the other hand, a display device is provided, comprising: a plurality of source driving circuits as described in any one of the above embodiments, at least one timing control circuit, and a display panel.

[0065] The at least one timing control circuit is configured to output a source data signal, a gate start signal, a first mode switching signal, a second mode switching signal, an initial latch enable signal and a source output enable signal; each timing control circuit is coupled to at least two source driver circuits.

[0066] The display panel is coupled to the at least one timing control circuit and the plurality of source driving circuits.

[0067] In some embodiments, the display device includes two timing control circuits; the plurality of source driver circuits are divided into two groups, each group of source driver circuits is coupled to one timing control circuit; the refresh frequency of the timing control circuit is X, and the amount of image data that can be transmitted per frame is Y; the target refresh frequency of the display panel is X0, and the target amount of image data required per frame is Y0;

[0068] In another aspect, a display driving method is provided, which is applied to the display device described in any one of the above embodiments. The display driving method includes:

[0069] In each frame, the timing control circuit sends a source data signal, a gate start signal, a mode switching signal, an initial latch enable signal and a source output enable signal to the source driver circuit, and the source driver circuit converts the source data signal into a data signal.

[0070] In odd frames:

[0071] The source driver circuit latches odd-numbered row data of the data signal according to the gate start signal, the first mode switching signal, the initial latch enable signal, and the source output enable signal, and outputs the odd-numbered row data for a first set duration.

[0072] The timing control circuit controls the sub-pixels of each row of the display panel to turn on row by row, and uses the odd-numbered row data for charging, wherein the charging time of the sub-pixels of the odd-numbered rows is a first set duration, and the charging time of the sub-pixels of the even-numbered rows is greater than or equal to half of the first set duration and less than the first set duration.

[0073] In even frames:

[0074] The source driver circuit latches the even-numbered row data of the data signal according to the gate start signal, the first mode switching signal, the initial latch enable signal and the source output enable signal, and outputs the even-numbered row data according to a second set duration.

[0075] The timing control circuit controls the sub-pixels of each row of the display panel to turn on row by row, and uses the even-numbered row data for charging, wherein the charging time of the sub-pixels of the even-numbered rows is a second set time length, and the charging time of the sub-pixels of the odd-numbered rows is greater than or equal to half of the second set time length and less than the second set time length.

[0076] In some embodiments, in an odd frame, in two adjacent rows of sub-pixels, when the charging time of the odd row of sub-pixels is half of a first set time length, the even row of sub-pixels is turned on for charging; in an even frame, in two adjacent rows of sub-pixels, when the charging time of the even row of sub-pixels is half of a second set time length, the odd row of sub-pixels is turned on for charging. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0078] Figure 1A is a structural diagram of a display device according to some embodiments;

[0079] Figure 1B is a structural diagram of another display device according to some embodiments;

[0080] Figure 2 is a structural diagram of another display device according to some embodiments;

[0081] Figure 3 is a structural diagram of a source driver circuit according to some embodiments;

[0082] Figure 4Ais a timing diagram of an odd-numbered frame signal according to some embodiments;

[0083] Figure 4B is a timing diagram of an even-numbered frame signal according to some embodiments;

[0084] Figure 5 is a structural diagram of another source driving circuit according to some embodiments;

[0085] Figure 6 is a structural diagram of yet another source driver circuit according to some embodiments;

[0086] Figure 7 is a structural diagram of another source driver circuit according to some embodiments;

[0087] Figure 8 is a circuit diagram of a logic control subcircuit according to some embodiments;

[0088] Figure 9 is a circuit diagram of a distinguishing unit according to some embodiments;

[0089] Figure 10 is a circuit diagram of a generating unit according to some embodiments;

[0090] Figure 11 is a circuit diagram of a latch signal generating module according to some embodiments;

[0091] Figure 12 is a circuit diagram of an enable signal generating module according to some embodiments;

[0092] Figure 13A is another odd-numbered frame signal timing diagram according to some embodiments;

[0093] Figure 13B is another even-numbered frame signal timing diagram according to some embodiments;

[0094] Figure 14 is a structural diagram of another source driver circuit according to some embodiments;

[0095] Figure 15 is a timing diagram of an odd-numbered frame or even-numbered frame signal according to some embodiments;

[0096] Figure 16 is a structural diagram of another source driver circuit according to some embodiments;

[0097] Figure 17 is a structural diagram of another source driver circuit according to some embodiments;

[0098] Figure 18is a structural diagram of another source driver circuit according to some embodiments;

[0099] Figures 19 to 23 is a flow chart of a source driving method according to some embodiments;

[0100] Figure 24 is a flow chart of another source driving method according to some embodiments;

[0101] Figure 25 is a flowchart of a display driving method according to some embodiments. DETAILED DESCRIPTION

[0102] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0103] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0104] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0105] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0106] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0107] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0108] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0109] As used herein, "equal" includes the stated conditions and conditions that are similar to the stated conditions, where the range of the similar conditions is within an acceptable range of deviation, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "equal" includes absolute equality and approximate equality, where the acceptable range of deviation for approximate equality can be, for example, that the difference between the two is less than or equal to 5% of either.

[0110] like Figure 1A and Figure 1B As shown, some embodiments of the present disclosure provide a display device 1000. The display device 1000 can be any component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, or the like.

[0111] The display device 1000 includes a plurality of source driving circuits 100 , at least one timing control circuit 200 and a display panel 300 .

[0112] The timing control circuit 200 is configured to output a source data signal W DT , gate start signal W GSP , the first mode switching signal W OD1 , the second mode switching signal W OD2 , initial latch enable signal W LA and source output enable signal W SOE Each timing control circuit 200 is coupled to at least two source driver circuits 100 .

[0113] In some examples, such as Figure 1A As shown, the display device 1000 may include a timing control circuit 200. In other examples, such as Figure 1B As shown, the display device 1000 may include a plurality of timing control circuits 200. The present disclosure does not limit the number of timing control circuits 200, as long as the normal display of the display device 1000 can be ensured.

[0114] In some examples, such as Figure 1A and Figure 1B As shown, the display device 1000 may include 24 source driving circuits, and each timing control circuit 200 may be coupled to 12 source driving circuits 100 .

[0115] The display panel 300 is coupled to at least one timing control circuit 200 and a plurality of source driving circuits 100 .

[0116] In some examples, such as Figure 1A and Figure 1B As shown, the display device 1000 may further include a plurality of flexible circuit boards 301, a plurality of printed circuit boards 302 and a plurality of chip-on-films ( Figure 1A and Figure 1B The display panel 300 is coupled to at least one timing control circuit 200 and a plurality of source driver circuits 100 using a flexible circuit board 301, a printed circuit board 302, and a chip-on-film.

[0117] For example, the source driver circuit 100 can be located on a flip chip film respectively, multiple flip chips can be bonded to a printed circuit board 302, each timing control circuit 200 can be set on a printed circuit board 302, and the two printed circuit boards 302 can be coupled through a flexible circuit board 301.

[0118] It is understandable that Figure 1A and Figure 1B The number of source driver circuits 100 is only an example, and the number of source driver circuits 100 in the display device 1000 in the present disclosure is not limited thereto.

[0119] For example, Figure 2 As shown, the display panel 300 may include multiple sub-pixels 310, multiple data lines DL, and multiple gate lines GL. Each sub-pixel 310 may include a pixel driving circuit 320. The pixel driving circuit 320 is generally composed of electronic devices such as thin film transistors (TFTs) and capacitors (Cs).

[0120] The plurality of sub-pixels 310 may be arranged in a plurality of rows along the column direction, for example Figure 2 The dashed box Q in the middle shows a row of sub-pixels. For example, the rows of sub-pixels are numbered (1) to (6) in order from top to bottom. The sub-pixels in rows (1), (3), and (5) are odd-numbered rows, and the sub-pixels in rows (2), (4), and (6) are even-numbered rows.

[0121] The source driving circuit 100 may provide data to the plurality of sub-pixels 310 in each row of sub-pixels 310 through the plurality of data lines DL.

[0122] In some examples, such as Figure 2 As shown, the display device 1000 may further include a grayscale control circuit 400 and a gate driving circuit 500 .

[0123] For example, the grayscale control circuit 400 is coupled to the timing control circuit 200 and the source driving circuit 100 . The grayscale control circuit 400 may be configured to provide a gamma signal to the source driving circuit 100 according to image data from the timing control circuit 200 .

[0124] For example, the gate driving circuit 500 may be coupled to the timing control circuit 200. The timing control circuit 200 may control the gate driving circuit 500 to provide gate scanning signals to each row of sub-pixels 310 through a plurality of gate lines GL, thereby controlling the charging time of each row of sub-pixels.

[0125] In some embodiments, as Figure 1B As shown, the display device 1000 includes two timing control circuits 200. A plurality of source driving circuits 100 are divided into two groups, and each group of source driving circuits 100 is coupled to one timing control circuit 200.

[0126] The refresh frequency of the timing control circuit 200 is X, and the amount of image data that can be transmitted per frame is Y; the target refresh frequency of the display panel 300 is X0, and the target amount of image data required per frame is Y0;

[0127] In this way, when the display device 1000 includes two timing control circuits 200, the refresh frequency X of the timing control circuit 200 can be half of the target refresh frequency X0, and the amount of image data Y that can be transmitted per frame is the same as the target image data amount Y0 required per frame. Alternatively, the refresh frequency X of the timing control circuit 200 can be the same as the target refresh frequency X0, and the amount of image data Y that can be transmitted per frame is half of the target image data amount Y0 required per frame. As a result, the display device has lower performance requirements for the timing control circuit 200, and the timing control circuit 200 is easier to implement, which is conducive to reducing the production cost of the timing control circuit 200, and further reducing the production cost of the display device 1000.

[0128] For example, when the target refresh frequency of the display panel 300 is 120 Hz, the refresh frequency of the timing control circuit 200 may be 60 Hz.

[0129] like Figure 3 As shown, some embodiments of the present disclosure provide a source driver circuit 100 , including a logic control sub-circuit 10 , a latch sub-circuit 20 , and an output sub-circuit 30 .

[0130] The logic control sub-circuit 10 is coupled to the source data signal terminal Vin, the gate start signal terminal GSP, the mode switch signal terminal ODEN, the initial latch enable signal terminal LAT and the source output enable signal terminal SOE. The logic control sub-circuit 10 is configured to receive the source data signal W from the source data signal terminal Vin. DT , the source data signal W DT Converted into data signal W D And, according to the gate start signal W from the gate start signal terminal GSP GSP , the first mode switching signal W from the mode switching signal terminal ODEN OD1 , the initial latch enable signal W from the initial latch enable signal terminal LAT LA and the source output enable signal W from the source output enable signal terminal SOE SOE , outputs a first latch signal W1, a second latch signal W2, a first enable signal W3 and a second enable signal W4.

[0131] For example, “the source data signal W DT Converted into data signal W D ", the source data signal W can be processed by means of data inversion, serial-to-parallel conversion, data sampling, etc. DT Processing is performed so that the source data signal W DT Converted into data signal W D The present disclosure does not provide any information on the source data signal W DT Converted into data signal W D way to restrict.

[0132] The latch sub-circuit 20 is coupled to the logic control sub-circuit 10. The latch sub-circuit 20 is configured to receive the data signal W from the logic control sub-circuit 10. D And, under the control of the first latch signal W1, the data signal W is latched in the odd frame. D Odd-numbered row data W D1 , under the control of the second latch signal W2, the data signal W is latched in the even frame D Even-numbered rows of data W D2 .

[0133] The output sub-circuit 30 is coupled to the logic circuit sub-circuit 10 and the latch sub-circuit 20. Figure 4A The output sub-circuit 30 is configured to receive odd-numbered row data W in odd-numbered frames. D1 , and under the control of the first enable signal W3, outputs odd row data W according to the first set time length T1 D1 The first set time length T1 is greater than the charging time of the even-numbered row sub-pixels 310 and is less than or equal to twice the charging time of the even-numbered row sub-pixels 310. Figure 4B , receive even-numbered line data W in even-numbered frames D2 , and under the control of the second enable signal W4, outputs the even row data W according to the second set time length T2 D2 The second set time length T2 is greater than the charging time of the odd-numbered row sub-pixels 310 and is less than or equal to twice the charging time of the odd-numbered row sub-pixels 310.

[0134] For example, the source data signal W DT , gate start signal W GSP , the first mode switching signal W OD1 , initial latch enable signal W LA and source output enable signal W SOE It can be provided by the timing control circuit 200.

[0135] Exemplarily, the gate start signal W GSP It can be used to represent each frame, where the gate driving circuit 500 starts to provide gate scanning signals to the multiple rows of gate lines GL and to each row of sub-pixels 310 .

[0136] For example, the change of the output voltage of the source driver circuit 100 in the odd frame can be as follows: Figure 4A Middle W OUT The output voltage variation of the source driving circuit 100 in the even frame can be as follows: Figure 4B W in OUT As shown in the waveform diagram.

[0137] Among them, in odd frames, the data voltage WD The odd-numbered rows of data W D1 (For example, Figure 4A 1, 3, 5, 7) are output, in the even frame, the data voltage W D Even-numbered rows of data W D2 (For example, Figure 4B 2, 4, 6) in are output.

[0138] For example, in Figure 4A , source output enable signal W SOE The time between two adjacent falling edges is the charging time of the sub-pixels in the even-numbered rows.

[0139] For example, in Figure 4B , source output enable signal W SOE The time between two adjacent falling edges is the charging time of the sub-pixels in the odd-numbered rows.

[0140] It should be noted that in Figure 4A and Figure 4B In FIG, G1 to G4 represent gate line signals. When the signals G1 to G4 are at a high level, the gate lines GL corresponding to G1 to G4 are turned on, and the sub-pixels 310 connected to the gate lines GL are charged.

[0141] In some embodiments of the present disclosure, the source driver circuit 100 outputs odd-numbered row data W according to the first set duration T1 in odd-numbered frames. D1 , the first set time length T1 is greater than the charging time of the even-numbered row sub-pixels and less than or equal to twice the charging time of the even-numbered row sub-pixels; and, in the even-numbered frame, the even-numbered row data W is output according to the second set time length T2 D2 The second set time duration T2 is greater than the charging time of the odd-numbered rows of sub-pixels and less than or equal to twice the charging time of the odd-numbered rows of sub-pixels. Thus, in odd frames, the charging time of the odd-numbered rows of sub-pixels 310 is longer, which helps ensure that the odd-numbered rows of sub-pixels 310 can display the target grayscale in odd frames. In even frames, the charging time of the even-numbered rows of sub-pixels 310 is also longer, which helps ensure that the even-numbered rows of sub-pixels 310 can display the target grayscale in even frames.

[0142] In some embodiments, see Figure 4A In odd frames, the first set time duration T1 is twice the charging time of the sub-pixels in the even rows. In this case, the sub-pixels 310 in the odd rows in the odd frames take longer to charge. When charging is complete, the output voltage of the source driver circuit 100 in the odd rows in the odd frames reaches a maximum value and does not change, thereby further ensuring that the sub-pixels 310 in the odd rows in the odd frames can display the target grayscale.

[0143] In other embodiments, participation Figure 4BIn even frames, the second set time duration T2 is twice the charging time of the odd-numbered rows of sub-pixels. In this case, the charging time of the even-numbered rows of sub-pixels 310 in even frames is longer. When charging is complete, the output voltage of the even-numbered rows of the source driver circuit 100 in even frames can reach a maximum value and no longer change, thereby further ensuring that the even-numbered rows of sub-pixels 310 in even frames can display the target grayscale.

[0144] In some other embodiments, in odd frames, the first set duration T1 is twice the charging time of the even-numbered row sub-pixels, and in even frames, the second set duration T2 is twice the charging time of the odd-numbered row sub-pixels. In this way, the charging time of the odd-numbered row sub-pixels 310 in odd frames is longer, and at the same time, the charging time of the even-numbered row sub-pixels 310 in even frames is also longer. When charging is completed, the output voltage of the source driver circuit 100 in the odd rows of odd frames can reach a maximum value, and the output voltage of the source driver circuit 100 in the even rows of even frames can also reach a maximum value, and both no longer change. This further ensures that the odd-numbered row sub-pixels 310 in odd frames can display the target grayscale, and the even-numbered row sub-pixels 310 in even frames can display the target grayscale.

[0145] In some embodiments, the first set time duration T1 is equal to the second set time duration T2. ​​In this way, the charging time of the sub-pixels 310 in the odd rows of odd frames and the sub-pixels 310 in the even rows of even frames are the same, and the charging time of the sub-pixels 310 in the even rows of odd frames and the sub-pixels 310 in the odd rows of even frames are the same, which helps to simplify the circuit structure of the source driver circuit 100, reduce the design difficulty of the source driver circuit 100, and thus reduce the manufacturing cost of the source driver circuit 100.

[0146] For example, the first set time length T1 and the second set time length T2 may both be 3.7 microseconds. In odd frames, the charging time of sub-pixels in even rows may be 1.85 microseconds, and in even frames, the charging time of sub-pixels in odd rows may be 1.85 microseconds.

[0147] Of course, the first set time length T1, the second set time length T2, the charging time of the sub-pixels in the even-numbered rows, and the charging time of the sub-pixels in the odd-numbered rows in the present disclosure are not limited thereto.

[0148] In some embodiments, as Figure 5 As shown, the logic control sub-circuit 10 includes a shield signal generating module 11, a latch signal generating module 12 and an enable signal generating module 13. The shield signal generating module 11 is coupled to the gate start signal terminal GSP and the mode switching signal terminal ODEN. The shield signal generating module 11 is configured to generate a signal according to the gate start signal W GSP and the first mode switching signal W OD1 , generating a first shielding signal W5 and a second shielding signal W6.

[0149] The latch signal generating module 12 is coupled to the shielding signal generating module 11 and the initial latch enable signal terminal LAT. The latch signal generating module 12 is configured to generate a latch signal according to the first shielding signal W5 and the initial latch enable signal W LA , generating a first latch signal W1; and, according to the second shielding signal W6 and the initial latch enable signal W LA , generating a second latch signal W2.

[0150] The enable signal generating module 13 is coupled to the shielding signal generating module 11 and the source output enable signal terminal SOE. The enable signal generating module 13 is configured to generate a first shielding signal W5 and a source output enable signal W SOE , generates a first enable signal W3; according to the second shielding signal W6 and the source output enable signal W SOE , generating a second enable signal W4.

[0151] In some embodiments, as Figure 6 and Figure 7 As shown, the shielding signal generating module 11 includes a distinguishing unit 111 and a generating unit 112 .

[0152] The distinguishing unit 111 is coupled to the pulse signal terminal CHOP, the gate start signal terminal GSP and the mode switching signal terminal ODEN. The distinguishing unit 111 is configured to, according to the pulse signal W from the pulse signal terminal CHOP, CH , gate start signal W GSP and the first mode switching signal W OD1 , output line characterization signal pair (W L1 , W L1B ) and frame characterization signal pair (W F1 , W F1B ). Line characterization signal pair (W L1 ,

[0153] W L1B ) represents odd and even rows, and the frame represents the signal pair (W F1 , W F1B ) represents odd frames and even frames.

[0154] For example, the pulse signal W of the pulse signal terminal CHOP CH The rising edge of the source output enable signal W SOE The rising edges of are at the same moment.

[0155] For example, the first row represents the signal W L1 It is low level during odd-numbered lines and high level during even-numbered lines. The first frame characterizes the signal W F1 It is a low level during odd-numbered frame times and a high level during even-numbered frame times.

[0156] Alternatively, the first row represents the signal W L1 It is high level during odd-numbered lines and low level during even-numbered lines. The first frame characterizes the signal W F1 It is high level during odd frame time and low level during even frame time.

[0157] The generating unit 112 is coupled to the distinguishing unit 111. The generating unit 112 is configured to generate the signal pair (W L1 , W L1B ), frame representation signal pair (W F1 , W F1B ) and the source output enable signal W SOE The inverted delayed signal W SBD , generating a first shielding signal W5 and a second shielding signal W6.

[0158] For example, the source output enable signal W SOE The inverted delayed signal W SBD The inverted delayed signal terminal SOEBD can be generated by the timing control circuit 200 and provided to the source driver circuit 100. Figure 6 , the generating unit 112 can be coupled to the inverted delay signal terminal SOEBD to receive the source output enable signal W SOE The inverted delayed signal W SBD .

[0159] For example, the source output enable signal W SOE The inverted delayed signal W SBD Alternatively, the source driver circuit 100 may output an enable signal W to the source. SOE Obtained by inverting and delaying. Figure 7 The source driver circuit 100 may further include an inverting delay module 14. The inverting delay module 14 is coupled to the source output enable signal terminal SOE and the generating unit 112. The inverting delay module 14 is configured to receive the source output enable signal W from the source output enable signal terminal SOE. SOE , and output enable signal W to the source SOE Perform data inversion delay processing to obtain the source output enable signal W SOE The inverted delayed signal W SBD , the inverted delayed signal W SBD Output to the generation unit 112.

[0160] For example, the inverting delay module 14 may include an RC delay circuit. Of course, the inverting delay module 14 in the present disclosure is not limited thereto.

[0161] For example, Figure 8 and Figure 9 As shown, the distinguishing unit 111 includes a NAND gate 1111 , a first NOT gate 1112 , a first trigger 1113 , a first AND gate 1114 , and a second trigger 1115 .

[0162] The NAND gate 1111 has a first input terminal coupled to the pulse signal terminal CHOP, and a second input terminal coupled to the gate start signal terminal GSP.

[0163] The first NOT gate 1112 has an input terminal coupled to the output terminal of the NAND gate 1111 .

[0164] A first flip-flop 1113 is provided. An enable terminal of the first flip-flop 1113 is coupled to an output terminal of the first NOT gate 1112. A reset terminal of the first flip-flop 1113 is coupled to the mode switching signal terminal ODEN. A first output terminal and a second output terminal of the first flip-flop 1113 are coupled to the generating unit 112. An input terminal of the first flip-flop 1113 is coupled to a first output terminal of the first flip-flop 1113. The first output terminal of the first flip-flop 1113 is configured to output a first frame characterization signal W. F1 The second output terminal of the first trigger 1113 is configured to output the second frame characterization signal W F1B , the first frame represents the signal W F1 and the second frame representation signal W F1B Inverted, forming a frame representation signal pair (W F1 , W F1B ).

[0165] A first AND gate 1114 has a first input terminal coupled to the output terminal of the NAND gate 1111 , and a second input terminal coupled to the mode switching signal terminal ODEN.

[0166] A second flip-flop 1115 is provided. An enable terminal of the second flip-flop 1115 is coupled to the pulse signal terminal CHOP. A reset terminal of the second flip-flop 1115 is coupled to the output terminal of the first AND gate 1114. A first output terminal and a second output terminal of the second flip-flop 1115 are coupled to the generating unit 112. An input terminal of the second flip-flop 1115 is coupled to a first output terminal of the second flip-flop 1115. The first output terminal of the second flip-flop 1115 is configured to output the first row characterization signal W. L1 The second output terminal of the second flip-flop 1115 is configured to output the second row characterization signal W L1B , the first row represents the signal W L1 and the second line represents the signal W L1B Inverted, forming a row characterization signal pair (W L1 , W L1B ).

[0167] For example, the first flip-flop 1113 and the second flip-flop 1115 may be edge-triggered D flip-flops. The enable terminals of the first flip-flop 1113 and the second flip-flop 1115 are valid when the signal rises.

[0168] For example, Figure 8 and Figure 10 As shown, the generating unit 112 includes a multiplier 1121 and a third flip-flop 1122 .

[0169] The first input terminal and the second input terminal of the multiplier 1121 are coupled to the distinguishing unit 111 and configured to receive the row characterization signal pair (W L1 , W L1B The third input terminal and the fourth input terminal of the multiplier 1121 are coupled to the distinguishing unit 111 and configured to receive the frame characterizing signal pair (W F1 , W F1B ).

[0170] The third flip-flop 1122 has an input terminal coupled to the output terminal of the multiplier 1121, and an enable terminal of the third flip-flop 1122 is configured to receive a source output enable signal W SOE The inverted delayed signal W SBD , the output terminal of the third flip-flop 1122 is configured to output the first shielding signal W5 and the second shielding signal W6.

[0171] For example, the third flip-flop 1122 may be an edge-triggered D flip-flop, wherein the enable terminal of the third flip-flop 1122 is valid when the signal rises.

[0172] For example, Figure 8 and Figure 11 As shown, the latch signal generating module 12 includes a second NOT gate 121 and a second AND gate 122 .

[0173] The second NOT gate 121 has an input terminal coupled to the shielding signal generating module 11 .

[0174] A second AND gate 122 has a first input coupled to the output of the second NOT gate 121, a second input coupled to the initial latch enable signal LAT, and an output of the second AND gate 122 configured to output the first latch signal W1 or the second latch signal W2.

[0175] For example, Figure 8 and Figure 12 As shown, the enable signal generating module 13 includes a signal generator 131 .

[0176] An input terminal of the signal generator 131 is coupled to the source output enable signal terminal SOE, and an enable terminal of the signal generator 131 is coupled to the shielding signal generating module 11. An output terminal of the signal generator 131 is configured to output a first enable signal W3 and a second enable signal W4.

[0177] For example, in odd frames, the source outputs the enable signal W SOE , gate start signal W GSP , pulse signal W CH , initial latch enable signal W LA , source output enable signal W SOE The inverted delayed signal W SBD The first row represents the signal W L1 , the first frame characterization signal W F1 , the signal W output by the multiplier 1121 F1L1 , the first shielding signal W5, the first latch signal W1, the first enable signal W3 and the odd row data W D1 The timing diagram is as follows Figure 13A shown.

[0178] by Figure 13A For example, Figure 8 The working process of the logic control sub-circuit 10 in the odd frame is briefly described. For example, the first mode switching signal W OD1 The rising edge of the first latch signal W1 is used to control the latch sub-circuit 20 to latch data, and the rising edge of the first enable signal W3 is used to control the output sub-circuit 30 to output data.

[0179] At time t0:

[0180] Pulse signal W CH From low level to high level, the pulse signal W CH The high level and gate start signal W GSP The high level of is converted to a low level by the NAND gate 1111, and then converted to a high level by the first NOT gate 1112, so that the enable terminal of the first flip-flop 1113 is valid (ie, rising edge triggered).

[0181] At this time, the input terminal of the first flip-flop 1113 is connected to the first output terminal of the first flip-flop 1113, so that the level output by the second output terminal of the first flip-flop 1113 is the same as the level of the first output terminal of the first flip-flop 1113 before time t0, that is, a high level. The level output by the first output terminal of the first flip-flop 1113 changes from the original high level to a low level at time t0.

[0182] The first output terminal of the first trigger 1113 outputs the first frame characterization signal W F1, the first frame represents the signal W F1 The low level of the first frame (ie, odd frame) represents the first frame. The second output terminal of the first trigger 1113 outputs the second frame characterization signal W F1B , the second frame represents the signal W F1B The high level also represents the first frame (i.e., odd-numbered frame).

[0183] Pulse signal W CH The level changes from low to high, making the enable terminal of the second flip-flop 1115 valid (ie, rising edge triggered).

[0184] At this time, the input terminal of the second flip-flop 1115 is connected to the first output terminal of the second flip-flop 1115, so that the level output by the second output terminal of the second flip-flop 1115 is the same as the level of the first output terminal of the second flip-flop 1115 before time t0, that is, a high level. The level output by the first output terminal of the second flip-flop 1115 changes from the original high level to a low level at time t0.

[0185] The first output terminal of the second flip-flop 1115 outputs the first row characterization signal W L1 , the first row represents the signal W L1 The low level of represents the first row (ie, odd row), and the second output terminal of the second flip-flop 1115 outputs the second row characterization signal W L1B , the second row represents the signal W L1B The high level of represents the first row (i.e., the odd row).

[0186] The multiplier 1121 receives the first row characterization signal W L1 The second row represents the signal W L1B , the first frame characterization signal W F1 and the second frame representation signal W F1B , output high level. That is, W F1L1 The level at time t0 becomes high.

[0187] Since the enable terminal of the third flip-flop 1122 is valid at the rising edge, at time t0, the source outputs the enable signal W SOE The inverted delayed signal W SBD The enable terminal of the third flip-flop 1122 is invalid, and the output terminal of the third flip-flop 1122 still outputs a low level. That is, the first shielding signal W5 outputted at the output terminal of the third flip-flop 1122 is a low level.

[0188] In this way, the source outputs the enable signal W SOE The inverted delayed signal W SBD Before the rising edge of the first shielding signal W5 arrives, the first shielding signal W5 passes through the second NOT gate 121 and is latched with the initial latch enable signal W LAThe waveform of the first latch signal W1 obtained after passing through the second AND gate 122 is the same as the initial latch enable signal W LA Thus, when the first row of data arrives, the rising edge of the first latch signal W1 can control the latch sub-circuit 20 to latch the first row of data.

[0189] Similarly, the source outputs the enable signal W SOE The inverted delayed signal W SBD Before the rising edge of , the first shielding signal W5 is low level, the enable terminal of the signal generator 131 is invalid, and the first enable signal W3 remains the same as the source output enable signal W SOE Thus, the first enable signal W3 is able to control the output sub-circuit 30 to output the third row data.

[0190] At time t1:

[0191] Source output enable signal W SOE The inverted delayed signal W SBD The enable terminal of the third flip-flop 1122 is valid, and the output terminal of the third flip-flop 1122 outputs a high level, that is, the first shielding signal W5 is converted from a low level to a high level.

[0192] In this way, the source outputs the enable signal W SOE The inverted delayed signal W SBD Before the next rising edge of , the first shielding signal W5 keeps high level. The first shielding signal W5 is connected to the initial latch enable signal W via the second NOT gate 121. LA The first latch signal W1 obtained after passing through the second AND gate 122 is always kept at a low level, so that after the second row of data arrives, the latch sub-circuit 20 no longer latches the second row of data.

[0193] Similarly, the source outputs the enable signal W SOE The inverted delayed signal W SBD Before the next rising edge of , the first shielding signal W5 keeps high level and is effective at the enable terminal of the signal generator 131. The first enable signal W3 no longer outputs the enable signal W along with the source. SOE Thus, the source driver circuit 100 always outputs odd-numbered row data.

[0194] At time t2:

[0195] Pulse signal W CH Once again from low level to high level, the gate start signal W GSP It is always low level, so the pulse signal W CH and gate start signal W GSPAfter passing through the NAND gate 1111 and the first NOT gate 1112 , the first NOT gate 1112 outputs a low level, without rising edge triggering, and the enable terminal of the first trigger 1113 is invalid.

[0196] The first output terminal of the first flip-flop 1113 keeps outputting a low level, and the second output terminal of the first flip-flop 1113 keeps outputting a high level, thereby still representing the first frame (ie, the odd frame).

[0197] Pulse signal W CH The level changes from low to high again, thereby making the enable terminal of the second flip-flop 1115 valid again (ie, rising edge triggered).

[0198] At this time, the input terminal of the second flip-flop 1115 is connected to the first output terminal of the second flip-flop 1115, so that the level output by the second output terminal of the second flip-flop 1115 is the same as the level of the first output terminal of the second flip-flop 1115 before time t2, that is, a low level. The level output by the first output terminal of the second flip-flop 1115 changes from the original low level to a high level at time t2.

[0199] The first output terminal of the second flip-flop 1115 outputs the first row characterization signal W L1 , the first row represents the signal W L1 The high level of represents the second row (ie, the even row), and the second output terminal of the second flip-flop 1115 outputs the second row characterization signal W L1B , the second row represents the signal W L1B A low level indicates the second row (ie, the even row).

[0200] The multiplier 1121 receives the first row characterization signal W L1 The second row represents the signal W L1B , the first frame characterization signal W F1 and the second frame representation signal W F1B , output low level. That is, W F1L1 The level at time t2 becomes a low level.

[0201] Since the enable terminal of the third flip-flop 1122 is valid at the rising edge, at time t2, the source outputs the enable signal W SOE The inverted delayed signal W SBD = is high level, therefore, the output terminal of the third flip-flop 1122 still outputs a high level. That is, the first shielding signal W5 outputted at the output terminal of the third flip-flop 1122 is high level.

[0202] In this way, the source outputs the enable signal W SOE The inverted delayed signal W SBD Before the rising edge of the first shielding signal W5 arrives, the first shielding signal W5 passes through the second NOT gate 121 and is latched with the initial latch enable signal WLA The first latch signal W1 obtained after passing through the second AND gate 122 always maintains a low level. Therefore, after the second row of data arrives, no rising edge appears in the first latch signal W1, and the latch sub-circuit 20 no longer latches the second row of data.

[0203] Similarly, the source outputs the enable signal W SOE The inverted delayed signal W SBD Before the rising edge of , the first shielding signal is high level and is valid at the enable terminal of the signal generator 131. The first enable signal W3 no longer outputs the enable signal W along with the source. SOE Thus, the source driver circuit 100 always outputs odd-numbered row data.

[0204] At time t3:

[0205] Source output enable signal W SOE The inverted delayed signal W SBD The enable terminal of the third flip-flop 1122 is valid, and the output terminal of the third flip-flop 1122 outputs a low level, that is, the first shielding signal W5 is converted from a high level to a low level.

[0206] In this way, the first shielding signal W5 is coupled to the initial latch enable signal W via the second NOT gate 121. LA The waveform of the first latch signal W1 obtained after passing through the second AND gate 122 is again combined with the initial latch enable signal W LA Thus, when the third row of data arrives, the rising edge of the first latch signal W1 can control the latch sub-circuit 20 to latch the third row of data.

[0207] Similarly, the first shielding signal W5 is at a low level, and the enable terminal of the signal generator 131 is invalid, and the first enable signal W3 remains at the same level as the source output enable signal W. SOE Thus, the first enable signal W3 is able to control the output sub-circuit 30 to output the third row data.

[0208] At time t4:

[0209] Pulse signal W CH From low level to high level, the same as time t2, the first output terminal of the first flip-flop 1113 keeps outputting low level, thereby still representing the first frame (ie, odd frame).

[0210] The enable terminal of the second flip-flop 1115 is again valid (i.e., rising edge triggered). At this point, the input terminal of the second flip-flop 1115 is connected to the first output terminal of the second flip-flop 1115, so that the level output by the second output terminal of the second flip-flop 1115 is the same as the level of the first output terminal of the second flip-flop 1115 before time t4, that is, a high level. The level output by the first output terminal of the second flip-flop 1115 changes from the original high level to a low level at time t4.

[0211] The first output terminal of the second flip-flop 1115 outputs the first row characterization signal W L1 , the first row represents the signal W L1 The low level of represents the third row (ie, the odd row), and the second output terminal of the second flip-flop 1115 outputs the second row characterization signal W L1B , the second row represents the signal W L1B The high level of represents the third row (ie, the odd row).

[0212] The multiplier 1121 receives the first row characterization signal W L1 The second row represents the signal W L1B , the first frame characterization signal W F1 and the second frame representation signal W F1B , output high level. That is, W F1L1 The level at time t4 becomes a high level.

[0213] Since the enable terminal of the third flip-flop 1122 is valid at the rising edge, at time t4, the source outputs the enable signal W SOE The inverted delayed signal W SBD = is high level, therefore, the output terminal of the third flip-flop 1122 still outputs a low level. That is, the first shielding signal W5 outputted at the output terminal of the third flip-flop 1122 is low level.

[0214] In this way, the first shielding signal W5 is coupled to the initial latch enable signal W via the second NOT gate 121. LA The waveform of the first latch signal W1 obtained after passing through the second AND gate 122 is still the same as the initial latch enable signal W LA Thus, when the third row of data arrives, the rising edge of the first latch signal W1 can control the latch sub-circuit 20 to latch the third row of data.

[0215] Similarly, the first shielding signal W5 is at a low level, and the enable terminal of the signal generator 131 is invalid, and the first enable signal W3 remains at the same level as the source output enable signal W. SOE Thus, the first enable signal W3 is able to control the output sub-circuit 30 to output the third row data.

[0216] Referring to the working process of the source driver circuit 100 from time t0 to time t4, in the odd frame, and after time t4, the first frame characterization signal W F1 Still outputting low level, the second frame represents signal W F1B Still outputs a high level, thus representing the first frame (i.e., odd-numbered frame).

[0217] The first row represents the signal W L1 Then the pulse signal W CH Under the control of the odd-numbered rising edge, the output is low level. The second line represents the signal W L1B Also in the pulse signal W CH Under the control of the odd-numbered rising edge of the pulse signal, the output is high level. CH The odd-numbered rising edge represents the odd rows.

[0218] The first row represents the signal W L1 Still in pulse signal W CH Under the control of the even-numbered rising edge, the output is high level. The second line represents the signal W L1B Also in the pulse signal W CH Under the control of the even-numbered rising edge of the pulse signal, the output is low level. CH The even-numbered rising edge of represents the even-numbered rows.

[0219] The multiplier 1121 also receives the first row characterization signal W L1 The second row represents the signal W L1B , the first frame characterization signal W F1 and the second frame representation signal W F1B , then output signal W F1L1 . In the pulse signal W CH When the odd-numbered rising edge of F1L1 From low level to high level, the pulse signal W CH When the even-numbered rising edge of F1L1 From high level to low level.

[0220] The first shielding signal W5 is then used to enable the output signal W at the source. SOE The inverted delayed signal W SBD Under the control of the signal W F1L1 The same level is achieved, so that the first latch signal W1 controls the latch sub-circuit 20 to latch only the odd-numbered row data in the odd-numbered frame, and the first enable signal W3 controls the output sub-circuit 30 to output only the odd-numbered row data in the odd-numbered frame.

[0221] For example, in even frames, the source outputs the enable signal W SOE , gate start signal W GSP , pulse signal WCH , initial latch enable signal W LA , source output enable signal W SOE The inverted delayed signal W SBD The first row represents the signal W L1 , the first frame characterization signal W F1 , the signal W output by the multiplier 1121 F1L1 , the second shielding signal W6, the second latch signal W2, the second enable signal W4 timing diagram and the even row data W D2 The timing diagram is as follows Figure 13B shown.

[0222] in, Figure 8 The working process of the logic control subcircuit 10 in the even frame will not be described here. The working process of the logic control subcircuit 10 in the even frame can be combined with the working process of the logic control subcircuit 10 in the odd frame and the working process of the logic control subcircuit 10 in the odd frame. Figure 13B Understand.

[0223] It is worth noting that in the even frames, the pulse signal W CH When the gate start signal W changes from low level to high level for the first time (i.e., the first rising edge), GSP At high level again, the pulse signal W CH The high level and gate start signal W GSP The high level of is converted to a low level by the NAND gate 1111, and then converted to a high level by the first NOT gate 1112, so that the enable terminal of the first flip-flop 1113 is valid (ie, rising edge triggered).

[0224] At this time, the input terminal of the first flip-flop 1113 is connected to the first output terminal of the first flip-flop 1113, so that the level output by the second output terminal of the first flip-flop 1113 is the same as the level of the first output terminal of the first flip-flop 1113 in odd frames, that is, a low level. The level output by the first output terminal of the first flip-flop 1113 is converted from the previous low level to a high level.

[0225] That is, the first frame characterizing signal W outputted from the first output terminal of the first trigger 1113 is F1 = is high, indicating the second frame (ie, even frame). The second output terminal of the first flip-flop 1113 outputs the second frame indicating signal W. F1B is low level, also representing the second frame (ie, even frame). And in the second frame (ie, even frame), the first frame represents the signal W F1 and the second frame representation signal W F1B The level no longer changes.

[0226] In some embodiments, the first mode switching signal W OD1The first mode switching signal W may be kept at a high level in both odd and even frames. OD1 It can be kept low in both odd and even frames.

[0227] In some embodiments, see Figure 14 and Figure 15 The logic control sub-circuit 10 is further configured to, according to the gate start signal W GSP and the second mode switching signal W from the mode switching signal terminal ODEN OD2 , receives and outputs the initial latch enable signal W LA and source output enable signal W SOE .

[0228] The latch module 20 is further configured to latch the enable signal W LA Under the control of the data signal W, the data signal W is latched in each frame. D Odd-numbered row data W D1 and even-numbered row data W D2 .

[0229] The output module 30 is further configured to output an enable signal W at the source. SOE Under the control of , odd-numbered row data W is output in each frame D1 and even-numbered row data W D2 The charging time of the odd-numbered row sub-pixels is equal to that of the even-numbered row sub-pixels. D1 and even-numbered row data W D2 The data output time is equal.

[0230] In this way, the source driver circuit 100 can simultaneously have two driving modes. The first mode outputs odd-numbered row data for a first set duration in odd frames, and outputs even-numbered row data for a second set duration in even frames. The second mode outputs both odd-numbered row data and even-numbered row data in every frame, with the output durations of the odd and even rows being equal. This improves the diversity of the driving modes of the source driver circuit 100.

[0231] In some embodiments, as Figure 16 As shown, the source driver circuit 100 further includes a level conversion and digital-to-analog conversion sub-circuit 40 .

[0232] The level conversion and digital-to-analog conversion sub-circuit 40 is coupled to the latch sub-circuit 20 and the output sub-circuit 30. The level conversion and digital-to-analog conversion sub-circuit 40 is configured to receive odd-numbered row data W in odd-numbered frames. D1 , and for odd-numbered rows of data W D1 Perform level conversion and digital-to-analog conversion; and, receive even-numbered line data W in even-numbered frames D2 , and for even-numbered rows of data W D2The present disclosure does not impose any specific limitation on the circuit structure of the level conversion and digital-to-analog conversion sub-circuit 40 .

[0233] For example, level conversion can amplify odd-numbered line data or even-numbered line data.

[0234] In some embodiments, as Figure 17 As shown, the source driver circuit 100 further includes an output buffer 50 coupled to the latch sub-circuit 20 and the output sub-circuit 30. The output buffer 50 is configured to receive odd-numbered row data W in odd-numbered frames. D1 , and temporarily store odd-numbered row data W D1 ; and, receiving even-numbered row data W in even-numbered frames D2 , and temporarily store the even-numbered row data W D2 .

[0235] The present disclosure does not impose any particular limitation on the circuit structure of the output buffer 50 .

[0236] In some embodiments, as Figure 18 As shown, the source driver circuit 100 may include a level conversion and digital-to-analog conversion sub-circuit 40 and an output buffer 50. In this case, the level conversion and digital-to-analog conversion sub-circuit 40 is coupled to the latch sub-circuit 20 and the output buffer 50, and the output buffer 50 is coupled to the level conversion and digital-to-analog conversion sub-circuit 40 and the output sub-circuit 30.

[0237] like Figure 19 As shown, in some embodiments of the present disclosure, a source driving method is provided, including:

[0238] S100, in each frame, receiving the source data signal W DT , the source data signal W DT Converted into data signal W D .

[0239] In odd frames:

[0240] S200, according to the gate start signal W GSP , the first mode switching signal W OD1 , initial latch enable signal W LA and source output enable signal W SOE , generating a first latch signal W1 and a first enable signal W3.

[0241] S300, under the control of the first latch signal W1, latch the data signal W D Odd-numbered row data W D1 .

[0242] S400 : Under the control of the first enable signal W1 , output odd-numbered row data for a first set time duration T1 , which is greater than the charging time of even-numbered row sub-pixels and less than or equal to twice the charging time of even-numbered row sub-pixels.

[0243] In even frames:

[0244] S200', according to the gate start signal W GSP , the first mode switching signal W OD1 , initial latch enable signal W LA and source output enable signal W SOE , generating a second latch signal W2 and a second enable signal W4.

[0245] S300′ latches the data signal W under the control of the second latch signal W2. D Even-numbered rows of data W D2 .

[0246] S400′ outputs the even row data W according to the second set time length T2 under the control of the second enable signal W2. D2 The second set time duration T2 is greater than the charging time of the sub-pixels in the odd-numbered rows, and is less than or equal to twice the charging time of the sub-pixels in the odd-numbered rows.

[0247] The beneficial effects that can be achieved by the source driving method provided in some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the above-mentioned source driving circuit, and will not be repeated here.

[0248] In some embodiments, in odd frames, the first set time duration T1 is twice the charging time of the sub-pixels in even rows.

[0249] In some other embodiments, in even frames, the second set time duration T2 is twice the charging time of the sub-pixels in odd rows.

[0250] In some other embodiments, in odd frames, the first set time duration T1 is twice the charging time of the sub-pixels in even rows, and in even frames, the second set time duration T2 is twice the charging time of the sub-pixels in odd rows.

[0251] In some embodiments, as Figure 20 As shown, step S200, according to the gate start signal W GSP , the first mode switching signal W OD1 , initial latch enable signal W LA and source output enable signal W SOE , generating a first latch signal W1 and a first enable signal W3, including:

[0252] S210, according to the gate start signal W GSP and the first mode switching signal WOD1 , generating a first shielding signal W5.

[0253] For example, Figure 21 As shown, S210, according to the gate start signal W GSP and the first mode switching signal W OD1 , generating a first shielding signal W5, comprising:

[0254] S211, receiving pulse signal W CH , according to the pulse signal W CH , gate start signal W GSP and the first mode switching signal W OD1 , generate row characterization signal pairs (W L1 , W L1B ) and frame characterization signal pair (W F1 , W F1B ). Line characterization signal pair (W L1 , W L1B ) includes the first row of mutually inverted characterization signals W L1 and the second line represents the signal W L1B , frame characterization signal pair (W F1 , W F1B ) includes the first frame representation signal W which is inversely proportional to each other F1 and the second frame representation signal W F1B .

[0255] S212, according to the row characterization signal pair (W L1 , W L1B ), frame representation signal pair (W F1 , W F1B ) and the source output enable signal W SOE The inverted delayed signal W SBD , generating a first shielding signal W5.

[0256] Among them, the first row represents the signal W L1 It is low level during odd-numbered lines and high level during even-numbered lines. The first frame characterizes the signal W F1 It is a low level during odd-numbered frame times and a high level during even-numbered frame times.

[0257] Alternatively, the first row represents the signal W L1 It is high level during odd-numbered lines and low level during even-numbered lines. The first frame characterizes the signal W F1 It is high level during odd frame time and low level during even frame time.

[0258] S220, according to the first shielding signal W5 and the initial latch enable signal W LA , generating a first latch signal W1.

[0259] S230, according to the first shielding signal W5 and the source output enable signal W SOE , generating a first enable signal W3.

[0260] In some embodiments, as Figure 22 As shown, S200', according to the gate start signal W GSP , the first mode switching signal W OD1 , initial latch enable signal W LA and source output enable signal W SOE , generating a second latch signal W2 and a second enable signal W4, including:

[0261] S210', according to the gate start signal W GSP and the first mode switching signal W OD1 , generating a second shielding signal W6.

[0262] For example, Figure 23 As shown, S210', according to the gate start signal W GSP and the first mode switching signal W OD1 , generating a second shielding signal W6, comprising:

[0263] S211', receiving pulse signal W CH , according to the pulse signal W CH , gate start signal W GSP and the first mode switching signal W OD1 , generate row characterization signal pairs (W L1 , W L1B ) and frame characterization signal pair (W F1 , W F1B ). Line characterization signal pair (W L1 , W L1B ) includes the first row of mutually inverted characterization signals W L1 and the second line represents the signal W L1B , frame characterization signal pair (W F1 , W F1B ) includes the first frame representation signal W which is inversely proportional to each other F1 and the second frame representation signal W F1B .

[0264] S212', according to the row characterization signal pair (W L1 , W L1B ), frame representation signal pair (W F1 , W F1B ) and the source output enable signal W SOE The inverted delayed signal W SBD , generating a second shielding signal W6.

[0265] Among them, the first row represents the signal W L1 It is low level during odd-numbered lines and high level during even-numbered lines; the first frame characterizes the signal W F1 It is low level in odd frame time and high level in even frame time; or, the first line represents signal W L1 It is high level during odd-numbered lines and low level during even-numbered lines; the first frame characterizes the signal W F1 It is high level during odd frame time and low level during even frame time.

[0266] S220′, according to the second shielding signal W6 and the initial latch enable signal W LA , generating a second latch signal W2.

[0267] S230′, according to the second shielding signal W6 and the source output enable signal W SOE , generating a second enable signal W4.

[0268] like Figure 24 As shown, in some embodiments of the present disclosure, another source driving method is provided, including:

[0269] S1. In each frame, receive the source data signal W DT , the source data signal W DT Converted into data signal W D .

[0270] S2, according to the gate start signal W GSP and the second mode switching signal W OD2 , receives and outputs the initial latch enable signal W LA and source output enable signal W SOE .

[0271] S3, at the initial latch enable signal W LA Under the control of the data signal W, the data signal W is latched in each frame. D Odd-numbered row data W D1 and even-numbered row data W D2 .

[0272] S4, output enable signal W at the source SOE Under the control of , odd-numbered row data W is output in each frame D1 and even-numbered row data W D2 The charging time of the sub-pixels in the odd-numbered rows is equal to the charging time of the sub-pixels in the even-numbered rows.

[0273] Some embodiments of the present disclosure provide a display driving method, which is applied to the display device 1000 described in any of the above embodiments. Figure 25 As shown, the display driving method includes:

[0274] S01: In each frame, the timing control circuit 200 sends a source data signal W to the source driver circuit 100. DT , gate start signal W GSP , the first mode switching signal W OD1 , initial latch enable signal W LA and source output enable signal W SOE , the source driving circuit 100 converts the source data signal W DT Convert data signal W D .

[0275] In odd frames:

[0276] S02, the source driving circuit 100 is activated according to the gate start signal W GSP , the first mode switching signal W OD1 , initial latch enable signal W LA and source output enable signal W SOE , latch data signal W D Odd-numbered row data W D1 , and output odd row data W according to the first set time length T1 D1 .

[0277] S03, the timing control circuit 200 controls the sub-pixels 310 of each row of the display panel 300 to be turned on row by row, and uses the odd row data W D1 Charging is performed, wherein the charging time of the odd-numbered sub-pixels is the first set time length T1, and the charging time of the even-numbered sub-pixels is greater than or equal to half of the first set time length T1 and less than the first set time length T1.

[0278] In even frames:

[0279] S02', the source driving circuit 100 generates a gate start signal W GSP , the first mode switching signal W OD1 , initial latch enable signal W LA and source output enable signal W SOE , latching the data signal W D Even-numbered row data W D2 , and output the even-numbered row data W according to the second set time length T1 D2 .

[0280] S03', the timing control circuit 200 controls the sub-pixels 310 of each row of the display panel 300 to be turned on row by row, and uses the even-numbered row data W D2 Charging is performed, wherein the charging time of the sub-pixels in the even rows is the second set time length T2, and the charging time of the sub-pixels in the odd rows is greater than or equal to half of the second set time length T2 and less than the second set time length T2.

[0281] The beneficial effects that can be achieved by the display driving method provided in some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the above-mentioned source driving circuit, and will not be repeated here.

[0282] In some embodiments, in odd frames, the charging time of the sub-pixels in even rows is equal to half of the first set time duration T1.

[0283] In some other embodiments, in even frames, the charging time of the sub-pixels in odd rows is equal to half of the second set time duration T2.

[0284] In some other embodiments, in odd frames, the charging time of sub-pixels in even rows is equal to half of the first set time duration T1, and in even frames, the charging time of sub-pixels in odd rows is equal to half of the second set time duration T2.

[0285] In some examples, such as Figure 4A and Figure 4B As shown, in an odd frame, in two adjacent rows of sub-pixels 310, when the charging time of the odd-numbered sub-pixels 310 is half of the first set time length T1, the even-numbered sub-pixels 310 are turned on for charging. In an even frame, in two adjacent rows of sub-pixels 310, when the charging time of the even-numbered sub-pixels 310 is half of the second set time length T2, the odd-numbered sub-pixels 310 are turned on for charging.

[0286] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A source driver circuit comprising: a logic control subcircuit coupled to the source data signal terminal, the gate start signal terminal, the mode switch signal terminal, the initial latch enable signal terminal, and the source output enable signal terminal; the logic control subcircuit is configured to receive a source data signal from the source data signal terminal and convert the source data signal into a data signal; and, outputting a first latch signal, a second latch signal, a first enable signal, and a second enable signal according to a gate start signal from the gate start signal terminal, a first mode switch signal from the mode switch signal terminal, an initial latch enable signal from the initial latch enable signal terminal, and a source output enable signal from the source output enable signal terminal; a latch subcircuit coupled to the logic control subcircuit; the latch subcircuit being configured to receive a data signal from the logic control subcircuit; and, under the control of the first latch signal, latch odd-numbered row data of the data signal in odd-numbered frames, and under the control of the second latch signal, latch even-numbered row data of the data signal in even-numbered frames; an output subcircuit coupled to the latch subcircuit and the logic control subcircuit; the output subcircuit being configured to receive the odd-numbered row data in an odd-numbered frame and, under the control of the first enable signal, output the odd-numbered row data for a first set duration, wherein the first set duration is greater than a charging time of sub-pixels in the even-numbered rows and less than or equal to twice the charging time of sub-pixels in the even-numbered rows; And, receiving the even row data in the even frame, and outputting the even row data according to the second set duration under the control of the second enable signal, wherein the second set duration is greater than the charging time of the odd row sub-pixels and less than or equal to twice the charging time of the odd row sub-pixels.

2. The source driver circuit according to claim 1, wherein: In odd frames, the first set time length is twice the charging time of the sub-pixels in even rows; and / or, in even frames, the second set time length is twice the charging time of the sub-pixels in odd rows.

3. The source driver circuit according to claim 1 or 2, wherein: The logic control subcircuit includes: a shielding signal generating module coupled to the gate start signal terminal and the mode switching signal terminal; the shielding signal generating module is configured to generate a first shielding signal and a second shielding signal according to the gate start signal and the first mode switching signal; a latch signal generating module coupled to the shielding signal generating module and the initial latch enable signal terminal; the latch signal generating module being configured to generate a first latch signal according to the first shielding signal and the initial latch enable signal; and to generate a second latch signal according to the second shielding signal and the initial latch enable signal; An enable signal generating module is coupled to the shielding signal generating module and the source output enable signal terminal; the enable signal generating module is configured to generate a first enable signal according to the first shielding signal and the source output enable signal; and to generate a second enable signal according to the second shielding signal and the source output enable signal.

4. The source driver circuit according to claim 3, wherein: The shielding signal generating module includes: a distinguishing unit coupled to the pulse signal terminal, the gate start signal terminal, and the mode switching signal terminal; the distinguishing unit is configured to output a row characterizing signal pair and a frame characterizing signal pair according to the pulse signal from the pulse signal terminal, the gate start signal, and the first mode switching signal; the row characterizing signal pair characterizes odd rows and even rows, and the frame characterizing signal pair characterizes odd frames and even frames; A generating unit is coupled to the distinguishing unit; the generating unit is configured to generate a first shielding signal and a second shielding signal according to the row characterizing signal pair, the frame characterizing signal pair and the inverted delayed signal of the source output enable signal.

5. The source driver circuit according to claim 4, wherein: The distinguishing unit includes: A NAND gate, wherein a first input terminal of the NAND gate is coupled to the pulse signal terminal, and a second input terminal of the NAND gate is coupled to the gate start signal terminal; a first NOT gate, wherein an input terminal of the first NOT gate is coupled to an output terminal of the NAND gate; a first flip-flop, wherein an enable terminal of the first flip-flop is coupled to the output terminal of the first NOT gate, a reset terminal of the first flip-flop is coupled to the mode switching signal terminal, a first output terminal and a second output terminal of the first flip-flop are coupled to the generating unit, and an input terminal of the first flip-flop is coupled to the first output terminal of the first flip-flop; the first output terminal of the first flip-flop is configured to output a first frame characterizing signal, and the second output terminal of the first flip-flop is configured to output a second frame characterizing signal, the first frame characterizing signal and the second frame characterizing signal being in opposite phases, forming a frame characterizing signal pair; a first AND gate, wherein a first input terminal of the first AND gate is coupled to the output terminal of the NAND gate, and a second input terminal of the first AND gate is coupled to the mode switching signal terminal; A second trigger, an enable terminal of the second trigger is coupled to the pulse signal terminal, a reset terminal of the second trigger is coupled to the output terminal of the first AND gate, a first output terminal and a second output terminal of the second trigger are coupled to the generation unit, and an input terminal of the second trigger is coupled to the first output terminal of the second trigger; the first output terminal of the second trigger is configured to output a first row characterization signal, and the second output terminal of the second trigger is configured to output a second row characterization signal, the first row characterization signal and the second row characterization signal are inverted to form a row characterization signal pair.

6. The source driver circuit according to claim 4 or 5, wherein: The generating unit includes: a multiplier; a first input terminal and a second input terminal of the multiplier are coupled to the distinguishing unit and configured to receive the row characterizing signal pair; a third input terminal and a fourth input terminal of the multiplier are coupled to the distinguishing unit and configured to receive the frame characterizing signal pair; a third trigger, wherein the input terminal of the third trigger is coupled to the output terminal of the multiplier, the enable terminal of the third trigger is configured to receive an inverted delayed signal of the source output enable signal, and the output terminal of the third trigger is configured to output a first shielding signal and a second shielding signal.

7. The source driver circuit according to any one of claims 3 to 6, wherein: The latch signal generating module includes: a second NOT gate, wherein an input end of the second NOT gate is coupled to the shielding signal generating module; A second AND gate, wherein the first input terminal of the second AND gate is coupled to the output terminal of the second NOT gate, and the second input terminal of the second AND gate is coupled to the initial latch enable signal terminal; the output terminal of the second AND gate is configured to output the first latch signal or the second latch signal.

8. The source driver circuit according to any one of claims 3 to 7, wherein: The enable signal generating module includes: A signal generator; an input terminal of the signal generator is coupled to the source output enable signal terminal, and an enable terminal of the signal generator is coupled to the shielding signal generating module; an output terminal of the signal generator is configured to output the first enable signal and the second enable signal.

9. The source driver circuit according to any one of claims 1 to 8, wherein: The logic control subcircuit is further configured to receive and output the initial latch enable signal and the source output enable signal according to the gate start signal and the second mode switching signal from the mode switching signal terminal; The latch subcircuit is further configured to, under the control of the initial latch enable signal, latch the odd-numbered row data and the even-numbered row data of the data signal in each frame; The output module is further configured to output odd-numbered row data and even-numbered row data in each frame under the control of the source output enable signal; the charging time of the odd-numbered row sub-pixels and the even-numbered row sub-pixels is equal.

10. The source driver circuit according to any one of claims 1 to 9, further comprising: a level conversion and digital-to-analog conversion subcircuit, coupled to the latch subcircuit and the output subcircuit; The level conversion and digital-to-analog conversion subcircuit is configured to receive the odd-numbered line data in an odd-numbered frame and perform level conversion and digital-to-analog conversion on the odd-numbered line data; Furthermore, the even-numbered row data is received in an even-numbered frame, and level conversion and digital-to-analog conversion are performed on the even-numbered row data.

11. The source driver circuit according to any one of claims 1 to 10, further comprising: an output buffer coupled to the latch sub-circuit and the output sub-circuit; The output buffer is configured to receive the odd-numbered line data in an odd-numbered frame and temporarily store the odd-numbered line data; and to receive the even-numbered line data in an even-numbered frame and temporarily store the even-numbered line data.

12. The source driver circuit according to any one of claims 1 to 11, wherein: The first set time length is equal to the second set time length.

13. A source driving method, comprising: In each frame, receiving a source data signal and converting the source data signal into a data signal; In odd frames: generating a first latch signal and a first enable signal according to a gate start signal, a first mode switching signal, an initial latch enable signal, and a source output enable signal; Under the control of the first latch signal, latching odd-numbered row data of the data signal; Under the control of the first enable signal, odd-numbered row data is output according to a first set duration; the first set duration is greater than the charging time of the even-numbered row sub-pixels and less than or equal to twice the charging time of the even-numbered row sub-pixels; In even frames: generating a second latch signal and a second enable signal according to the gate start signal, the first mode switching signal, the initial latch enable signal, and the source output enable signal; Under the control of the second latch signal, latching the even-numbered row data of the data signal; Under the control of the second enable signal, outputting even-numbered row data according to a second set duration; The second set time length is greater than the charging time of the sub-pixels in the odd-numbered rows, and less than or equal to twice the charging time of the sub-pixels in the odd-numbered rows.

14. The source driving method according to claim 13, wherein: In odd frames, the first set time length is twice the charging time of the sub-pixels in even rows; and / or, in even frames, the second set time length is twice the charging time of the sub-pixels in odd rows.

15. The source driving method according to claim 13 or 14, wherein: The step of generating a first latch signal and a first enable signal according to a gate start signal, a first mode switching signal, an initial latch enable signal, and a source output enable signal comprises: generating a first shielding signal according to the gate start signal and the first mode switching signal; generating a first latch signal according to the first shielding signal and the initial latch enable signal; generating a first enable signal according to the first shielding signal and the source output enable signal; The generating of a second latch signal and a second enable signal according to the gate start signal, the first mode switching signal, the initial latch enable signal and the source output enable signal comprises: generating a second shielding signal according to the gate start signal and the first mode switching signal; generating a second latch signal according to the second shielding signal and the initial latch enable signal; A second enable signal is generated according to the second shielding signal and the source output enable signal.

16. The source driving method according to claim 15, wherein: Generating a first shielding signal according to the gate start signal and the first mode switching signal includes: receiving a pulse signal, and generating a row characterizing signal pair and a frame characterizing signal pair according to the pulse signal, the gate start signal, and the first mode switching signal; the row characterizing signal pair comprising a first row characterizing signal and a second row characterizing signal in opposite phases, and the frame characterizing signal pair comprising a first frame characterizing signal and a second frame characterizing signal in opposite phases; generating a first shielding signal according to the pair of row characterizing signals, the pair of frame characterizing signals, and an inverted delayed signal of the source output enable signal; Generating a second shielding signal according to the gate start signal and the first mode switching signal includes: receiving a pulse signal, and generating a row characterizing signal pair and a frame characterizing signal pair according to the pulse signal, the gate start signal, and the first mode switching signal; the row characterizing signal pair comprising a first row characterizing signal and a second row characterizing signal in opposite phases, and the frame characterizing signal pair comprising a first frame characterizing signal and a second frame characterizing signal in opposite phases; generating a second shielding signal according to the pair of row characterizing signals, the pair of frame characterizing signals, and an inverted delayed signal of the source output enable signal; The first line characterization signal is at a low level during odd line time and at a high level during even line time; the first frame characterization signal is at a low level during odd frame time and at a high level during even frame time; or The first line characterization signal is at a high level during odd line times and at a low level during even line times; the first frame characterization signal is at a high level during odd frame times and at a low level during even frame times.

17. A display device comprising: A plurality of source driver circuits according to any one of claims 1 to 12; at least one timing control circuit configured to output a source data signal, a gate start signal, a first mode switching signal, a second mode switching signal, an initial latch enable signal, and a source output enable signal; Each timing control circuit is coupled to at least two source driver circuits; The display panel is coupled to the at least one timing control circuit and the plurality of source driving circuits.

18. The display device according to claim 17, wherein: The display device includes two timing control circuits; The plurality of source driving circuits are divided into two groups, and each group of source driving circuits is coupled to a timing control circuit; The refresh frequency of the timing control circuit is X, and the amount of image data that can be transmitted per frame is Y; the target refresh frequency of the display panel is X0, and the target amount of image data required per frame is Y0; 19. A display driving method, applied to the display device according to claim 17 or 18; The display driving method includes: In each frame, the timing control circuit sends a source data signal, a gate start signal, a mode switching signal, an initial latch enable signal, and a source output enable signal to the source driver circuit, and the source driver circuit converts the source data signal into a data signal; In odd frames: The source driver circuit latches odd-numbered row data of the data signal according to the gate start signal, the first mode switching signal, the initial latch enable signal, and the source output enable signal, and outputs the odd-numbered row data for a first set duration; The timing control circuit controls the sub-pixels of each row of the display panel to turn on row by row, and uses the odd-numbered row data to charge the sub-pixels, wherein the charging time of the sub-pixels of the odd-numbered rows is a first set time length, and the charging time of the sub-pixels of the even-numbered rows is greater than or equal to half of the first set time length and less than the first set time length; In even frames: The source driving circuit latches the even-numbered row data of the data signal according to the gate start signal, the first mode switching signal, the initial latch enable signal and the source output enable signal, and outputs the even-numbered row data according to a second set duration; The timing control circuit controls the sub-pixels of each row of the display panel to turn on row by row, and uses the even-numbered row data for charging, wherein the charging time of the sub-pixels of the even-numbered rows is a second set time length, and the charging time of the sub-pixels of the odd-numbered rows is greater than or equal to half of the second set time length and less than the second set time length.

20. The display driving method according to claim 19, wherein: In an odd-numbered frame, in two adjacent rows of sub-pixels, when the charging time of the sub-pixels in the odd-numbered row is half of the first set time length, the sub-pixels in the even-numbered row are turned on for charging; In an even frame, in two adjacent rows of sub-pixels, when the charging time of the sub-pixels in the even row is half of the second set time length, the sub-pixels in the odd row are turned on for charging.

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