Semiconductor structure
By employing a stacked structure and photonic bandgap design in LED optoelectronic devices, the light reflection problem caused by the lack of gallium nitride substrates was solved, thereby improving luminous efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ENKRIS SEMICON
- Filing Date
- 2020-11-18
- Publication Date
- 2026-06-02
AI Technical Summary
Due to the lack of intrinsic gallium nitride substrates, when LED optoelectronic devices are fabricated on heterogeneous substrates, a large amount of light is reflected, resulting in low light extraction efficiency.
It employs a layered structure, including stacked islands and semiconductor layers of different materials, and improves luminous efficiency by selectively reflecting light through photonic band structure.
By adjusting the arrangement period and material composition of the stacked islands, selective light reflection was achieved, thereby improving the luminous efficiency of LED optoelectronic devices.
Smart Images
Figure CN116547823B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor structure. Background Technology
[0002] Currently, due to the lack of intrinsic gallium nitride substrates, LED optoelectronic devices are manufactured on heterogeneous substrates, such as sapphire, silicon carbide, and silicon.
[0003] However, due to the high refractive index of gallium nitride, most of the light is reflected when it reaches the surface of the LED optoelectronic device, causing a large amount of light to be confined inside the chip, resulting in low light extraction efficiency.
[0004] Therefore, how to further improve the luminous efficiency of LED optoelectronic devices remains a pressing problem to be solved. Summary of the Invention
[0005] This application provides a semiconductor structure that can improve the luminous efficiency of semiconductor devices.
[0006] To achieve the above objectives, an embodiment of this application provides a semiconductor structure, the semiconductor structure comprising:
[0007] A stacked structure, the stacked structure comprising one stacked structural unit or multiple stacked structural units arranged in a horizontal direction; each of the stacked structural units comprises multiple stacked islands separated from each other in a horizontal direction;
[0008] An N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer are sequentially stacked on the stacked structure.
[0009] Optionally, the stacked structure is a photonic crystal structure.
[0010] Optionally, when there are multiple stacked structural units, adjacent stacked structural units may partially overlap; or, adjacent stacked structural units may be separated from each other.
[0011] Optionally, the island in the stack includes a buffer layer and a first semiconductor layer stacked sequentially.
[0012] Optionally, the islands in the stack include alternately stacked second and third semiconductor layers;
[0013] The material of the second semiconductor layer is Alx1Iny1Ga1-x1-y1N; the material of the third semiconductor layer is Alx2Iny2Ga1-x2-y2N; wherein the values of X1, Y1, X2 and Y2 are all in the range of 0 to 1.
[0014] Optionally, the stacked structure is constructed using the stacked structural unit as the smallest repeating unit;
[0015] Each of the stacked structural units includes at least three horizontally separated islands in the stack.
[0016] Optionally, the cross-sectional shape of the island in the stack can be circular or polygonal.
[0017] Optionally, if the cross-section of the stacked island is circular, the diameter of the cross-section of the stacked island is less than or equal to 50 μm;
[0018] If the cross-section of the stacked island is polygonal, the diameter of the smallest circumscribed circle of the cross-section of the stacked island is less than or equal to 50 μm.
[0019] Optionally, there is a gap between adjacent islands in the stack, and the side of the N-type semiconductor layer adjacent to the stack structure also has a recess that is recessed in a direction away from the stack structure, the recess corresponding to the formation of the gap.
[0020] Optionally, the stacked structure, the N-type semiconductor layer, the light-emitting layer, and the P-type semiconductor layer are fabricated using epitaxial technology.
[0021] Optionally, the semiconductor structure further includes a substrate and a nucleation layer:
[0022] In the vertical direction, the nucleation layer is disposed between the substrate and the stacked structure. The nucleation layer has grooves to form a plurality of nucleation layer islands that are separated from each other in the horizontal direction. Each stacked island corresponds to the island of each nucleation layer.
[0023] Optionally, the substrate material is sapphire, silicon, silicon carbide, or gallium nitride.
[0024] Optionally, the semiconductor structure further includes:
[0025] A reflective layer, along the vertical direction, is disposed on the side of the P-type semiconductor layer away from the light-emitting layer;
[0026] A transfer layer, in the vertical direction, is disposed on the side of the reflective layer away from the P-type semiconductor layer.
[0027] Optionally, the reflective layer and the transfer layer are fabricated using chip manufacturing processes.
[0028] Optionally, the reflective layer is a metal layer.
[0029] Optionally, the material of the metal layer is Ag; or,
[0030] The metal layer comprises a first metal layer and a second metal layer stacked together, wherein the material of the first metal layer is Ni and the material of the second metal layer is Ag.
[0031] Optionally, the reflective layer includes a stacked indium tin oxide layer and / or a DBR layer.
[0032] Optionally, the DBR layer is formed by alternating layers of a first material layer of titanium oxide and a second material layer of silicon oxide.
[0033] In the semiconductor structure described above, a stacked structure is provided, and the selective reflection of light is achieved by utilizing the different arrangement periods of the islands in the stack. This is because the islands in the stack give the stacked structure a photonic band structure, and the color of the reflected light changes with the position of the band gap, thereby ultimately improving the luminous efficiency of the semiconductor structure. Attached Figure Description
[0034] Figure 1 This is a schematic cross-sectional view of the semiconductor structure in the vertical direction of Embodiment 1 of this application.
[0035] Figures 2(a)-2(c) This is a schematic cross-sectional view of the semiconductor structure stacked in Embodiment 1 of this application along the horizontal direction.
[0036] Figures 3(a)-3(d) This is a process flow diagram of the semiconductor structure fabrication method of Embodiment 1 of this application.
[0037] Figure 4 This is a schematic cross-sectional view of the semiconductor structure in the vertical direction of Embodiment 2 of this application.
[0038] Figures 5(a)-5(c) This is a schematic cross-sectional view of the semiconductor structure stacked in the horizontal direction of Embodiment 2 of this application.
[0039] Figures 6(a)-6(b) This is a process flow diagram of the semiconductor structure fabrication method of Embodiment 2 of this application.
[0040] Figure 7 This is a schematic cross-sectional view of the semiconductor structure in the vertical direction of Embodiment 3 of this application.
[0041] Figures 8(a)-8(c) This is a process flow diagram of the semiconductor structure fabrication method of Embodiment 3 of this application. Detailed Implementation
[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0043] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, the technical or scientific terms used in this application should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The words “a” or “one” and similar terms used in this specification and claims do not indicate a limitation of quantity, but rather indicate the presence of at least one. The words “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” covers the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The words “connected” or “linked” and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. “A plurality” includes two, equivalent to at least two. The singular forms “a,” “the,” and “the” used in this specification and appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0044] Example 1
[0045] like Figure 1 and Figures 2(a)-2(c) As shown, this embodiment provides a semiconductor structure. The semiconductor structure includes: a substrate 10; a nucleation layer 20 disposed on the substrate 10; and a stacked structure 30 disposed on the nucleation layer 20.
[0046] The stacked structure 30 includes three stacked structural units 31 arranged along the horizontal direction X. The stacked structural unit 31 is the smallest repeating unit in the stacked structure 30; that is, the stacked structural unit 31 is the smallest repeatable unit of the stacked structure 30. In other embodiments, the stacked structure 30 may include only one stacked structural unit 31; or, the stacked structure 30 may include two stacked structural units 31, four stacked structural units 31, or other numbers of stacked structural units 31.
[0047] Each stacked structural unit 31 includes a plurality of stacked islands 311 separated from each other along the horizontal direction X. Preferably, each stacked structural unit 31 includes at least three stacked islands 311 separated from each other along the horizontal direction X, which are sequentially stacked on the stacked structure 30, comprising an N-type semiconductor layer 40, a light-emitting layer 50, and a P-type semiconductor layer 60. The stacked structure 30, the N-type semiconductor layer 40, the light-emitting layer 50, and the P-type semiconductor layer 60 are fabricated using epitaxial growth technology.
[0048] The nucleation layer 20 has a groove 21 to form a plurality of nucleation layer islands that are separated from each other along the horizontal direction X, and each stacked island 311 is provided corresponding to each nucleation layer island.
[0049] There is a gap 312 between adjacent islands 311 in the stack. On the side of the N-type semiconductor layer 40 adjacent to the stacked structure 30, a recess 41 is formed that is recessed away from the stacked structure 30. The recess 41 is formed corresponding to the gap 312.
[0050] The substrate 10 is made of sapphire, silicon, silicon carbide, or gallium nitride. The nucleation layer 20 is made of AlN.
[0051] In this embodiment, the stacked structure 30 is a multilayer material stacked structure, that is, the island 311 in the stack includes a buffer layer 313 and a first semiconductor layer 314 stacked sequentially. The material of the first semiconductor layer 314 is a group III nitride.
[0052] The cross-sectional shape of the stacked island 311 can be circular or polygonal. As shown in Figure 2(a), the cross-sectional shape of the stacked island 311 is circular. If the cross-sectional shape of the stacked island 311 is circular, the diameter R of the cross-section of the stacked island 311 is less than or equal to 50 μm. As can be seen from Figure 2(a), in this embodiment, the stacked structure 30 includes three stacked structure units 31; each stacked structure unit 31 includes three stacked islands 311, and the three stacked islands 311 are separated from each other in the horizontal direction. Adjacent stacked structure units 31 can partially overlap by sharing one stacked island 311, but are not limited to this; they can also partially overlap by sharing two stacked islands 311; or, adjacent stacked structure units 31 can not overlap, that is, they can be separated from each other.
[0053] When the cross-sectional shape of the stacked island 311 is polygonal, preferably, the cross-sectional shape of the stacked island 311 is hexagonal, as shown in Figure 2(b). However, it is not limited to this; the cross-sectional shape of the stacked island 311 can also be other polygons, as shown in Figure 2(c), where the cross-sectional shape of the stacked island 311 is rectangular, or it can be other polygonal shapes, such as triangles, quadrilaterals, hexagons, etc. The diameter of the smallest circumscribed circle of the cross-section of the stacked island 311 is less than or equal to 50 μm.
[0054] Similarly, as shown in Figure 2(b), in this embodiment, the stacked structure 30 includes two stacked structure units 31; each stacked structure unit 31 includes four stacked islands 311, which are horizontally separated from each other. Adjacent stacked structure units 31 can partially overlap by sharing a stacked island 311. The embodiment in Figure 2(c) is the same as the embodiment in Figure 2(b), and will not be described again here.
[0055] It should be noted that, in Figures 2(a)-2(c) The dashed lines are for better illustrating the structure of the stacked structure 30, rather than representing its actual existence.
[0056] Figures 3(a)-3(d) This is a process flow diagram of the semiconductor structure fabrication method according to Embodiment 1 of this application. The fabrication method includes:
[0057] S100: As shown in Figure 3(a), a nucleation layer 20 is formed on the substrate 10 along the vertical direction Y. The material of the substrate 10 is sapphire, silicon, silicon carbide, or gallium nitride. The material of the nucleation layer 20 is AlN.
[0058] S200: As shown in Figure 3(b), grooves 21 are formed on the nucleation layer 20 to form multiple nucleation layer islands that are separated from each other along the horizontal direction X.
[0059] S300: As shown in Figure 3(c), a plurality of stacked islands 311 separated from each other along the horizontal direction X are formed on the nucleation layer 20; each stacked island 311 is formed on top of each nucleation layer island. The stacked island 311 includes a buffer layer 313 and a first semiconductor layer 314 stacked sequentially. The material of the first semiconductor layer 314 is a group III nitride.
[0060] The cross-sectional shape of the stacked island 311 can be circular or polygonal. If the cross-sectional shape of the stacked island 311 is circular, the diameter of the cross-sectional shape is less than or equal to 50 μm; when the cross-sectional shape of the stacked island 311 is polygonal, preferably, the cross-sectional shape is hexagonal, but not limited to this, the cross-sectional shape of the stacked island 311 can also be other polygons, and the diameter of the smallest circumscribed circle of the cross-sectional shape is less than or equal to 50 μm. The stacked structure 30 is manufactured by an epitaxial process.
[0061] S400: As shown in Figure 3(d), an N-type semiconductor layer 40, a light-emitting layer 50, and a P-type semiconductor layer 60 are formed on one of the plurality of stacked islands 311. The N-type semiconductor layer 40, the light-emitting layer 50, and the P-type semiconductor layer 60 are fabricated by epitaxial growth.
[0062] The semiconductor structure in this embodiment achieves selective light reflection by setting a stacked structure 30 and utilizing the different arrangement periods of the islands 311 in the stack. This is because the islands 311 give the stacked structure 30 a photonic band structure, and the color of the reflected light changes with the position of the band gap, thereby ultimately improving the luminous efficiency of the semiconductor structure.
[0063] Example 2
[0064] like Figure 4 As shown, this embodiment also provides a semiconductor structure, which is basically the same as the semiconductor structure in Embodiment 1. In this embodiment, the stacked island 311 includes alternating stacked second semiconductor layers 315 and third semiconductor layers 316, wherein the two sides of the stacked island 311 opposite each other in the vertical direction are both second semiconductor layers 315.
[0065] The material of the second semiconductor layer 315 is Alx1Iny1Ga1-x1-y1; the material of the third semiconductor layer 316 is Alx2Iny2Ga1-x2-y2N; wherein the values of X1, Y1, X2 and Y2 are all in the range of 0 to 1.
[0066] The cross-sectional shape of the stacked island 311 can be circular or polygonal. As shown in Figure 5(a), the cross-sectional shape of the stacked island 311 is circular. If the cross-sectional shape of the stacked island 311 is circular, the diameter of the cross-sectional shape of the stacked island 311 is less than or equal to 50 μm.
[0067] As shown in Figure 5(a), in this embodiment, the stacked structure 30 includes three stacked structural units 31; each stacked structural unit 31 includes three stacked islands 311, which are horizontally separated from each other. Adjacent stacked structural units 31 can partially overlap by sharing one stacked island 311, but are not limited to this; they can also partially overlap by sharing two stacked islands 311; or, adjacent stacked structural units 31 can not overlap, i.e., they can be separated from each other.
[0068] When the cross-sectional shape of the stacked island 311 is polygonal, preferably, the cross-sectional shape of the stacked island 311 is rhomboid, as shown in Figure 5(b). However, it is not limited to this; the cross-sectional shape of the stacked island 311 can also be other polygons, as shown in Figure 5(c), where the cross-sectional shape of the stacked island 311 is quadrilateral, or it can be other polygonal shapes, such as triangles, hexagons, etc. The diameter of the smallest circumscribed circle of the cross-section of the stacked island 311 is less than or equal to 50 μm.
[0069] Similarly, as shown in Figure 5(b), in this embodiment, the stacked structure 30 includes two stacked structure units 31; each stacked structure unit 31 includes four stacked islands 311, which are horizontally separated from each other. Adjacent stacked structure units 31 can partially overlap by sharing a stacked island 311. The embodiment in Figure 5(c) is the same as the embodiment in Figure 5(b), and will not be described again here.
[0070] It should be noted that, in Figures 5(a)-5(c) The dashed lines are for better illustrating the structure of the stacked structure 30, rather than representing its actual existence.
[0071] like Figures 6(a)-6(b) As shown, another aspect of this embodiment also provides a method for preparing a semiconductor structure, used to prepare the above-mentioned semiconductor structure. This preparation method is basically the same as the preparation method in Example 1, except that:
[0072] In step S300, as shown in Figure 6(a), the stacked island 311 includes alternating layers of second semiconductor layers 315 and third semiconductor layers 316, wherein the two opposite sides of the stacked island 311 in the vertical direction are both second semiconductor layers 315. The material of the second semiconductor layer 315 is Alx1Iny1Ga1-x1-y1; the material of the third semiconductor layer 316 is Alx2Iny2Ga1-x2-y2N; wherein the values of X1, Y1, X2, and Y2 are all in the range of 0 to 1.
[0073] In step S400, as shown in FIG6(b), an N-type semiconductor layer 40, a light-emitting layer 50 and a P-type semiconductor layer 60 are formed on the multiple stacked islands 311.
[0074] Example 3
[0075] like Figure 7 As shown, this embodiment also provides a semiconductor structure, which is basically the same as the semiconductor structure in Embodiment 1, except that the semiconductor structure does not include the substrate 10 and the nucleation layer 20, and the semiconductor structure also includes a reflective layer 70 and a transfer layer 80.
[0076] Along the vertical Y-direction, the reflective layer 70 is disposed on the side of the P-type semiconductor layer 60 away from the light-emitting layer 50. Along the vertical Y-direction, the transfer layer 80 is disposed on the side of the reflective layer 70 away from the P-type semiconductor layer 60. The reflective layer 70 and the transfer layer 80 are fabricated using chip manufacturing processes.
[0077] Preferably, the reflective layer 70 is a metal layer. More preferably, the metal layer is made of Ag; or, the metal layer comprises a first metal layer and a second metal layer stacked together; the first metal layer is made of Ni, and the second metal layer is made of Ag. However, this is not a limitation; in other embodiments, the reflective layer 70 comprises a stacked indium tin oxide layer and / or a DBR layer. The DBR layer is formed by alternating layers of a first material layer of titanium oxide and a second material layer of silicon oxide.
[0078] like Figures 8(a)-8(c) Another aspect of this embodiment provides a method for fabricating a semiconductor structure, used to fabricate the aforementioned semiconductor structure. This fabrication method includes all the steps of the fabrication method of Example 1, and further includes:
[0079] Step S600: As shown in FIG8(a), a reflective layer 70 is formed on the P-type semiconductor layer 60, and the reflective layer 70 is fabricated by chip technology. Preferably, the reflective layer 70 is a metal layer. Preferably, the material of the metal layer is Ag; or, the metal layer comprises a first metal layer and a second metal layer stacked together; the material of the first metal layer is Ni, and the material of the second metal layer is Ag. However, it is not limited thereto. In other embodiments, the reflective layer 70 comprises a stacked indium tin oxide layer and a DBR layer. The DBR layer is formed by alternating layers of a first material layer of titanium oxide and a second material layer of silicon oxide.
[0080] Step S700: As shown in Figure 8(b), a transfer layer 80 is formed on the reflective layer 70. The transfer layer 80 is fabricated using chip technology.
[0081] Step S800: As shown in Figure 8(c), the nucleation layer 20 and the substrate 10 are peeled off.
[0082] The semiconductor stacked structure in this embodiment is not limited to a one-dimensional stacked structure, but can also be a two-dimensional or three-dimensional stacked structure. The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A semiconductor structure, characterized in that, The semiconductor structure includes: A stacked structure (30) includes multiple stacked structural units (31) arranged in a horizontal direction; each stacked structural unit (31) includes multiple stacked islands (311) separated from each other in a horizontal direction; the stacked structure (30) is made by epitaxial process; the stacked islands (311) have different arrangement periods; the stacked islands (311) give the stacked structure (30) a photonic band structure; The stacked island (311) includes a buffer layer (313) and a first semiconductor layer (314) stacked sequentially, or the stacked island includes a second semiconductor layer (315) and a third semiconductor layer (316) stacked alternately. An N-type semiconductor layer (40), a light-emitting layer (50), and a P-type semiconductor layer (60) are sequentially stacked on the stacked structure (30). There is a gap (312) between adjacent islands (311) in the stack; a recess (41) is also formed on the side of the N-type semiconductor layer (40) adjacent to the stack structure (30) in a direction away from the stack structure (30), the recess (41) is formed corresponding to the gap (312), and the recess (41) is connected to the gap.
2. The semiconductor structure as described in claim 1, characterized in that, The stacked structure (30) is a photonic crystal structure.
3. The semiconductor structure as described in claim 1, characterized in that, When there are multiple stacked structural units (31), adjacent stacked structural units (31) partially overlap; or, adjacent stacked structural units (31) are separated from each other.
4. The semiconductor structure as described in claim 1, characterized in that, The material of the second semiconductor layer (315) is Alx1Iny1Ga1-x1-y1N; the material of the third semiconductor layer (316) is Alx2Iny2Ga1-x2-y2N; wherein the values of X1, Y1, X2 and Y2 are all in the range of 0~1.
5. The semiconductor structure as described in claim 1, characterized in that, The stacked structural unit (31) is the smallest repeating unit that constitutes the stacked structure (30). Each of the stacked structural units (31) includes at least three horizontally separated islands (311) in the stack.
6. The semiconductor structure as described in claim 1, characterized in that, The cross-section of the stacked island (311) is circular or polygonal.
7. The semiconductor structure as described in claim 6, characterized in that, If the cross-section of the stacked island (311) is circular, the diameter of the cross-section of the stacked island (311) is less than or equal to 50 μm; If the cross-section of the stacked island (311) is polygonal, the diameter of the smallest circumscribed circle of the cross-section of the stacked island (311) is less than or equal to 50 μm.
8. The semiconductor structure as described in claim 1, characterized in that, The N-type semiconductor layer (40), the light-emitting layer (50), and the P-type semiconductor layer (60) are fabricated using epitaxial technology.
9. The semiconductor structure according to any one of claims 1-8, characterized in that, The semiconductor structure further includes a substrate (10) and a nucleation layer (20): Along the vertical direction, the nucleation layer (20) is disposed between the substrate (10) and the stacked structure (30). The nucleation layer (20) has a groove (21) to form a plurality of nucleation layer islands that are separated from each other in the horizontal direction. Each stacked island (311) is disposed corresponding to each nucleation layer island.
10. The semiconductor structure as described in claim 9, characterized in that, The substrate (10) is made of sapphire, silicon, silicon carbide or gallium nitride.
11. The semiconductor structure according to any one of claims 1-8, characterized in that, The semiconductor structure also includes: A reflective layer (70) is disposed vertically on the side of the P-type semiconductor layer (60) away from the light-emitting layer (50); A transfer layer (80) is disposed vertically on the side of the reflective layer (70) away from the P-type semiconductor layer (60).
12. The semiconductor structure as claimed in claim 11, characterized in that, The reflective layer (70) and the transfer layer (80) are fabricated using chip technology.
13. The semiconductor structure as described in claim 11, characterized in that, The reflective layer (70) is a metal layer.
14. The semiconductor structure as described in claim 13, characterized in that, The metal layer is made of silver; or, the metal layer comprises a first metal layer and a second metal layer stacked together, wherein the first metal layer is made of Ni and the second metal layer is made of Ag.
15. The semiconductor structure as claimed in claim 11, characterized in that, The reflective layer (70) comprises a stacked indium tin oxide layer and / or a DBR layer.
16. The semiconductor structure as claimed in claim 15, characterized in that, The DBR layer is composed of alternating layers of titanium oxide as the first material layer and silicon oxide as the second material layer.