Clock synchronization method and communication apparatus

Abstract

A clock synchronization method and a communication device, the method comprising: multiplexing a local analog clock signal and a first data signal to obtain a first multiplexed signal; sending the first multiplexed signal to a first device; receiving a second multiplexed signal from the first device; demultiplexing the second multiplexed signal to obtain a second data signal and a first analog clock signal, the first analog clock signal being the local analog clock signal experiencing a transmission delay; obtaining a first signal according to the first analog clock signal, the first signal being a time delay compensation amount or a second analog clock signal, the second analog clock signal being the local analog clock signal after time delay compensation; processing data according to the first signal to obtain a first data signal after time delay compensation. The precision of clock synchronization can be improved.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to a clock synchronization method and a communication device. Background Technology

[0002] In distributed multiple-input multiple-output (D-MIMO) systems, higher channel spatial resolution can be achieved by distributing radio equipment (REs) more remotely relative to radio equipment control (RECs), thereby improving system capacity and user experience. For example, an REC can be a base-band unit (BBU), and an RE can be a remote radio unit (RRU). Clock synchronization between the REC and REs is fundamental to ensuring communication quality in D-MIMO systems. Currently, REC and REs are primarily synchronized using digital clocks based on timestamps, where timestamps are transmitted within digital signals. However, the uncertainty of timestamp loading and unloading delays leads to clock synchronization deviations between the REC and REs. The current clock synchronization accuracy is insufficient to meet the service requirements of some higher-quality communication services. Therefore, improving clock synchronization accuracy is a current research hotspot. Summary of the Invention

[0003] This application provides a clock synchronization method and a communication device that can improve the accuracy of clock synchronization.

[0004] In one aspect, a clock synchronization method is provided, which can be executed by a communication device or a module (such as a chip) configured in (or used in) the communication device.

[0005] The method includes: multiplexing a third analog clock signal with a first data signal to obtain a first multiplexed signal; sending the first multiplexed signal to a first device; receiving a second multiplexed signal from the first device; demultiplexing the second multiplexed signal to obtain a second data signal and a first analog clock signal, wherein the first analog clock signal is the third analog clock signal that has undergone a transmission delay; obtaining a first signal based on the first analog clock signal, wherein the first signal is a delay compensation amount or a second analog clock signal, wherein the second analog clock signal is the third analog clock signal after delay compensation; and processing data based on the first signal to obtain a first data signal after delay compensation.

[0006] According to the above scheme, the second device combines the analog signal of the local analog clock signal with the data signal and sends it to the first device. The receiving device then multiplexes the received analog clock signal with the data signal and feeds it back to the second device. This allows the second device to determine the path delay based on the clock signal fed back from the first device and to perform delay processing on the data signal sent to the first device, ensuring that the data signal arrives at the first device synchronized with the clock of the second device. This reduces the clock synchronization deviation caused by the uncertainty of the loading and unloading delays of digital timestamps, thus improving the accuracy of clock synchronization.

[0007] In conjunction with the first aspect, in some implementations of the first aspect, sending the first multiplexed signal to the first device includes: modulating the first multiplexed signal onto an optical carrier to obtain a first optical signal; sending the first optical signal to the first device, the first optical signal including the first multiplexed signal; and receiving the second multiplexed signal from the first device includes: receiving the second optical signal from the first device, the second optical signal including the second multiplexed signal; and demodulating the second optical signal to obtain the second multiplexed signal.

[0008] According to the above scheme, the first multiplexed signal can be transmitted to the remote end via optical fiber to maximize the integrity of the transmission process clock signal, thereby ensuring high-quality recovery of the clock at the remote end and guaranteeing the stability of the clock.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the multiplexing of the third analog clock signal and the first data signal to obtain the first multiplexed signal includes: time-division multiplexing the third analog clock signal and the first data signal to obtain the first multiplexed signal.

[0010] According to the above scheme, the local analog clock signal is multiplexed with the data before transmission, which can accurately measure the transmission path delay of the service without affecting the normal operation of the service.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the first multiplexed signal obtained by time-division multiplexing the third analog clock signal and the first data signal includes: when controlling the first switch to switch to the first state, the first multiplexed signal output by the first switch includes the first data signal; when controlling the first switch to switch to the second state, the first multiplexed signal output by the first switch includes the third analog clock signal.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, obtaining a second data signal and a first analog clock signal by demultiplexing the second multiplexed signal includes: detime-division multiplexing the second multiplexed signal and outputting the second data signal and the first analog clock signal.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the output of the second data signal and the first analog clock signal after de-time-division multiplexing the second multiplexed signal includes: when controlling the second switching switch to switch to the third state, the second switching switch outputs the second data signal in the second multiplexed signal; when controlling the second switching switch to switch to the fourth state, the second switching switch outputs the first analog clock signal in the second multiplexed signal.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the multiplexing of the third analog clock signal and the first data signal to obtain the first multiplexed signal includes: frequency-division multiplexing the third analog clock signal and the first data signal to output the first multiplexed signal; and / or, the demultiplexing of the second multiplexed signal to obtain the second data signal and the first analog clock signal includes: frequency-division multiplexing the second multiplexed signal to output the second data signal and the first analog clock signal.

[0015] According to the above scheme, the local analog clock signal is multiplexed with the data before transmission, which can accurately measure the transmission path delay of the service without affecting the normal operation of the service.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, outputting the first signal after performing time delay compensation on the third analog clock signal based on the first analog clock signal includes: determining the time delay compensation amount between the first analog clock signal and the third analog clock signal using a symmetrical dual-mixing time difference measurement method.

[0017] According to the above scheme, the accuracy of time delay measurement can be improved by adopting a symmetrical dual-frequency mixing time difference measurement method.

[0018] Secondly, a clock synchronization method is provided, which can be executed by a communication device or a module (such as a chip) configured in (or used in) the communication device.

[0019] The method includes: receiving a first multiplexed signal from a second device; demultiplexing the first multiplexed signal to obtain a first data signal and a fourth analog clock signal; multiplexing the fourth analog clock signal and the second data signal to obtain a second multiplexed signal; and sending the second multiplexed signal to the second device.

[0020] In conjunction with the second aspect, in some implementations of the second aspect, receiving the first multiplexed signal from the second device includes: receiving a first optical signal from the second device, the first optical signal including the first multiplexed signal; demodulating the first optical signal to obtain the first multiplexed signal; and sending the second multiplexed signal to the second device includes: modulating the second multiplexed signal onto an optical carrier to obtain a second optical signal; and sending the second optical signal to the second device, the second optical signal including the second multiplexed signal.

[0021] In conjunction with the second aspect, in some implementations of the second aspect, the method of multiplexing the fourth analog clock signal and the second data signal to obtain the second multiplexed signal includes: time-division multiplexing the fourth analog clock signal and the second data signal to output the second multiplexed signal.

[0022] In conjunction with the second aspect, in some implementations of the second aspect, the second multiplexed signal is output after time-division multiplexing the fourth analog clock signal and the second data signal, including: when the third switch is controlled to switch to the first state, the second multiplexed signal output by the third switch includes the second data signal; when the third switch is controlled to switch to the second state, the second multiplexed signal output by the third switch includes the fourth analog clock signal.

[0023] In conjunction with the second aspect, in some implementations of the second aspect, obtaining the first data signal and the fourth analog clock signal by demultiplexing the first multiplexed signal includes: obtaining the first data signal and the fourth analog clock signal by detime-division multiplexing the first multiplexed signal.

[0024] In conjunction with the second aspect, in some implementations of the second aspect, the first data signal and the fourth analog clock signal are obtained by de-time-division multiplexing the first multiplexed signal, including: when the fourth switch is controlled to switch to the third state, the fourth switch outputs the first data signal in the first multiplexed signal; when the fourth switch is switched to the fourth state, the fourth switch outputs the fourth analog clock signal in the first multiplexed signal.

[0025] In conjunction with the second aspect, in some implementations of the second aspect, obtaining a first data signal and a fourth analog clock signal by demultiplexing the first multiplexed signal includes: demultiplexing the first multiplexed signal by frequency division multiplexing and outputting the first data signal and the fourth analog clock signal; and obtaining a second multiplexed signal by multiplexing the fourth analog clock signal and the second data signal includes: frequency division multiplexing the fourth analog clock signal and the second data signal and outputting the second multiplexed signal.

[0026] Thirdly, a clock synchronization device is provided, comprising: a combining module, an oscillator, a clock synchronization module, a data processing module, a splitting module, and a transceiver module; the combining module is used to combine a third analog clock signal from the oscillator with a first data signal from the data processing module to obtain a first multiplexed signal, and output the first multiplexed signal to the transceiver module; the transceiver module is used to transmit the first multiplexed signal to a first device; the transceiver module is also used to receive a second multiplexed signal from the first device, and output the second multiplexed signal to the splitting module; the splitting module is used to split the second multiplexed signal to obtain a second data signal and a third analog clock signal. A first analog clock signal is provided, and the first analog clock signal is output to the clock synchronization module. The first analog clock signal is the third analog clock signal that has undergone a transmission delay. The clock synchronization module is used to obtain a first signal based on the first analog clock signal and the third analog clock signal from the oscillator, and output the first signal to the data processing module. The first signal is either a delay compensation amount between the first analog clock signal and the third analog clock signal or a second analog clock signal, where the second analog clock signal is the third analog clock signal after delay compensation. The data processing module is used to process data based on the first signal to obtain a first data signal after delay compensation.

[0027] In conjunction with the third aspect, in some implementations of the third aspect, the transceiver module includes an electro-optic modulation unit, a photodetector unit, and a transceiver unit. The transceiver module is used to transmit the first multiplexed signal to the first device, including: the electro-optic modulation unit modulating the first multiplexed signal onto an optical carrier to obtain a first optical signal, and outputting the first optical signal to the transceiver unit; the transceiver unit transmitting the first optical signal to the first device, the first optical signal including the first multiplexed signal; and the transceiver module further being used to receive a second multiplexed signal from the first device, including: the transceiver unit further receiving a second optical signal from the first device, the second optical signal including the second multiplexed signal; and the photodetector unit demodulating the second optical signal to obtain a second multiplexed signal.

[0028] In conjunction with the third aspect, in some implementations of the third aspect, the combining module is specifically used to time-division multiplex the third analog clock signal with the first data signal and output the first multiplexed signal.

[0029] In conjunction with the third aspect, in some implementations of the third aspect, the combining module includes a first switching switch. When the first switching switch is switched to a first state, the first multiplexed signal output by the first switching switch includes the first data signal; or, when the first switching switch is switched to a second state, the first multiplexed signal output by the first switching switch includes the third analog clock signal.

[0030] In conjunction with the third aspect, in some implementations of the third aspect, the splitter module is specifically used to demultiplex the second multiplexed signal and output the second data signal and the first analog clock signal.

[0031] In conjunction with the third aspect, in some implementations of the third aspect, the splitter module includes a second switching switch. When the second switching switch is switched to the third state, the second switching switch outputs the second data signal in the second multiplexed signal to the data processing module; or, when the second switching switch is switched to the fourth state, the second switching switch outputs the first analog clock signal in the second multiplexed signal to the clock synchronization module.

[0032] In conjunction with the third aspect, in some implementations of the third aspect, the combining module is specifically used to frequency-division multiplex the third analog clock signal and the first data signal and output the first multiplexed signal; and / or, the splitting module is specifically used to de-frequency-division multiplex the second multiplexed signal and output the second data signal and the first analog clock signal.

[0033] In conjunction with the third aspect, in some implementations of the third aspect, the clock synchronization module uses a symmetrical dual-mixing time difference measurement method to determine the delay compensation amount between the first analog clock signal and the third analog clock signal.

[0034] Fourthly, a clock synchronization device is provided, comprising: a transceiver module, a splitter module, a combiner module, and a data processing module; the transceiver module is configured to receive a first multiplexed signal from a second device and output the first multiplexed signal to the splitter module; the splitter module is configured to split the first multiplexed signal to obtain a first data signal and a fourth analog clock signal, and output the fourth analog clock signal to the combiner module; the combiner module is configured to combine the fourth analog clock signal and a second data signal from the data processing module to obtain a second multiplexed signal, and output the second multiplexed signal to the transceiver module; the transceiver module is further configured to transmit the second multiplexed signal to the second device.

[0035] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the transceiver module includes an electro-optic modulation unit, a photodetector unit, and a transceiver unit. The transceiver module is used to receive a first multiplexed signal from the second device, including: the transceiver unit receiving a first optical signal from the second device, the first optical signal including the first multiplexed signal; the photodetector unit demodulating the first optical signal to obtain the first multiplexed signal; and the transceiver module is further used to transmit a second multiplexed signal to the second device, including: the electro-optic modulation unit modulating the second multiplexed signal onto an optical carrier to obtain a second optical signal, and outputting the second optical signal to the transceiver unit; the transceiver unit further transmitting the second optical signal to the second device, the second optical signal including the second multiplexed signal.

[0036] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the combining module is specifically used to time-division multiplex the fourth analog clock signal and the second data signal and output the second multiplexed signal.

[0037] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the combining module includes a third switching switch. When the third switching switch is switched to the first state, the second multiplexed signal output by the third switching switch includes the second data signal; or, when the third switching switch is switched to the second state, the second multiplexed signal output by the third switching switch includes the fourth analog clock signal.

[0038] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the splitter module is specifically used to demultiplex the first multiplexed signal and output the first data signal and the fourth analog clock signal.

[0039] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the splitting module includes a fourth switching switch. When the fourth switching switch is switched to the third state, the fourth switching switch outputs the first data signal in the first multiplexed signal to the data processing module; or, when the fourth switching switch is switched to the fourth state, the fourth switching switch outputs the fourth analog clock signal in the first multiplexed signal to the combining module.

[0040] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the splitting module is specifically used to demultiplex the first multiplexed signal and output the first data signal and the fourth analog clock signal, and / or the combining module is specifically used to frequency-multiplex the fourth analog clock signal and the second data signal and output the second multiplexed signal.

[0041] Fifthly, a communication system is provided, including the clock synchronization device of any one of the third aspects and the clock synchronization device of any one of the fourth aspects. Attached Figure Description

[0042] Figure 1 This is a schematic block diagram of the communication system provided in the embodiments of this application;

[0043] Figure 2 This is a schematic flowchart of a clock synchronization method provided in an embodiment of this application;

[0044] Figure 3 This is a schematic structural diagram of the communication device provided in the embodiments of this application;

[0045] Figure 4 This is a schematic structural diagram of a combining module provided in an embodiment of this application;

[0046] Figure 5 This is another schematic structural diagram of the combining module provided in the embodiments of this application;

[0047] Figure 6 This is a schematic structural diagram of a splitter module provided in an embodiment of this application;

[0048] Figure 7 This is another schematic structural diagram of the splitter module provided in the embodiments of this application;

[0049] Figure 8 This is a schematic structural diagram of a clock synchronization module provided in an embodiment of this application;

[0050] Figure 9 This is another schematic structural diagram of the clock synchronization module provided in the embodiments of this application;

[0051] Figure 10 This is another schematic structural diagram of the communication device provided in the embodiments of this application;

[0052] Figure 11 This is another schematic structural diagram of the communication device provided in the embodiments of this application;

[0053] Figure 12 This is another schematic structural diagram of the communication device provided in the embodiments of this application;

[0054] Figure 13 This is another schematic structural diagram of the communication device provided in the embodiments of this application;

[0055] Figure 14 This is another schematic block diagram of the communication system provided in the embodiments of this application. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings.

[0057] The technical solutions of this application embodiment can be applied to various communication systems, such as: Long Term Evolution (LTE) systems (including LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems), 5th Generation (5G) communication systems, Wireless Fidelity (WiFi) systems, and future mobile communication systems (e.g., 6th Generation (6G) communication systems, etc.).

[0058] Figure 1 This is a schematic diagram of a communication system 100 applicable to embodiments of this application.

[0059] As shown in Figure 1, the communication system 100 may include at least one REC, for example Figure 1 The REC shown. The communication system 100 may also include at least one RE that can be remotely configured, for example... Figure 1 The examples are RE1, RE2, RE3, and RE4. For instance, Figure 1 The REC and RE shown can be the BBU and RRU of a macro base station using a distributed base station structure, respectively. The REC can transmit the processed baseband signal to the RE, which then converts the baseband signal into a radio frequency signal for transmission. To avoid interference between signals transmitted by different REs, the REs need to be clocked with the REC, and the REC coordinates the timing of signal transmission from different REs.

[0060] Currently, REC and RE are primarily based on digital time synchronization using timestamps, which synchronizes the clock by transmitting timestamps within digital signals. However, the uncertainty in the loading and unloading delays of timestamps can lead to clock synchronization deviations. Furthermore, delay measurement in digital time synchronization relies on the resolution of the sampling clock, i.e., the sampling clock frequency. Improving the accuracy of delay measurement requires increasing the sampling clock frequency. However, increasing the sampling clock frequency can lead to instability in the transmission link, thereby reducing the reliability of the communication system.

[0061] This application proposes a clock synchronization method. The REC (Real Clock Controller) combines its local analog clock signal with the data signal it needs to send to the RE (Relay Controller), and then sends this combination to the RE. The RE then multiplexes the received analog clock signal with the data signal the REC needs to send back to the RE and feeds it back to the REC. This allows the REC to determine the path delay based on the clock signal fed back from the RE and to process the delay in its data signal, ensuring that the data signal sent by the REC to the RE arrives at the RE with the REC's clock synchronized. It should be noted that the clock signals transmitted in this application are all analog signals, or analog clock signals. Compared to digital clock signals, the technical solution of this application can reduce the clock synchronization deviation caused by the uncertainty of the loading and unloading delays of digital timestamps, thereby improving the accuracy of clock synchronization.

[0062] The clock synchronization method proposed in this application will be described in detail below with reference to the accompanying drawings.

[0063] Figure 2 This is a schematic flowchart of a clock synchronization method provided in an embodiment of this application.

[0064] The clock synchronization method provided in this application can be executed by a communication device or communication apparatus. Figure 2 The embodiment uses the second device as REC and the first device as RE for clock synchronization as an example for illustration, but this application is not limited to this. The clock synchronization method can also be applied between two devices that need to be synchronized. For example, the master clock node and slave clock node in a time-sensitive network (TSN) can use this clock synchronization method to achieve clock synchronization.

[0065] S210, REC multiplexes the third analog clock signal and the first data signal to obtain the first multiplexed signal.

[0066] The third analog clock signal is the local analog clock signal of REC, that is, the clock signal output by the oscillator of REC. The first data signal is the data signal that REC will send to RE.

[0067] In one implementation, REC time-division multiplexes the local analog clock signal with the first data signal to obtain the first multiplexed signal.

[0068] In other words, the first multiplexed signal contains a first data signal for one time period and a local analog clock signal for another time period. Alternatively, the local analog clock signal appears periodically in the first multiplexed signal, with the local analog clock signal lasting for a certain period within each cycle.

[0069] For example, REC may multiplex the local analog clock signal within the time interval between two data frames, or predefine a time unit in a data frame as the time unit of the local analog clock signal, but this application is not limited to this.

[0070] Optionally, REC can control the first switching switch to achieve multiplexing of the local analog clock signal and the first data signal.

[0071] For example, when the REC controls the first switch to switch to the first state, the first multiplexed signal output by the first switch includes the first data signal; when the REC controls the first switch to switch to the second state, the first multiplexed signal output by the first switch includes the local analog clock signal, but this application is not limited thereto.

[0072] In another implementation, REC frequency-division multiplexes the local analog clock signal with the first data signal and outputs the first multiplexed signal.

[0073] For example, the first multiplexed signal has a certain frequency domain bandwidth, and the local analog clock signal and the first data signal are carried on different frequency bands, but this application is not limited to this.

[0074] S220, REC sends the first multiplexed signal to RE.

[0075] Accordingly, RE receives the first multiplexed signal from REC.

[0076] Optionally, the REC can modulate the first multiplexed signal onto an optical carrier to obtain a first optical signal, and send the first optical signal to the RE, wherein the first optical signal includes the first multiplexed signal.

[0077] Accordingly, after receiving the first optical signal, the RE demodulates the first optical signal to obtain the first multiplexed signal.

[0078] S230, RE demultiplexes the first multiplexed signal to obtain the fourth analog clock signal and the first data signal.

[0079] The first multiplexed signal received by RE is the first multiplexed signal that has undergone the transmission delay between REC and RE. The fourth analog clock signal is the clock signal of REC's local analog clock signal after undergoing the transmission delay between REC and RE. The fourth analog clock signal is an analog signal.

[0080] According to the specific implementation in S210, if the local analog clock signal and the first data signal are multiplexed in a time-division multiplexing manner to obtain the first multiplexed signal, then the RE demultiplexes the first multiplexed signal to obtain the fourth analog clock signal and the first data signal.

[0081] Optionally, RE can control the fourth switching switch to demultiplex the first multiplexed signal to obtain the fourth analog clock signal and the first data signal.

[0082] For example, when the RE controls the fourth switch to switch to the third state, the fourth switch outputs the first data signal in the first multiplexed signal; when the RE controls the fourth switch to switch to the fourth state, the fourth switch outputs the fourth analog clock signal in the first multiplexed signal, but this application is not limited thereto.

[0083] According to the specific implementation in S210, if the local analog clock signal and the first data signal are multiplexed using frequency division multiplexing to obtain the first multiplexed signal, then the RE demultiplexes the first multiplexed signal to obtain the fourth analog clock signal and the first data signal.

[0084] For example, RE extracts the fourth analog clock signal from the frequency band where the fourth analog clock signal is located within the frequency domain bandwidth of the first multiplexed signal, and extracts the first data signal from the frequency band where the first data signal is located, but this application is not limited thereto.

[0085] S240, RE multiplexes the fourth analog clock signal and the second data signal to obtain the second multiplexed signal.

[0086] The second data signal is the data signal that RE will send to REC.

[0087] In one implementation, the RE time-division multiplexes the fourth analog clock signal with the second data signal to obtain the second multiplexed signal.

[0088] Optionally, RE can control a third switching switch to achieve multiplexing of the fourth analog clock signal and the second data signal.

[0089] For example, when the RE controls the third switch to switch to the first state, the second multiplexed signal output by the third switch includes the second data signal; when the RE controls the third switch to switch to the second state, the second multiplexed signal output by the third switch includes the fourth analog clock signal, but this application is not limited thereto.

[0090] In another implementation, RE performs frequency division multiplexing of the fourth analog clock signal and the second data signal and outputs the second multiplexed signal.

[0091] S250, RE sends the second multiplexed signal to REC.

[0092] Accordingly, RE receives the second multiplexed signal from REC.

[0093] Optionally, the RE can modulate the second multiplexed signal onto an optical carrier to obtain a second optical signal, and then send the second optical signal to the REC.

[0094] Accordingly, after receiving the second optical signal, REC demodulates the second optical signal to obtain the second multiplexed signal.

[0095] S260, REC demultiplexes the second multiplexed signal to obtain the first analog clock signal and the second data signal.

[0096] Wherein, the first analog clock signal is an analog signal, the second multiplexed signal received by REC is a second multiplexed signal that has undergone the transmission delay between RE and REC, and the first analog clock signal is the fourth analog clock signal after the transmission delay between RE and REC. In other words, the first analog clock signal is the clock signal of REC's local analog clock signal after undergoing the transmission delay between REC and RE and the transmission delay between RE and REC.

[0097] S270, REC determines the first signal based on the first analog clock signal and the third analog clock signal.

[0098] The REC can determine the path transmission delay and obtain the delay compensation amount based on the delay value between the first analog clock signal and the third analog clock signal (i.e., the local analog clock signal). Alternatively, the REC can perform delay compensation on the local analog clock signal based on the path transmission delay to obtain the second analog clock signal. In other words, the second analog clock signal is the clock signal obtained after delay compensation of the local analog clock signal. The first signal is either the delay compensation amount or the second analog clock signal.

[0099] In one implementation, REC can calculate the phase offset between the first analog clock signal and the local analog clock signal, and determine the path transmission delay based on the phase offset.

[0100] For example, REC determines the loop (i.e., REC to RE and RE to REC) transmission delay value ΔT1 based on the phase offset between the first analog clock signal and the local analog clock signal. Based on ΔT1, the single-path transmission delay value is approximately ΔT1 / 2. The second analog clock signal is obtained by advancing the time of the local analog clock signal by ΔT1 / 2. However, this application is not limited to this.

[0101] In another implementation, REC can use a symmetrical dual-mixing time difference measurement method to determine the time delay compensation between the first analog clock signal and the local analog clock signal.

[0102] For example, REC uses the same frequency to convert the first analog clock signal and the local analog clock signal to obtain the low-frequency signals of the two clock signals. That is, after amplifying the phase of the first analog clock signal and the local analog clock signal by a first ratio, the amplified phase offset between the amplified first analog clock signal and the local analog clock signal is calculated. Then, the amplified phase offset is reduced by a first ratio to obtain a more accurate phase offset between the first analog clock signal and the local analog clock signal. Based on the phase offset, the loop transmission delay value ΔT2 is determined, and the single-path transmission delay value is determined to be approximately ΔT2 / 2. The single-path transmission delay value ΔT2 / 2 is used as the delay compensation amount, but this application is not limited to this.

[0103] According to the above scheme, the symmetrical dual-mixing time difference measurement method can measure more accurate path delay and improve the synchronization accuracy.

[0104] S280, REC obtains the first data signal after time delay compensation based on the first signal processing data.

[0105] In S270, REC obtains a first signal based on a first analog clock signal. REC can process data according to this first signal, causing the clock of the first data signal to be sent from REC to RE to be advanced, i.e., the processed data signal is a delay-compensated first data signal. The delay-compensated first data signal can reach RE after experiencing the transmission delay between REC and RE, and is synchronized with the clock of REC.

[0106] For example, when the first signal is a delay compensation amount, REC can process the data according to the delay compensation amount and the local analog clock signal, so that the clock of the first data signal to be sent from REC to RE is advanced. Alternatively, REC can process the first data signal according to the second analog clock signal, so that the delay-compensated first data signal arrives at RE after experiencing the transmission delay from REC to RE and is synchronized with the clock of REC. However, this application is not limited to this.

[0107] According to the above scheme, the REC multiplexes its local analog clock signal with the data signal to be transmitted and transmits it to the RE. The RE then feeds back the received clock signal to the REC. This ensures that the REC's local analog clock signal returns to the REC after experiencing a loop transmission delay. The REC determines the single-path delay value and compensates for the local analog clock signal. The compensated clock signal is then used to process the data signal, ensuring that the data signal is synchronized with the REC's clock when it is transmitted to the RE. The REC can repeatedly multiplex its local analog clock signal with the data signal to be transmitted, for example, periodically multiplexing the local analog clock signal with the data signal to be transmitted to periodically correct the loop delay, improve the accuracy of data signal delay compensation, and achieve adaptive link delay compensation.

[0108] This scheme enables REC to perform system coordination, reducing interference between signals from multiple REs. It can reduce clock synchronization deviations caused by the uncertainty of digital timestamp loading and unloading delays, thereby improving clock synchronization accuracy.

[0109] The above combination Figure 2 The clock synchronization method provided in the embodiments of this application has been described below, in conjunction with... Figure 3 The following figures illustrate the communication device provided in the embodiments of this application.

[0110] Figure 3 This is a schematic block diagram of the communication device 300 provided in the embodiments of this application.

[0111] In one possible design, the communication device 300 may correspond to the REC in the above method embodiments, or be a chip configured in (or used for) the REC. The communication device 300 can perform the corresponding operations or steps performed by the REC in method 200 of this application embodiment.

[0112] like Figure 3 As shown, the communication device 300 may include a combining module 301, a clock synchronization module 302, a data processing module 303, a splitting module 304, a transceiver module 305, and a local oscillator 306.

[0113] In this communication device 300, the combining module is connected to the data processing module, the local oscillator, and the transceiver module, respectively. The combining module is used to combine the local analog clock signal (e.g., from the local oscillator) from the local oscillator... Figure 3 The first multiplexed signal is obtained by combining the Clk0 signal from the data processing module with the first data signal from the data processing module, and the first multiplexed signal is output to the transceiver module.

[0114] In one possible design, the combining module is a first switching switch used to time-division multiplex the local analog clock signal and the first data signal to obtain a first multiplexed signal. When the first switching switch is switched to a first state, the first switching switch outputs the first data signal input by the data processing module; when the first switching switch is switched to a second state, the first switching switch outputs the local analog clock signal.

[0115] For example, the first switch is Figure 4 The single-pole double-throw switch 401 shown, when the first switch is switched to the first state, i.e., the first switch is connected to connection point A, the first multiplexed signal output by the switch to the transceiver module includes the first data signal; when the first switch is switched to the second state, i.e., the first switch is connected to connection point B, the first multiplexed signal output by the switch to the transceiver module includes the local analog clock signal. However, this application is not limited to this.

[0116] In another possible design, the combining module is a power divider combiner, used to frequency divide and multiplex the local analog clock signal with the first data signal to obtain the first multiplexed signal.

[0117] For example, the combining module is Figure 5 The power divider / combiner 501 in the middle frequency-division multiplexes the local analog clock signal from the local oscillator with the first data signal from the data processing module and outputs the first multiplexed signal to the transceiver module. The first data signal and the local analog clock signal can be carried on different frequency band resources of the first multiplexed signal. However, this application is not limited to this.

[0118] The transceiver module is connected to the combining module and the splitting module. The transceiver module is used to transmit the first multiplexed signal to a first device (e.g., the first device may be an RE or the first device may be configured on an RE, but this application is not limited thereto). The transceiver module is also used to receive a second multiplexed signal from the first device and output the second multiplexed signal to the splitting module.

[0119] Optionally, the communication device 300 and the first device can transmit electrical signals, for example, the communication device 300 and the first device can be connected by a cable. Alternatively, the communication device 300 and the first device can transmit optical signals, for example, the communication device 300 and the first device can be connected by an optical fiber.

[0120] Optionally, the transceiver module includes an electro-optic modulation unit, a photoelectric detection unit, and a transceiver unit, wherein the transceiver module is used to transmit the first multiplexed signal to the first device, including:

[0121] The electro-optic modulation unit is used to modulate the first multiplexed signal onto an optical carrier to obtain a first optical signal, and output the first optical signal to the transceiver unit;

[0122] The transceiver unit is used to send the first optical signal to the first device, the first optical signal including the first multiplexed signal;

[0123] Furthermore, the transceiver module is also used to receive a second multiplexed signal from the first device, including:

[0124] The transceiver unit is also used to receive a second optical signal from the first device, the second optical signal including the second multiplexed signal;

[0125] The photoelectric detection unit is used to demodulate the second optical signal to obtain the second multiplexed signal.

[0126] Optionally, the electro-optic modulation unit may be an electro-optic modulator, which modulates the first multiplexed signal onto an optical carrier to obtain a first optical signal, the first optical signal including the first multiplexed signal. Additionally, the photodetector unit may be a photoelectric converter, which demodulates a second optical signal (including a second multiplexed signal) from the first device to obtain a second multiplexed signal.

[0127] For example, after the electro-optic modulator in the transceiver module modulates the amplitude and phase of the first multiplexed signal onto an optical carrier to obtain a first optical signal, the transceiver module transmits the first optical signal to the first device. And, after receiving a second optical signal from the first device, the photoelectric converter in the transceiver module demodulates the amplitude and phase of the second optical signal, converting the second optical signal into an electrical signal, i.e., a second multiplexed signal. The transceiver module outputs the second multiplexed signal to the splitter module, but the application is not limited to this.

[0128] In this communication device 300, the splitter module is connected to the transceiver module, the clock synchronization module, and the data processing module. This splitter module is used to split the second multiplexed signal to obtain a second data signal and a first analog clock signal (e.g., ...). Figure 3 The first analog clock signal is output to the clock synchronization module, and the second data signal is output to the data processing module.

[0129] In one possible design, the second multiplexed signal from the first device is a time-division multiplexed signal, and the splitter module is a second switch used to time-division multiplex the local analog clock signal and the first data signal to obtain the first multiplexed signal. When the second switch is switched to the third state, the second switch outputs the second data signal to the data processing module; when the second switch is switched to the fourth state, the second switch outputs the first analog clock signal to the clock synchronization module.

[0130] For example, the second switch is Figure 6 The single-pole double-throw switch 601 shown, when the second switch is switched to the third state, i.e., the second switch is connected to connection point C, outputs the second data signal from the second multiplexed signal to the data processing module; when the second switch is switched to the fourth state, i.e., the second switch is connected to connection point D, outputs the first analog clock signal from the second multiplexed signal to the clock synchronization module. However, this application is not limited to this.

[0131] In another possible design, the second multiplexed signal from the first device is a frequency division multiplexed signal, and the splitter module is a power divider used to demultiplex the second multiplexed signal to obtain a first analog clock signal and a second data signal.

[0132] For example, the splitter module is Figure 7 The power divider 701 in the middle demultiplexes the second multiplexed signal to obtain a first analog clock signal and a second data signal. Furthermore, the power divider 701 outputs the first analog clock signal to the clock synchronization module and the second data signal to the data processing module. However, this application is not limited to this.

[0133] In this communication device 300, a clock synchronization module is connected to a splitter module, a local oscillator, and a data processing module. The clock synchronization module is used to obtain a first signal (e.g., a first analog clock signal input from the splitter module and a local analog clock signal input from the local oscillator) based on the first analog clock signal input from the splitter module and the local analog clock signal input from the local oscillator. Figure 3 (as shown), and outputs the first signal to the data processing module.

[0134] For example, Figure 8 This is a schematic structural diagram of the clock synchronization module provided in an embodiment of this application. The clock synchronization module first calculates the loop transmission delay value based on the first analog clock signal Clk1 and the local analog clock signal Clk0, and then obtains the single-path transmission delay value. The clock synchronization module then compensates Clk0 based on the single-path transmission delay value to obtain the second analog clock signal Clk2 (i.e., the first signal is the second analog clock signal), and outputs Clk2 as the first signal in the aforementioned embodiment to the data processing module. Specifically, the demultiplexed Clk1 signal is passed through a low-pass filter (LPF) and mixed with Clk0 at three times the frequency to obtain a mixed delay signal at twice the frequency. This mixed delay signal is then passed through a band-pass filter (BPF) and down-frequency-diminished before being used to compensate Clk0 to obtain Clk2, but this application is not limited to this.

[0135] For example, Figure 9 This is another schematic structural diagram of the clock synchronization module provided in an embodiment of this application. The clock synchronization module uses a symmetrical dual-mixing time difference measurement method to obtain the transmission delay. For example, the clock synchronization module uses frequency f1 to convert Clk1 and Clk0 to different frequencies. The converted Clk1 and Clk0 are then passed through a zero-crossing comparator to obtain data signals. The delay value between Clk1 and Clk0 is then calculated to obtain a single-path delay value ΔT. This single-path delay value ΔT is then used as a delay compensation amount. The clock synchronization module outputs this delay compensation amount ΔT as the first signal to the data processing module in the aforementioned embodiment. However, this application is not limited to this.

[0136] Please continue reading Figure 3 In this communication device 300, the data processing module is connected to the clock synchronization module, the splitter module, and the combiner module, respectively. The data processing module processes data based on the first signal input from the clock synchronization module to obtain a time-delay compensated first data signal.

[0137] In one embodiment, the first signal is a second analog clock signal. The data processing module processes the data according to the second analog clock signal, so that the clock of the first data signal to be sent is advanced, that is, the first data signal after time delay compensation is obtained after processing.

[0138] After delay compensation, the first data signal undergoes a transmission delay from REC to RE and arrives at RE, where it is synchronized with the clock of REC.

[0139] In another embodiment, the first signal is a delay compensation amount. The data processing module can process the data according to the delay compensation amount and the local analog clock signal, so that the clock of the first data signal to be sent is advanced, and the delay-compensated first data signal is obtained.

[0140] The first data signal processed by the data processing module can overcome the transmission delay from the communication device 300 to the first device, so that the first data signal arrives at the first device in sync with the clock of the communication device 300.

[0141] After delay compensation, the first data signal is input to the combining module and multiplexed with the local analog clock signal to obtain the first multiplexed signal. The communication device 300 cyclically multiplexes the local analog clock signal with the data signal to be transmitted. For example, periodically multiplexing the local analog clock signal with the data signal to be transmitted can periodically correct the loop delay, improve the accuracy of data signal delay compensation, and realize the adaptive link delay compensation.

[0142] In one example, Figure 10 This is a schematic block diagram of a communication device 1000 provided in an embodiment of this application. The communication device 1000 includes a combining module 1001 (i.e., a first switching switch), a clock synchronization module 1002, and a data processing module 1003. The data processing module includes a serializer for processing data to be transmitted and a deserializer for processing received data. The communication device 1000 also includes a splitting module 1004 (i.e., a second switching switch) and a transceiver module 1005. The transceiver module includes an electro-optic modulation unit, a photodetector unit, and a transceiver. The electro-optic modulation unit can be a laser generator, such as a laser diode (LD), and the photodetector unit can be a photodiode (PD), but this application is not limited to these. The LD can convert the first multiplexed signal into a first optical signal, which includes the first multiplexed signal. The communication device 1000 transmits the first optical signal to a first device via the transceiver. The PD can photoelectrically convert the second optical signal received from the first device by the transceiver to obtain a second multiplexed signal. However, this application is not limited to this.

[0143] In another example, Figure 11 This is a schematic block diagram of a communication device 1100 provided in an embodiment of this application. The communication device 1100 includes a combining module 1101 (i.e., a first switching switch), a clock synchronization module 1102, a data processing module 1103, a splitting module 1104 (i.e., a second switching switch), and a transceiver module 1105. The clock synchronization module 1102 uses a symmetrical double-mixing time difference measurement method to obtain the transmission delay value. Other modules are... Figure 10 The communication devices described above are the same and will not be repeated here.

[0144] It should be noted that, Figure 10 and Figure 11 In the communication device shown, the combining module can be replaced with, for example... Figure 5 The power splitter and combiner shown, as well as the splitter module, can be replaced with... Figure 7 The power divider shown is an example. However, this application is not limited to this.

[0145] Figure 12 This is a schematic block diagram of the communication device 1200 provided in the embodiments of this application.

[0146] In one possible design, the communication device 1200 may correspond to the RE in the above method embodiments, or be a chip configured in (or used for) the RE. The communication device 300 may perform the corresponding operations or steps performed by the RE in method 200 of this application embodiment.

[0147] like Figure 12 As shown, the communication device 300 may include a transceiver module 1201, a splitter module 1202, a combiner module 1203, and a data processing module 1204.

[0148] The transceiver module is used to receive a first multiplexed signal from a second device (e.g., REC or a device configured in REC) and output the first multiplexed signal to the splitter module;

[0149] The splitter module is used to split the first multiplexed signal to obtain a first data signal and a fourth analog clock signal, and output the fourth analog clock signal to the combiner module.

[0150] In one possible design, the splitter module is specifically used to demultiplex the first multiplexed signal and output the first data signal and the fourth analog clock signal.

[0151] Optionally, the splitter module includes a fourth switch. When the fourth switch is switched to the third state, the fourth switch outputs the first data signal to the data processing module. When the fourth switch is switched to the fourth state, the fourth switch outputs the fourth analog clock signal to the combiner module.

[0152] In another possible design, the splitter module is specifically used to demultiplex the first multiplexed signal and output the first data signal and the first analog clock signal.

[0153] The combining module is used to combine the fourth analog clock signal and the second data signal from the data processing module to obtain a second multiplexed signal, and output the second multiplexed signal to the transceiver module; the transceiver module is also used to send the second multiplexed signal to the second device.

[0154] In one possible design, the combining module is specifically used to time-division multiplex the fourth analog clock signal with the second data signal and output the second multiplexed signal.

[0155] Optionally, the combining module includes a third switching switch. When the third switching switch is switched to the first state, the third switching switch outputs the second data signal input by the data processing module; when the third switching switch is switched to the second state, the third switching switch outputs the fourth analog clock signal input by the splitting module.

[0156] In another possible design, the combining module is specifically used to frequency-division multiplex the first analog clock signal and the second data signal and output the second multiplexed signal.

[0157] Optionally, the transceiver module includes an electro-optic modulation unit, a photoelectric detection unit, and a transceiver unit. The transceiver module is used to receive a first multiplexed signal from the second device, including:

[0158] The transceiver unit is used to receive a first optical signal from the second device, the first optical signal including a first multiplexed signal;

[0159] The photoelectric detection unit is used to demodulate the first optical signal to obtain the first multiplexed signal.

[0160] And, the transceiver module is used to send the second multiplexed signal to the second device, including:

[0161] The electro-optic modulation unit is used to modulate the second multiplexed signal onto an optical carrier to obtain a second optical signal, and output the second optical signal to the transceiver unit;

[0162] The transceiver unit is also used to send the second optical signal to the second device, the second optical signal including a second multiplexed signal.

[0163] For example, Figure 13This is a schematic structural diagram of a communication device 1300 provided in an embodiment of this application. The communication device 1300 includes a transceiver module 1301 that converts received optical signals into electrical signals and converts electrical signals to be transmitted into optical signals; and a splitter module 1302, i.e., a third switching switch, used to demultiplex a first multiplexed signal to obtain a first analog clock signal and a first data signal. If the first data signal undergoes time delay compensation by a second device, or is obtained by the second device based on a time delay-compensated clock, the first data signal is synchronized with the clock of the second device. The splitter module 1302 outputs the first analog clock signal to a combiner module 1303 (optionally, it can be input to the combiner module 1303 after LPF filtering). The combiner module 1303 multiplexes the first analog clock signal and the second data signal to obtain a second multiplexed signal, which is then output to the transceiver module 1301. However, this application is not limited to this.

[0164] According to the method provided in the embodiments of this application, this application also provides a system that includes one or more of the aforementioned second devices. The system may further include one or more of the aforementioned first devices.

[0165] Figure 14 This is another schematic diagram of the communication system provided in an embodiment of this application. The communication system includes a first device and a second device. The first device may be a RE or a device or chip configured in the RE, and the second device may be a REC or a device or chip configured in the REC. The first device and the second device can communicate via optical fiber, for example, by transmitting a first optical signal carrying a first multiplexed signal and a second optical signal carrying a second multiplexed signal via optical fiber, but this application is not limited thereto.

[0166] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when executed by one or more processors, causes a device including the processor to perform... Figure 2 The method in the illustrated embodiment.

[0167] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code that, when executed by one or more processors, causes a device including the processor to perform... Figure 2 The method in the illustrated embodiment.

[0168] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0169] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0170] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0171] In the embodiments of this application, provided there is no logical contradiction, the embodiments may reference each other. For example, the methods and / or terms between method embodiments may reference each other, the functions and / or terms between device embodiments may reference each other, and the functions and / or terms between device embodiments and method embodiments may reference each other.

[0172] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A communication device, characterized in that, include: Combiner module, oscillator, clock synchronization module, data processing module, splitter module, and transceiver module; The combining module is used to combine the third analog clock signal from the oscillator with the first data signal from the data processing module to obtain a first multiplexed signal, and output the first multiplexed signal to the transceiver module. The transceiver module is used to send the first multiplexed signal to the first device; The transceiver module is also used to receive a second multiplexed signal from the first device, and to output the second multiplexed signal to the splitter module; The splitting module is used to split the second multiplexed signal to obtain a second data signal and a first analog clock signal, and to output the first analog clock signal to the clock synchronization module. The first analog clock signal is the third analog clock signal that has undergone transmission delay. The clock synchronization module is used to obtain a first signal based on the first analog clock signal and the third analog clock signal from the oscillator, and output the first signal to the data processing module. The first signal is either a time delay compensation amount between the first analog clock signal and the third analog clock signal or a second analog clock signal. The second analog clock signal is the third analog clock signal after time delay compensation. The data processing module is used to obtain a time-delay-compensated first data signal based on the first signal processed data. The clock synchronization module uses a symmetrical dual-mixing time difference measurement method to determine the time delay compensation between the first analog clock signal and the third analog clock signal.

2. The apparatus according to claim 1, characterized in that, The transceiver module includes an electro-optic modulation unit, a photoelectric detection unit, and a transceiver unit. The transceiver module is used to send the first multiplexed signal to the first device, including: The electro-optic modulation unit is used to modulate the first multiplexed signal onto an optical carrier to obtain a first optical signal, and output the first optical signal to the transceiver unit; The transceiver unit is used to send the first optical signal to the first device, the first optical signal including the first multiplexed signal; and... The transceiver module is further configured to receive a second multiplexed signal from the first device, including: The transceiver unit is also configured to receive a second optical signal from the first device, wherein the second optical signal includes the second multiplexed signal; The photoelectric detection unit is used to demodulate the second optical signal to obtain the second multiplexed signal.

3. The apparatus according to claim 1 or 2, characterized in that, The combining module is specifically used to time-division multiplex the third analog clock signal with the first data signal and output the first multiplexed signal.

4. The apparatus according to claim 3, characterized in that, The combining module includes a first switching switch. When the first switch is switched to the first state, the first multiplexed signal output by the first switch includes the first data signal; or, When the first switch is switched to the second state, the first multiplexed signal output by the first switch includes the third analog clock signal.

5. The apparatus according to any one of claims 1 to 4, characterized in that, The splitter module is specifically used to demultiplex the second multiplexed signal and output the second data signal and the first analog clock signal.

6. The apparatus according to claim 5, characterized in that, The branching module includes a second switching switch. When the second switch is switched to the third state, the second switch outputs the second data signal from the second multiplexed signal to the data processing module; or, When the second switch is switched to the fourth state, the second switch outputs the first analog clock signal in the second multiplexed signal to the clock synchronization module.

7. The apparatus according to claim 1 or 2, characterized in that, The combining module is specifically used to frequency-division multiplex the third analog clock signal and the first data signal and output the first multiplexed signal; and / or, The splitter module is specifically used to demultiplex the second multiplexed signal and output the second data signal and the first analog clock signal.

8. A communication device, characterized in that, include: Transceiver module, splitter module, combiner module, and data processing module; The transceiver module is used to receive a first multiplexed signal from the second device and output the first multiplexed signal to the splitter module; The splitting module is used to split the first multiplexed signal to obtain a first data signal and a fourth analog clock signal, and output the fourth analog clock signal to the combining module; The combining module is used to combine the fourth analog clock signal and the second data signal from the data processing module to obtain a second multiplexed signal, and output the second multiplexed signal to the transceiver module. The transceiver module is also used to send the second multiplexed signal to the second device.

9. The apparatus according to claim 8, characterized in that, The transceiver module includes an electro-optic modulation unit, a photoelectric detection unit, and a transceiver unit. The transceiver module is used to receive a first multiplexed signal from the second device, including: The transceiver unit is used to receive a first optical signal from the second device, wherein the first optical signal includes the first multiplexed signal; The photoelectric detection unit is used to demodulate the first optical signal to obtain the first multiplexed signal; Furthermore, the transceiver module is also configured to send the second multiplexed signal to the second device, including: The electro-optic modulation unit is used to modulate the second multiplexed signal onto an optical carrier to obtain a second optical signal, and output the second optical signal to the transceiver unit; The transceiver unit is also used to send the second optical signal to the second device, the second optical signal including the second multiplexed signal.

10. The apparatus according to claim 8 or 9, characterized in that, The combining module is specifically used to time-division multiplex the fourth analog clock signal and the second data signal and output the second multiplexed signal.

11. The apparatus according to claim 10, characterized in that, The combining module includes a third switching switch. When the third switch is switched to the first state, the second multiplexed signal output by the third switch includes the second data signal; or, When the third switch is switched to the second state, the second multiplexed signal output by the third switch includes the fourth analog clock signal.

12. The apparatus according to any one of claims 8 to 10, characterized in that, The splitter module is specifically used to demultiplex the first multiplexed signal and output the first data signal and the fourth analog clock signal.

13. The apparatus according to claim 12, characterized in that, The branching module includes a fourth switching switch. When the fourth switch is switched to the third state, the fourth switch outputs the first data signal from the first multiplexed signal to the data processing module; or... When the fourth switch is switched to the fourth state, the fourth switch outputs the fourth analog clock signal from the first multiplexing signal to the combining module.

14. The apparatus according to claim 8 or 9, characterized in that, The splitter module is specifically used to demultiplex the first multiplexed signal and output the first data signal and the fourth analog clock signal, and / or, The combining module is specifically used to frequency-division multiplex the fourth analog clock signal and the second data signal and output the second multiplexed signal.

15. A communication method, characterized in that, include: The first multiplexed signal is obtained by multiplexing the third analog clock signal with the first data signal. Send the first multiplexed signal to the first device; Receive a second multiplexed signal from the first device; After demultiplexing the second multiplexed signal, a second data signal and a first analog clock signal are obtained. The first analog clock signal is the third analog clock signal that has undergone a transmission delay. A first signal is obtained based on the first analog clock signal, wherein the first signal is either a time delay compensation amount or a second analog clock signal, and the second analog clock signal is the third analog clock signal after time delay compensation; The first data signal after time delay compensation is obtained based on the first signal processing data; Also includes: After performing time delay compensation on the third analog clock signal based on the first analog clock signal, the first signal is output, including: The time delay compensation between the first analog clock signal and the third analog clock signal is determined by using a symmetrical dual-mixing time difference measurement method.

16. The method according to claim 15, characterized in that, Sending the first multiplexed signal to the first device includes: The first multiplexed signal is modulated onto an optical carrier to obtain a first optical signal; The first optical signal is sent to the first device, wherein the first optical signal includes the first multiplexed signal; And, receiving the second multiplexed signal from the first device includes: Receive a second optical signal from the first device, wherein the second optical signal includes the second multiplexed signal; The second optical signal is demodulated to obtain the second multiplexed signal.

17. The method according to claim 15 or 16, characterized in that, The process of multiplexing the third analog clock signal with the first data signal to obtain the first multiplexed signal includes: The first multiplexed signal is obtained by time-division multiplexing the third analog clock signal with the first data signal.

18. The method according to claim 17, characterized in that, The step of time-division multiplexing the third analog clock signal with the first data signal to obtain the first multiplexed signal includes: When the first switching switch is switched to the first state, the first multiplexed signal output by the first switching switch includes the first data signal; When the first switching switch is switched to the second state, the first multiplexed signal output by the first switching switch includes the third analog clock signal.

19. The method according to any one of claims 15 to 18, characterized in that, The step of demultiplexing the second multiplexed signal to obtain the second data signal and the first analog clock signal includes: After demultiplexing the second multiplexed signal, the second data signal and the first analog clock signal are output.

20. The method according to claim 19, characterized in that, The step of demultiplexing the second multiplexed signal and outputting the second data signal and the first analog clock signal includes: When the second switch is switched to the third state, the second switch outputs the second data signal from the second multiplexed signal; When the second switch is switched to the fourth state, the second switch outputs the first analog clock signal in the second multiplexed signal.

21. The method according to claim 15 or 16, characterized in that, The step of multiplexing the third analog clock signal with the first data signal to obtain the first multiplexed signal includes: frequency-division multiplexing the third analog clock signal with the first data signal and outputting the first multiplexed signal; and / or, The step of demultiplexing the second multiplexed signal to obtain the second data signal and the first analog clock signal includes: demultiplexing the second multiplexed signal and outputting the second data signal and the first analog clock signal.

22. A communication method, characterized in that, include: Receive the first multiplexed signal from the second device; The first multiplexed signal is demultiplexed to obtain a first data signal and a fourth analog clock signal; The second multiplexed signal is obtained by multiplexing the fourth analog clock signal and the second data signal; Send the second multiplexed signal to the second device.

23. The method according to claim 22, characterized in that, The receiving of the first multiplexed signal from the second device includes: Receive a first optical signal from the second device, wherein the first optical signal includes the first multiplexed signal; Demodulate the first optical signal to obtain the first multiplexed signal; And, sending the second multiplexed signal to the second device includes: The second multiplexed signal is modulated onto an optical carrier to obtain a second optical signal; The second optical signal is sent to the second device, and the second optical signal includes the second multiplexed signal.

24. The method according to claim 22 or 23, characterized in that, The process of multiplexing the fourth analog clock signal and the second data signal to obtain the second multiplexed signal includes: The second multiplexed signal is output after time-division multiplexing the fourth analog clock signal with the second data signal.

25. The method according to claim 24, characterized in that, The step of time-division multiplexing the fourth analog clock signal with the second data signal and outputting the second multiplexed signal includes: When the third switching switch is switched to the first state, the second multiplexed signal output by the third switching switch includes the second data signal; When the third switch is switched to the second state, the second multiplexed signal output by the third switch includes the fourth analog clock signal.

26. The method according to any one of claims 22 to 24, characterized in that, The step of demultiplexing the first multiplexed signal to obtain the first data signal and the fourth analog clock signal includes: The first multiplexed signal is detime-division multiplexed to obtain the first data signal and the fourth analog clock signal.

27. The method according to claim 26, characterized in that, The step of demultiplexing the first multiplexed signal to obtain the first data signal and the fourth analog clock signal includes: When the fourth switching switch is switched to the third state, the fourth switching switch outputs the first data signal in the first multiplexed signal; When the fourth switch is switched to the fourth state, the fourth switch outputs the fourth analog clock signal from the first multiplexed signal.

28. The method according to claim 22 or 23, characterized in that, The process of demultiplexing the first multiplexed signal to obtain the first data signal and the fourth analog clock signal includes: After the first multiplexed signal is demultiplexed, the first data signal and the fourth analog clock signal are output. And, the process of multiplexing the fourth analog clock signal and the second data signal to obtain the second multiplexed signal includes: The second multiplexed signal is output after frequency division multiplexing the fourth analog clock signal and the second data signal.

29. A communication system, characterized in that, It includes the communication device according to any one of claims 1 to 7, and the communication device according to any one of claims 8 to 14.

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