A chip testing method, system, device and storage medium

Abstract

The application relates to the chip testing field and discloses a chip testing method, a system, equipment and a storage medium, the method comprising the following steps: controlling the opening or closing of a relay to regulate the power-on time and power-off time of a chip for multiple times; the relay is electrically connected with a chip testing board; a toggle switch is in an always-on state during testing; test logs of each power-on of the chip are read in real time; the state of the chip during testing is obtained according to the reading result of the test logs, so as to determine whether the chip is continuously tested or the statistical test result of the chip is generated. The above method adopts the relay, thereby saving the manual operation of the toggle switch, greatly simplifying the testing steps; the opening or closing of the relay can improve the accuracy of the test result; the logs are read in real time, once an abnormality is found, the testing can be immediately stopped, the statistical result is generated, the burden of the tester is reduced, and the testing efficiency and quality are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing, and in particular to a chip testing method, system, device, and storage medium. Background Technology

[0002] Chip testing is used to verify the correct functionality of a chip. Currently, most chip testing requires designing and building your own test system. Self-built test systems focus more on implementing individual test functions but neglect ease of use and accuracy. The testing process generally involves tedious manual labor and statistical analysis, and the accuracy often depends on the tester's experience, leading to low testing efficiency.

[0003] Power-on failure is a common chip malfunction where a module fails to function properly after power is applied. It requires careful troubleshooting by testers. This type of failure can originate from many sources, including design, layout, photolithography, packaging, and even firmware. Probabilistic power-on failures necessitate screening a large number of chips and statistically analyzing the abnormal conditions. Due to the relatively rudimentary testing tools available, a single batch of tests may require manually toggling test switches tens of thousands of times, compromising both convenience and accuracy. This lack of accuracy leads to inaccurate statistical results, potentially overlooking many details and making the root cause of the failure even more difficult to pinpoint.

[0004] Therefore, how to solve the problems of low efficiency and difficulty in guaranteeing accuracy in chip testing is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a chip testing method, system, device, and storage medium, which can simplify testing steps, improve the accuracy of test results and statistical results, and improve testing efficiency and quality. The specific solution is as follows:

[0006] A chip testing method, comprising:

[0007] The relay is controlled to turn on or off, thereby adjusting the power-on and power-off times of the chip multiple times; the relay is electrically connected to a toggle switch on the chip test board; the toggle switch is normally open during the test.

[0008] Read the test logs of the chip every time it is powered on in real time;

[0009] The chip status during the test is obtained based on the results read from the test log to determine whether to continue the test; if not, the chip status during the test is obtained and statistical test results of the chip are generated.

[0010] Preferably, in the chip testing method provided in the embodiments of the present invention, controlling the relay to turn on or off includes:

[0011] Send an activation command to the relay to control the relay to activate;

[0012] After waiting for the opening time corresponding to the opening command, a closing command is sent to the relay to control the relay to close, and then waits for a set time after closing.

[0013] The operation of sending the turn-on command and the turn-off command to the relay is executed repeatedly.

[0014] Preferably, in the chip testing method provided in the embodiments of the present invention, before controlling the relay to turn on or off, the method further includes:

[0015] Set the parameters to be counted to zero, open the log file and statistics file, and output the handles of the log file and statistics file; the parameters to be counted include the number of tested chips, the number of passes, the number of first anomalies, the number of probability anomalies, and the probability anomaly time statistics array.

[0016] Preferably, in the chip testing method provided in the embodiments of the present invention, obtaining the chip status during the test based on the test log to determine whether to continue the test includes:

[0017] Determine whether the test log contains paragraphs indicating that the test passed or paragraphs indicating that the test failed, and obtain the result of reading the log;

[0018] Determine if the number of iterations exceeds a set number, and obtain the result of the iteration count.

[0019] Based on the reading logs and the results of the loop count, the chip status during the test is obtained to determine whether to continue the test.

[0020] Preferably, in the chip testing method provided in the embodiments of the present invention, while acquiring the chip state during the testing process, it further includes:

[0021] Choose to illuminate the continuous test indicator, the abnormality indicator, or the system fault indicator;

[0022] If the abnormal indicator light is lit, it is determined whether the chip is experiencing an abnormality upon first power-on; if so, the first abnormality count is updated; if not, the probability abnormality count is updated, and the loop count is written into the probability abnormality time statistics array.

[0023] If the abnormal indicator light is not lit, the chip test is considered to have passed, and the pass count is updated.

[0024] Preferably, in the chip testing method provided in the embodiments of the present invention, generating statistical test results for the chip includes:

[0025] Create a format string and write the number of tested chips, the number of passes, the number of first anomalies, and the number of probability anomalies into the format string according to a set format;

[0026] The shutdown time array is indexed using each element in the probability anomaly time statistics array and converted into a string, which is then written into the formatted string.

[0027] The final formatted string is written to the statistics file.

[0028] Preferably, the chip testing method provided in the embodiments of the present invention further includes:

[0029] The control panel displays the chip status and statistical test results in real time.

[0030] This invention also provides a chip testing system, comprising:

[0031] The control switch module is used to control the opening or closing of the relay to adjust the power-on and power-off times of the chip multiple times; the relay is electrically connected to the toggle switch on the chip test board; the toggle switch is normally open during the test.

[0032] The log reading module is used to read the test log of the chip each time it is powered on in real time, and obtain the chip status during the test based on the results of the test log reading to determine whether to continue the test.

[0033] The results statistics module is used to generate statistical test results for the chip when the log reading module determines that the test should not continue.

[0034] This invention also provides a chip testing device, including a processor and a memory, wherein the processor executes a computer program stored in the memory to implement the chip testing method described above as provided in this invention.

[0035] This invention also provides a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the chip testing method described above as provided in this invention.

[0036] As can be seen from the above technical solution, the chip testing method provided by the present invention includes: controlling the opening or closing of a relay to adjust the power-on and power-off times of the chip multiple times; the relay is electrically connected to a toggle switch on the chip test board; the toggle switch is normally open during the test; the test log of each power-on of the chip is read in real time; the chip status during the test is obtained based on the results of the test log reading to determine whether to continue the test; if not, the statistical test results of the chip are generated.

[0037] The chip testing method provided by this invention eliminates the need for manual switching by using relays, greatly simplifying the testing process. Controlling the relay's opening and closing significantly improves the accuracy of test results, freeing them from interference from the tester's actions. Real-time log reading accurately determines the chip's state during testing, allowing for a decision on whether to continue testing or compile results. Upon detecting an anomaly, the test can be immediately stopped, generating statistical test results. This eliminates the need for testers to manually select whether to continue testing based on the logs or to manually record results after each test, reducing their workload, improving the accuracy of statistical results, and ultimately greatly enhancing testing efficiency and quality.

[0038] Furthermore, the present invention also provides a corresponding system, device, and computer-readable storage medium for chip testing methods, further making the above methods more practical. The system, device, and computer-readable storage medium have corresponding advantages. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0040] Figure 1 A flowchart of a chip testing method provided in an embodiment of the present invention;

[0041] Figure 2 This is a state transition diagram of the chip testing method provided in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of the structure of the log reading module provided in an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of the front panel structure provided in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the chip testing system provided in an embodiment of the present invention. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] This invention provides a chip testing method, such as... Figure 1 As shown, it includes the following steps:

[0047] S101. Controls the relay to turn on or off, thereby repeatedly adjusting the power-on and power-off times of the chip; the relay is electrically connected to the toggle switch on the chip test board; the toggle switch is normally open during the test.

[0048] It should be noted that the toggle switch on the chip test board is a mechanical switch, which connects or disconnects the circuit by manually moving the switch handle. The relay used in this invention is also a mechanical switch. This invention controls the relay to turn on or off through a program, thereby precisely controlling the power-on time of the chip and completing all tests for a chip in one go.

[0049] Preferably, the relay of this invention can be a USB relay, which is a USB smart control switch that receives signals from a USB port to achieve switching functionality. The relay is powered by the power pins of the USB port and transmits data using the data pins of the USB port, eliminating the need for separate power and communication modules as with traditional relays. The relay's control ports are normally closed, normally open, and a common terminal. The common and normally open terminals are connected to a toggle switch on the chip test board, and during testing, the toggle switch is opened to the normally open state, allowing the relay to repeatedly control the power-on and power-off of the chip test board. Preferably, the USB relay can be an LCUS-1 type USB relay, but other models can also be used; no limitation is made here.

[0050] S102. Real-time reading of the test log for each power-on of the chip;

[0051] It is understandable that a chip passing test means passing multiple consecutive power-on and power-off tests with different waiting times. Each power-on will generate a test log. In this invention, the test log can be captured in real time, and the test can be stopped if an anomaly is detected. Step S102 can be executed by the log reading module designed in this invention, which can track the latest test log in real time and capture key information.

[0052] S103. Obtain the chip status during the test based on the test log reading results to determine whether to continue the test; if not, generate the chip's statistical test results.

[0053] Specifically, the test logs can be used to determine whether the chip is malfunctioning or the system is faulty. The chip status during the test can be obtained, and the chip status can be used to determine whether to continue testing or to collect the results. For example, if the chip is malfunctioning, the test does not need to continue, and the statistical test results of the chip can be generated directly, which can be displayed in the form of a report in practical applications. If the chip is not malfunctioning, the test can continue.

[0054] In the chip testing method provided in this embodiment of the invention, the use of relays eliminates the need for manual switching, greatly simplifying the testing process. Testers can focus solely on the system test report. Controlling the relay's opening and closing significantly improves the accuracy of test results, eliminating interference from the tester's manual methods. Real-time log reading accurately determines the chip's state during testing, allowing for a decision on whether to continue testing or compile results. Upon detecting an anomaly, subsequent testing can be immediately stopped, generating statistical test results for the chip. This eliminates the need for testers to manually select whether to continue testing based on the test log or to manually record test results after each test, reducing their workload, improving the accuracy of statistical results, and ultimately greatly enhancing testing efficiency and quality.

[0055] Furthermore, in a specific implementation, in the chip testing method provided in the embodiments of the present invention, step S101, controlling the opening or closing of the relay, may specifically include: sending an opening command to the relay to control the relay to open; after waiting for the opening time corresponding to the opening command, sending a closing command to the relay to control the relay to close; and waiting for a set time after closing; and repeatedly executing the operation of sending opening and closing commands to the relay.

[0056] It should be noted that the relay uses serial communication, meaning it can be directly controlled by a computer. The switching commands are program-controlled, and the switching time is precisely adjustable. In practical applications, the relay's USB port is plugged into the computer, and the driver for the USB-to-serial chip CH340 can be installed. The relay can then be controlled programmatically. For example, the serial port baud rate can be set to 9600, and sending A00101A2 in hexadecimal to the relay's serial port will turn it on; sending A00100A1 will turn it off. By designing the command sending interval, the relay's on and off times can be controlled. Continuously sending switching commands allows all tests for a single chip to be completed at once.

[0057] For example, some chips have power-on anomalies. These chips need to be screened to distinguish between those with initial power-on anomalies, those with probabilistic power-on anomalies (i.e., those with power-on anomalies after a delay), and those that successfully power on. Statistics on the probabilistically power-on anomalies should also be compiled. The test plan involves 20 consecutive power-on cycles, each with the same power-on time, and the disconnection intervals increasing from short to long. SSCOM serial port debugging software can be used to set a series of communication commands for the relay. The first command sends A00101A2 in hexadecimal to open the relay (sequence 1), with a delay of 1000ms. The second command sends A00100A1 in hexadecimal to close the relay (sequence 2), with a delay of 100ms. Subsequent odd-numbered commands send A00101A2 with a 1000ms delay, and even-numbered commands send A00100A1 with a delay of the number of commands / 2 * 100ms. After setting up the serial port, clicking "cycle sending" allows you to read the logs of each power-on cycle to determine if a chip has a power-on anomaly. Therefore, all tests for a chip can be completed at once.

[0058] It should be noted that the control program architecture of this invention can be understood as a finite state automaton, such as... Figure 2 As shown, the finite state automaton of this invention can switch between seven states: initialization, waiting operation, adding a new sample, single test, log capture, statistical results, and writing to a statistical document. The specific working method of each state is described below.

[0059] In specific implementation, in the chip testing method provided in the embodiments of the present invention, before executing step S101 to control the relay to turn on or off, it may also include: setting the parameter to be counted to zero, opening the log file and the statistics file, and outputting the log file handle LH and the statistics file handle SH; the parameter to be counted here may include the number of tested chips AN, the number of passes PN, the number of first anomalies (i.e., the chip has an anomaly after the first power-on) FE, the number of probability anomalies (also known as delayed anomalies, which can be understood as an anomaly that will only appear after multiple power-ons, which may be related to the number of power-ons or the interval between two power-ons) DE, and the probability anomaly time statistics array DT[].

[0060] The above process describes the initialization state of a finite state automaton. Upon startup, the finite state automaton immediately enters the initialization state and performs initialization operations: zeroing the parameters that need to be statistically analyzed, and opening the log file and statistics file. The parameters that need to be zeroed are: number of tested chips AN, pass count PN, first anomaly count FE, probability anomaly count DE, and probability anomaly time statistics array DT[]. The log file path browsing option is File - Existing, the operation is Open, and the permission is Read-only. The statistics file path browsing option is File - New or Existing, the operation is Open or Create, and the permission is Read-Write. After the files are opened, the log file handle LH and the statistics file handle SH are output. After initialization, the automaton immediately enters the waiting operation state.

[0061] In the waiting operation state, it is necessary to wait for an event (such as an event on the front panel) to occur. The finite state automaton adds responses to three events: the "Add Test" button is pressed, the "Result Statistics" button is pressed, and the "Initialize" button is pressed, which respectively jump to the "Add Sample" state, the "Write to Statistics Document" state, and the "Initialize" state.

[0062] In the new sample state, set the cycle count CI to zero, turn off the sample abnormality indicator and system fault indicator, and enter the single test state during normal testing.

[0063] In a single test, the process is executed sequentially in four steps: First, an on command A00101A2 is sent to the relay; second, the relay waits for the set on time OT; third, an off command A00100A1 is sent to the relay; and fourth, the off time array CT[] is indexed using the loop count CI, and the relay waits according to the indexed time. After completion, the process jumps to the log reading state.

[0064] In a specific implementation, in the chip testing method provided in the embodiments of the present invention, step S103 obtains the chip status during the test based on the test log to determine whether to continue the test. Specifically, it may include: determining whether the test log contains a section that passed the test or a section that failed the test, and obtaining a judgment result of reading the log; determining whether the number of loops is greater than a set number, and obtaining a judgment result of the number of loops; and obtaining the chip status during the test based on the judgment result of reading the log and the number of loops, to determine whether to continue the test.

[0065] Furthermore, in specific implementation, while acquiring the chip status during the test, the following can also be included: selecting to light up the continuous test indicator, the abnormality indicator, or the system fault indicator; if the abnormality indicator is lit, it is determined whether the chip is experiencing an initial power-on abnormality; if so, the initial abnormality count is updated; if not, the probability abnormality count is updated, and the loop count is written into the probability abnormality time statistics array; if the abnormality indicator is not lit, the chip test is determined to have passed, and the pass count is updated.

[0066] The above process describes the log reading state of a finite state automaton. In the log reading state, the following functions need to be implemented: Retrieve the most recently generated log segment after the previous test, and determine if the log contains segments indicating a passed test or a failed test. Increment the loop count by one and check if it exceeds a set number. Based on the read log and the loop count determination result, select to illuminate the continuous test indicator, the exception indicator, or the system fault indicator, and then transition to the single test state, the result statistics state, or the waiting operation state.

[0067] To implement the corresponding functionality in the log reading state, a log reading module needs to be designed and written. For example... Figure 3 As shown, the first step is to capture the latest test log and determine whether it contains sections indicating a passed or failed test. This requires the following steps: First, call the log file handle LH and access the function to set the file position, setting the current position to 300 characters backward from the end of the file. Then, call the function to read the text file, reading 300 characters from the current position to the end of the file, and writing the file handle to LH for future calls. From the read strings, search for characteristic strings indicating a passed test. If found, the test is considered passed and recorded as event A. Next, search for characteristic strings indicating a failed test. If found, the test is considered failed and recorded as event B. Then, determine the test status. Increment the loop count CI and simultaneously measure the size of the shutdown time array s_CT[]. If CI is less than s_CT[], record it as event C. If both events A and C are true, illuminate the continuous test indicator and jump to the single test status. If event B is true, illuminate the exception indicator. If event B is true or event C is false, jump to the result statistics status. If both event A and event B are false, the system error indicator light will illuminate, and the system will transition to a waiting operation state.

[0068] In the result statistics state, first increment the number of tested chips AN by one, and check if the abnormal indicator light is lit. If it is not lit, it means that the chip test has passed, increment the pass count PN by one, and set the enumeration indicator to "Test Passed". If the abnormal indicator light is lit, it is necessary to determine whether the chip is abnormal on the first power-on or the delayed power-on, and check if the loop count is equal to 1. If it is true, increment the first abnormal count FE by one and set the enumeration indicator to "First Abnormal"; if it is false, increment the probability abnormal count DE by one, set the enumeration indicator to "Probability Abnormal", and write the loop count into the probability abnormal time statistics array DT[].

[0069] In specific implementation, in the chip testing method provided in the embodiments of the present invention, step S103 generates statistical test results of the chip, which may specifically include: creating a format string, writing the number of tested chips AN, the number of passes PN, the number of first anomalies FE, and the number of probability anomalies DE into the format string according to a set format; using each element in the probability anomaly time statistics array DT[] to index the shutdown time array CT[], and converting it into a string to write into the format string; and writing the finally obtained format string into a statistics file.

[0070] The above process describes the writing statistics document state of the finite state automaton. Specifically, after transitioning from the waiting operation state to the writing statistics document state, the finite state automaton will perform the writing statistics document operation. A format string is created, and the number of tested chips AN, the pass count PN, the first anomaly count FE, and the probability anomaly count DE are written to the string according to the set format. A loop is created, using each element in the probability anomaly time statistics array DT[] to index the shutdown time array CT[], and converting it into a string to be written to the format string just created. The statistics file handle SH is called, setting the statistics file handle SH to the end of the file, and then the final format string is written to the statistics file, and the output file handle is written to the statistics file handle.

[0071] The above describes the complete functions of the seven states. In actual operation, the finite state automaton jumps between these seven states to achieve functions such as cyclic testing, chip status statistics, system monitoring, and outputting statistical files.

[0072] Furthermore, in specific implementations, the chip testing method provided in the embodiments of the present invention may further include: controlling the front panel to display the chip status and statistical test results in real time.

[0073] In practical applications, the front panel serves as the user interface in a LabVIEW virtual instrument. LabVIEW is a graphical programming software used to design virtual instruments, facilitating modification, copying, and distribution. The entire program can be designed using LabVIEW graphical programming, including the front panel interface, such as... Figure 4 As shown, the interface provides a section for designing test parameters and a section for real-time display of chip status and statistical analysis of test results. Simply clicking the confirmation button completes the chip testing and writes the results to the statistical file. This user-friendly interface allows for real-time reading of the chip status under test, statistical results of tested chips, and the system's operating status. It is simple to operate, with test parameters displayed on the front panel, allowing for custom design and flexible adjustment of test parameters, increasing the versatility of test solutions, and also enabling system fault detection.

[0074] Specifically, the front panel may have the following controls: controls for connecting relays and files, controls for setting test parameters, controls for displaying test status, controls for displaying statistical results, and controls for switching operation statuses. Among these, the controls for connecting relays include the VISA resource name; the controls for connecting files include log file path input controls and statistics file path input controls; the controls for setting test parameters include start time value input controls and stop time value input array controls; the controls for displaying test statuses include continuous test indicator lights, system fault indicator lights, exception flag indicator lights, and chip test result enumeration controls; the controls for displaying statistical results include the number of chips tested, the number of passes, the number of first-time exceptions, the number of probabilistic exceptions, the number of cycles, and a probabilistic exception time statistics array; and the controls for switching operation statuses include a new test button, a result statistics button, and an initialization button.

[0075] From the front panel, the program operates as follows: The VISA resource name is connected to the relay port, the log file path input control is connected to the log file, and the statistics file path input control is connected to the statistics file. Upon program startup, the system enters an initialization state, successfully connecting the relay and file, and resetting all controls displaying statistical results to zero. The system then enters a waiting state. After installing the test chip, clicking the "Add Test" button initiates a new sample state, resetting the loop count to zero, and turning off the sample error indicator and system fault indicator. The system then enters a single test state. After the relay completes one switching action, the system enters a log reading state. In the log reading state, the loop count is incremented. If the previous test passed and the loop count is less than the set dimension of the shutdown time array, the continuous test indicator lights up, and the system returns to the single test state. If the previous test resulted in an error, the error indicator lights up. If the previous test resulted in an error or the loop count exceeds the dimension of the shutdown time array, the continuous test indicator turns off, and the system enters the result statistics state. If no test passed or an error was detected, the system fault indicator lights up, the continuous test indicator turns off, and the system enters a waiting test state. In the results statistics state, the number of tested chips is incremented by one. The system will determine whether the chip passed the test, experienced an initial failure, or had a probabilistic failure based on whether the anomaly indicator light is illuminated and the number of cycles, and will increment the corresponding number accordingly. If a probabilistic failure exists, the system will also record the location of the probabilistic failure. The system then enters a waiting state. In the waiting state, if the results statistics button is pressed, the system will enter the write statistics file state, appending the statistics results to the end of the statistics file before entering the waiting state again. If the initialization button is pressed in the waiting state, the system will re-initialize.

[0076] It should be added that the relay-based continuously adjustable digital switch solution used in this invention is not only suitable for chip testing, but also for other applications requiring repeated precise switching. The finite state automaton design makes the program suitable not only for power-on anomaly testing, but also for testing other probabilistic events.

[0077] Based on the same inventive concept, this invention also provides a chip testing system. Since the principle of this system in solving the problem is similar to that of the aforementioned chip testing method, the implementation of this system can refer to the implementation of the chip testing method, and the repeated parts will not be described again.

[0078] In specific implementation, the chip testing system provided in this embodiment of the invention, such as... Figure 5 As shown, it specifically includes:

[0079] Control switch module 1 is used to control the relay to turn on or off, so as to adjust the power-on and power-off time of the chip multiple times; the relay is electrically connected to the toggle switch of the chip test board; the toggle switch is normally open during the test.

[0080] Log reading module 2 is used to read the test log of the chip each time it is powered on in real time, and obtain the chip status during the test based on the test log reading results to determine whether to continue the test;

[0081] Result statistics module 3 is used to generate statistical test results for the chip when the log reading module determines that testing should not continue.

[0082] In the chip testing system provided in this embodiment of the invention, the interaction of the three modules can simplify the testing steps, improve the accuracy of the test results, and eliminate the need for testers to constantly choose whether to continue testing based on the test log, or to manually record the test results after each test. This reduces the burden on testers, improves the accuracy of statistical results, and thus greatly improves the efficiency and quality of testing.

[0083] In a specific implementation, in the chip testing system provided in the embodiments of the present invention, the control switch module 1 can be used to send an on command to the relay to control the relay to turn on; after waiting for the on time corresponding to the on command, a off command is sent to the relay to control the relay to turn off, and after turning off, wait for a set time; the operation of sending on command and off command to the relay is executed cyclically.

[0084] In a specific implementation, the chip testing system provided in the embodiments of the present invention may further include: an initialization module, used to set the parameter to be counted to zero, open the log file and the statistics file, and output the log file handle LH and the statistics file handle SH.

[0085] In a specific implementation, in the chip testing system provided in the embodiments of the present invention, the log reading module 2 may specifically include:

[0086] The log judgment unit is used to determine whether the test log contains a passage indicating that the test passed or a passage indicating that the test failed, and to obtain the judgment result of reading the log.

[0087] The loop count determination unit is used to determine whether the loop count is greater than the set number of loops and obtain the result of the loop count determination.

[0088] The status acquisition unit is used to obtain the chip status during the test based on the log reading and the judgment result of the loop count, so as to determine whether to continue the test; at the same time, it selects to light up the continuous test indicator, the abnormality indicator, or the system fault indicator; if the abnormality indicator is lit, it determines whether the chip is experiencing an abnormality on the first power-on; if so, it updates the first abnormality count; if not, it updates the probability abnormality count and writes the loop count to the probability abnormality time statistics array; if the abnormality indicator is not lit, it determines that the chip test has passed and updates the pass count.

[0089] In specific implementation, in the chip testing system provided in the embodiments of the present invention, the result statistics module 3 may specifically include:

[0090] The string creation unit is used to create a formatted string, which writes the number of tested pieces AN, the number of passes PN, the number of first anomalies FE, and the number of probability anomalies DE into the formatted string according to the set format.

[0091] The file writing unit is used to index the shutdown time array CT[] using each element in the probability anomaly time statistics array DT[], convert it into a string and write it into a format string; the final format string is then written to the statistics file.

[0092] In specific implementation, the chip testing system provided in the embodiments of the present invention may further include: an information display module, used to control the front panel to display the chip status and statistical test results in real time.

[0093] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0094] Accordingly, this invention also discloses a chip testing device, including a processor and a memory; wherein, when the processor executes a computer program stored in the memory, it implements the chip testing method disclosed in the foregoing embodiments.

[0095] For more detailed information on the above methods, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0096] Furthermore, the present invention also discloses a computer-readable storage medium for storing a computer program; when the computer program is executed by a processor, it implements the aforementioned disclosed chip testing method.

[0097] For more detailed information on the above methods, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0098] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems, devices, and storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0099] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0100] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0101] In summary, the chip testing method provided by this invention includes: controlling the opening and closing of a relay to repeatedly adjust the power-on and power-off times of the chip; the relay is electrically connected to a toggle switch on the chip test board; the toggle switch is normally open during the test; real-time reading of the test log for each power-on of the chip; obtaining the chip status during the test based on the results of the test log reading to determine whether to continue the test; if not, generating statistical test results for the chip. The above chip testing method uses a relay to eliminate the need for manual switching, greatly simplifying the testing steps; controlling the opening and closing of the relay significantly improves the accuracy of the test results, eliminating interference from the tester's manual methods; real-time log reading accurately determines the chip's status during the test, deciding whether to continue testing or collect statistical results. If an anomaly is detected, the subsequent test can be immediately stopped, and statistical test results for the chip can be generated. This eliminates the need for testers to manually select whether to continue testing based on the test log or to manually record test results after each test, reducing the burden on testers, improving the accuracy of statistical results, and thus greatly improving testing efficiency and quality. Furthermore, the present invention also provides a corresponding system, device, and computer-readable storage medium for chip testing methods, further making the above methods more practical. The system, device, and computer-readable storage medium have corresponding advantages.

[0102] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0103] The chip testing method, system, equipment, and storage medium provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A chip testing method, characterized in that, include: Set the parameters to be counted to zero, open the log file and statistics file, and output the log file handle and statistics file handle; the parameters to be counted include the number of tested chips, the number of passes, the number of first anomalies, the number of probability anomalies, and the probability anomaly time statistics array; Send an on command to the relay to control the relay to turn on; after waiting for the on time corresponding to the on command, send an off command to the relay to control the relay to turn off, and wait for a set time after turning off; The operation of sending the start command and the stop command to the relay is executed cyclically. In a single test state, it is executed in four steps in sequence: first, a start command is sent to the relay; second, wait for a set start time; third, a stop command is sent to the relay; and fourth, the stop time array is indexed using the number of loops, and the wait time is based on the index time, which increases with the number of loops. The common terminal and normally open terminal of the relay are connected to a toggle switch on the chip test board. The toggle switch is normally open during the test. The test logs of the chip are read in real time each time it is powered on; a chip passing the test means that multiple consecutive power-on and power-off tests with different waiting times have passed, and a test log will be generated each time it is powered on. Determine whether the test log contains paragraphs indicating that the test passed or paragraphs indicating that the test failed, and obtain the result of reading the log; Determine if the number of iterations exceeds a set number, and obtain the result of the iteration count. Based on the reading logs and the results of the loop count, the chip status during the test is obtained to determine whether to continue the test; While acquiring the chip status during the test, select to light up the continuous test indicator, the abnormality indicator, or the system fault indicator; if the abnormality indicator is lit, determine whether the chip is experiencing an initial power-on abnormality; if yes, update the initial abnormality count; if no, update the probability abnormality count and write the loop count into the probability abnormality time statistics array; if the abnormality indicator is not lit, determine that the chip has passed the test and update the pass count. If no further testing is required, create a format string and write the number of tested chips, the number of passes, the number of first anomalies, and the number of probability anomalies into the format string according to the set format. The shutdown time array is indexed using each element in the probability anomaly time statistics array and converted into a string, which is then written into the formatted string. The final formatted string is written into the statistics file to generate the statistical test results for the chip.

2. The chip testing method according to claim 1, characterized in that, Also includes: The control panel displays the chip status and statistical test results in real time.

3. A chip testing system, characterized in that, include: The initialization module is used to set the parameters to be counted to zero, open the log file and the statistics file, and output the handles of the log file and the statistics file; the parameters to be counted include the number of tested chips, the number of passes, the number of first anomalies, the number of probability anomalies, and the probability anomaly time statistics array; The control switch module is used to send an on command to the relay to control the relay to turn on; after waiting for the on time corresponding to the on command, it sends an off command to the relay to control the relay to turn off, and then waits for a set time after turning off; the operation of sending the on command and the off command to the relay is repeated cyclically; in a single test state, it is executed in four steps in sequence: first, an on command is sent to the relay; second, it waits for the set on time; third, an off command is sent to the relay; fourth, the off time array is indexed using the number of loops, and the waiting time is based on the indexed time, which increases with the number of loops; the common terminal and normally open terminal of the relay are connected to a toggle switch on the chip test board; the toggle switch is normally open during the test; The log reading module is used to read the test logs of the chip each time it is powered on in real time. A chip passing test means that multiple consecutive power-on and power-off tests with different waiting times have passed. Test logs will be generated each time the chip is powered on. The chip status during the test is obtained based on the results read from the test log to determine whether to continue the test; The log reading module includes: a log judgment unit, used to judge whether the test log contains a passage indicating a successful test or a passage indicating a failed test, and obtain a judgment result for reading the log; a count judgment unit, used to judge whether the number of loops is greater than a set number, and obtain a judgment result for the number of loops; and a status acquisition unit, used to acquire the chip status during the test based on the reading log and the judgment result for the number of loops, in order to determine whether to continue the test; while acquiring the chip status during the test, it selects to light up a continuous test indicator, an abnormality indicator, or a system fault indicator; if the abnormality indicator is lit, it is determined whether the chip is experiencing an initial power-on abnormality; if so, the initial abnormality count is updated; if not, the probability abnormality count is updated, and the number of loops is written into the probability abnormality time statistics array; if the abnormality indicator is not lit, the chip test is determined to be successful, and the success count is updated; The result statistics module is used to generate statistical test results for the chip when the log reading module determines that further testing is unnecessary. The result statistics module includes: a string creation unit, used to create a formatted string and write the number of tested chips, the number of passes, the number of first anomalies, and the number of probability anomalies into the formatted string according to a set format; a file writing unit, used to index the shutdown time array using each element in the probability anomaly time statistics array and convert it into a string to write into the formatted string; and finally, write the obtained formatted string into the statistics file.

4. A chip testing device, characterized in that, It includes a processor and a memory, wherein the processor implements the chip testing method as described in claim 1 or 2 when executing a computer program stored in the memory.

5. A computer-readable storage medium, characterized in that, Used to store a computer program, wherein the computer program, when executed by a processor, implements the chip testing method as described in claim 1 or 2.

Images