Current generation unit, method, optical detection module, method and display device

Abstract

The present invention provides a current generation unit, method, optical detection module, method, and display device. The current generation unit includes a bias current output terminal, a reference voltage supply circuit, a reset circuit, a current drive circuit, an output control circuit, a data writing circuit, a first energy storage circuit, and a compensation control circuit; the data writing circuit writes data voltage to the first end of the current drive circuit under the control of a writing control signal; the compensation control circuit controls the connection or disconnection between the second node and the second end of the current drive circuit under the control of the writing control signal; the current drive circuit generates a bias current flowing through the first end and the second end of the current drive circuit under the control of the potential of the second node. The present invention has a threshold voltage compensation function for a current drive transistor, and the current value of the generated bias current is independent of the threshold voltage of the current drive transistor included in the current drive circuit, and the bias current is a constant current.

Description

Technical Field

[0001] The present invention relates to the technical field of optical detection, and in particular, to a current generation unit, a method, an optical detection module, a method, and a display device. Background Art

[0002] In the existing display technology, fingerprint recognition has become a common function of intelligent devices. Integrating the fingerprint recognition technology into the display screen reduces costs and space. An optoelectronic sensor is fabricated on the display screen, and then fingerprint information is established by sensing the difference in photocurrent signals of the optoelectronic sensor at the valleys and ridges of the fingerprint through the optical path and the reflected light of the fingerprint. Since the light reflected by the fingerprint is relatively weak and due to the area limitation of the optoelectronic sensor, the photocurrents at the valleys and ridges sensed by the optoelectronic sensor are less than pA level and need to be amplified before being collected by an external circuit. Due to integration with the display screen, a current driving transistor (the current driving transistor can be a thin film transistor) is used to amplify the current generated by the optoelectronic sensor. By compensating the threshold voltage of the current driving transistor, different current driving transistors can have the same current amplification factor. During the process of compensating the threshold voltage of the current driving transistor, one method is to provide a constant bias current to the photocurrent amplification circuit to establish the bias voltage of the photocurrent amplification circuit, and at the same time write the threshold voltage into the energy storage unit. When the generation unit that provides the constant bias current to the photocurrent amplification circuit is integrated into the display screen and the constant bias current is driven by the thin film transistor in the display screen, there will be a problem that the constant bias current output by the generation unit varies with the change of the threshold voltage of the current driving transistor. Summary of the Invention

[0003] The main object of the present invention is to provide a current generation unit, a method, an optical detection module, a method, and a display device, so as to solve the problem in the prior art that when the generation unit that provides a constant bias current to the photocurrent amplification circuit is integrated into the display screen and the constant bias current is driven by the thin film transistor in the display screen, the constant bias current output by the generation unit varies with the change of the threshold voltage of the current driving transistor.

[0004] To achieve the above object, an embodiment of the present invention provides a current generation unit, including a bias current output terminal, a reference voltage providing circuit, a reset circuit, a current driving circuit, an output control circuit, a data writing circuit, a first energy storage circuit, and a compensation control circuit, wherein,

[0005] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the second node. The first energy storage circuit is used for storing electrical energy;

[0006] The reference voltage providing circuit is electrically connected to the supply voltage control line, the reference voltage terminal, and the first node respectively, and is configured to control the writing of the reference voltage provided by the reference voltage terminal to the first node under the control of the supply voltage control signal provided by the supply voltage control line;

[0007] The reset circuit is electrically connected to the reset control line, the reset voltage terminal, and the second node respectively, and is configured to write the reset voltage provided by the reset voltage terminal to the second node under the control of the reset control signal provided by the reset control line;

[0008] The data writing circuit is electrically connected to the writing control line, the data line, and the first end of the current driving circuit respectively, and is configured to write the data voltage provided by the data line to the first end of the current driving circuit under the control of the writing control signal provided by the writing control line;

[0009] The compensation control circuit is electrically connected to the writing control line, the second node, and the second end of the current driving circuit respectively, and is configured to control the connection or disconnection between the second node and the second end of the current driving circuit under the control of the writing control signal;

[0010] The output control circuit is electrically connected to the output control line, the first node, the first end of the current driving circuit, the bias current output terminal, the second end of the current driving circuit, and the first voltage terminal respectively, and is configured to control the connection or disconnection between the first node and the first end of the current driving circuit, control the connection or disconnection between the first end of the current driving circuit and the bias current output terminal, and control the connection or disconnection between the second end of the current driving circuit and the first voltage terminal under the control of the output control signal provided by the output control line;

[0011] The current driving circuit is configured to generate a bias current flowing through the first end and the second end of the current driving circuit under the control of the potential of the second node.

[0012] Optionally, the reference voltage providing circuit includes a first transistor, and the reset circuit includes a second transistor;

[0013] The control electrode of the first transistor is electrically connected to the supply voltage control line, the first electrode of the first transistor is electrically connected to the reference voltage terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0014] The control electrode of the second transistor is electrically connected to the reset control line, the first electrode of the second transistor is electrically connected to the reset voltage terminal, and the second electrode of the second transistor is electrically connected to the second node.

[0015] Optionally, the compensation control circuit includes a third transistor, and the data writing circuit includes a fourth transistor;

[0016] The control electrode of the third transistor is electrically connected to the writing control line, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the second end of the current driving circuit;

[0017] The control electrode of the fourth transistor is electrically connected to the writing control line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the first end of the current driving circuit.

[0018] Optionally, the output control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0019] The control electrode of the fifth transistor is electrically connected to the output control line, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the first end of the current driving circuit;

[0020] The control electrode of the sixth transistor is electrically connected to the output control line, the first electrode of the sixth transistor is electrically connected to the first end of the current driving circuit, and the second electrode of the sixth transistor is electrically connected to the bias current output terminal;

[0021] The control electrode of the seventh transistor is electrically connected to the output control line, the first electrode of the seventh transistor is electrically connected to the second end of the current driving circuit, and the second electrode of the seventh transistor is electrically connected to the first voltage terminal.

[0022] Optionally, the current driving circuit includes a current driving transistor, and the first energy storage circuit includes a first storage capacitor;

[0023] The control electrode of the current driving transistor is electrically connected to the control end of the current driving circuit, the first electrode of the current driving transistor is electrically connected to the first end of the current driving circuit, and the second electrode of the current driving transistor is electrically connected to the second end of the current driving circuit;

[0024] The first end of the first storage capacitor is electrically connected to the first node, and the second end of the first storage capacitor is electrically connected to the second node.

[0025] The present invention also provides a current generation method, which is applied to the above current generation unit. The current generation cycle includes a reset stage, a data voltage writing stage, and a current output stage arranged in sequence; the current generation method includes:

[0026] In the reset stage, under the control of a supply voltage control signal, a reference voltage providing circuit writes a reference voltage to a first node, and a reset circuit writes a reset voltage to a second node under the control of a reset control signal, so that at the start of the data writing stage, a current driving circuit can be controlled by the potential of the second node to connect between a first end and a second end of the current driving circuit;

[0027] In the data writing stage, a data line provides a data voltage, the reference voltage providing circuit writes a reference voltage to the first node under the control of the supply voltage control signal, a data writing circuit writes the data voltage to a first end of the current driving circuit under the control of a writing control signal, and a compensation control circuit controls connection between the second node and the second end of the current driving circuit under the control of the writing control signal;

[0028] At the start of the data writing stage, the current driving circuit is controlled by the potential of the second node to connect between the first end and the second end of the current driving circuit, so as to charge a first energy storage circuit with the data voltage and change the potential of the second node until the current driving circuit disconnects the connection between its first end and its second end. At this time, the potential of the second node becomes Vdata - Vth, where Vth is the absolute value of the threshold voltage of a current driving transistor included in the current driving circuit;

[0029] In the current output stage, an output control circuit controls connection between the second end of the current driving circuit and a first voltage terminal, controls connection between the first node and the first end of the current driving circuit, and controls connection between the first end of the current driving circuit and a bias current output terminal under the control of an output control signal. The current driving circuit generates a bias current to output the bias current through the bias current output terminal.

[0030] Optionally, the current generation method according to at least one embodiment of the present invention further includes:

[0031] In the reset stage and the data writing stage, the output control circuit controls disconnection between the first node and the first end of the current driving circuit, controls disconnection between the first end of the current driving circuit and the bias current output terminal, and controls disconnection between the second end of the current driving circuit and the first voltage terminal under the control of the output control signal.

[0032] The present invention further provides an optical detection module, including the above-mentioned current generation unit.

[0033] Optionally, the optical detection module described in the embodiments of the present invention further includes an optical detection unit; the bias current output terminal of the current generation unit is electrically connected to the detection line;

[0034] The optical detection unit includes a photosensitive circuit, a second energy storage circuit, a transmission control circuit, and a driving circuit;

[0035] The photosensitive circuit is used to sense an optical signal and convert the optical signal into a corresponding photocurrent signal, and output the photocurrent signal through the photocurrent output terminal;

[0036] The second energy storage circuit is electrically connected to the control terminal of the driving circuit and is used to store electrical energy;

[0037] The control terminal of the driving circuit is electrically connected to the photocurrent output terminal, and the first terminal of the driving circuit is electrically connected to the second voltage terminal;

[0038] The transmission control circuit is respectively electrically connected to the scan line, the transmission control line, the control terminal of the driving circuit, the second terminal of the driving circuit, and the detection line, and is used to control the connection or disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scan signal provided by the scan line, and control the connection or disconnection between the second terminal of the driving circuit and the detection line under the control of the transmission control signal provided by the transmission control line;

[0039] The driving circuit is used to generate a photocurrent flowing through the first terminal and the second terminal of the driving circuit under the control of the potential of its control terminal.

[0040] Optionally, the optical detection module described in the embodiments of the present invention may further include a detection circuit;

[0041] The detection circuit is electrically connected to the detection line, and is used to receive the photocurrent from the detection line and obtain the characteristics of the optical signal according to the photocurrent when the transmission control circuit controls the connection between the second terminal of the driving circuit and the detection line under the control of the transmission control signal and controls the disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scan signal.

[0042] Optionally, the transmission control circuit includes a first control transistor and a second control transistor;

[0043] The control electrode of the first control transistor is electrically connected to the transmission control line, the first electrode of the first control transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the first control transistor is electrically connected to the detection line;

[0044] The control electrode of the second control transistor is electrically connected to the scanning line, the first electrode of the second control transistor is electrically connected to the control terminal of the driving circuit, and the second electrode of the second control transistor is electrically connected to the second terminal of the driving circuit.

[0045] Optionally, the second energy storage circuit includes a second storage capacitor, the driving circuit includes a driving transistor, and the photosensitive circuit includes a photodiode;

[0046] The first terminal of the second storage capacitor is electrically connected to the control electrode of the driving transistor, and the second terminal of the second storage capacitor is electrically connected to the second voltage terminal;

[0047] The first electrode of the driving transistor is electrically connected to the second voltage terminal, and the second electrode of the driving transistor is electrically connected to the second terminal of the driving circuit;

[0048] The anode of the photodiode is electrically connected to the control electrode of the driving transistor, and the cathode of the photodiode is electrically connected to the second voltage terminal.

[0049] The present invention also provides a light detection method, which is applied to the above-mentioned light detection module, and the detection period includes a current output stage, a current integration stage, and a collection stage arranged in sequence; the light detection method includes:

[0050] In the current output stage, the current generation unit outputs a bias current to the detection line through the bias current output terminal; under the control of the scanning signal, the transmission control circuit controls the connection between the control terminal and the second terminal of the driving circuit, and under the control of the transmission control signal, controls the connection between the second terminal of the driving circuit and the detection line;

[0051] In the current integration stage, under the control of the scanning signal, the transmission control circuit controls the disconnection between the control terminal and the second terminal of the driving circuit, and under the control of the transmission control signal, controls the disconnection between the second terminal of the driving circuit and the detection line. The photosensitive circuit senses the optical signal and converts the optical signal into a corresponding photocurrent signal, and outputs the photocurrent signal through the photocurrent output terminal to charge or discharge the second energy storage circuit, thereby changing the potential of the control terminal of the driving circuit;

[0052] In the collection stage, the driving circuit is used to generate a light detection current under the control of the potential of its control terminal. Under the control of the scanning signal, the transmission control circuit controls the disconnection between the control terminal and the second terminal of the driving circuit, and under the control of the transmission control signal, controls the connection between the second terminal of the driving circuit and the detection line to provide the light detection current to the detection line.

[0053] The present invention also provides a display device, including the above-mentioned light detection module.

[0054] Optionally, the optical detection module includes an optical detection array, a plurality of current generation units, multiple columns of detection lines, and a detection integrated circuit; the optical detection module is disposed on a substrate; the optical detection array includes a plurality of rows and columns of optical detection units;

[0055] The detection integrated circuit is electrically connected to the multiple columns of detection lines, for receiving the optical detection current from the detection lines, and obtaining the characteristics of the optical signal according to the optical detection current;

[0056] The optical detection units in the same column are electrically connected to the detection lines in the same column; the optical detection units are configured to convert the received optical signal into an optical detection current, and provide the optical detection current to the corresponding column of detection lines;

[0057] The current generation unit is electrically connected to the corresponding column of detection lines, for providing a corresponding bias voltage to the corresponding column of detection lines;

[0058] The detection integrated circuit is disposed on the first side of the substrate;

[0059] The current generation unit is disposed between the detection integrated circuit and the optical detection array; or, the current generation unit is disposed on the second side of the substrate, and the first side and the second side are opposite sides.

[0060] Optionally, the display device according to at least one embodiment of the present invention further includes a driving circuit;

[0061] The driving circuit is configured to provide a scanning signal and a transmission control signal to the optical detection units;

[0062] The detection integrated circuit is further configured to provide a clock signal and a scanning start signal to the driving circuit;

[0063] The driving circuit is disposed on the third side and / or the fourth side of the substrate.

[0064] The current generation unit, method, optical detection module, method, and display device according to the embodiments of the present invention can conveniently generate a bias current, the bias current is a constant current, and the current value of the bias current is independent of the threshold voltage of the current driving transistor included in the current driving circuit. Description of the Drawings

[0065] Figure 1 is a structural diagram of the current generation unit according to the embodiment of the present invention;

[0066] Figure 2 is a circuit diagram of the current generation unit according to at least one embodiment of the present invention;

[0067] Figure 3 is the working timing diagram of at least one embodiment of the current generation unit shown in the present invention; Figure 2

[0068] Figure 4 is the structural diagram of the optical detection module according to at least one embodiment of the present invention;

[0069] Figure 5 is the structural diagram of the optical detection module according to at least one embodiment of the present invention;

[0070] Figure 6 is the circuit diagram of the optical detection module according to at least one embodiment of the present invention;

[0071] Figure 7 is the circuit diagram of the optical detection module according to at least one embodiment of the present invention;

[0072] Figure 8 is as described in the present invention Figure 7 the working timing diagram of the optical detection module shown;

[0073] Figure 9 is the structural diagram of the display device according to at least one embodiment of the present invention. Detailed implementation manners

[0074] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0075] The transistors used in all embodiments of the present invention can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two poles of the transistor other than the control pole, one pole is called the first pole and the other pole is called the second pole.

[0076] During actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be the drain and the second pole can be the source; or, the first pole can be the source and the second pole can be the drain.

[0077] As Figure 1 shown, the current generation unit described in the embodiments of the present invention includes a bias current output terminal O1, a reference voltage providing circuit 11, a reset circuit 12, a current driving circuit 13, an output control circuit 14, a data writing circuit 15, a first energy storage circuit 16 and a compensation control circuit 17, where

[0078] ​The first end of the first energy storage circuit 16 is electrically connected to the first node A, and the second end of the first energy storage circuit 16 is electrically connected to the second node B. The first energy storage circuit 16 is used for storing electrical energy;

[0079] The reference voltage providing circuit 11 is respectively electrically connected to the supply voltage control line ID, the reference voltage terminal Vr1, and the first node A, and is used for controlling to write the reference voltage Vref provided by the reference voltage terminal Vr1 into the first node A under the control of the supply voltage control signal provided by the supply voltage control line ID;

[0080] The reset circuit 12 is respectively electrically connected to the reset control line IR, the reset voltage terminal Vr2, and the second node B, and is used for writing the reset voltage Vini provided by the reset voltage terminal Vr2 into the second node B under the control of the reset control signal provided by the reset control line TR;

[0081] The data writing circuit 15 is respectively electrically connected to the writing control line IG, the data line Data, and the first end of the current driving circuit 13, and is used for writing the data voltage Vdata provided by the data line Data into the first end of the current driving circuit 13 under the control of the writing control signal provided by the writing control line IG;

[0082] The compensation control circuit 17 is respectively electrically connected to the writing control line IG, the second node B, and the second end of the current driving circuit 13, and is used for controlling the connection or disconnection between the second node B and the second end of the current driving circuit 13 under the control of the writing control signal;

[0083] The output control circuit 14 is respectively electrically connected to the output control line Kbias, the first node A, the first end of the current driving circuit 13, the bias current output terminal O1, the second end of the current driving circuit 13, and the first voltage terminal V1, and is used for controlling the connection or disconnection between the first node A and the first end of the current driving circuit 13, controlling the connection or disconnection between the first end of the current driving circuit 13 and the bias current output terminal O1, and controlling the connection or disconnection between the second end of the current driving circuit 13 and the first voltage terminal V1 under the control of the output control signal provided by the output control line Kbias;

[0084] The current driving circuit 13 is used for generating a bias current Ibias flowing through the first end and the second end of the current driving circuit 13 under the control of the potential of the second node B.

[0085] In at least one embodiment of the present invention, the first voltage terminal V1 can be a ground terminal or a low voltage terminal, but is not limited thereto.

[0086] The bias current Ibias can be conveniently generated by the current generation unit according to the embodiment of the present invention. The bias current Ibias is a constant current, and the current value of Ibias is independent of the threshold voltage of the current driving transistor included in the current driving circuit 13, which can ensure the constant current consistency among multiple channels.

[0087] The current generation unit according to the embodiment of the present invention can be integrated on the display panel, can compensate for the threshold voltage of the current driving transistor, and can solve the problem of the difference in the constant bias current among different channels caused by the change of the threshold voltage of the current driving transistor.

[0088] In at least one embodiment of the present invention, the constant bias current can be driven by a thin film transistor in the display panel;

[0089] That the bias current can be driven by a thin film transistor in the display panel means that: the bias current can be generated by the current driving transistor integrated in the display panel, and the current driving transistor can be a thin film transistor.

[0090] In at least one embodiment of the present invention, the channel can be Figure 9 the first column detection line SL1 to the Nth column detection line SLN in

[0091] When the current generation unit according to the present invention is as Figure 1 shown in operation, the current generation cycle can include a reset stage, a data voltage writing stage, and a current output stage set successively;

[0092] In the reset stage, under the control of the supply voltage control signal, the reference voltage providing circuit 11 writes the reference voltage Vref to the first node A, and under the control of the reset control signal, the reset circuit 12 writes the reset voltage Vini to the second node B, so as to reset the potential of the first end of the first energy storage circuit 16 to the reference voltage Vref, and reset the potential of the second end of the second energy storage circuit 16 to the reset circuit Vini, so as to reset the voltage across the first energy storage circuit 16 to the same level; the setting of the reset voltage Vini needs to satisfy that at the start of the data writing stage, the current driving circuit 13 can be controlled by the potential of the second node B to connect the first end and the second end of the current driving circuit 13;

[0093] In the data writing stage, the data line Data provides a data voltage Vdata. The reference voltage providing circuit 11 writes a reference voltage Vref to the first node A under the control of a voltage supply control signal. The data writing circuit 15 writes the data voltage Vdata to the first end of the current driving circuit 13 under the control of a writing control signal. The compensation control circuit 17 controls the connection between the second node B and the second end of the current driving circuit 13 under the control of the writing control signal.

[0094] At the beginning of the data writing stage, the current driving circuit 13 controls the connection between the first end and the second end of the current driving circuit 13 under the control of the potential of the second node B, so as to charge the first energy storage circuit 16 with the data voltage Vdata, change the potential of the second node B until the current driving circuit 13 disconnects the connection between its first end and the second end. At this time, the potential of the second node B becomes Vdata - Vth, where Vth is the threshold voltage of the current driving transistor included in the current driving circuit 13; the voltage across the first energy storage circuit 16 (the voltage across the first energy storage circuit 16 can be the difference between the potential of the first end and the potential of the second end of the first energy storage circuit 16) is Vref - (Vdata - Vth).

[0095] In the current output stage, the output control circuit 14 controls the connection between the second end of the current driving circuit 13 and the first voltage terminal V1, controls the connection between the first node A and the first end of the current driving circuit 13, and controls the connection between the first end of the current driving circuit 13 and the bias current output terminal O1 under the control of an output control signal. The current driving circuit 13 generates a bias current Ibias to output the bias current Ibias through the bias current output terminal O1.

[0096] In the reset stage and the data writing stage, the output control circuit 14 controls the disconnection between the first node A and the first end of the current driving circuit 13, controls the disconnection between the first end of the current driving circuit 13 and the bias current output terminal O1, and controls the disconnection between the second end of the current driving circuit 13 and the first voltage terminal under the control of an output control signal.

[0097] In at least one embodiment of the present invention, in the current output stage, the current driving circuit 13 generates the bias current Ibias under the action of the voltage (this voltage is Vref - (Vdata - Vth)) stored in the first energy storage circuit 16.

[0098] In Figure 1In at least one embodiment of the current generation unit shown, the current driving circuit 13 may include a current driving transistor. When at least one embodiment of the current generation unit is operating,

[0099] At the start of the data writing phase, since a reset voltage Vini is written to the second node B during the reset phase, when Vini is less than Vdata - Vth, the current driving transistor is turned on, and the data voltage Vdata charges the first energy storage circuit 16 through the current driving transistor, causing the potential of the second node B to rise from Vini. When the potential of the second node B rises to Vdata - Vth, the current driving transistor is turned off. At this time, the potential of the second node B is Vdata - Vth, and the voltage across the first energy storage circuit 16 is Vref - Vdata + Vth;

[0100] During the current output phase,

[0101] where Vgs is the gate - source voltage of the current driving transistor, μ is the electron mobility rate, C OX is the gate oxide capacitance per unit area of the current driving transistor, is the aspect ratio of the current driving transistor; it can be seen from the calculation formula of Ibias that Ibias is independent of the threshold voltage of the current driving transistor.

[0102] Optionally, the reference voltage providing circuit includes a first transistor, and the reset circuit includes a second transistor;

[0103] The control electrode of the first transistor is electrically connected to the supply voltage control line, the first electrode of the first transistor is electrically connected to the reference voltage terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0104] The control electrode of the second transistor is electrically connected to the reset control line, the first electrode of the second transistor is electrically connected to the reset voltage terminal, and the second electrode of the second transistor is electrically connected to the second node.

[0105] Optionally, the compensation control circuit includes a third transistor, and the data writing circuit includes a fourth transistor;

[0106] The control electrode of the third transistor is electrically connected to the writing control line, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the second end of the current driving circuit;

[0107] The control electrode of the fourth transistor is electrically connected to the write control line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the first end of the current driving circuit.

[0108] Optionally, the output control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0109] The control electrode of the fifth transistor is electrically connected to the output control line, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the first end of the current driving circuit;

[0110] The control electrode of the sixth transistor is electrically connected to the output control line, the first electrode of the sixth transistor is electrically connected to the first end of the current driving circuit, and the second electrode of the sixth transistor is electrically connected to the bias current output terminal;

[0111] The control electrode of the seventh transistor is electrically connected to the output control line, the first electrode of the seventh transistor is electrically connected to the second end of the current driving circuit, and the second electrode of the seventh transistor is electrically connected to the first voltage terminal.

[0112] Optionally, the current driving circuit includes a current driving transistor, and the first energy storage circuit includes a first storage capacitor;

[0113] The control electrode of the current driving transistor is electrically connected to the control terminal of the current driving circuit, the first electrode of the current driving transistor is electrically connected to the first end of the current driving circuit, and the second electrode of the current driving transistor is electrically connected to the second end of the current driving circuit;

[0114] The first end of the first storage capacitor is electrically connected to the first node, and the second end of the first storage capacitor is electrically connected to the second node.

[0115] As Figure 2 shown, on the basis of the embodiment of the current generation unit shown in Figure 1 shown, the reference voltage providing circuit 11 includes a first transistor T1, and the reset circuit 12 includes a second transistor T2;

[0116] The gate of the first transistor T1 is electrically connected to the supply voltage control line ID, the source of the first transistor T1 is electrically connected to the reference voltage terminal Vr1, and the drain of the first transistor T1 is electrically connected to the first node A; the reference voltage terminal Vr1 is used to provide a reference voltage Vref;

[0117] The gate of the second transistor T2 is electrically connected to the reset control line IR, the source of the second transistor T2 is electrically connected to the reset voltage terminal Vr2, and the drain of the second transistor T2 is electrically connected to the second node B; the reset voltage terminal Vr2 is used to provide a reset voltage Vini;

[0118] The compensation control circuit 17 includes a third transistor T3, and the data writing circuit 15 includes a fourth transistor T4; the current driving circuit 13 includes a current driving transistor TID;

[0119] The gate of the third transistor T3 is electrically connected to the writing control line IG, the source of the third transistor T3 is electrically connected to the second node B, and the drain of the third transistor T3 is electrically connected to the drain of the current driving transistor TID;

[0120] The gate of the fourth transistor T4 is electrically connected to the writing control line IG, the source of the fourth transistor T4 is electrically connected to the data line Data, and the drain of the fourth transistor T4 is electrically connected to the source of the current driving transistor TID;

[0121] The output control circuit 14 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7;

[0122] The gate of the fifth transistor T5 is electrically connected to the output control line Kbias, the source of the fifth transistor T5 is electrically connected to the first node A, and the drain of the fifth transistor T5 is electrically connected to the source of the current driving transistor TID;

[0123] The gate of the sixth transistor T6 is electrically connected to the output control line Kbias, the source of the sixth transistor T6 is electrically connected to the source of the current driving transistor TID, and the drain of the sixth transistor T6 is electrically connected to the bias current output terminal O1;

[0124] The gate of the seventh transistor T7 is electrically connected to the output control line Kbias, the source of the seventh transistor T7 is electrically connected to the drain of the current driving transistor TID, and the drain of the seventh transistor T7 is electrically connected to the ground terminal;

[0125] The first energy storage circuit 16 includes a first storage capacitor Cst1;

[0126] The first end of the first storage capacitor Cst1 is electrically connected to the first node A, and the second end of the first storage capacitor Cst1 is electrically connected to the second node B.

[0127] At Figure 2In at least one embodiment of the current generation unit shown, all the transistors are p-type thin film transistors, but this is not limiting.

[0128] In Figure 2 In at least one embodiment of the current generation unit shown, the reference voltage Vref and the data voltage Vdata determine the magnitude of the constant current value (the constant current value is Ibias). The reset voltage is determined according to the set Vdata and the threshold voltage of the driving transistor TID. In order to ensure that Vdata and Vth can be successfully written into the first energy storage circuit 16, Vini needs to satisfy Vini < Vdata - Vth. Generally, the voltage value of the reference voltage Vref can be about 4.6V, and the voltage value of the reset voltage Vini can be about -3V, but this is not limiting. In actual operation, the voltage values of the reference voltage Vref and the reset voltage Vini can also be other values.

[0129] As Figure 3 As shown, in the present invention Figure 2 In at least one embodiment of the current generation unit shown when working, the current generation cycle may include a reset stage S1, a data voltage writing stage S2, and a current output stage S3 set successively;

[0130] In the reset stage S1, Kbias and IG output high levels, IR and ID both output low levels, T6, T5, T7, T4, and T3 are turned off, T2 and T1 are turned on, Vref is written into the first node A, and Vini is written into the second node B, so that TID can be turned on at the start of the data voltage writing stage S2;

[0131] In the data voltage writing stage S2, Kbias and IR provide high levels, ID and IG output low levels, T5, T6, T7, and T2 are all turned off, T1, T4, and T3 are all turned on; Data provides the data voltage Vdata, and Vdata is written through T4 to the source of TID; Vini is less than Vdata - Vth, and Vth is the absolute value of the threshold voltage of the driving transistor TID;

[0132] At the start of the data voltage writing stage S2, TID is turned on, and Vdata is used to charge Cst1 through TID and T3. After a sufficient charging time until the potential of the second node B becomes Vdata - Vth, TID is turned off. At this time, the voltage across Cst1, VAB = VA - VB = Vref - Vdata + Vth; where VA is the potential of the first node A and VB is the potential of the second node B;

[0133] In the current output stage S3, Kbias provides a low level, IG, ID, and TG provide high levels, T5, T6, and T7 are turned on, and T2, T1, T4, and T3 are all turned on. The voltage across Cst1 is applied to the gate-source terminal of TID. The gate-source voltage of TID = VBA = VB - VA = Vdata - Vref - Vth. Then the output current of TID is the bias current Ibias. where μ is the electron migration rate, C OX is the gate oxide capacitance per unit area of TID, is the width-to-length ratio of TID; by adjusting Vdata and Vref, the corresponding bias current Ibias can be obtained. The bias current Ibias can be a constant current and is independent of the absolute value Vth of the threshold voltage of TID.

[0134] The current generation method described in the embodiments of the present invention is applied to the above current generation unit. The current generation cycle includes a reset stage, a data voltage writing stage, and a current output stage arranged in sequence; the current generation method includes:

[0135] In the reset stage, the reference voltage providing circuit writes the reference voltage to the first node under the control of the voltage supply control signal, and the reset circuit writes the reset voltage to the second node under the control of the reset control signal, so that at the beginning of the data writing stage, the current driving circuit can be controlled by the potential of the second node to connect the first end and the second end of the current driving circuit;

[0136] In the data writing stage, the data line provides the data voltage. The reference voltage providing circuit writes the reference voltage to the first node under the control of the voltage supply control signal. The data writing circuit writes the data voltage to the first end of the current driving circuit under the control of the writing control signal. The compensation control circuit controls the connection between the second node and the second end of the current driving circuit under the control of the writing control signal;

[0137] At the beginning of the data writing stage, the current driving circuit is controlled by the potential of the second node to connect the first end and the second end of the current driving circuit, so as to charge the first energy storage circuit with the data voltage and change the potential of the second node until the current driving circuit disconnects the connection between its first end and the second end. At this time, the potential of the second node becomes Vdata - Vth, where Vth is the absolute value of the threshold voltage of the current driving transistor included in the current driving circuit;

[0138] During the current output phase, under the control of an output control signal, the output control circuit controls the connection between the second end of the current driving circuit and the first voltage terminal, controls the connection between the first node and the first end of the current driving circuit, and controls the connection between the first end of the current driving circuit and the bias current output terminal. The current driving circuit generates a bias current to output the bias current through the bias current output terminal.

[0139] By adopting the current generation method described in the embodiments of the present invention, a bias current Ibias can be conveniently generated. The bias current Ibias is a constant current, and the current value of Ibias is independent of the threshold voltage of the current driving transistor included in the current driving circuit 13.

[0140] The current generation method described in at least one embodiment of the present invention further includes:

[0141] During the reset phase and the data writing phase, under the control of an output control signal, the output control circuit controls the disconnection between the first node and the first end of the current driving circuit, controls the disconnection between the first end of the current driving circuit and the bias current output terminal, and controls the disconnection between the second end of the current driving circuit and the first voltage terminal.

[0142] The optical detection module described in the embodiments of the present invention includes the above-mentioned current generation unit.

[0143] As Figure 4 shown, the optical detection module described in at least one embodiment of the present invention may include a current generation unit 40 and an optical detection unit; the bias current output terminal of the current generation unit 40 is electrically connected to the detection line SL; the optical detection unit includes a photosensitive circuit 41, a second energy storage circuit 42, a transmission control circuit 43, and a driving circuit 44;

[0144] The photosensitive circuit 41 is used to sense an optical signal and convert the optical signal into a corresponding photocurrent signal, and output the photocurrent signal through a photocurrent output terminal;

[0145] The second energy storage circuit 42 is electrically connected to the control terminal of the driving circuit 44 and is used to store electrical energy;

[0146] The control terminal of the driving circuit 44 is electrically connected to the photocurrent output terminal, and the first end of the driving circuit 44 is electrically connected to the second voltage terminal V2;

[0147] The transmission control circuit 43 is electrically connected to the scan line Gn, the transmission control line Ksn, the control end of the drive circuit 44, the second end of the drive circuit 44, and the detection line SL respectively, and is configured to control the connection or disconnection between the control end and the second end of the drive circuit 44 under the control of the scan signal provided by the scan line Gn, and control the connection or disconnection between the second end of the drive circuit 44 and the detection line SL under the control of the transmission control signal provided by the transmission control line Ksn;

[0148] The drive circuit 44 is configured to generate a light detection current flowing through the first end and the second end of the drive circuit 44 under the control of the potential at its control end.

[0149] Optionally, the second voltage terminal V2 may be a high voltage terminal, but is not limited thereto.

[0150] In at least one embodiment of the present invention, the photosensitive circuit 41 may include a photosensor. For example, the photosensor may be a photodiode, but is not limited thereto.

[0151] As in the present invention Figure 4 When at least one embodiment of the light detection module shown is in operation, the detection period may include a current output stage, a current integration stage, and a collection stage set successively;

[0152] In the current output stage, the current generation unit 40 outputs a bias current Ibias to the detection line SL through the bias current output terminal; the transmission control circuit 43 controls the connection between the control end and the second end of the drive circuit 44 under the control of the scan signal, and controls the connection between the second end of the drive circuit 44 and the detection line under the control of the transmission control signal;

[0153] In the current integration stage, the transmission control circuit 43 controls the disconnection between the control end and the second end of the drive circuit 44 under the control of the scan signal, and controls the disconnection between the second end of the drive circuit 44 and the detection line SL under the control of the transmission control signal. The photosensitive circuit 41 senses the optical signal and converts the optical signal into a corresponding photocurrent signal, and outputs the photocurrent signal through the photocurrent output terminal to charge the second energy storage circuit 42, thereby changing the potential at the control end of the drive circuit 44;

[0154] In the acquisition stage, the driving circuit 44 is used to generate a photo-detection current under the control of the potential at its control terminal. The transmission control circuit 43 controls the disconnection between the control terminal of the driving circuit 44 and the second terminal of the driving circuit 44 under the control of a scanning signal, and controls the connection between the second terminal of the driving circuit 44 and the detection line SL under the control of a transmission control signal, so as to supply the photo-detection current to the detection line SL.

[0155] As Figure 5 shown, based on at least one embodiment of the photo-detection module shown in Figure 4 at least one embodiment of the photo-detection module according to the present invention may further include a detection circuit 51;

[0156] The detection circuit 51 is electrically connected to the detection line SL, and is configured to receive the photo-detection current from the detection line SL and obtain the characteristics of the optical signal according to the photo-detection current when the transmission control circuit 43 controls the connection between the second terminal of the driving circuit 44 and the detection line SL under the control of the transmission control signal and controls the disconnection between the control terminal of the driving circuit 44 and the second terminal of the driving circuit 44 under the control of a scanning signal.

[0157] Optionally, the transmission control circuit includes a first control transistor and a second control transistor;

[0158] The control electrode of the first control transistor is electrically connected to the transmission control line, the first electrode of the first control transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the first control transistor is electrically connected to the detection line;

[0159] The control electrode of the second control transistor is electrically connected to the scanning line, the first electrode of the second control transistor is electrically connected to the control terminal of the driving circuit, and the second electrode of the second control transistor is electrically connected to the second terminal of the driving circuit.

[0160] Optionally, the second energy storage circuit includes a second storage capacitor, the driving circuit includes a driving transistor, and the photosensitive circuit includes a photodiode;

[0161] The first terminal of the second storage capacitor is electrically connected to the control electrode of the driving transistor, and the second terminal of the second storage capacitor is electrically connected to the second voltage terminal;

[0162] The first electrode of the driving transistor is electrically connected to the second voltage terminal, and the second electrode of the driving transistor is electrically connected to the second terminal of the driving circuit;

[0163] The anode of the photodiode is electrically connected to the control electrode of the driving transistor, and the cathode of the photodiode is electrically connected to the second voltage terminal.

[0164] As shown Figure 6 in, based on at least one embodiment of the optical detection module shown Figure 5 in, the transmission control circuit 43 includes a first control transistor Tc1 and a second control transistor Tc2; the driving circuit 44 includes a driving transistor T0;

[0165] The gate of the first control transistor Tc1 is electrically connected to the transmission control line Ksn, the source of the first control transistor Tc1 is electrically connected to the drain of the driving transistor T0, and the drain of the first control transistor Tc1 is electrically connected to the detection line SL;

[0166] The gate of the second control transistor Tc2 is electrically connected to the scan line Sn, the source of the second control transistor Tc2 is electrically connected to the gate of the driving transistor T0, and the drain of the second control transistor Tc2 is electrically connected to the drain of the driving transistor T0;

[0167] The second energy storage circuit 42 includes a second storage capacitor Cst2, and the photosensitive circuit 41 includes a photodiode D;

[0168] The first end of the second storage capacitor Cst2 is electrically connected to the gate of the driving transistor T0, and the second end of the second storage capacitor Cst2 is electrically connected to the high voltage terminal; the high voltage terminal is used to provide a high voltage VDD;

[0169] The source of the driving transistor T0 is electrically connected to the high voltage terminal;

[0170] The anode of the photodiode D is electrically connected to the gate of the driving transistor T0, and the cathode of the photodiode D is electrically connected to the high voltage terminal.

[0171] In Figure 6 at least one embodiment of the optical detection module shown, all the transistors are p-type thin film transistors, but not limited thereto.

[0172] As shown Figure 7 in, based on at least one embodiment of the optical detection module shown Figure 6 in, the current generation unit 40 includes a bias current output terminal O1, a reference voltage providing circuit 11, a reset circuit 12, a current driving circuit 13, an output control circuit 14, a data writing circuit 15, a first energy storage circuit 16, and a compensation control circuit 17;

[0173] The reference voltage providing circuit 11 includes a first transistor T1, and the reset circuit 12 includes a second transistor T2;

[0174] The gate of the first transistor T1 is electrically connected to the supply voltage control line ID, the source of the first transistor T1 is electrically connected to the reference voltage terminal Vr1, and the drain of the first transistor T1 is electrically connected to the first node A; the reference voltage terminal Vr1 is used to provide a reference voltage Vref;

[0175] The gate of the second transistor T2 is electrically connected to the reset control line IR, the source of the second transistor T2 is electrically connected to the reset voltage terminal Vr2, and the drain of the second transistor T2 is electrically connected to the second node B; the reset voltage terminal Vr2 is used to provide a reset voltage Vini;

[0176] The compensation control circuit 17 includes a third transistor T3, and the data writing circuit 15 includes a fourth transistor T4; the current driving circuit 13 includes a current driving transistor TID;

[0177] The gate of the third transistor T3 is electrically connected to the writing control line IG, the source of the third transistor T3 is electrically connected to the second node B, and the drain of the third transistor T3 is electrically connected to the drain of the current driving transistor TID;

[0178] The gate of the fourth transistor T4 is electrically connected to the writing control line IG, the source of the fourth transistor T4 is electrically connected to the data line Data, and the drain of the fourth transistor T4 is electrically connected to the source of the current driving transistor TID;

[0179] The output control circuit 14 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7;

[0180] The gate of the fifth transistor T5 is electrically connected to the output control line Kbias, the source of the fifth transistor T5 is electrically connected to the first node A, and the drain of the fifth transistor T5 is electrically connected to the source of the current driving transistor TID;

[0181] The gate of the sixth transistor T6 is electrically connected to the output control line Kbias, the source of the sixth transistor T6 is electrically connected to the source of the current driving transistor TID, and the drain of the sixth transistor T6 is electrically connected to the bias current output terminal O1; the bias current output terminal O1 is electrically connected to the detection line SL;

[0182] The gate of the seventh transistor T7 is electrically connected to the output control line Kbias, the source of the seventh transistor T7 is electrically connected to the drain of the current driving transistor TID, and the drain of the seventh transistor T7 is electrically connected to the ground terminal;

[0183] The first energy storage circuit 16 includes a first storage capacitor Cst1;

[0184] The first end of the first storage capacitor Cst1 is electrically connected to the first node A, and the second end of the first storage capacitor Cst1 is electrically connected to the second node B.

[0185] In Figure 7 In at least one embodiment of the illustrated optical detection module, all the transistors are p-type thin film transistors, but this is not a limitation.

[0186] In Figure 7 In at least one embodiment of the illustrated optical detection module, T0, Tc2, and Cst2 can form a photocurrent amplification circuit for amplifying the photocurrent generated by the photodiode D.

[0187] As Figure 8 As shown, when at least one embodiment of the optical detection module of the present invention as Figure 7 shown operates,

[0188] In the reset stage S1, Kbias and IG output high levels, IR and ID both output low levels, T6, T5, T7, T4, and T3 are turned off, T2 and T1 are turned on, Vref is written to the first node A, and Vini is written to the second node B so that TID can be turned on at the start of the data voltage writing stage S2;

[0189] In the data voltage writing stage S2, Kbias and IR provide high levels, ID and IG output low levels, T5, T6, T7, and T2 are all turned off, T1, T4, and T3 are all turned on; Data provides the data voltage Vdata, and Vdata is written to the source of TID through T4; Vini is less than Vdata - Vth, where Vth is the absolute value of the threshold voltage of TID;

[0190] At the start of the data voltage writing stage S2, TID is turned on, and Vdata is used to charge Cst1 through TID and T3. After a sufficient charging time, until the potential of the second node B becomes Vdata - Vth, TID is turned off. At this time, the voltage VAB across Cst1 = VA - VB = Vref - Vdata + Vth; where VA is the potential of the first node A and VB is the potential of the second node B;

[0191] In the reset stage S1 and the data voltage writing stage S2, Ksn and Gn both output high levels, and Tc1 and Tc2 are both turned off;

[0192] In the current output stage S3, Kbias provides a low level, IG, ID, and TG provide high levels, T5, T6, and T7 are turned on, and T2, T1, T4, and T3 are all turned on. The voltage across Cst1 is applied to the gate-source terminal of TID. The gate-source voltage of TID = VBA = VB - VA = Vdata - Vref - Vth. Then the output current of TID is the bias current Ibias. where μ is the electron migration rate, C OX is the gate oxide capacitance per unit area of TID, is the width-to-length ratio of TID, and Vgs is the gate-source voltage of TID; by adjusting Vdata and Vref, the corresponding bias current Ibias can be obtained. The bias current Ibias can be a constant current and is independent of the threshold voltage of TID.

[0193] In the current output stage S3, both Gn and Ksn output low levels, Tc1 and Tc2 are turned on, and Ibias is written into T0 through SL, generating a bias voltage Vbias at the gate of T0. At this time, the current flowing through T0 is equal to Ibias.

[0194] The current flowing through T0 is equal to β(VDD - Vbias - Vth2) 2 ; where β is the current transfer coefficient of T0; Vth2 is the absolute value of the threshold voltage of T0.

[0195]

[0196] In the current integration stage S4, Gn, Ksn, Kbias, IR, ID, and IG all output high levels. The photodiode D senses the optical signal and generates a corresponding photocurrent signal IRD. Cst2 is charged through IRD, and the charge ΔQcst2 injected into Cst2 = IRD × T, where T is the charging time, causing a voltage change in Cst2. The gate potential of T0 becomes Vbias’, and Vbias’ is equal to where C2z is the capacitance value of Cst2;

[0197] In the acquisition stage S5, Ksn provides a low level, and Gn, Kbias, IR, ID, and IG all output high levels. Tc1 is turned on, and the current output by T0 is the optical detection current. The optical detection current Is is output to the detection circuit 51 through the detection line SL. The detection circuit 51 can obtain the characteristics of the optical signal based on the optical detection current Is.

[0198]

[0199] where β is the current transfer coefficient of T0.

[0200] In Figure 7 In at least one embodiment of the optical detection module shown, when the anode of the photodiode D is electrically connected to the high voltage terminal and the cathode of the photodiode D is electrically connected to the gate of T0, during the current integration stage, Cst2 is discharged through the IRD.

[0201] The optical detection method according to the embodiment of the present invention is applied to the above-mentioned optical detection module, and the detection period includes a current output stage, a current integration stage, and an acquisition stage arranged in sequence; the optical detection method includes:

[0202] In the current output stage, the current generation unit outputs a bias current to the detection line through the bias current output terminal; the transmission control circuit, under the control of the scan signal, controls the connection between the control terminal and the second terminal of the drive circuit, and under the control of the transmission control signal, controls the connection between the second terminal of the drive circuit and the detection line;

[0203] In the current integration stage, the transmission control circuit, under the control of the scan signal, controls the disconnection between the control terminal and the second terminal of the drive circuit, and under the control of the transmission control signal, controls the disconnection between the second terminal of the drive circuit and the detection line. The photosensitive circuit senses the optical signal and converts the optical signal into a corresponding photocurrent signal, and outputs the photocurrent signal through the photocurrent output terminal to charge or discharge the second energy storage circuit, changing the potential of the control terminal of the drive circuit;

[0204] In the acquisition stage, the drive circuit is used to generate an optical detection current under the control of the potential of its control terminal. The transmission control circuit, under the control of the scan signal, controls the disconnection between the control terminal and the second terminal of the drive circuit, and under the control of the transmission control signal, controls the connection between the second terminal of the drive circuit and the detection line to provide the optical detection current to the detection line.

[0205] The display device according to the embodiment of the present invention includes the above-mentioned optical detection module.

[0206] In specific implementation, the optical detection module may include an optical detection array, a plurality of current generation units, multiple columns of detection lines, and a detection integrated circuit; the optical detection module is arranged on a substrate; the optical detection array includes multiple rows and multiple columns of optical detection units;

[0207] The detection integrated circuit is electrically connected to the multiple columns of detection lines, and is used for the optical detection current from the detection lines and obtaining the characteristics of the optical signal according to the optical detection current;

[0208] The light detection units in the same column are electrically connected to the detection lines in the same column; the light detection units are configured to convert the received optical signals into light detection currents and provide the light detection currents to the corresponding column detection lines;

[0209] The current generation unit is electrically connected to the corresponding column detection lines and is configured to provide corresponding bias voltages to the corresponding column detection lines;

[0210] The detection integrated circuit is disposed on the first side of the substrate;

[0211] The current generation unit is disposed between the detection integrated circuit and the light detection array; alternatively, the current generation unit is disposed on the second side of the substrate, and the first side and the second side are opposite sides.

[0212] In at least one embodiment of the present invention, the first side may be the lower side, and the second side may be the upper side, but not limited thereto.

[0213] The display device according to at least one embodiment of the present invention may further include a driving circuit;

[0214] The driving circuit is configured to provide a scanning signal and a transmission control signal to the light detection units;

[0215] The detection integrated circuit is further configured to provide a clock signal and a scanning start signal to the driving circuit;

[0216] The driving circuit is disposed on the third side and / or the fourth side of the substrate.

[0217] In specific implementation, the third side and the fourth side may be opposite sides. For example, the third side may be the left side, and the fourth side may be the right side, but not limited thereto.

[0218] Optionally, the driving circuit may be a GOA (Gate On Array, a gate driving circuit disposed on an array substrate) circuit.

[0219] As Figure 9 shown, the display device may include a plurality of rows and columns of light detection units disposed on the substrate;

[0220] In Figure 9Among them, the light detection unit labeled S11 is the first-row and first-column light detection unit, the light detection unit labeled S12 is the first-row and second-column light detection unit, the light detection unit labeled S13 is the first-row and third-column light detection unit, the light detection unit labeled S14 is the first-row and fourth-column light detection unit, the light detection unit labeled S1N-2 is the first-row and (N-2)-th column light detection unit, the light detection unit labeled S1N-1 is the first-row and (N-1)-th column light detection unit, and the light detection unit labeled S1N is the first-row and N-th column light detection unit; N is an integer greater than 6;

[0221] The light detection unit labeled S21 is the second-row and first-column light detection unit, the light detection unit labeled S22 is the second-row and second-column light detection unit, the light detection unit labeled S23 is the second-row and third-column light detection unit, the light detection unit labeled S24 is the second-row and fourth-column light detection unit, the light detection unit labeled S2N-2 is the second-row and (N-2)-th column light detection unit, the light detection unit labeled S2N-1 is the second-row and (N-1)-th column light detection unit, and the light detection unit labeled S2N is the second-row and N-th column light detection unit;

[0222] The light detection unit labeled S31 is the third-row and first-column light detection unit, the light detection unit labeled S32 is the third-row and second-column light detection unit, the light detection unit labeled S33 is the third-row and third-column light detection unit, the light detection unit labeled S34 is the third-row and fourth-column light detection unit, the light detection unit labeled S3N-2 is the third-row and (N-2)-th column light detection unit, the light detection unit labeled S3N-1 is the third-row and (N-1)-th column light detection unit, and the light detection unit labeled S3N is the third-row and N-th column light detection unit;

[0223] The light detection unit labeled S41 is the fourth-row and first-column light detection unit, the light detection unit labeled S42 is the fourth-row and second-column light detection unit, the light detection unit labeled S43 is the fourth-row and third-column light detection unit, the light detection unit labeled S44 is the fourth-row and fourth-column light detection unit, the light detection unit labeled S4N-2 is the fourth-row and (N-2)-th column light detection unit, the light detection unit labeled S4N-1 is the fourth-row and (N-1)-th column light detection unit, and the light detection unit labeled S4N is the fourth-row and N-th column light detection unit;

[0224] The light detection unit labeled SM-11 is the (M-1)-th row and first-column light detection unit, the light detection unit labeled SM-12 is the (M-1)-th row and second-column light detection unit, the light detection unit labeled SM-13 is the (M-1)-th row and third-column light detection unit, the light detection unit labeled SM-14 is the (M-1)-th row and fourth-column light detection unit, the light detection unit labeled SM-1N-2 is the (M-1)-th row and (N-2)-th column light detection unit, the light detection unit labeled SM-1N-1 is the (M-1)-th row and (N-1)-th column light detection unit, and the light detection unit labeled SM-1N is the (M-1)-th row and N-th column light detection unit; M is an integer greater than 5;

[0225] The optical detection unit labeled SM1 is the optical detection unit in the first column of the M-th row, the optical detection unit labeled SM2 is the optical detection unit in the second column of the M-th row, the optical detection unit labeled SM3 is the optical detection unit in the third column of the M-th row, the optical detection unit labeled SM4 is the optical detection unit in the fourth column of the M-th row, the optical detection unit labeled SMN-2 is the optical detection unit in the (N-2)-th column of the M-th row, the optical detection unit labeled SMN-1 is the optical detection unit in the (N-1)-th column of the M-th row, and the optical detection unit labeled SMN is the optical detection unit in the N-th column of the M-th row;

[0226] The detection line labeled SL1 is the first column detection line, the detection line labeled SL2 is the second column detection line, the detection line labeled SL3 is the third column detection line, the detection line labeled SL4 is the fourth column detection line, the detection line labeled SLN-2 is the (N-2)-th column detection line, the detection line labeled SLN-1 is the (N-1)-th column detection line, and the detection line labeled SLN is the N-th column detection line;

[0227] The optical detection units located in the first column are all electrically connected to SL1, the optical detection units located in the second column are all electrically connected to SL2, the optical detection units located in the third column are all electrically connected to SL3, the optical detection units located in the fourth column are all electrically connected to SL4, the optical detection units located in the (N-2)-th column are all electrically connected to SLN-2, the optical detection units located in the (N-1)-th column are all electrically connected to SLN-1, and the optical detection units located in the N-th column are all electrically connected to SLN;

[0228] As Figure 9 shown, the display device may include a first GOA circuit 91 and a second GOA circuit 92;

[0229] The structure of each of the optical detection units may be the same as the structure of the optical detection unit in Figure 6 . If the area of the photodiode is large enough, the second storage capacitor can utilize its junction capacitance;

[0230] The first GOA (Gate On Array, the gate driving circuit disposed on the array substrate) circuit 91 and the second GOA circuit 92 respectively provide a scanning signal and a transmission control signal for each row of optical detection units to complete amplifying the tiny leakage current of the photodiode into a detectable current through the driving transistor.

[0231] In Figure 9 at least one embodiment of the display device shown, a detection integrated circuit 90 is disposed on the lower side of the substrate. The detection integrated circuit 90 serves as the detection circuit, and at the same time, the detection integrated circuit 90 can be used to provide a clock signal CLK and a scan start signal STV for the first GOA circuit 91 and the second GOA circuit 92.

[0232] In Figure 9In at least one embodiment of the display device shown, the detection integrated circuit 90 is electrically connected to the first column detection line SL1, the second column detection line SL2, the third column detection line SL3, the fourth column detection line SL4, the (N - 2)th column detection line SLN - 2, the (N - 1)th column detection line SLN - 1, and the Nth column detection line SLN respectively, and is configured to receive the optical detection currents from the above-mentioned detection lines and obtain the characteristics of the corresponding optical signals according to the optical detection currents.

[0233] Figure 9 At least one embodiment of the display device shown may further include a first current generation unit F11, a second current generation unit F12, a third current generation unit F13, a fourth current generation unit F14, an (N - 2)th current generation unit F1N - 2, an (N - 1)th current generation unit F1N - 1, and an Nth current generation unit F1N;

[0234] The first current generation unit F11 is electrically connected to the first column detection line SL1 and is configured to provide a corresponding bias voltage for the first column detection line SL1;

[0235] The second current generation unit F12 is electrically connected to the second column detection line SL2 and is configured to provide a corresponding bias voltage for the second column detection line SL2;

[0236] The third current generation unit F13 is electrically connected to the third column detection line SL3 and is configured to provide a corresponding bias voltage for the third column detection line SL3;

[0237] The fourth current generation unit F14 is electrically connected to the fourth column detection line SL4 and is configured to provide a corresponding bias voltage for the fourth column detection line SL4;

[0238] The (N - 2)th current generation unit F1N - 2 is electrically connected to the (N - 2)th column detection line SLN - 2 and is configured to provide a corresponding bias voltage for the (N - 2)th column detection line SLN - 2;

[0239] The (N - 1)th current generation unit F1N - 1 is electrically connected to the (N - 1)th column detection line SLN - 1 and is configured to provide a corresponding bias voltage for the (N - 1)th column detection line SLN - 1;

[0240] The Nth current generation unit F1N is electrically connected to the Nth column detection line SLN and is configured to provide a corresponding bias voltage for the Nth column detection line SLN.

[0241] In Figure 9 In at least one embodiment shown, each current generation unit is disposed between the detection integrated circuit 90 and the optical detection array, and the optical detection array includes the above-mentioned multiple rows and multiple columns of optical detection units.

[0242] In at least one embodiment of the present invention, each of the current generation units may also be disposed on the opposite side of the detection integrated circuit 90, that is, each of the current generation units may be disposed above the sensing array.

[0243] In at least one embodiment of the present invention, each of the current generation units and each of the light detection units may be integrated in the display panel included in the display device according to at least one embodiment of the present invention.

[0244] In at least one embodiment of the present invention, the display device may be an OLED (organic light emitting diode) display device, but is not limited thereto; in actual operation, the display device may also be other types of display devices.

[0245] The display device provided by the embodiments of the present invention may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0246] The above are the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A current generating unit, characterized in that, It includes a bias current output terminal, a reference voltage providing circuit, a reset circuit, a current driving circuit, an output control circuit, a data writing circuit, a first energy storage circuit, and a compensation control circuit. Among them, The first end of the first energy storage circuit is electrically connected to the first node, the second end of the first energy storage circuit is electrically connected to the second node, and the first energy storage circuit is used for storing electrical energy; The reference voltage providing circuit is respectively electrically connected to the supply voltage control line, the reference voltage terminal, and the first node, and is used for controlling to write the reference voltage provided by the reference voltage terminal into the first node under the control of the supply voltage control signal provided by the supply voltage control line; The reset circuit is respectively electrically connected to the reset control line, the reset voltage terminal, and the second node, and is used for writing the reset voltage provided by the reset voltage terminal into the second node under the control of the reset control signal provided by the reset control line; The data writing circuit is respectively electrically connected to the write control line, the data line, and the first end of the current driving circuit, and is used for writing the data voltage provided by the data line into the first end of the current driving circuit under the control of the write control signal provided by the write control line; The compensation control circuit is respectively electrically connected to the write control line, the second node, and the second end of the current driving circuit, and is used for controlling the connection or disconnection between the second node and the second end of the current driving circuit under the control of the write control signal; The output control circuit is respectively electrically connected to the output control line, the first node, the first end of the current driving circuit, the bias current output terminal, the second end of the current driving circuit, and the first voltage terminal, and is used for controlling the connection or disconnection between the first node and the first end of the current driving circuit, controlling the connection or disconnection between the first end of the current driving circuit and the bias current output terminal, and controlling the connection or disconnection between the second end of the current driving circuit and the first voltage terminal under the control of the output control signal provided by the output control line; The current driving circuit is used for generating a bias current flowing through the first end and the second end of the current driving circuit under the control of the potential of the second node.

2. The current generation unit according to claim 1, wherein The reference voltage providing circuit includes a first transistor, and the reset circuit includes a second transistor; The control electrode of the first transistor is electrically connected to the supply voltage control line, the first electrode of the first transistor is electrically connected to the reference voltage terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the reset control line, the first electrode of the second transistor is electrically connected to the reset voltage terminal, and the second electrode of the second transistor is electrically connected to the second node.

3. The current generation unit according to claim 1, wherein The compensation control circuit includes a third transistor, and the data writing circuit includes a fourth transistor; The control electrode of the third transistor is electrically connected to the write control line, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the second end of the current driving circuit; The control electrode of the fourth transistor is electrically connected to the write control line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the first end of the current driving circuit.

4. The current generation unit according to claim 1, wherein The output control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; The control electrode of the fifth transistor is electrically connected to the output control line, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the first end of the current driving circuit; The control electrode of the sixth transistor is electrically connected to the output control line, the first electrode of the sixth transistor is electrically connected to the first end of the current driving circuit, and the second electrode of the sixth transistor is electrically connected to the bias current output terminal; The control electrode of the seventh transistor is electrically connected to the output control line, the first electrode of the seventh transistor is electrically connected to the second end of the current driving circuit, and the second electrode of the seventh transistor is electrically connected to the first voltage terminal.

5. The current generation unit according to claim 1, wherein The current driving circuit includes a current driving transistor, and the first energy storage circuit includes a first storage capacitor; The control electrode of the current driving transistor is electrically connected to the control terminal of the current driving circuit, the first electrode of the current driving transistor is electrically connected to the first end of the current driving circuit, and the second electrode of the current driving transistor is electrically connected to the second end of the current driving circuit; The first end of the first storage capacitor is electrically connected to the first node, and the second end of the first storage capacitor is electrically connected to the second node.

6. A current generation method, applied to the current generation unit according to any one of claims 1 to 5, characterized in that The current generation period includes a reset stage, a data voltage writing stage, and a current output stage arranged in sequence; The current generation method includes: In the reset stage, the reference voltage providing circuit writes a reference voltage to the first node under the control of the voltage supply control signal, and the reset circuit writes a reset voltage to the second node under the control of the reset control signal, so that at the start of the data writing stage, the current driving circuit can control the connection between the first end and the second end of the current driving circuit under the control of the potential of the second node; In the data writing stage, the data line provides a data voltage, the reference voltage providing circuit writes a reference voltage to the first node under the control of the voltage supply control signal, the data writing circuit writes the data voltage to the first end of the current driving circuit under the control of the writing control signal, and the compensation control circuit controls the connection between the second node and the second end of the current driving circuit under the control of the writing control signal; At the start of the data writing stage, the current driving circuit controls the connection between the first end and the second end of the current driving circuit under the control of the potential of the second node, so as to charge the first energy storage circuit with the data voltage and change the potential of the second node until the current driving circuit disconnects the connection between its first end and the second end, and at this time the potential of the second node becomes Vdata - Vth, where Vth is the absolute value of the threshold voltage of the current driving transistor included in the current driving circuit; In the current output stage, under the control of an output control signal, the output control circuit controls the connection between the second terminal of the current driving circuit and the first voltage terminal, controls the connection between the first node and the first terminal of the current driving circuit, and controls the connection between the first terminal of the current driving circuit and the bias current output terminal. The current driving circuit generates a bias current to output the bias current through the bias current output terminal.

7. The current generation method according to claim 6, characterized in that It further includes: In the reset stage and the data writing stage, under the control of the output control signal, the output control circuit controls the disconnection between the first node and the first terminal of the current driving circuit, controls the disconnection between the first terminal of the current driving circuit and the bias current output terminal, and controls the disconnection between the second terminal of the current driving circuit and the first voltage terminal.

8. An optical detection module, characterized in that, It includes the current generation unit as described in any one of claims 1 to 5.

9. The optical detection module according to claim 8, wherein, It further includes a light detection unit; the bias current output terminal of the current generation unit is electrically connected to a detection line; The light detection unit includes a photosensitive circuit, a second energy storage circuit, a transmission control circuit, and a driving circuit; The photosensitive circuit is configured to sense an optical signal and convert the optical signal into a corresponding photocurrent signal, and output the photocurrent signal through a photocurrent output terminal; The second energy storage circuit is electrically connected to the control terminal of the driving circuit and is configured to store electrical energy; The control terminal of the driving circuit is electrically connected to the photocurrent output terminal, and the first terminal of the driving circuit is electrically connected to a second voltage terminal; The transmission control circuit is electrically connected to a scanning line, a transmission control line, the control terminal of the driving circuit, the second terminal of the driving circuit, and the detection line respectively, and is configured to control the connection or disconnection between the control terminal and the second terminal of the driving circuit under the control of a scanning signal provided by the scanning line, and control the connection or disconnection between the second terminal of the driving circuit and the detection line under the control of a transmission control signal provided by the transmission control line; The driving circuit is configured to generate a light detection current flowing through the first terminal and the second terminal of the driving circuit under the control of the potential of its control terminal.

10. The optical detection module according to claim 9, characterized in that, It further includes a detection circuit; The detection circuit is electrically connected to the detection line, and is configured to receive the light detection current from the detection line and obtain the characteristics of the optical signal based on the light detection current when the transmission control circuit controls the connection between the second terminal of the driving circuit and the detection line under the control of the transmission control signal and controls the disconnection between the control terminal and the second terminal of the driving circuit under the control of a scanning signal.

11. The optical detection module according to claim 9, wherein, The transmission control circuit includes a first control transistor and a second control transistor; The control electrode of the first control transistor is electrically connected to the transmission control line, the first electrode of the first control transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the first control transistor is electrically connected to the detection line; The control electrode of the second control transistor is electrically connected to the scanning line, the first electrode of the second control transistor is electrically connected to the control terminal of the driving circuit, and the second electrode of the second control transistor is electrically connected to the second terminal of the driving circuit.

12. The optical detection module according to claim 9, wherein, The second energy storage circuit includes a second storage capacitor, the driving circuit includes a driving transistor, and the photosensitive circuit includes a photodiode; The first end of the second storage capacitor is electrically connected to the control electrode of the driving transistor, and the second end of the second storage capacitor is electrically connected to the second voltage terminal; The first electrode of the driving transistor is electrically connected to the second voltage terminal, and the second electrode of the driving transistor is electrically connected to the second terminal of the driving circuit; The anode of the photodiode is electrically connected to the control electrode of the driving transistor, and the cathode of the photodiode is electrically connected to the second voltage terminal.

13. A light detection method, applied to the light detection module according to any one of claims 8 to 12, characterized in that, The detection period includes a current output stage, a current integration stage, and a collection stage that are set successively; the optical detection method includes: In the current output stage, the current generation unit outputs a bias current to the detection line through the bias current output terminal; the transmission control circuit, under the control of the scanning signal, controls the connection between the control terminal and the second terminal of the driving circuit, and under the control of the transmission control signal, controls the connection between the second terminal of the driving circuit and the detection line; In the current integration stage, the transmission control circuit, under the control of the scanning signal, controls the disconnection between the control terminal and the second terminal of the driving circuit, and under the control of the transmission control signal, controls the disconnection between the second terminal of the driving circuit and the detection line. The photosensitive circuit senses the optical signal and converts the optical signal into a corresponding photocurrent signal, and outputs the photocurrent signal through the photocurrent output terminal to charge or discharge the second energy storage circuit, thereby changing the potential of the control terminal of the driving circuit; In the collection stage, the driving circuit is used to generate an optical detection current under the control of the potential of its control terminal. The transmission control circuit, under the control of the scanning signal, controls the disconnection between the control terminal and the second terminal of the driving circuit, and under the control of the transmission control signal, controls the connection between the second terminal of the driving circuit and the detection line to provide the optical detection current to the detection line.

14. A display device, characterized in that, Comprising the optical detection module according to any one of claims 8 to 12.

15. The display device according to claim 14, characterized in that, The optical detection module includes an optical detection array, a plurality of current generation units, multiple columns of detection lines, and a detection integrated circuit; the optical detection module is disposed on a substrate; the optical detection array includes a plurality of rows and columns of optical detection units; The detection integrated circuit is electrically connected to the multiple columns of detection lines, for receiving the optical detection current from the detection lines, and obtaining the characteristics of the optical signal according to the optical detection current; The optical detection units in the same column are electrically connected to the same column of the detection lines; the optical detection units are used to convert the received optical signal into an optical detection current and provide the optical detection current to the corresponding column of detection lines; The current generation unit is electrically connected to the corresponding column of detection lines, for providing a corresponding bias voltage to the corresponding column of detection lines; The detection integrated circuit is disposed on the first side of the substrate; The current generating unit is disposed between the detection integrated circuit and the optical detection array; Alternatively, the current generating unit is disposed on a second side of the substrate, and the first side and the second side are opposite sides.

16. The display device according to claim 15, wherein It further includes a driving circuit; The driving circuit is configured to provide a scanning signal and a transmission control signal for the optical detection unit; The detection integrated circuit is further configured to provide a clock signal and a scanning start signal for the driving circuit; The driving circuit is disposed on a third side of the substrate and / or a fourth side of the substrate.

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