Amplification circuit, control method, and memory

Abstract

This disclosure relates to the field of semiconductor circuit design, and particularly to amplifier circuits, control methods, and memories, including: a sensing amplifier circuit, including a readout node, a complementary readout node, a first node, and a second node; an isolation circuit coupled to the readout node, the complementary readout node, a bit line, and a complementary bit line; the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line during the sensing amplification phase; an offset cancellation circuit coupled to the bit line, the complementary bit line, the readout node, and the complementary readout node; the offset cancellation circuit is configured to couple the bit line to the complementary readout node and the complementary bit line to the readout node during the offset cancellation phase; and a processing circuit coupled to the offset cancellation circuit, configured to acquire the memory temperature and adjust the duration of the offset cancellation phase based on the memory temperature to dynamically adjust the processing time of the offset cancellation phase based on the temperature to optimize memory performance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to an amplifier circuit, a control method, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) stores data through the charge in cell capacitors; cell capacitors couple bit lines and complementary bit lines. In DRAM, when performing read, write, or refresh operations, the amplifier circuit needs to read and amplify the voltage difference between the bit lines and complementary bit lines.

[0003] Transistors that make up an amplifier circuit may have different device characteristics due to factors such as process variations and temperature. For example, compatible transistors may have different threshold voltages. These different device characteristics can cause offset noise in the amplifier circuit. The presence of offset noise in the amplifier circuit reduces the effective read margin of the amplifier circuit, thereby reducing the performance of DRAM. Summary of the Invention

[0004] By adding an offset cancellation stage before the sensing amplification stage, offset noise in the amplification circuit can be eliminated. However, the offset cancellation stage requires additional data processing time, which will affect the data processing timing of the memory. Ensuring the accuracy of offset cancellation and reducing the processing time of the offset cancellation stage is of great significance to improving the performance of the memory.

[0005] This disclosure provides an amplifier circuit, a control method, and a memory that, while ensuring the accuracy of offset elimination, dynamically adjusts the processing time of the offset elimination stage based on temperature to optimize memory performance.

[0006] This disclosure provides an amplification circuit coupled to a bit line and a complementary bit line, comprising: a sensing amplification circuit including a readout node, a complementary readout node, a first node, and a second node, wherein the first node is used to receive a high level and the second node is used to receive a low level during a sensing amplification phase and an offset cancellation phase; an isolation circuit coupled to the readout node, the complementary readout node, the bit line, and the complementary bit line; the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line during the sensing amplification phase; an offset cancellation circuit coupled to the bit line, the complementary bit line, the readout node, and the complementary readout node; the offset cancellation circuit is configured to couple the bit line to the complementary readout node and the complementary bit line to the readout node during the offset cancellation phase; and a processing circuit coupled to the offset cancellation circuit, configured to acquire a memory temperature and adjust the duration of the offset cancellation phase based on the memory temperature.

[0007] Higher memory temperatures allow the sensing amplifier circuit to complete offset cancellation and sensing amplification more quickly, while lower memory temperatures require a longer time. Accordingly, the offset cancellation time can be appropriately shortened when memory temperature rises and appropriately extended when memory temperature falls. By adaptively adjusting the duration of the offset cancellation phase based on memory temperature, the memory offset cancellation time can be dynamically adjusted to optimize memory performance.

[0008] Additionally, the processing circuit includes: a temperature detection circuit configured to acquire the memory temperature; a configuration circuit coupled to the temperature detection circuit configured to acquire an offset elimination time corresponding to the memory temperature based on the memory temperature; and a control circuit coupled to the configuration circuit and the offset elimination circuit configured to provide an offset elimination signal for the offset elimination time during the offset elimination phase.

[0009] In addition, if the memory temperature rises, the processing circuit is configured to shorten the duration of the offset elimination phase based on the memory temperature; if the memory temperature falls, the processing circuit is configured to extend the duration of the offset elimination phase based on the memory temperature.

[0010] Additionally, the offset cancellation circuit includes: a first offset cancellation transistor, with one terminal of its source or drain coupled to a bit line and the other terminal coupled to a complementary readout node, and a gate for receiving an offset cancellation signal; the first offset cancellation transistor is configured to, during the offset cancellation phase, couple the complementary readout node to the bit line based on the offset cancellation signal being turned on; a second offset cancellation transistor, with one terminal of its source or drain coupled to the complementary bit line and the other terminal coupled to the readout node, and a gate for receiving the offset cancellation signal; the second offset cancellation transistor is configured to, during the offset cancellation phase, couple the readout node to the complementary bit line based on the offset cancellation signal being turned on.

[0011] Additionally, the configuration circuit includes: a storage sub-circuit configured to store the logical relationship between memory temperature and offset elimination time; and an analysis sub-circuit coupled to the temperature detection circuit and the storage sub-circuit; the analysis sub-circuit is configured to obtain the offset elimination time corresponding to the memory temperature based on the logical relationship.

[0012] Additionally, the amplification circuit further includes: a first power supply circuit coupled to a first node, including a power supply node; the first power supply circuit is configured to couple the power supply node to the first node during the offset cancellation phase and the sensing amplification phase; and a second power supply circuit coupled to a second node, including a ground node; the first power supply circuit is configured to couple the ground node to the second node during the offset cancellation phase and the sensing amplification phase.

[0013] Additionally, the first power supply circuit includes: a first control transistor; one terminal of the first control transistor, either its source or drain, is coupled to a power node, and the other terminal is coupled to a first node, with its gate used to receive a control signal; the second power supply circuit includes: a second control transistor; one terminal of the second control transistor, either its source or drain, is coupled to a second node, and the other terminal is coupled to a ground node, with its gate used to receive a control signal; the control signal is used to turn on the first control transistor and the second control transistor during the offset cancellation phase and the sensing amplification phase.

[0014] Additionally, the sensing amplification circuit includes: a first P-type transistor, with one terminal of its source or drain coupled to a first node, the other terminal coupled to a complementary readout node, and a gate coupled to a readout node; a second P-type transistor, with one terminal of its source or drain coupled to the first node, the other terminal coupled to a readout node, and a gate coupled to a complementary readout node; a first N-type transistor, with one terminal of its source or drain coupled to a second node, the other terminal coupled to a complementary readout node, and a gate coupled to a bit line; and a second N-type transistor, with one terminal of its source or drain coupled to the second node, the other terminal coupled to a readout node, and a gate coupled to a bit line. A coupled complementary bit line; an isolation circuit, comprising: a first isolation transistor, one terminal of which is coupled to the bit line and the other terminal of which is coupled to a readout node, and a gate for receiving an isolation signal; the first isolation transistor is configured to, during a sense amplification phase, couple the readout node to the bit line based on the isolation signal being turned on; a second isolation transistor, one terminal of which is coupled to the complementary bit line and the other terminal of which is coupled to a complementary readout node, and a gate for receiving an isolation signal; the second isolation transistor is configured to, during a sense amplification phase, couple the complementary readout node to the complementary readout bit line based on the isolation signal being turned on.

[0015] Additionally, the amplification circuit includes: a preprocessing circuit coupled to the readout node and the complementary readout node; during the charging phase, the preprocessing circuit is coupled to at least one of the readout node or the complementary readout node and is configured to precharge the bit line, the complementary bit line, the readout node, and the complementary readout node to a preset voltage based on a precharge signal; during the equalization phase, the preprocessing circuit is coupled to both the readout node and the complementary readout node and is configured to synchronize the node voltage of the readout node and the node voltage of the complementary readout node based on an equalization signal.

[0016] Additionally, the preprocessing circuit includes: a charging transistor, one of its source or drain terminals coupled to a readout node or a complementary readout node, and the other terminal coupled to a node providing a preset voltage, with its gate used to receive a charging signal; the charging transistor is configured to precharge the bit line, complementary bit line, readout node, and complementary readout node to the preset voltage based on the charging signal being turned on during the charging phase; and an equalization transistor, one of its source or drain terminals coupled to a readout node, and the other terminal coupled to a complementary readout node, with its gate used to receive an equalization signal; the equalization transistor is configured to synchronize the node voltage of the readout node and the node voltage of the complementary readout node based on the equalization signal being turned on during the equalization phase.

[0017] This disclosure also provides a control method that uses the amplification circuit provided in the above embodiments, including: acquiring the memory temperature; and adjusting the duration of the offset elimination stage based on the memory temperature, so as to optimize the memory performance by dynamically adjusting the processing time of the offset elimination stage based on the temperature while ensuring the accuracy of offset elimination.

[0018] In addition, the duration of the offset elimination phase is adjusted based on the memory temperature, including: if the memory temperature increases, the duration of the offset elimination phase is shortened based on the memory temperature; if the memory temperature decreases, the duration of the offset elimination phase is extended based on the memory temperature.

[0019] In addition, the control method also includes: obtaining the offset elimination time corresponding to the memory temperature based on the memory temperature; adjusting the duration of the offset elimination phase based on the memory temperature, including: adjusting the duration of the offset elimination phase based on the offset elimination time.

[0020] In addition, obtaining the offset elimination time corresponding to the memory temperature based on the memory temperature includes: obtaining the offset elimination time corresponding to the memory temperature based on logical relationships.

[0021] This disclosure also provides a memory that includes the amplification circuit provided in the above embodiments. The amplification circuit is configured to perform data read and write operations to optimize the memory performance by dynamically adjusting the processing time of the offset elimination stage based on temperature while ensuring the accuracy of offset elimination. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 A virtual structural diagram of an amplifier circuit provided in an embodiment of this disclosure;

[0024] Figure 2 A schematic diagram of a circuit structure for an amplifier circuit provided in an embodiment of this disclosure;

[0025] Figure 3 A schematic diagram of another circuit structure of the amplifier circuit provided in one embodiment of the present disclosure;

[0026] Figure 4 This is a schematic diagram of the processing circuit provided in an embodiment of the present disclosure;

[0027] Figure 5 This is a schematic diagram of the configuration circuit provided in one embodiment of the present disclosure;

[0028] Figure 6 A schematic diagram of the structure of a first power supply circuit provided in an embodiment of this disclosure;

[0029] Figure 7 This is a schematic diagram of the structure of a second power supply circuit provided in an embodiment of the present disclosure;

[0030] Figure 8 A schematic diagram of the timing of each signal during data reading and writing of an amplifier circuit provided in another embodiment of this disclosure;

[0031] Figure 9 A schematic flowchart illustrating a control method provided in another embodiment of this disclosure;

[0032] Figure 10 This is a schematic diagram of the structure of a memory provided in yet another embodiment of this disclosure. Detailed Implementation

[0033] Transistors that make up an amplifier circuit may have different device characteristics due to factors such as process variations and temperature. For example, compatible transistors may have different threshold voltages. These different device characteristics can cause offset noise in the amplifier circuit. The presence of offset noise in the amplifier circuit reduces the effective read margin of the amplifier circuit, thereby reducing the performance of DRAM.

[0034] By adding an offset cancellation stage before the sensing amplification stage, offset noise in the amplification circuit can be eliminated. However, the offset cancellation stage requires additional data processing time, which will affect the data processing timing of the memory. Ensuring the accuracy of offset cancellation and reducing the processing time of the offset cancellation stage is of great significance to improving the performance of the memory.

[0035] One embodiment of this disclosure provides an amplifier circuit that, while ensuring the accuracy of offset elimination, dynamically adjusts the processing time of the offset elimination stage based on temperature to optimize memory performance.

[0036] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0037] Figure 1 This is a virtual structural diagram of the amplifier circuit provided in this embodiment. Figure 2 This is a schematic diagram of a circuit structure for the amplifier circuit provided in this embodiment. Figure 3 This is a schematic diagram of another circuit structure for the amplifier circuit provided in this embodiment. Figure 4 This is a schematic diagram of the processing circuit provided in this embodiment. Figure 5 This is a schematic diagram of the configuration circuit provided in this embodiment. Figure 6 This is a schematic diagram of the structure of the first power supply circuit provided in this embodiment. Figure 7 This is a schematic diagram of the second power supply circuit provided in this embodiment. The following is a detailed description of the amplifier circuit provided in this embodiment with reference to the accompanying drawings:

[0038] refer to Figures 1-3 An amplifier circuit, coupled to bit line BL and complementary bit line BLB, includes:

[0039] The sensing amplifier circuit 101 includes a readout node SABL, a complementary readout node SABLB, a first node PCS, and a second node NCS. During the sensing amplification stage and the offset cancellation stage, the first node PCS is used to receive a high level, and the second node NCS is used to receive a low level.

[0040] Specifically, the first node PCS is coupled to the power node to receive a high level provided by the power node; the second node NCS is coupled to the ground node to receive a low level provided by the ground node.

[0041] The isolation circuit 102 is coupled to the readout node SABL, the complementary readout node SABLB, the bit line BL, and the complementary bit line BLB. The isolation circuit 102 is configured to couple the readout node SABL to the bit line BL and the complementary readout node SABLB to the complementary bit line BLB during the sensing amplification phase.

[0042] Offset cancellation circuit 103 is coupled to read node SABL, complementary read node SABLB, bit line BL and complementary bit line BLB. Offset cancellation circuit 103 is configured to couple bit line BL to complementary read node SABLB and complementary bit line BLB to read node SABL during offset cancellation phase.

[0043] The processing circuit 105 and the coupling offset cancellation circuit 103 are configured to acquire the memory temperature and adjust the duration of the offset cancellation phase based on the memory temperature, wherein the memory temperature is the temperature of the memory to which the amplifier circuit belongs.

[0044] Specifically, if the memory temperature rises, the processing circuit 105 is configured to shorten the duration of the offset elimination phase based on the memory temperature; if the memory temperature decreases, the processing circuit 105 is configured to extend the duration of the offset elimination phase based on the memory temperature.

[0045] All other things being equal, the higher the memory temperature, the faster the sensing amplifier circuit 101 can complete offset cancellation and sensing amplification; conversely, the lower the memory temperature, the longer it takes for the sensing amplifier circuit 101 to complete these processes. Accordingly, when the memory temperature rises, the offset cancellation time is appropriately shortened; when the memory temperature decreases, the offset cancellation time is appropriately extended. By adaptively adjusting the duration of the offset cancellation phase according to the memory temperature, dynamic adjustment of the memory offset cancellation time is achieved to optimize memory performance.

[0046] Furthermore, during data transmission in the memory, the signal transmission rate is primarily determined by the resistance of the transmission lines. Higher temperatures result in greater resistance, requiring longer data transmission times; lower temperatures result in lower resistance, shortening data transmission time. In other words, as the memory temperature increases, the offset elimination time decreases, but the data transmission time increases accordingly; conversely, as the memory temperature decreases, the offset elimination time increases, but the data transmission time decreases accordingly. Therefore, setting the offset elimination time to dynamically adjust according to temperature can cancel out the time variations in the external circuitry, without affecting the overall data read timing of the memory. The data transmission time (e.g., tRCD) within the data transmission path can also be individually set based on the memory temperature.

[0047] It should be noted that, in specific applications, the data transmission time in the data transmission path can be set to different parameters individually according to the memory temperature.

[0048] refer to Figure 2 , Figure 2 The sensing amplifier circuit 101 shown includes only one first node PCS and one second node NCS, reference Figure 3 , Figure 3 The sensing amplifier circuit 101 shown includes multiple first nodes PCS and multiple second nodes NCS, which respectively provide high and low levels; it should be noted that, Figure 3 The circuit structure shown is illustrated using three first nodes (PCS) and three second nodes (NCS) as an example, and does not constitute a limitation on this embodiment.

[0049] refer to Figures 1-3 and combined Figure 4 The processing circuit 105 includes: a temperature detection circuit 411 configured to acquire the memory temperature; a configuration circuit 412 coupled to the temperature detection circuit 411 configured to acquire an offset cancellation time corresponding to the memory temperature; and a control circuit 413 coupled to the configuration circuit 412 and the offset cancellation circuit 103 configured to provide an offset cancellation signal (Offset Cancellation, OC) for the offset cancellation time during the offset cancellation phase.

[0050] refer to Figure 2 and Figure 3 In this embodiment, the offset cancellation circuit 103 includes: a first offset cancellation transistor. <21> One terminal of the source or drain is coupled to the bit line BL, and the other terminal is coupled to the complementary readout node SABLB. The gate is used to receive the offset cancellation signal OC; the first offset cancellation transistor... <21> It is configured to couple the complementary readout node SABLB to the bit line BL based on the offset cancellation signal OC being turned on during the offset cancellation phase. The second offset cancellation transistor... <22> One terminal of the source or drain is coupled to the complementary bit line BLB, and the other terminal is coupled to the readout node SABL. The gate is used to receive the offset cancellation signal OC; the second offset cancellation transistor... <22> It is configured to couple the readout node SABL to the complementary bit line BLB based on the offset cancellation signal OC being turned on during the offset cancellation phase.

[0051] It should be noted that the first offset cancellation transistor <21> Second offset cancellation transistor <22> It can be set to an NMOS transistor or a PMOS transistor. This embodiment does not use the first offset cancellation transistor. <21> Second offset cancellation transistor <22> The specific type is limited.

[0052] Specifically, the first offset elimination transistor <21> Second offset cancellation transistor <22> The offset cancellation signal OC is turned on so that the sensing amplifier circuit 101 generates a compensation voltage between the bit line BL and the complementary bit line BLB. The duration of the offset cancellation signal OC is determined based on the offset cancellation time, thereby controlling the duration of the offset cancellation phase according to the temperature.

[0053] refer to Figure 4 and combined Figure 5 The configuration circuit 412 includes: a storage sub-circuit 430 configured to store the logical relationship between memory temperature and offset elimination time; and an analysis sub-circuit 420 coupled to the temperature detection circuit 411 and the storage sub-circuit 430. The analysis sub-circuit 420 is configured to obtain the offset elimination time corresponding to the memory temperature based on the logical relationship.

[0054] Specifically, the storage circuit 430 stores a logical relationship between the storage memory temperature and the offset elimination time. This logical relationship indicates the offset elimination time corresponding to a specific storage memory temperature. In some embodiments, the same storage memory temperature range corresponds to the same offset elimination time, while different storage memory temperature ranges have different offset elimination times. In other embodiments, each storage memory temperature corresponds to a different offset elimination time, meaning that the storage memory temperature and offset elimination time have a mapping relationship. The analysis sub-circuit 420 obtains the offset elimination time corresponding to the storage temperature based on the storage temperature obtained by the temperature detection circuit 411 and the logical relationship in the storage sub-circuit 430.

[0055] As mentioned above, memory temperature affects the offset elimination time and data transfer time. In some embodiments, the logical relationship between memory temperature and offset elimination time is configured to unify the offset elimination time and data transfer time under different memory temperatures. Specifically, a preset offset elimination time and a preset data transfer time under a preset memory temperature are obtained, the data transfer time under different memory temperatures is obtained, and the data change direction and data change amount between the data transfer time and the preset data transfer time under different memory temperatures are obtained. Based on the preset offset elimination time, the data change direction, and the data change amount, the offset elimination time corresponding to different memory temperatures is obtained.

[0056] In some embodiments, reference Figure 3 The amplifier circuit also includes: a reference circuit. Figure 6 A first power supply circuit 200, coupled to a first node PCS, includes a power node V; the first power supply circuit 200 is configured to couple the power node V to the first node PCS during the offset cancellation phase and the sensing amplification phase; Reference Figure 7The second power supply circuit 300 is coupled to the second node NCS and includes a ground node GND; the second power supply circuit 300 is configured to couple the ground node GND to the second node NCS during the offset cancellation phase and the sensing amplification phase.

[0057] Specifically, the first power supply circuit 200 includes: a first control transistor. <41> The first control transistor has one terminal of its source or drain coupled to a power supply node V, and the other terminal coupled to a first node PCS. Its gate is used to receive a control signal K. The second power supply circuit 300 includes: a second control transistor. <42> The second control transistor has one terminal of its source or drain coupled to the second node NCS, and the other terminal coupled to the ground node GND. Its gate is used to receive the control signal K. The control signal K is used to turn on the first control transistor during the offset cancellation phase and the sensing amplification phase. <41> Second control transistor <42> .

[0058] Specifically, in the offset cancellation stage and the sensing amplification stage, the first control transistor <41> Based on the control signal K being turned on, power node V is coupled to the first node PCS; the second control transistor <42> Based on the control signal K being turned on, the ground node GND is coupled to the second node NCS.

[0059] The control signal K is provided based on the memory of the amplifier circuit. In some embodiments, the first control transistor... <41> Second control transistor <42> The transistor is turned on based on the same control signal K; in some embodiments, the control signal K includes multiple sub-control signals, with the first control transistor being... <41> Second control transistor <42> Based on different self-control signals for conduction.

[0060] It should be noted that the first control transistor <41> It can be set to an NMOS transistor or a PMOS transistor. Since the pull-up capability of a PMOS transistor is better than that of an NMOS transistor, in this embodiment, the first control transistor is... <41> PMOS transistors are used.

[0061] It should be noted that this embodiment uses a second control transistor. <42> Based on high-level conduction, i.e., the second control transistor <42> Taking an NMOS transistor as an example does not constitute a limitation of this embodiment. Since the pull-down capability of an NMOS transistor is superior to that of a PMOS transistor, the second control transistor... <42> Setting the transistor to an NMOS transistor can increase the rate at which the sensing amplifier circuit 101 generates a compensation voltage between the bit line BL and the complementary bit line BLB; in other embodiments, the second control transistor can also be set to a PMOS transistor, in which case the power supply voltage of the first control power supply is less than the power supply voltage of the second control power supply.

[0062] In addition, this embodiment is based on Figure 3 The circuit shown is explained in the diagram, therefore it is adapted to Figure 3 The circuit shown has three first nodes (PCS) and two second nodes (NCS), each with a controller that implements control over the three first control transistors. <41> and three second control transistors <42> Control; in some embodiments, the control signal K is also used to select and turn on the first control transistor. <41> Second control transistor <42> .

[0063] Continue to refer to Figure 2 and Figure 3 In this embodiment, the sensing amplifier circuit 101 includes: a first P-type transistor. <p1>One terminal of the source or drain is coupled to the first node PCS, and the other terminal is coupled to the complementary readout node SABLB; the gate is coupled to the readout node SABL; the second P-type transistor <p2>One terminal of the source or drain is coupled to the first node PCS, and the other terminal is coupled to the readout node SABL; the gate is coupled to the complementary readout node SABLB; the first N-type transistor <n1>One terminal of the source or drain is coupled to the second node NCS, and the other terminal is coupled to the complementary readout node SABLB. The gate is coupled to the bit line BL. (Second N-type transistor) <n2>One of the terminals in the source or drain is coupled to the second node NCS, and the other terminal is coupled to the readout node SABL. The gate is coupled to the complementary bit line BLB.

[0064] Continue to refer to Figure 2 and Figure 3 In this embodiment, the isolation circuit 102 includes: a first isolation transistor. <11> One terminal of the source or drain is coupled to the bit line BL, and the other terminal is coupled to the readout node SABL. The gate is used to receive the isolation signal (Isolation Cancellation, ISO); the first isolation transistor. <11> It is configured to couple the readout node SABL to the bit line BL based on the isolation signal ISO being turned on during the sensing amplification phase. Second isolation transistor <12> One terminal of the source or drain is coupled to the complementary bit line BLB, and the other terminal is coupled to the complementary readout node SABLB. The gate is used to receive the isolation signal ISO; the second isolation transistor <12> It is configured to couple the complementary readout node SABLB to the complementary bit line BLB based on the isolation signal ISO being turned on during the sensing amplification phase.

[0065] It should be noted that the first isolation transistor <11> Second isolation transistor <12> It can be set to an NMOS transistor or a PMOS transistor. This embodiment does not specify the first isolation transistor. <11> Second isolation transistor <12> The specific type is limited.

[0066] Continue to refer to Figure 2 and Figure 3 In this embodiment, the amplification circuit further includes: a preprocessing circuit 104 coupled to the readout node SABL and the complementary readout node SABLB; during the charging phase, the preprocessing circuit 104 is coupled to at least one of the readout node SABL or the complementary readout node SABLB and is configured to precharge the bit line BL, the complementary bit line BLB, the readout node SABL, and the complementary readout node SABLB to a preset voltage Vdd based on a precharge cancellation signal (PRE); during the equalization phase, the preprocessing circuit 104 is coupled to both the readout node SABL and the complementary readout node SABLB and is configured to synchronize the node voltage of the readout node SABL and the node voltage of the complementary readout node SABLB based on an equalization cancellation signal (EQ).

[0067] It should be noted that the preset voltage Vdd is the internal power supply voltage of the memory to which the amplifier circuit belongs.

[0068] Specifically, the preprocessing circuit includes: a charging transistor. <31> One terminal of the source or drain is coupled to a readout node SABL or a complementary readout node SABLB, and the other terminal is coupled to a node that provides a preset voltage Vdd. The gate is used to receive the charging signal PRE; charging transistor. <31> Configured to precharge bit line BL, complementary bit line BLB, readout node SABL, and complementary readout node SABLB to a preset voltage Vdd during the charging phase, based on the charging signal PRE being turned on. Equalization transistor <32> One terminal of the source or drain is coupled to the readout node SABL, and the other terminal is coupled to the complementary readout node SABLB. The gate is used to receive the equalization signal EQ; equalization transistor. <32> It is configured to, during the equalization phase, synchronously read out the node voltage of node SABL and the node voltage of complementary node SABLB based on the equalization signal EQ being turned on.

[0069] It should be noted that the charging transistor <31> and equalization transistors <32> It can be set to an NMOS transistor or a PMOS transistor. This embodiment does not specify the charging transistor. <31> and equalization transistors <32> The specific type is limited.

[0070] The higher the memory temperature, the faster the sensing amplifier circuit 101 can complete offset cancellation and sensing amplification; the lower the memory temperature, the longer the sensing amplifier circuit 101 needs to complete offset cancellation and sensing amplification. Accordingly, when the memory temperature rises, the offset cancellation time is appropriately shortened; when the memory temperature falls, the offset cancellation time is appropriately extended. By adaptively adjusting the duration of the offset cancellation stage according to the memory temperature, the memory offset cancellation time can be dynamically adjusted to optimize memory performance.

[0071] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.

[0072] It should be noted that the features disclosed in the amplifier circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new amplifier circuit embodiments.

[0073] Another embodiment of this disclosure provides a control method that uses the amplification circuit provided in the above embodiments to shorten the processing time of the offset elimination stage while ensuring the accuracy of offset elimination, thereby optimizing the performance of the memory.

[0074] Figure 8 This is a schematic diagram of the timing of each signal in the amplifier circuit provided in this embodiment during data reading and writing. Figure 9 The following is a flowchart illustrating the control method provided in this embodiment. The control method provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0075] refer to Figure 8 and combined Figure 2 and Figure 3 Regarding the amplifier circuit provided in the above embodiments:

[0076] In phase S1, i.e. the charging phase, an isolation signal ISO, an offset cancellation signal OC, and an equalization signal EQ are provided to couple the bit line BL, the complementary bit line BLB, the readout node SABL, and the complementary readout node SABLB to each other, and a charging signal PRE is provided to precharge the bit line BL, the complementary bit line BLB, the readout node SABL, and the complementary readout node SABLB to a preset voltage Vdd.

[0077] It should be noted that the preset voltage Vdd is the internal power supply voltage of the memory to which the amplifier circuit belongs.

[0078] In stage S2, the offset cancellation stage, offset noise in the amplifier circuit is eliminated.

[0079] Specifically, refer to Figure 9 In the offset elimination stage, step 501 is to obtain the memory temperature.

[0080] Step 502: Adjust the duration of the offset elimination phase based on the memory temperature.

[0081] Specifically, the duration of the offset elimination phase is adjusted based on the memory temperature, including: if the memory temperature increases, the duration of the offset elimination phase is shortened based on the memory temperature; if the memory temperature decreases, the duration of the offset elimination phase is extended based on the memory temperature.

[0082] In some embodiments, between steps 501 and 502, the method further includes: obtaining an offset elimination time corresponding to the memory temperature based on the memory temperature; and adjusting the duration of the offset elimination phase based on the memory temperature, including: adjusting the duration of the offset elimination phase based on the offset elimination time. That is, step 502 involves adjusting the duration of the offset elimination phase based on the offset elimination time.

[0083] Specifically, obtaining the offset elimination time corresponding to the memory temperature based on the memory temperature includes: obtaining the offset elimination time corresponding to the memory temperature based on logical relationships. In one example, referencing... Figure 5 The memory stores a logical relationship between the memory temperature and the offset elimination time. The logical relationship indicates the offset elimination time corresponding to a specific memory temperature, thereby enabling the acquisition of the offset elimination time corresponding to the memory temperature based on the acquired memory temperature and the logical relationship.

[0084] In some embodiments, the same memory temperature range corresponds to the same offset elimination time, while different memory temperature ranges have different offset elimination times; in other embodiments, each memory temperature corresponds to a different offset elimination time, that is, there is a mapping relationship between memory temperature and offset elimination time.

[0085] In addition, memory temperature affects the offset elimination time and data transfer time. In some embodiments, the logical relationship between memory temperature and offset elimination time is configured to unify the offset elimination time and data transfer time under different memory temperatures. Specifically, a preset offset elimination time and a preset data transfer time under a preset memory temperature are obtained, the data transfer time under different memory temperatures is obtained, and the data change direction and data change amount between the data transfer time and the preset data transfer time under different memory temperatures are obtained. Based on the preset offset elimination time, the data change direction, and the data change amount, the offset elimination time corresponding to different memory temperatures is obtained.

[0086] In the S3 stage, which is the charge sharing stage, the word line WL is turned on to conduct the corresponding memory cell, and the charge stored in the memory cell is shared to the bit line BL or the complementary bit line BLB. Then, based on the isolation signal ISO, the bit line BL is coupled to the read node SABL, and the complementary bit line BLB is coupled to the complementary read node SABLB.

[0087] In the S4 stage, which is the sensing amplification stage, the voltage difference between the bit line BL and the complementary bit line BLB is amplified.

[0088] In the S5 stage, which is at the end of the sensing amplification stage, data is read out / written.

[0089] It should be noted that the features disclosed in the control method provided in the above embodiments can be arbitrarily combined without conflict to obtain new control method embodiments.

[0090] Another embodiment of this disclosure provides a memory that includes the amplification circuit provided in the above embodiments. The amplification circuit is configured to perform data read and write operations, and while ensuring the accuracy of offset elimination, dynamically adjusts the processing time of the offset elimination stage based on temperature to optimize the performance of the memory.

[0091] Figure 10 This is a schematic diagram of the memory structure in this embodiment. The memory provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0092] refer to Figure 10 Memory can be a storage cell or device based on semiconductor devices or components. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0093] The memory device can input / output data via the data line DQ in response to control commands CMD and address signals received from an external device, such as a memory controller. The memory device includes a memory cell array 10, a command decoder 30, control logic 40, an address buffer 20, a row decoder 21, a column decoder 22, an amplifier circuit 50, and a data input / output circuit 60.

[0094] The memory cell array 10 includes a plurality of memory cells provided in a matrix format arranged in multiple rows and columns. The memory cell array 10 includes a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL can be connected to rows of the memory cells, and the plurality of bit lines BL can be connected to columns of the memory cells.

[0095] Command decoder 30 can decode write enable signal / WE, row address strobe signal / RAS, column address strobe signal / CAS, chip select signal / CS, etc. received from external devices such as memory controllers, and can allow control logic 40 to generate control signals corresponding to control command CMD.

[0096] The control commands (CMD) can include activation commands, read commands, write commands, precharge commands, etc.

[0097] Address buffer 20 receives address signals from the memory controller, which is an external device. Address signals include a row address RA for addressing rows of the memory cell array 10 and a column address CA for addressing columns of the memory cell array 10. Address buffer 120 can send the row address RA to row decoder 21 and the column address CA to column decoder 22.

[0098] The row decoder 21 can select any one of the multiple word lines WL connected to the memory cell array 10. The row decoder 21 can decode the row address RA received from the address buffer 120, select any word line corresponding to the row address RA, and activate the selected word line WL.

[0099] The column decoder 22 can select a predetermined number of bit lines from a plurality of bit lines BL of the memory cell array 10. The column decoder 22 can decode the column address CA received from the address buffer 120 and select the predetermined number of bit lines BL corresponding to the received column address CA.

[0100] Amplifier circuit 50 is connected to the bit line BL of memory cell array 10. Amplifier circuit 50 can read the voltage change of selected bit line among multiple bit lines BL, amplify the voltage change, and output the amplified voltage change.

[0101] The data input / output circuit 60 can output data via the data line DQ based on the voltage read and amplified by the amplifier circuit 50.

[0102] Amplifier circuit 50 can receive isolation signal ISO and offset cancellation signal OC from control logic 40. Amplifier circuit 50 can perform offset cancellation operation in response to isolation signal ISO and offset cancellation signal OC. For example, offset represents the characteristic difference between the semiconductor devices constituting amplifier circuit 50, such as the difference between the threshold voltages of different semiconductor devices.

[0103] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. An amplifier circuit coupled to bit lines and complementary bit lines, characterized in that, include: The sensing amplification circuit includes a readout node, a complementary readout node, a first node, and a second node. During the sensing amplification stage and the offset cancellation stage, the first node is used to receive a high level, and the second node is used to receive a low level. An isolation circuit is coupled to the readout node, the complementary readout node, the bit line, and the complementary bit line; the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line during the sensing amplification phase. An offset cancellation circuit is coupled to the bit line, the complementary bit line, the readout node, and the complementary readout node; the offset cancellation circuit is configured to couple the bit line to the complementary readout node and the complementary bit line to the readout node during the offset cancellation phase; The processing circuit, coupled to the offset elimination circuit, is configured to acquire the memory temperature and, based on the memory temperature, adjust the duration of the offset elimination phase.

2. The amplifier circuit according to claim 1, characterized in that, The processing circuit includes: A temperature detection circuit is configured to acquire the temperature of the memory. The configuration circuit, coupled to the temperature detection circuit, is configured to obtain the offset elimination time corresponding to the memory temperature based on the memory temperature; A control circuit, coupled to the configuration circuit and the offset cancellation circuit, is configured to provide an offset cancellation signal for the offset cancellation time during the offset cancellation phase.

3. The amplifier circuit according to claim 2, characterized in that, include: If the memory temperature rises, the processing circuit is configured to shorten the duration of the offset elimination phase based on the memory temperature. If the memory temperature decreases, the processing circuit is configured to extend the duration of the offset elimination phase based on the memory temperature.

4. The amplifier circuit according to claim 2, characterized in that, include: The offset cancellation circuit includes: A first offset cancellation transistor has one terminal of its source or drain coupled to the bit line and the other terminal coupled to the complementary readout node, with its gate used to receive the offset cancellation signal. The first offset cancellation transistor is configured to, during the offset cancellation phase, conduct based on the offset cancellation signal to couple the complementary readout node to the bit line; The second offset cancellation transistor has one terminal of its source or drain coupled to the complementary bit line, and the other terminal coupled to the readout node. Its gate is used to receive the offset cancellation signal. The second offset cancellation transistor is configured to couple the readout node to the complementary bit line based on the offset cancellation signal being turned on during the offset cancellation phase.

5. The amplifier circuit according to claim 2, characterized in that, The configuration circuit includes: The storage sub-circuit is configured to store the logical relationship between memory temperature and offset elimination time; An analysis sub-circuit is coupled to the temperature detection circuit and the storage sub-circuit; the analysis sub-circuit is configured to obtain the offset elimination time corresponding to the memory temperature based on the logical relationship.

6. The amplifier circuit according to claim 1, characterized in that, Also includes: A first power supply circuit, coupled to the first node, includes a power node; the first power supply circuit is configured to couple the power node to the first node during the offset cancellation phase and the sensing amplification phase. A second power supply circuit, coupled to the second node, includes a ground node; the first power supply circuit is configured to couple the ground node to the second node during the offset cancellation phase and the sensing amplification phase.

7. The amplifier circuit according to claim 6, characterized in that, include: The first power supply circuit includes: a first control transistor; The first control transistor has one terminal of its source or drain coupled to the power supply node, and the other terminal coupled to the first node, with its gate used to receive control signals. The second power supply circuit includes: a second control transistor; The second control transistor has one terminal of its source or drain coupled to the second node, and the other terminal coupled to the ground node, with its gate used to receive the control signal; The control signal is used to turn on the first control transistor and the second control transistor during the offset elimination phase and the sensing amplification phase.

8. The amplifier circuit according to claim 1, characterized in that, The sensing amplification circuit includes: The first P-type transistor has one terminal of its source or drain coupled to the first node, the other terminal coupled to the complementary readout node, and its gate coupled to the readout node; The second P-type transistor has one terminal of its source or drain coupled to the first node, the other terminal coupled to the readout node, and its gate coupled to the complementary readout node; The first N-type transistor has one terminal of its source or drain coupled to the second node, the other terminal coupled to the complementary readout node, and its gate coupled to the bit line; The second N-type transistor has one terminal of its source or drain coupled to the second node, the other terminal coupled to the readout node, and its gate coupled to the complementary bit line. The isolation circuit includes: The first isolation transistor has one terminal of its source or drain coupled to the bit line and the other terminal coupled to the readout node, and its gate is used to receive the isolation signal. The first isolation transistor is configured to, during the sensing amplification phase, conduct based on the isolation signal to couple the readout node to the bit line; The second isolation transistor has one terminal of its source or drain coupled to the complementary bit line, and the other terminal coupled to the complementary readout node. Its gate is used to receive the isolation signal. The second isolation transistor is configured to couple the complementary readout node to the complementary bit line based on the isolation signal being turned on during the sensing amplification phase.

9. The amplifier circuit according to claim 1, characterized in that, Also includes: Preprocessing circuitry, coupled to the readout node and the complementary readout node; During the charging phase, the preprocessing circuit, coupled to at least one of the readout node or the complementary readout node, is configured to precharge the bit line, the complementary bit line, the readout node, and the complementary readout node to a preset voltage based on a precharge signal. During the equalization phase, the preprocessing circuit, which simultaneously couples the readout node and the complementary readout node, is configured to synchronize the node voltage of the readout node and the node voltage of the complementary readout node based on the equalization signal.

10. The amplifier circuit according to claim 9, characterized in that, The preprocessing circuit includes: A charging transistor, with one terminal of its source or drain coupled to the readout node or the complementary readout node, and the other terminal coupled to a node that provides the preset voltage, and a gate for receiving the charging signal; The charging transistor is configured to, during the charging phase, precharge the bit line, the complementary bit line, the readout node, and the complementary readout node to a preset voltage based on the charging signal being turned on; The equalization transistor has one terminal of its source or drain coupled to the readout node and the other terminal coupled to the complementary readout node, with its gate used to receive the equalization signal. The equalization transistor is configured to, during the equalization phase, synchronize the node voltage of the readout node and the node voltage of the complementary readout node based on the equalization signal being turned on.

11. A control method, employing the amplifier circuit according to any one of claims 1 to 10, characterized in that, include: Obtain the memory temperature; The duration of the offset elimination phase is adjusted based on the memory temperature.

12. The control method according to claim 11, characterized in that, Adjusting the duration of the offset elimination phase based on the memory temperature includes: If the memory temperature rises, the duration of the offset elimination phase is shortened based on the memory temperature. If the memory temperature decreases, the duration of the offset elimination phase is extended based on the memory temperature.

13. The control method according to claim 11, characterized in that, Also includes: The offset elimination time corresponding to the memory temperature is obtained based on the memory temperature; Adjusting the duration of the offset elimination phase based on the memory temperature includes: adjusting the duration of the offset elimination phase based on the offset elimination time.

14. The control method according to claim 13, characterized in that, The step of obtaining the offset elimination time corresponding to the memory temperature based on the memory temperature includes: obtaining the offset elimination time corresponding to the memory temperature based on a logical relationship.

15. A memory, characterized in that, The amplifier circuit includes any one of claims 1 to 10, and the amplifier circuit is configured to perform data read and write operations.

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