Amplification circuit, control method, and memory
By adding an offset cancellation stage to the DRAM and utilizing power supply voltage differences to eliminate offset noise in the amplifier circuit, the performance problem caused by transistor device characteristic differences is solved, and memory performance is optimized.
CN116564381BActive Publication Date: 2026-07-17CHANGXIN MEMORY TECH INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-27
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In existing DRAM, the amplifier circuits suffer from offset noise due to differences in transistor device characteristics, which affects the effective read margin and performance.
Method used
An offset elimination stage is added before the sensing amplification stage. By utilizing the difference in power supply voltage, a larger power supply voltage is provided in the offset elimination stage to eliminate the offset caused by differences in transistor manufacturing and shorten the offset elimination time.
Benefits of technology
While ensuring the accuracy of offset elimination, the processing time of the offset elimination stage is reduced, thus optimizing memory performance.
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Smart Images
Figure CN116564381B_ABST
Abstract
The present disclosure relates to the field of semiconductor circuit design, and particularly relates to an amplification circuit, a control method and a memory, comprising: a sensing amplification circuit comprising a readout node, a complementary readout node, a first node and a second node; an isolation circuit is configured to, in a sensing amplification phase, couple the readout node to a bit line and couple the complementary readout node to a complementary bit line; an offset cancellation circuit is configured to, in an offset cancellation phase, couple the bit line to the complementary readout node and couple the complementary bit line to the readout node; a first power supply circuit is coupled to the first node and comprises a first power supply and a second power supply, the power supply voltage of the first power supply being higher than that of the second power supply; the first power supply circuit is configured to, in the offset cancellation phase, couple the first power supply to the first node, and in the sensing amplification phase, couple the second power supply to the first node, so as to shorten the processing time of the offset cancellation phase, thereby optimizing the performance of the memory.
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