Semiconductor structure and method of manufacturing the same

Abstract

The embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof. The method comprises: providing a substrate; forming a first recessed region from a first surface of the substrate, at least two protruding structures being reserved in the first recessed region; any two adjacent protruding structures of the at least two protruding structures have at least partially non-overlapping regions in the projection along the direction perpendicular to the protruding structures; filling insulating material in the first recessed region; thinning from a second surface of the substrate until the insulating material is exposed on the second surface; wherein the second surface is the back surface of the first surface; removing part of the protruding structures from the second surface to form a second recessed region; filling conductive material in the second recessed region to form a bit line; forming a bit line lead-out structure connected with the bit line at the position corresponding to the non-overlapping region on the surface of the bit line.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Semiconductor memories can access data by controlling the charging and discharging of storage capacitors using transistor arrays. The drain (or source) of the transistor is electrically connected to the bit line. After the bit line is formed on the substrate, a bit line lead-out structure needs to be formed on the bit line to achieve electrical connection between the bit line and the external control circuit.

[0003] However, as the integration density of semiconductor devices continues to increase, the distance between bit lines is constantly decreasing, leading to a decrease in the distance between bit line lead-out structures. This makes it easier for interconnections to occur between adjacent bit line lead-out structures, resulting in short circuits and even semiconductor device failure. Therefore, reducing short circuits between adjacent bit line lead-out structures has become an urgent problem to solve. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for manufacturing the same.

[0005] In a first aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, comprising:

[0006] Provide substrate;

[0007] A first recessed region is formed from a first surface of the substrate, and at least two protruding structures are retained in the first recessed region; any two adjacent protruding structures have at least partially non-overlapping projections along a direction perpendicular to the extension of the protruding structure.

[0008] The first recessed region is filled with insulating material to form a dielectric layer;

[0009] Thinning is performed from the second surface of the substrate until the dielectric layer is exposed on the second surface; wherein the second surface is the back side of the first surface;

[0010] A portion of the protruding structure is removed from the second surface to form a second recessed region;

[0011] The second recessed region is filled with conductive material to form a bit line;

[0012] A bit line lead-out structure connected to the bit line is formed at a position on the bit line surface corresponding to the non-overlapping region.

[0013] In some embodiments, forming a first recessed region from a first surface of the substrate, wherein at least two protruding structures are retained in the first recessed region, includes:

[0014] A plurality of first barrier structures are formed on the first surface of the substrate;

[0015] The substrate not covered by the first barrier structure is etched to form the first recessed region; wherein the substrate covered by the first barrier structure is retained as the at least two protruding structures.

[0016] In some embodiments, forming a plurality of first barrier structures on the first surface of the substrate includes:

[0017] Multiple rectangular ring-shaped second barrier structures are formed on the first surface of the substrate;

[0018] A first mask layer is applied to the plurality of second blocking structures to cover at least a portion of each second blocking structure; wherein, at least two opposite sides of the second blocking structure have unmasked areas;

[0019] Etch the second barrier structure that is not covered by the first mask layer;

[0020] Remove the first mask layer, wherein each of the unetched second barrier structures comprises two of the first barrier structures.

[0021] In some embodiments, each unetched second barrier structure includes two first barrier structures that are centrally symmetrical with respect to the center of the second barrier structure.

[0022] In some embodiments, forming a plurality of rectangular ring-shaped second barrier structures on the first surface of the substrate includes:

[0023] Multiple rectangular second mask structures are formed on the first surface of the substrate;

[0024] A second barrier structure is formed around the second mask structure, surrounding the second mask layer.

[0025] In some embodiments, forming a plurality of rectangular second mask structures on the first surface of the substrate includes:

[0026] A second mask layer is applied to the first surface of the substrate;

[0027] A rectangular photoresist layer is formed on the second mask layer;

[0028] Remove the second mask layer from the area not covered by the photoresist layer, and remove the photoresist layer; wherein the second mask layer that is not removed is the second mask structure.

[0029] In some embodiments, prior to the thinning from the second surface of the substrate, the method further includes:

[0030] Provides carrier wafers;

[0031] The first surface of the substrate is bonded to the carrier wafer;

[0032] Flip the substrate so that the second surface faces vertically upward.

[0033] In a second aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0034] Substrate;

[0035] A first recessed region located on the first surface of the substrate; at least two protruding structures are retained in the first recessed region; any two adjacent protruding structures have at least partially non-overlapping projections along a direction perpendicular to the extension of the protruding structure.

[0036] The dielectric layer is located in the first recessed region;

[0037] A second recessed region located on the second surface of the substrate, situated between the dielectric layers;

[0038] Bit lines are located within the second recessed region; the bit lines are made of conductive material.

[0039] The bit line lead-out structure is located on the non-overlapping region corresponding to the bit line surface and is connected to the bit line.

[0040] In some embodiments, the bit line lead-out structure has a third surface and a fourth surface facing away from each other; wherein the third surface is connected to the bit line; and the area of ​​the fourth surface is larger than the area of ​​the third surface.

[0041] In some embodiments, two adjacent bit lines are centrally symmetric structures.

[0042] This embodiment of the present disclosure effectively increases the window distance between adjacent bit line lead-out structures by setting bit line lead-out structures in the non-overlapping region along the bit line extension direction of adjacent bit lines, making it less likely for adjacent bit line lead-out structures to short-circuit. Furthermore, the bit line lead-out structures are formed in the peripheral region of the transistor array, improving the effective utilization rate of the peripheral region and improving the performance of the device without affecting the space used by the transistor array. Attached Figure Description

[0043] Figure 1 This is a cross-sectional view of a substrate to be formed with bit lines in a method for manufacturing a semiconductor structure provided in some embodiments;

[0044] Figure 2 This is a cross-sectional view showing the bonding of a wafer to a substrate in a method for manufacturing a semiconductor structure provided in some embodiments.

[0045] Figure 3A This is a top view of a semiconductor structure manufacturing method provided in some embodiments after substrate thinning;

[0046] Figure 3B This is a cross-sectional view of a substrate after thinning in a method for manufacturing a semiconductor structure provided in some embodiments;

[0047] Figure 4A This is a top view of a semiconductor structure fabrication method provided in some embodiments after the bit line material has been formed;

[0048] Figure 4B This is a cross-sectional view after bit line material is formed in a method for manufacturing a semiconductor structure provided in some embodiments;

[0049] Figure 5A This is a top view after bit lines have been formed in a method for manufacturing a semiconductor structure provided in some embodiments;

[0050] Figure 5B This is a cross-sectional view after bit lines are formed in a method for manufacturing a semiconductor structure provided in some embodiments;

[0051] Figure 6A This is a top view of the substrate after the bit line lead-out structure has been formed in some embodiments;

[0052] Figure 6B This is a cross-sectional view of the substrate after the bit line lead-out structure has been formed in some embodiments;

[0053] Figure 7 A flowchart illustrating a semiconductor structure manufacturing method provided in this disclosure embodiment;

[0054] Figure 8 This is a schematic diagram of the structure of a substrate provided in an embodiment of the present disclosure;

[0055] Figure 9A This is a top view of a method for forming a protrusion structure in a semiconductor structure manufacturing process provided by an embodiment of the present disclosure;

[0056] Figure 9B This is a cross-sectional view of a method for forming a protrusion structure in a semiconductor structure manufacturing process provided by an embodiment of the present disclosure;

[0057] Figure 10A This is a top view of a method for forming a dielectric layer in a semiconductor structure manufacturing process according to an embodiment of the present disclosure;

[0058] Figure 10BThis is a cross-sectional view of a semiconductor structure manufacturing method in which a dielectric layer is formed, according to an embodiment of the present disclosure.

[0059] Figure 11A This is a top view of a semiconductor structure manufacturing method provided in this disclosure after substrate thinning;

[0060] Figure 11B This is a cross-sectional view of a semiconductor structure manufacturing method provided in this disclosure after substrate thinning;

[0061] Figure 12A This is a top view of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, in which a second recessed region is formed.

[0062] Figure 12B This is a cross-sectional view of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, in which a second recessed region is formed.

[0063] Figure 13A This is a top view of a method for forming bit lines in a semiconductor structure manufacturing process provided in this disclosure embodiment;

[0064] Figure 13B This is a cross-sectional view of a method for forming bit lines in a semiconductor structure manufacturing process provided in this disclosure embodiment;

[0065] Figure 13C A cross-sectional view of forming bit lines in another method of manufacturing a semiconductor structure provided in this disclosure embodiment;

[0066] Figure 14A A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0067] Figure 14B A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure;

[0068] Figure 14C A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure;

[0069] Figure 15A This is a top view of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, in which a first barrier structure is formed.

[0070] Figure 15B This is a cross-sectional view of a semiconductor structure manufacturing method according to an embodiment of the present disclosure, showing the formation of a first barrier structure.

[0071] Figure 16A This is a top view of a method for forming a second barrier structure in a semiconductor structure manufacturing process provided by an embodiment of the present disclosure;

[0072] Figure 16BThis is a cross-sectional view of a method for forming a second barrier structure in a semiconductor structure manufacturing process provided by an embodiment of the present disclosure;

[0073] Figure 17A This is a top view of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, in which a first mask layer is covered on a second barrier structure.

[0074] Figure 17B This is a cross-sectional view of a semiconductor structure manufacturing method provided in this disclosure, in which a first mask layer is covered on a second barrier structure.

[0075] Figure 18A This is a top view of a method for forming a second mask structure in a semiconductor structure manufacturing process provided by an embodiment of the present disclosure;

[0076] Figure 18B This is a cross-sectional view of a method for forming a second mask structure in a semiconductor structure manufacturing process provided by an embodiment of the present disclosure;

[0077] Figure 19A This is a top view of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, in which a second barrier structure is formed around a second mask structure;

[0078] Figure 19B This is a cross-sectional view of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, in which a second barrier structure is formed around a second mask structure;

[0079] Figure 20A A top view of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, in which a photoresist layer is formed on a second mask layer;

[0080] Figure 20B A cross-sectional view of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, in which a photoresist layer is formed on a second mask layer;

[0081] Figure 21A This is a top view of a method for forming a second mask structure in a semiconductor structure manufacturing process provided by an embodiment of the present disclosure;

[0082] Figure 21B This is a cross-sectional view of a method for forming a second mask structure in a semiconductor structure manufacturing process provided by an embodiment of the present disclosure;

[0083] Figure 22A This is a top view of a method for forming bit lines in a semiconductor structure manufacturing process provided in this disclosure embodiment;

[0084] Figure 22B A top view of the bit line formation in another method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0085] Figure 22C A top view of forming bit lines in another method of manufacturing a semiconductor structure provided in this disclosure embodiment;

[0086] Figures 23A-23D This is a schematic diagram illustrating a method for manufacturing a semiconductor structure provided in some embodiments;

[0087] Figures 24A-24D This is a process diagram of a semiconductor structure manufacturing method provided in an embodiment of this disclosure.

[0088] Substrate: 100; Supporting wafer: 101; First surface: S1; Second surface: S2; Third surface: S3; Fourth surface: S4; Bump structure: 301; Insulating layer: 302; Bit line: 303; Dielectric layer: 304; Bit line lead-out structure 305; First recessed region: 401; Second recessed region: 402; First blocking structure: 403; Second blocking structure: 404; First mask layer: 405; Second mask structure: 406; Photoresist layer: 407; Second mask layer: 408. Detailed Implementation

[0089] To facilitate understanding of this disclosure, exemplary embodiments thereof will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0090] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of actual embodiments, nor well-known functions and structures, may be described herein.

[0091] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0092] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0093] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0094] In some embodiments, in the semiconductor memory manufacturing process, the bit lines of transistors can be formed through the following steps:

[0095] like Figure 1 As shown, a substrate 100 is provided to form a bit line. The thickness direction of the substrate 100 or the direction perpendicular to the surface of the substrate 100 is defined as the Z direction. The top or bottom surface of the substrate 100 perpendicular to the Z direction is a first surface S1 and a second surface S2 facing away from each other, respectively. Two intersecting X and Y directions are defined in the first surface S1 or the second surface S2 perpendicular to the Z direction. A transistor array may be present in the substrate, and the transistor array may include at least one transistor. In some embodiments, the transistor array may also be connected to a storage capacitor, and one transistor may be connected to one storage capacitor. The side of the storage capacitor adjacent to the second surface S2 is the second surface. The storage capacitor and the bit line are located on opposite surfaces, that is, the bit line is formed on the first surface S1 of the substrate.

[0096] like Figure 2As shown, a carrier wafer 101 is provided, and the carrier wafer 101 is bonded to the first surface S1 of the substrate 100 to which the bit line is to be formed. After bonding, the carrier wafer 101 and the substrate 100 are flipped so that the second surface S2 faces vertically upward.

[0097] The substrate is thinned along the second surface S2, such as... Figure 3A and Figure 3B As shown, Figure 3A This is a top view of the thinned substrate along the S2 surface. Figure 3B for Figure 3A A cross-sectional view along the X direction. Thinning processes include, but are not limited to, dry etching, wet etching, and CMP, until the insulating material in the substrate 100 is exposed.

[0098] like Figure 4A and Figure 4B As shown, Figure 4A This is a top view along the S2 surface after the deposition of the substrate material. Figure 4B for Figure 4A A cross-sectional view along the X direction. The method for depositing bit lines 303 includes sequentially depositing one or more layers of doped polysilicon, metal silicide (e.g., titanium silicide), and tungsten on the second surface S2 of the transistor array. Then, a self-aligned double patterning (SADP) technique is used to form a... Figure 5A and 5B The semiconductor structure shown, Figure 5A This is a top view of the formed bitline structure viewed along the surface of S2. Figure 5B For along Figure 5A A cross-sectional view in the X direction. The bit line is located on the second surface S2 of the substrate 100.

[0099] Formed on the bit line 303 as follows Figure 6A and Figure 6B The bit line lead-out structure 305 is shown. Figure 6A This is a top view looking from the second surface S2 towards the first surface S1. Figure 6B For along Figure 6A A cross-sectional view along the X direction. It can be seen that the spacing between the bit lines is too small, resulting in an insufficient window distance for the bit line lead-out structure 305. This may lead to short circuits between the bit line lead-out structures 305, which in turn can cause semiconductor device failure.

[0100] This disclosure provides a method for manufacturing a semiconductor structure, the method including as follows: Figure 7 The steps shown are as follows:

[0101] Step S101: Provide substrate 100;

[0102] Step S102: A first recessed region 401 is formed from the first surface of the substrate, wherein at least two protrusions 301 are retained in the first recessed region; any two adjacent protrusions 301 have at least partially non-overlapping regions in their projections along a direction perpendicular to the extension of the protrusions 301.

[0103] Step S103: Fill the first recessed region 401 with insulating material to form a dielectric layer 304;

[0104] Step S104: Thinning is performed from the second surface S2 of the substrate 100 until the dielectric layer 304 is exposed on the second surface S2; wherein the second surface S2 is the back side of the first surface S1;

[0105] Step S105: Remove part of the protruding structure 301 from the second surface S2 to form a second recessed region 402;

[0106] Step S106: Fill the second recessed region 402 with conductive material to form bit line 303;

[0107] Step S107: A bit line lead-out structure 305 connected to the bit line 303 is formed at a position on the surface of the bit line 303 corresponding to the non-overlapping region.

[0108] For step S101 above, the following is provided: Figure 8 The substrate 100 shown has a surface that is any surface perpendicular to the substrate thickness direction. The substrate thickness direction, or the direction perpendicular to the substrate surface, is defined as the Z-direction. The thickness of the substrate along the Z-direction is H. The top or bottom surface of the substrate perpendicular to the Z-direction is a first surface S1 and a second surface S2, respectively, facing away from each other. Two intersecting X and Y directions are defined within the first surface S1 or the second surface S2 perpendicular to the Z-direction. In some embodiments, the X-direction can be the direction in which the gate of a transistor is formed, and the Y-direction can be the direction in which the bit line of a transistor is formed. The semiconductor substrate may include a P-type semiconductor material substrate, such as a silicon (Si) substrate or a germanium (Ge) substrate; an N-type semiconductor substrate, such as an indium phosphide (InP) substrate; a composite semiconductor material substrate, such as a silicon-germanium (SiGe) substrate; a silicon-on-insulator (SOI) substrate; and a germanium-on-insulator (GeOI) substrate. Furthermore, the substrate in this embodiment may also be a substrate with partially formed device structures, such as a transistor array or a substrate with some wiring, which is not limited here.

[0109] In step S102 above, the substrate is processed from its first surface S1 using etching and deposition processes to form a shape as shown above. Figure 9A and 9BThe first recessed region 401 shown is located in the substrate, wherein, Figure 9A This is a top view looking from the first surface S1 toward the second surface S2. Figure 9B For along Figure 9A A cross-sectional view along the X direction. At least two protruding structures 301 are retained in the first recessed region 401; the cross-sectional shape of the protruding structure 301 along the Z direction can be any shape, such as a rectangle, a combination of rectangles and other shapes (e.g., L-shape), etc., without limitation. The projections of any two adjacent protruding structures 301 along a direction perpendicular to the extension of the protruding structure 301 have at least partially non-overlapping regions. In some embodiments, the shapes of any two adjacent protruding structures 301 can be different, or all the protruding structures 301 in the first recessed region 401 can be different; in other embodiments, the shape of each protruding structure 301 can be completely identical. However, regardless of the specific shape of the protruding structures 301, and regardless of whether their shapes are the same or different, the projections of any two adjacent protruding structures 301 along a direction perpendicular to the extension of the protruding structure 301 (i.e., the relatively longer side of the protruding structure 301) have overlapping and non-overlapping regions. In subsequent steps, at least two protrusions 301 located in the first recessed region 401 are used to define the shape of at least two bit lines subsequently formed.

[0110] For step S103 above, the first recessed region 401 is filled with insulating material to form a dielectric layer 304, such as Figure 10A and 10B As shown, where, Figure 10A This is a top view looking from the first surface S1 toward the second surface S2. Figure 10B For along Figure 10AA cross-sectional view in the X direction. A dielectric layer 304 is present between at least two protrusions 301. The dielectric layer 304 can be formed by filling with an insulating material. The dielectric layer 304 can be formed using a growth process, such as in-situ steam generation (ISSG) in a selective growth manner. ISSG is a thermal annealing deposition method that forms a high-quality oxide film by heating in a cavity and introducing oxygen atoms to bond with atoms in the semiconductor substrate. Deposition processes can also be used, including CVD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD), etc.

[0111] In some embodiments, the filling insulating material is not only formed between the protrusions 301 but also covers the upper surface of the protrusions 301. In this case, methods including but not limited to dry etching, wet etching, and CMP can be used to process the insulating material covering the upper surface of the protrusions 301 until the upper surface of the protrusions 301 is exposed again.

[0112] In step S104 above, the substrate 100 is thinned from its second surface S2 until... Figure 11A and 11B The insulating material shown is exposed on the second surface S2; wherein, the second surface S2 is the back surface of the first surface S1; the thinning methods include, but are not limited to, etching processes and chemical mechanical polishing (CMP). Figure 11A As shown, Figure 11A This is a top view of the thinned substrate viewed from the second surface S2 towards the first surface S1. Figure 11B for Figure 11A In a cross-sectional view along the X direction, after thinning the second surface S2, the dielectric layer 304 is exposed, and the protrusion structure 301 between the dielectric layers 304 can be seen. In some embodiments, after thinning, viewed from the second surface, the dielectric layer 304 and the upper surface of the protrusion structure 301 are located in the same plane.

[0113] In step S105 above, a portion of the protrusion structure 301 is removed from the second surface S2 to form a shape as described above. Figure 12A and12B The second recessed region 402 shown; wherein, Figure 12A This is a top view taken from the direction of the second surface S2 towards the first surface S1. Figure 12B for Figure 12A A cross-sectional view along the X direction.

[0114] The portion of the protrusion structure 301 between the dielectric layers 304 is etched from the direction of the second surface S2 to form a second recessed region 402 that is recessed relative to the dielectric layers 304. In some embodiments, the portion of the protrusion structure 301 may have a conductive channel for a transistor; in other embodiments, the portion of the protrusion structure 301 may be used in a subsequent step to form a conductive channel for a transistor, the conductive channel of which may be perpendicular to the thickness direction of the substrate 100.

[0115] Regarding step S106 above, the second recessed region 402 is filled with conductive material to form a shape as shown in the figure. Figure 13A and 13B Bit line 303 is shown; where, Figure 13A This is a top view taken from the direction of the second surface S2 towards the first surface S1. Figure 13B for Figure 13A The image shows a cross-sectional view along the X-direction. A conductive material is filled in the second recessed region 402 using methods including, but not limited to, growth or deposition processes. The conductive material includes, but is not limited to, tungsten, cobalt, copper, aluminum, polysilicon (including doped polysilicon), doped silicon, metal silicides (e.g., titanium silicide), or any combination thereof. The bit line 303 can use one or more of the above conductive materials; therefore, the bit line 303 can be single-layered or multi-layered. The bit line 303 is formed in the second recessed region 402, and the second recessed region 402 is connected to the raised structure 301. A portion of the structure in the raised structure 301 can form a conductive channel for the transistor; therefore, the bit line 303 can be directly connected to the conductive channel. The bit line 303 formed in this way will not suffer from alignment failures during bit line formation due to overall warpage and local stress issues of the bit line structure to be formed.

[0116] In some embodiments, before forming the bit line 303 in the second recessed region 402, an insulating layer 302 may also be formed in the second recessed region 402. The second recessed region 402 has a plurality of opposing sidewalls, such as Figure 13CAs shown, an insulating layer 302 is formed on the plurality of sidewalls. The insulating layer 302 can be formed by a growth process or a deposition process. The formed insulating layer 302 covers the plurality of sidewalls in the second recessed region 402 and covers at least part of the protruding structure 301. After the sidewalls of the second recessed region 402 are covered by the insulating layer 302, they become trenches. Conductive material can be covered in the trenches by a growth process or a deposition process. One or more conductive materials can be used to form the bit line 303. Forming the insulating layer 302 in the second recessed region 402 helps to narrow the size of the bit line 303. The insulating layer 302 can be silicon dioxide or other insulating materials. The material of the insulating layer 302 can be the same as or different from that of the dielectric layer 304.

[0117] Regarding step S107 above, a shape is formed at the position corresponding to the non-overlapping region on the bit line surface as shown above. Figure 14A and 14B The bit line lead-out structure 305 shown is connected to the bit line. Wherein, Figure 14A This is a top view taken from the direction of the second surface S2 towards the first surface S1. Figure 14B for Figure 14A The image shows a cross-sectional view along the X direction. Since bit lines 303 are formed on protrusions 301, the shape of bit lines 303 is defined by the shape of protrusions 301. Because the projections of adjacent protrusions 301 in a direction perpendicular to their extension have overlapping and non-overlapping regions, the projections of adjacent bit lines 303 in the direction of extension of bit lines 303 (i.e., the routing direction of bit lines 303) also have overlapping and non-overlapping regions. In some embodiments, a transistor array is formed in the overlapping region of the projections of adjacent bit lines 303 in the direction of extension of bit lines 303. Bit line lead-out structures 305 connected to the bit lines 303 are formed at positions corresponding to the non-overlapping regions on the surface of the bit lines 303, such that the bit line lead-out structures 305 of two adjacent bit lines 303 are separated by overlapping regions. The bit line lead-out structures 305 are formed in the peripheral region of the transistor array. It is understood that there is at least a transistor array distance between two adjacent bit line lead-out structures 305.

[0118] In this embodiment, the window distance between adjacent bit line lead-out structures 305 is effectively increased, making it less likely for adjacent bit line lead-out structures 305 to short-circuit. Furthermore, the bit line lead-out structures 305 are formed in the peripheral region of the transistor array. By effectively utilizing the peripheral region, the performance of the device is improved without affecting the space used by the transistor array.

[0119] In some embodiments, step S102: forming a first recessed region 401 from the first surface S1 of the substrate, wherein at least two protrusion structures 301 are retained in the first recessed region 401, includes:

[0120] Step S201: A plurality of first barrier structures 403 are formed on the first surface S1 of the substrate 100;

[0121] Step S202: Etch the substrate 100 not covered by the first blocking structure 403 to form the first recessed region; wherein the substrate 100 covered by the first blocking structure 403 is retained as the at least two protruding structures 301.

[0122] Regarding step S201 above, forming on the first surface of the substrate as shown in the figure Figure 15A and 15B The plurality of first blocking structures 403 shown; wherein, Figure 15A This is a top view taken from the direction of the first surface S1 towards the second surface S2. Figure 15B for Figure 15A The image shows a cross-sectional view along the X-direction. Different patterns (structures) can be obtained on the substrate using different masks combined with photolithography processes. The pattern of the first barrier structure 403 can be the same as the pattern of the protrusion structure 301 to be formed. Compared to the material forming the first barrier structure 403, the material of the substrate 100 has a high etching selectivity (i.e., only the substrate 100 will be etched without damaging the first barrier structure 403, which is beneficial for the first barrier structure 403 to protect the underlying substrate 100). Anisotropic etching processes can be used, making the lateral etching rate much lower than the longitudinal etching rate, thereby preserving the substrate material under the first barrier structure. Etching methods include, but are not limited to, dry etching and wet etching.

[0123] In step S202 above, etching the substrate 100 that is not shielded by the first barrier structure 403 forms, as shown in... Figure 9A and 9B The first recessed region 401 shown; wherein, as Figure 9BAs shown, the substrate 100 shielded by the first blocking structure 403 retains the at least two protruding structures 301. Since the first blocking structure 403 protects the substrate 100 beneath it, the substrate 100 covered by the first blocking structure 403 is retained, while the substrate 100 not protected by the first blocking structure 403 is etched downwards to form the first recessed region 401. The retained substrate 100 under the first blocking structure 403 protrudes relative to the first recessed region 401. It is important to note that when etching the substrate 100 to form the first recessed region 401, the substrate 100 should not be etched through; that is, the etching depth should be less than the thickness of the substrate 100. If the substrate is etched through in this step, multiple discrete protruding structures composed of the remaining substrate 100 will be formed. These protruding structures may collapse due to insufficient support, which is detrimental to the subsequent filling of insulating material between the protruding structures to form the dielectric layer 304.

[0124] In some embodiments, step S201: the formation of such a structure on the first surface S1 of the substrate 100... Figure 15A and 15B The plurality of first blocking structures 403 shown include:

[0125] Step S301: Forming on the first surface of the substrate as shown in the figure Figure 16A and 16B The multiple rectangular ring-shaped second blocking structures 404 are shown;

[0126] Step S302: Cover the plurality of second blocking structures 404 with such Figure 17A and 17B The first mask layer 405 shown blocks at least a portion of each of the second blocking structures 404; wherein, there are unblocked areas on at least two opposite sides of the second blocking structure 404;

[0127] Step S303: Etch the second barrier structure 404 that is not covered by the first mask layer 405;

[0128] Step S304: Remove the first mask layer 405, wherein each unetched second barrier structure 404 includes two first barrier structures 403.

[0129] In some embodiments, such as Figure 15A and 15B As shown, the shape of the first blocking structure 403 is the same as the shape of the bit line 303 to be formed. For example, if the structure of the bit line 303 to be formed is L-shaped, then the first blocking structure 403 is L-shaped.

[0130] In some embodiments, the first barrier structure 403 can be formed using a second barrier structure 404, the second barrier structure 404 being a rectangular ring shape. Therefore, for step S301 above, a structure such as... can be formed on the first surface S1 of the substrate 100. Figure 16A and 16B The multiple rectangular annular second blocking structures 404 shown herein, wherein, Figure 16A This is a top view taken from the direction of the first surface S1 towards the second surface S2. Figure 16B for Figure 16A A cross-sectional view along the X direction.

[0131] Regarding step S302 above, in such a way Figure 16A and 16B The plurality of second blocking structures 404 shown are covered with a first mask layer 405 for shielding at least a portion of each second blocking structure 404; wherein, at least two opposite sides of the rectangular annular second blocking structure 404 have unshielded areas; as shown Figure 17A and 17B As shown, where, Figure 17A This is a top view taken from the direction of the first surface S1 towards the second surface S2. Figure 17B for Figure 17A A cross-sectional view along the X direction.

[0132] The pattern of the first mask layer 405 can be irregular, for example, it can be a zigzag shape. The first mask layer 405 needs to mask at least a portion of each of the second blocking structures 404 in order to change the shape of the second blocking structures 404 so that the formed first blocking structure 403 is different from the second blocking structure 404. The rectangular annular structure of the second blocking structure 404 has two pairs of opposite sides (a pair of long sides and a pair of short sides). In some embodiments, there are unblocked areas on the pair of long sides and / or the pair of short sides. In some embodiments, the unblocked areas are etched; in other embodiments, the blocked areas are etched.

[0133] For step S303 above, the second blocking structure 404 that is not covered by the first mask layer 405 is etched; the shape of the second blocking structure 404 is changed to the shape of the first blocking structure 403 by etching the uncovered area of ​​the rectangular ring-shaped second blocking structure 404.

[0134] For step S304 above, removing the first mask layer 405, wherein each unetched second barrier structure 404 includes two first barrier structures 403; using processes including but not limited to dry etching and wet etching, the first mask layer 405 located on the first barrier structures 403 is removed, leaving as follows: Figure 15A and Figure 15BThe first blocking structure 403 is shown. The first mask layer 405 has a high etching selectivity relative to the first blocking structure 403, and the etching method can use anisotropic etching, making the lateral etching rate much lower than the longitudinal etching rate. This allows the second blocking structure 404 under the first mask layer 405 to be retained without changing its shape due to lateral etching. The un-etched second blocking structure is composed of two first blocking structures 403. That is, after the portion of the second blocking structure 404 not blocked by the first mask layer 405 is etched, and then the first mask layer 405 is removed, two first blocking structures 403 remain. The rectangular ring structure is divided into two long sides and two short sides. In some embodiments, one first blocking structure 403 is composed of a portion of one long side and / or a portion of one short side of the rectangular ring structure; therefore, one rectangular ring structure can form two first blocking structures 403. The two first blocking structures 403 formed by each rectangular ring structure can be the same or different, and the first blocking structures 403 formed by different ring structures can also be the same or different.

[0135] In some embodiments, each unetched second barrier structure 404 includes two first barrier structures 403 that are centrally symmetrical with respect to the center of the second barrier structure 404.

[0136] Each rectangular annular second blocking structure 404 has a center, which is the intersection of the perpendicular bisector of its long side and the perpendicular bisector of its short side. In some embodiments, the two first blocking structures 403 formed after etching one second blocking structure 404 are mutually symmetrical about this center.

[0137] In some embodiments, each second barrier structure 404 can form two mutually centrally symmetrical first barrier structures 403 after being etched. The two mutually centrally symmetrical first barrier structures 403 are referred to as a first barrier structure group. However, the multiple (at least two) first barrier structure groups formed by multiple (at least two) second barrier structures 404 are not all the same.

[0138] In some embodiments, each group of first blocking structures formed by each second blocking structure 404 (e.g., consisting of L-shapes and L-shapes inverted by 180 degrees) is identical. This allows the subsequently formed bitline structures to be more regular and arranged in a more orderly manner.

[0139] In some embodiments, step S301: as Figure 16A and Figure 16B As shown, the second barrier structure 404, which forms a plurality of rectangular rings on the first surface S1 of the substrate 100, includes:

[0140] Step S401: Forming on the first surface of the substrate as shown in the figure Figure 18A and Figure 18B The multiple rectangular second mask structures 406 shown;

[0141] Step S402: Form a shape around the second mask structure 406 as shown in the image. Figure 19A and 19B The second barrier structure 404 shown surrounds the second mask structure.

[0142] In some embodiments, a plurality of rectangular annular second barrier structures 404 on the first surface S1 of the substrate 100 can be formed by the following steps: First, for step S401 above, a plurality of rectangular annular second barrier structures 404 are formed on the first surface S1 of the substrate 100 as shown in the figure. Figure 18A and Figure 18B The multiple rectangular second mask structures 406 shown can be formed using a patterned mask through a photolithography process, or they can be structures composed of materials with a high etching selectivity relative to the underlying substrate 100. The second mask structure 406 can be a parallelogram structure; in some embodiments, a rectangular structure is used.

[0143] Regarding step S402 above, a structure is formed around the second mask structure 406 as shown in the image. Figure 19A He Ru Figure 19B The second barrier structure 404 is shown surrounding the second mask structure 406. In some embodiments, the second mask structure 406 is a parallelogram with four sidewalls, and an annular structure attached to the four sidewalls can be formed on these four sidewalls by a growth process or a deposition process. This annular structure is used to constitute the second barrier structure. That is, the shape of the second barrier structure 404 is defined by the second mask structure 406. In some embodiments, the second barrier structure 404 is a rectangular annular structure.

[0144] In some embodiments, step S401: the formation of such a structure on the first surface of the substrate... Figure 18A and Figure 18B The multiple rectangular second mask structures shown include:

[0145] Step S501: Cover the first surface S1 of the substrate 100 with a second mask layer 408;

[0146] Step S502: Form a layer on the second mask layer as shown in the figure. Figure 20A and Figure 20B As shown, a rectangular photoresist layer 407;

[0147] Step S503: Remove the second mask layer 408 from the area not covered by the photoresist layer 407, and remove the photoresist layer 407; wherein, the second mask layer 408 that is not removed is the second mask structure 406.

[0148] In some embodiments, forming a plurality of rectangular second mask structures 406 on the first surface S1 of the substrate 100 can be achieved through the following steps: For step S501, a second mask layer 408 is covered on the first surface S1 of the substrate 100. The second mask layer 408 is used for the subsequent formation of the second mask structures 406. It is understood that the material of the second mask layer 408 is the same as the material of the second mask structure 406. By subsequently etching the unnecessary portions of the second mask layer 408, what remains is the second mask structure 406.

[0149] Regarding step S502 above, forming on the second mask layer 408 as shown in the figure Figure 20A and Figure 20B The rectangular photoresist layer 407 shown can be formed using photolithography. In some embodiments, photoresist is coated on the second mask layer 408 to which the second mask structure 406 is to be formed. A photomask (the pattern on the photomask is opaque) is aligned with the photoresist layer. When the photoresist is positive resist, the exposed portion of the photoresist changes from an insoluble substance to a soluble substance. The soluble portion can be removed using a chemical solvent, leaving an island area on the photoresist layer that corresponds to the opaque portion of the photomask.

[0150] The shape of this island area corresponds to the shape of the photoresist layer 407. In some embodiments, the photoresist layer 407 is rectangular. It can be understood that a rectangular photoresist layer 407 can also be formed by using negative adhesive by changing the pattern of the opaque area of ​​the photomask.

[0151] For step S503 above, the second mask layer 408 in the area not covered by the photoresist layer 407 is removed, and the photoresist layer 407 is also removed; wherein, the second mask layer 408 that is not removed is the second mask structure 406. Forming as... Figure 21A and Figure 21B The second mask structure 406 is shown. Wherein, Figure 21A This is a top view taken along the direction from S1 to S2. Figure 21B This is a cross-sectional view along the X direction. For example... Figure 20BAs shown, the photoresist layer 407 covers a portion of the second mask layer 408. The second mask layer 408 not covered by the photoresist layer 407 can be removed using processes including, but not limited to, dry etching and wet etching. Compared to the photoresist layer 407, the second mask layer 408 has a high etching selectivity (i.e., only the second mask layer 408 will be etched without damaging the photoresist layer 407, which is beneficial for the photoresist layer 407 to protect the underlying second mask layer 408). Anisotropic etching can be used, making the lateral etching rate much lower than the longitudinal etching rate, thus allowing the second mask layer 408 under the photoresist layer 407 to be preserved. Figure 18A and 18B As shown, the shape of the retained second mask layer 408, i.e. the second mask structure 406, is consistent with the shape of the photoresist layer 407. In some embodiments, the photoresist layer 407 is rectangular, so the retained second mask layer 408, i.e. the second mask structure 406, is also rectangular.

[0152] In some embodiments, the second mask layer 408 may be an amorphous carbon layer and / or a silicon oxynitride layer.

[0153] The second mask layer 408 can be a single layer made of one material or a multilayer composite layer made of multiple materials. During actual formation and etching, the composite layer is treated as a single unit. In some embodiments, the material of the second mask layer can be amorphous carbon and / or silicon oxynitride, i.e., the second mask layer can be an amorphous carbon layer and / or a silicon oxynitride layer. Using a composite layer of amorphous carbon and silicon oxynitride as the second mask layer, followed by the formation of the second mask structure, results in a high etching selectivity for the underlying substrate and makes it easier to achieve a vertical rectangular structure and minimize substrate etching.

[0154] In some embodiments, the second mask layer 408 may further include a polysilicon layer and / or an oxide layer.

[0155] In some embodiments, before step S104: the method further includes:

[0156] Step S601: Provide carrier wafer 101;

[0157] Step S602: Bond the first surface S1 of the substrate 100 to the carrier wafer 101;

[0158] Step S603: Flip the substrate 100 so that the second surface S2 faces vertically upward.

[0159] In some implementations, the substrate 100 can be directly flipped so that the second surface S2 of the substrate 100 faces upwards, and then it can be thinned. However, this can easily lead to damage to the first surface S1 of the substrate 100.

[0160] Therefore, in some embodiments, before thinning the second surface S2 of the substrate 100 in step S104, the following steps may also be included:

[0161] In some embodiments, before thinning the second surface S2 of the substrate, the first surface S1 of the substrate can be fixed to a support structure to prevent damage to the already formed transistor array structure during the thinning of the second surface S2. The support structure can be a carrier wafer, so step S601, providing the carrier wafer 101, can be performed. The carrier wafer 101 can use the same material as the substrate 100. For example, when the substrate 100 is a silicon substrate, the carrier wafer 101 can be a silicon wafer. Then, step S602 is performed to bond the first surface S1 of the substrate to the surface of the carrier wafer 101. At this time, the second surface S2 is still facing downwards. Because the second surface S2 needs to be processed subsequently, step S603, flipping the substrate 100 so that the second surface S2 faces vertically upwards, can be performed. This facilitates the subsequent thinning process from the second surface S2 in step S104.

[0162] This disclosure also provides a semiconductor structure, such as... Figure 14A and 14B As shown:

[0163] Substrate 100;

[0164] A first recessed region 401 is located on the first surface S1 of the substrate 100; at least two protrusions 301 are retained in the first recessed region 401; any two adjacent protrusions 301 have at least partially non-overlapping regions in the projection along the direction perpendicular to the extension of the protrusions 301.

[0165] Dielectric layer 304 is located in the first recessed region;

[0166] The second recessed region 402 located on the second surface S2 of the substrate 100 is located between the dielectric layers 304;

[0167] Bit line 303 is located within the second recessed region 402; bit line 303 is made of conductive material.

[0168] Bit line lead-out structure 305 is located on the non-overlapping area corresponding to the surface of bit line 303 and is connected to bit line 303.

[0169] like Figure 14A and 14B As shown, where, Figure 14A This is a top view of the semiconductor structure. Figure 14B This is a front view of the semiconductor structure along the X direction.

[0170] The semiconductor substrate 100 has a certain thickness, thus having a first surface S1 and a second surface S2 facing away from each other. Viewed from the first surface S1, the substrate has a first recessed region 401, and the first recessed region 401 contains at least two protrusion structures 301. Each protrusion structure 301 can be used to subsequently form a conductive channel for at least one transistor array. The transistor array is used to implement functions such as data storage and read / write. At least one conductive channel formed by the same protrusion structure 301 is referred to as a conductive channel group. The first recessed region 401 may have a dielectric layer 304 formed of an insulating material, i.e., different conductive channel groups are isolated by the dielectric layer 304.

[0171] Looking from the second surface S2 toward the first surface S1, the substrate 100 has a second recessed region 402, which is located among multiple dielectric layers 304, meaning that the height of the dielectric layers 304 is higher than the second recessed region 402. Below the second recessed region 402 is a protruding structure 301.

[0172] Looking from the second surface S2 toward the first surface S1, there is a bit line 303 on the protruding structure 301, that is, in the second recessed region 402. The bit line 303 is made of conductive material.

[0173] In some embodiments, the cross-sectional view of the protrusion 301 in the first recessed region 401 along the Z direction is the same as the cross-sectional view of the corresponding bit line 303 along the Z direction.

[0174] Therefore, when any two adjacent projections along the direction perpendicular to the extension of the protrusion structure 301 have at least a partially non-overlapping area, then the projections between any two adjacent bit lines 303 formed on the protrusion structure 301 along the direction perpendicular to the extension of the bit line 303 (i.e. the wiring direction of the bit line 303) also have at least a partially non-overlapping area.

[0175] Bit line 303 is located in the second recessed region 402 formed by dielectric layer 304. The second recessed region 402 is connected to the protruding structure 301. Therefore, bit line 303 is closely connected to the protruding structure 301. The protruding structure 301 may have a conductive channel. Therefore, bit line 303 can be closely connected to the conductive channel.

[0176] In some embodiments, an insulating layer 302 is also provided in the second recessed region 402, such as Figure 14CAs shown, the insulating layer 302 covers multiple sidewalls in the second recessed region 402 and at least partially covers the protruding structure 301 to form a trench with the sidewalls covered by the insulating layer 302. It is understood that the opening of the trench is smaller than the opening of the second recessed region 402. The insulating layer 302 can be silicon dioxide or other insulating materials, and the material of the insulating layer 302 can be the same as or different from that of the dielectric layer 304.

[0177] After the sidewall of the second recessed region 402 is covered by the insulating layer 302, it becomes a trench. A conductive material is then placed within the trench. One or more conductive materials can be used to form the bit line 303. For example, in some embodiments, one conductive material can be used to fill the trench until it is flush with the first end of the conductive channel. In other embodiments, three conductive materials can be used to fill the trench in stages until it is flush with the first end of the conductive channel. The opening width of the trench is the first width of the exposed first end of the conductive channel. The conductive material includes, but is not limited to, tungsten, cobalt, copper, aluminum, polycrystalline silicon, doped silicon, silicides, or any combination thereof. Therefore, the bit line 303 can include a single film layer (using one conductive material) or multiple film layers (using multiple conductive materials). This disclosure does not limit this. Multiple bit lines 303 are formed based on multiple vertically interlaced stripe structures; that is, the shape of the multiple bit lines is also a vertically interlaced stripe structure.

[0178] In some embodiments, the projections of any two adjacent bit lines 303 along a direction perpendicular to the extension of the bit line 303 have at least a partial overlap region. Therefore, the projections of adjacent bit lines 303 along the extension direction of the bit line also have overlapping and non-overlapping regions. In some embodiments, the overlapping region of the projections of adjacent bit lines 303 along the extension direction of the bit line 303 and the overlapping region of the semiconductor structure with bit lines along the extension direction of the bit line 303 also contain a transistor array. A bit line lead-out structure 305 connected to the bit line 303 is provided on the surface of the bit line 303 at a position corresponding to the non-overlapping region, such that the bit line lead-out structures 305 of two adjacent bit lines 303 are separated by the overlapping region. The bit line lead-out structures 305 are located in the peripheral region of the transistor array. It can be understood that two adjacent bit line lead-out structures 305 are at least separated by the distance of one transistor array.

[0179] In some embodiments, the transistor array can be a Vertical Channel Array Transistor (VCAT) architecture, a planar transistor architecture, or a Buried Channel Array Transistor (BCAT) architecture. VCAT offers higher storage density compared to BCAT. In VCAT, the source and drain of the transistors are located at the top and bottom of the vertical channel region. During semiconductor device fabrication, by combining wafer bonding and back-side substrate thinning techniques, bit lines or other structures can be separately positioned on two opposite sides of the wafer. For example, in Dynamic Random Access Memory (DRAM), the bit lines and capacitors of the DRAM memory array can be separately positioned on two sides of the same wafer. This simplifies the circuit layout of word lines, bit lines, and capacitors, reducing the manufacturing complexity of the semiconductor device.

[0180] In this embodiment of the disclosure, by setting the bit line lead-out structure 305 in the non-overlapping region of adjacent bit lines 303 along the bit line wiring direction, the window distance of the bit line lead-out structure 305 is effectively increased, making it difficult for the bit line lead-out structures 305 to short-circuit. Furthermore, the bit line lead-out structure 305 is formed in the peripheral region of the transistor array. By effectively utilizing the peripheral region, the performance of the device is improved without affecting the original size of the transistor array.

[0181] In some embodiments, such as Figure 14B As shown, the bit line lead-out structure 305 has a third surface S3 and a fourth surface S4 facing away from each other; wherein the third surface S3 is connected to the bit line 303; and the area of ​​the fourth surface S4 is larger than the area of ​​the third surface S3.

[0182] A bit line lead-out structure 305 is provided in the non-overlapping region of adjacent bit lines 303, and the bit line lead-out structure 305 has a third surface S3 and a fourth surface S4 facing away from each other; wherein, the third surface S3 is connected to the bit line 303; in some embodiments, the area of ​​the third surface S3 connected to the bit line 303 (the cross-sectional area along the direction parallel to the first surface) is smaller than that of the fourth surface S4 (the cross-sectional area along the direction parallel to the first surface), so that the bit line lead-out structure 305 has a larger contact area when connected to other structures, which is beneficial for energizing the bit line. The shapes of the third surface S3 and the fourth surface S4 can be circular, elliptical, rectangular, etc., and are not limited here.

[0183] In some embodiments, such as Figure 14A As shown, the two adjacent bit lines 303 are centrally symmetrical structures.

[0184] In some embodiments, two adjacent bit lines 303 are centrally symmetrical. Multiple such bit lines 303 are more regular and arranged in a more orderly manner. Thus, the bit line lead-out structures 305 formed in the non-overlapping regions of adjacent bit lines 303 are also more regular and orderly.

[0185] In some embodiments, such as Figure 22A As shown, bit line 303 can be a series of vertical stripes that intersect vertically, such as... Figure 22B As shown, bit line 303 can be an L-shape with alternating vertical lines, an L-shape inverted by 180°, or as shown in the figure. Figure 22C As shown, bit line 303 can be an alternating T-shape or an inverted T-shape at 180°.

[0186] This disclosure also provides the following examples:

[0187] In some embodiments, the bit line lead-out structure 305 may be formed by the following steps:

[0188] Formed on substrate 100 Figure 23A The rectangular annular second barrier structure 404 shown can be formed by first forming a rectangular second mask structure 406 on the substrate 100 using a photolithography process. Then, silicon oxide is deposited on the four sidewalls of the rectangular second mask structure 406 using an ALD process to form the rectangular annular second barrier structure 404. Finally, the rectangular second mask structure 406 is removed using an etching process, leaving the rectangular annular second barrier structure 404.

[0189] Then, the rectangular annular second barrier structure 404 is further processed using photolithography. Specifically, a photoresist layer is coated onto the rectangular annular second barrier structure 404, as shown below. Figure 23B The first mask layer 405, which shows an opaque rectangular pattern, is aligned with the photoresist layer, and the photoresist is exposed. The photoresist used is a positive photoresist, and the opaque rectangular pattern portion under the first mask layer 405 will be retained. After removing the photoresist layer, the opaque rectangular pattern portion overlapping with the second blocking structure 404 will remain, forming a shape as shown. Figure 23C The multiple first blocking structures 403 shown are vertical strips, and all of the multiple first blocking structures 403 are completely covered by their projections perpendicular to their extension direction. There is no area where the projections of two adjacent first blocking structures 403 perpendicular to their extension direction are not covered.

[0190] Multiple bit lines 303 are formed based on multiple first barrier structures 403. In some embodiments, the first barrier structures 403 can be exposed by etching the entire active region of the second surface S2 of the substrate 100. Then, the first barrier structures 403 are further etched to form a second recessed region 402, and then the bit lines 303 are formed in the second recessed region 402. It can be seen that the window distance left for the bit line lead-out structure 305 is very small, and only a small number of bit lines can be formed. Figure 23D The multiple bit line lead-out structures 305 shown are illustrated.

[0191] Such adjacent bit line lead-out structures 305 are prone to short circuits, which can even lead to semiconductor device failure.

[0192] In some embodiments, the bit line lead-out structure 305 may also be formed by the following steps:

[0193] Formed on substrate 100 Figure 24A The rectangular annular second barrier structure 404 shown can be formed by first forming a rectangular second mask structure 406 on the substrate 100 using a photolithography process. Then, silicon oxide is deposited on the four sidewalls of the rectangular second mask structure 406 using an ALD process to form the rectangular annular second barrier structure 404. Finally, the rectangular second mask structure 406 is removed using an etching process, leaving the rectangular annular second barrier structure 404.

[0194] Then, the rectangular annular second barrier structure 404 is further processed using photolithography. Specifically, a photoresist layer is coated onto the rectangular annular second barrier structure 404, as shown below. Figure 24B An opaque, jagged first mask layer 405, with a serrated shape relative to the top and bottom of a rectangle, is aligned with the photoresist layer, and the photoresist is exposed. The photoresist used is a positive photoresist. The opaque rectangular pattern portion under the first mask layer 405 will be retained. After removing the photoresist layer, the opaque rectangular pattern portion overlapping the second blocking structure 404 will remain, forming a shape as shown. Figure 24C The multiple first blocking structures 403 shown are vertical strips arranged in an alternating pattern. There are overlapping and non-overlapping areas between any two adjacent first blocking structures 403 when projected along their extension direction perpendicular to their extension direction.

[0195] It is understood that the shape of the first mask layer 405 is not limited to a jagged shape with concave and convex sides relative to a rectangle; the shape of the first mask layer 405 can be changed according to the shape of the first blocking structure.

[0196] A first recessed region 401 is formed from the first surface S1 of the substrate 100 based on a plurality of first barrier structures 403, wherein at least two protruding structures 301 are retained in the first recessed region 401; any two adjacent protruding structures 301 have at least partially non-overlapping regions in the projection along the direction perpendicular to the extension of the protruding structures; and insulating material is filled in the first recessed region to form a dielectric layer 304.

[0197] Then, thinning is performed from the second surface S2 of the substrate 100 until the dielectric layer is exposed on the second surface. A portion of the protruding structure is further removed from the second surface S2 of the substrate 100 to form a second recessed region 402. Conductive material is filled into the second recessed region 402 to form bit lines 303. Therefore, the shapes of the plurality of bit lines 303 are based on the shapes of the plurality of first blocking structures 403.

[0198] Continue to form at the position corresponding to the non-overlapping region on the surface of bit line 303, as shown in the figure. Figure 24D The bit line lead-out structure 305 shown is such that two adjacent bit line lead-out structures 305 are separated by the overlapping region between adjacent bit lines. A transistor array can be formed in the overlapping region between adjacent bit lines, that is, the bit line lead-out structure 305 is formed in the peripheral region of the transistor array. It can be understood that two adjacent bit line lead-out structures 305 are separated by at least the distance of a transistor array. Therefore, the semiconductor structure formed by the embodiments of this disclosure effectively increases the window distance of the bit line lead-out structures 305, making it difficult for the bit line lead-out structures 305 to be short-circuited, and effectively ensuring the performance of the device.

[0199] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0200] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0201] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: Provide substrate; A first recessed region is formed from a first surface of the substrate, and at least two protruding structures are retained in the first recessed region; any two adjacent protruding structures have at least partially non-overlapping projections along a direction perpendicular to the extension of the protruding structure. The first recessed region is filled with insulating material to form a dielectric layer; Thinning is performed from the second surface of the substrate until the dielectric layer is exposed on the second surface; wherein the second surface is the back side of the first surface; A portion of the protruding structure is removed from the second surface to form a second recessed region; The second recessed region is filled with conductive material to form a bit line; A bit line lead-out structure connected to the bit line is formed at a position on the bit line surface corresponding to the non-overlapping region.

2. The method according to claim 1, characterized in that, The first recessed region is formed from the first surface of the substrate, and the first recessed region retains at least two protruding structures, including: A plurality of first barrier structures are formed on the first surface of the substrate; The substrate not covered by the first barrier structure is etched to form the first recessed region; wherein the substrate covered by the first barrier structure is retained as the at least two protruding structures.

3. The method according to claim 2, characterized in that, The formation of a plurality of first barrier structures on the first surface of the substrate includes: Multiple rectangular ring-shaped second barrier structures are formed on the first surface of the substrate; A first mask layer is applied to the plurality of second blocking structures to cover at least a portion of each second blocking structure; wherein, at least two opposite sides of the second blocking structure have unmasked areas; Etch the second barrier structure that is not covered by the first mask layer; Remove the first mask layer, wherein each of the unetched second barrier structures comprises two of the first barrier structures.

4. The method according to claim 3, characterized in that, Each of the unetched second barrier structures comprises two first barrier structures that are centrally symmetrical with respect to the center of the second barrier structure.

5. The method according to claim 3, characterized in that, The second barrier structure, which forms a plurality of rectangular rings on the first surface of the substrate, includes: Multiple rectangular second mask structures are formed on the first surface of the substrate; A second barrier structure is formed around the second mask structure.

6. The method according to claim 5, characterized in that, The second mask structure, which forms a plurality of rectangular shapes on the first surface of the substrate, includes: A second mask layer is applied to the first surface of the substrate; A rectangular photoresist layer is formed on the second mask layer; Remove the second mask layer from the area not covered by the photoresist layer, and remove the photoresist layer; wherein the second mask layer that is not removed is the second mask structure.

7. The method according to claim 1, characterized in that, Prior to the thinning from the second surface of the substrate, the method further includes: Provides carrier wafers; The first surface of the substrate is bonded to the carrier wafer; Flip the substrate so that the second surface faces vertically upward.

8. A semiconductor structure, characterized in that, The semiconductor structure includes: Substrate; A first recessed region located on the first surface of the substrate; at least two protruding structures are retained in the first recessed region; any two adjacent protruding structures have at least partially non-overlapping projections along a direction perpendicular to the extension of the protruding structure. The dielectric layer is located in the first recessed region; A second recessed region located on the second surface of the substrate, situated between the dielectric layers; Bit lines are located within the second recessed region; the bit lines are made of conductive material. The bit line lead-out structure is located on the non-overlapping region corresponding to the bit line surface and is connected to the bit line.

9. The semiconductor structure according to claim 8, characterized in that, The bit line lead-out structure has a third surface and a fourth surface facing away from each other; wherein the third surface is connected to the bit line; and the area of ​​the fourth surface is larger than the area of ​​the third surface.

10. The semiconductor structure according to claim 8, characterized in that, The two adjacent bit lines are centrally symmetric structures.

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