Modify parity data using poison data units

Abstract

The present invention relates to systems, apparatus, and methods related to modifying parity data using poisonous data units. An example method may include receiving, from a controller of a memory device, a first set of bits including data and a second set of at least one bit indicating whether the first set of bits includes one or more erroneous or corrupted bits. The method may further include generating, at an encoder of the memory device, parity data associated with the first set of bits. The method may further include generating, at logic of the memory device, modified parity data with the parity data and the second set of at least one bit. The method may further include writing the first set of bits and the modified parity data in an array of the memory device.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor memories and methods, and more particularly, to apparatus, systems, and methods for modifying parity data using poison data units. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory can provide persistent data by retaining stored data when power is not supplied and can include NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host when the computer or electronic system is operating. For example, data, commands, and / or instructions may be transferred between the host and the memory device during operation of the computing or other electronic system. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a functional block diagram of a computing system in the form of a memory system including a controller and a memory device according to several embodiments of the present disclosure.

[0005] Figure 2 is a functional block diagram of a computing system in accordance with several embodiments of the present disclosure.

[0006] Figure 3 is a diagram illustrating bit patterns according to several embodiments of the present disclosure.

[0007] Figure 4 is a functional block diagram illustrating encoding parity data into modified parity data according to several embodiments of the present disclosure.

[0008] Figure 5 is another functional block diagram illustrating decoding of modified parity data according to several embodiments of the present disclosure.

[0009] Figure 6 is a flow chart representing an example method for encoding parity data using poison data units according to several embodiments of the present disclosure.

[0010] Figure 7 is a flow chart representing an example method for decoding modified parity data using poison data units according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] Systems, devices, and methods related to modifying parity data using poison data units are described. In some embodiments, a controller may receive data and poison data units associated with the data. An encoder component may generate parity data associated with the data. The controller may combine the parity data with the poison data units to generate modified parity data associated with the data. The modified parity data may be stored in a memory cell array.

[0012] The data received from the host (e.g., received to the memory system) may be incorrect or corrupted. Such incorrect or corrupted data may be referred to as "toxic data". A toxic data unit (e.g., a bit) may be used to indicate whether the received data is toxic data. The toxic data unit may be received, for example, as part of a write command. As an example, a toxic bit value of "1" may indicate that the data received corresponding to the write command is toxic data, and a toxic bit value of "0" may indicate that the data received corresponding to the write command is not toxic data. Embodiments are not limited to this. For example, a toxic bit value of "0" may be used to indicate toxic data, and a bit value of "1" may be used to indicate that the data is not toxic data.

[0013] In some prior art methods, a memory cell array may store poisonous data units associated with different portions of data that may or may not be poisonous data (depending on the value of the poisonous data unit). For example, in these prior art methods, X data bits may be received, and Z error correction code (ECC) bits may be generated from the X data bits. In a scenario where ECC protected data is stored without determining whether the data is poisonous, X+Z=Y bits may be stored. In a scenario where poisonous data is monitored, Y+1 bits may be stored, where the "+1" bit is a poisonous bit indicating whether the data is poisonous data (e.g., "1" indicates that the data is poisonous, and "0" indicates that the data is not poisonous).

[0014] However, as will be further described below, the poisonous data unit may not be stored directly in the memory array or memory device. For example, the poisonous data unit may be combined or incorporated into the parity data associated with the transmitted data, and thereby save the memory space that would otherwise store the individual poisonous data units. This will include storing Y bits (X data bits + Z ECC bits), while the ECC still protects the data and indicates whether the data is poisonous data. The poisonous data can be determined by reading these Y bits. In this way, the amount of space used to store a specific portion of the data in the memory array can be minimized. In other words, the data and its associated parity data can be stored in a specific amount of memory space. The specific amount of memory space can also be combined or incorporated into the poisonous data unit by combining or incorporating the parity data and storing the parity data in the same amount of memory space as when the parity data is not combined or incorporated into the poisonous data unit to store the poisonous data unit.

[0015] As described in more detail herein, a controller coupled to a memory device may receive a portion of data and associated poisonous data units from an external device (e.g., a host or some other external memory device). The data may be encoded, and parity data may be generated for protecting the data. The received poisonous data units may be incorporated into the parity data to maintain whether the data is poisonous without storing the individual poisonous data units themselves. The data and modified parity data may be stored in the memory device. In response to an external device requesting that the data be transmitted back to the external device, the modified parity data may be decoded, as will be described below, and the data and poisonous data units may be transmitted back to the external device. In this way, the data and its associated poisonous data units may be maintained without storing the individual poisonous data units in the memory device, thereby saving more memory space.

[0016] In some embodiments, the memory system including the memory device may be a Compute Express Link (CXL) compatible memory system (e.g., the memory system may include a PCIe / CXL interface). CXL is a high-speed central processing unit (CPU)-to-device and CPU-to-memory interconnect designed to accelerate next-generation data center performance. CXL technology maintains memory coherency between the CPU memory space and the memory on the attached device, which allows resource sharing to achieve higher performance, reduce software stack complexity, and reduce overall system cost.

[0017] CXL is designed as an industry open standard interface for high-speed communications as accelerators are increasingly used to complement CPUs to support emerging applications such as artificial intelligence and machine learning. CXL technology is built on the Peripheral Component Interconnect Express (PCIe) infrastructure, leveraging the PCIe physical and electrical interfaces to provide advanced protocols such as input / output (I / O) protocols, memory protocols (e.g., initially allowing the host and accelerator to share memory), and coherent interfaces in the domain.

[0018] In the following detailed description of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which are shown by way of illustration how one or more embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is understood that other embodiments may be utilized and that process changes, electrical changes, and structural changes may be made without departing from the scope of the present disclosure.

[0019] As used herein, designators such as "N," "M," and the like, particularly with respect to reference element symbols in the figures, indicate that the number of particular features so designated may be included. It should also be understood that the terminology used herein is only for describing specific embodiments and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" may include both singular and plural referents unless the context clearly indicates otherwise. In addition, "several," "at least one," and "one or more" (e.g., a number of memory banks) may refer to one or more memory banks, while "a plurality" is intended to refer to more than one such thing.

[0020] In addition, the words "can" and "may" are used throughout this application in a permissive (e.g., possible, able to) rather than mandatory (e.g., must) sense. The term "include" and its derivatives mean "include (but not limited to)". As the context requires, the terms "coupled" and "coupled" mean physically connected directly or indirectly or used to access and move (transmit) commands and / or data.

[0021] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 111 may refer to Figure 1 Element "11" in , and similar elements in Figure 21. A group or a plurality of similar elements or components may generally be referred to herein by a single element number. For example, a plurality of reference elements 130-1 to 130-N may be collectively referred to as 130. It should be understood that the elements shown in various embodiments herein may be added, exchanged and / or eliminated to provide several additional embodiments of the present disclosure. In addition, the proportions and / or relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be understood in a limiting sense.

[0022] Figure 1 is a functional block diagram of a computing system 100 in the form of an apparatus including a memory system 110, including a controller 115 and memory devices 130-1 through 130-N, in accordance with several embodiments of the present disclosure. As used herein, an "apparatus" may refer to, but is not limited to, any of a variety of structures or combinations of structures, such as, for example, a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. Figure 1 In the embodiments described in the accompanying drawings, the memory device 130 may include one or more memory modules (e.g., a single in-line memory module, a dual in-line memory module, etc.). The memory device 130 may include volatile memory and / or non-volatile memory. In several embodiments, the memory devices 130 may each include a multi-chip device. The multi-chip device may include several different memory types and / or memory modules. For example, the memory system may include non-volatile or volatile memory on any type of module.

[0023] The memory device 130 may provide main memory for the computing system 100 or may be used as additional memory or storage for the entire computing system 100. The memory device 130 may include one or more arrays of memory cells (e.g., volatile and / or non-volatile memory cells). The array may be, for example, a flash array having a NAND architecture. Embodiments are not limited to a particular type of memory device. For example, the memory device may include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, among others. Although shown as a single memory device 130, it should be understood that multiple memory devices are contemplated within the scope of the present disclosure.

[0024] In embodiments where the memory device 130 includes persistent or non-volatile memory, the memory device 130 may be a flash memory device, such as a NAND or NOR flash memory device. However, embodiments are not limited thereto, and the memory device 130 may include: other non-volatile memory devices, such as non-volatile random access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM); "emerging" memory devices, such as ferroelectric RAM devices including ferroelectric capacitors that may exhibit hysteresis characteristics, 3-D cross point (3D XP) memory devices, etc.; or combinations thereof.

[0025] As an example, a ferroelectric RAM device may include a ferroelectric capacitor and may perform bit storage based on the amount of voltage or charge applied thereto. In such an example, relatively small and relatively large voltages allow the ferroelectric RAM device to exhibit properties similar to normal dielectric materials (e.g., dielectric materials with relatively high dielectric constants), but at various voltages between the relatively small and relatively large voltages, the ferroelectric RAM device may exhibit polarization reversal that produces nonlinear dielectric behavior.

[0026] As another example, a 3D XP non-volatile memory array can perform bit storage based on bulk resistance changes in conjunction with a stackable crossbar data access array. Additionally, in contrast to many flash-based memories, 3D XP non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells.

[0027] In some embodiments, the controller 115 may be a media controller, such as a non-volatile memory express (NVMe) controller. For example, the controller 115 may be configured to perform operations such as copying, writing, reading, error correction, etc. for the memory device 130. In addition, the controller 115 may include dedicated circuit systems and / or instructions to perform the various operations described herein. That is, in some embodiments, the controller 115 may include circuit systems and / or instructions that can be executed to modify parity data using poisonous data units (also referred to herein as the second group of at least one bit, where the second group of at least one bit indicates whether the first group of bits includes one or more erroneous or damaged bits). In some embodiments, the circuit systems and / or instructions provided to the controller 115 may control the modification of parity data using poisonous data units and the storage of the data (also referred to herein as the first group of bits including data) and the modified parity data in the memory device 130.

[0028] In some embodiments, the control circuit system 114 within each of the memory devices 130 may be configured to perform operations such as copying, writing, reading, error correction, etc. The control circuit system 114 may include an ECC component 107. The ECC component 107 may operate based on various types of ECC codes, such as Hamming codes, Reed-Solomon (RS) codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, cyclic redundancy check (CRC) codes, Golay codes, Reed-Muller codes, Goppa codes, and Denniston codes, among others. As a non-limiting example, the ECC component 107 may operate based on a Hamming code and generate parity symbols (as ECC symbols). The ECC component 107 may include circuit systems and / or firmware to perform ECC operations. ECC component 107 may include an ECC encoder ("ENC") 111 and an ECC decoder 113. ECC encoder 111 may include logic and / or circuitry that may cause parity data to be modified so as to include poisonous data within the modified parity data. ECC decoder ("DEC") 113 may include logic and / or circuitry that may cause parity data to be decoded (as will be described below in conjunction with Figure 4 120 ) to extract the poisonous data units for providing to the external device and / or the logic and / or circuit system of the host 120 .

[0029] In a non-limiting example, an apparatus (e.g., computing system 100 or memory system 110) includes a memory system controller 115 and memory devices 130-1 to 130-N. Controller 115 may receive data from an external device (e.g., host 120), and the data may include poison data, such as poison data units, which indicate whether a particular portion of the data is poisonous (e.g., corrupted or incorrect). In some embodiments, host 120 may send write requests to memory system 110 and cause data associated with each of the write requests to be written to a cache (not illustrated) and / or to memory device 130. In some embodiments, controller 115 may receive write requests at a rate of thirty-two (32) gigatransfers per second (e.g., in some embodiments, controller 115 may receive write requests according to a CXL protocol). Controller 115 may also receive read requests and cause data stored in memory device 130 to be retrieved and written to, for example, host 120. A cache associated with memory system 110 may include a plurality of cache lines, which may each be configured to store approximately sixty-four (64) bytes of data. However, embodiments are not limited to this particular cache line size, and the cache line size may be selected to correspond to a line size associated with an external processing device (eg, a CPU of host 120).

[0030] The memory system controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory system controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory system 110, including handling communications between the memory system 110 and the host system 120.

[0031] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory system controller 115, but in another embodiment of the present invention, the memory subsystem 110 does not include a memory system controller 115, but may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory system).

[0032] In general, the memory system controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory system controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs)) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with the memory device 130. The memory system controller 115 may further include a host interface circuit system that communicates with the host system 120 via a physical host interface (e.g., the PCIe / CXL interface described above). The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0033] like Figure 1 1, host 120 may be coupled to memory system 110 via interface 103. Interface 103 may be any type of communication path, bus, or the like that allows information to be transferred between host 120 and memory system 110. Non-limiting examples of interfaces may include a peripheral component interconnect (PCI) interface, a peripheral component interconnect express (PCIe) interface, a serial advanced technology attachment (SATA) interface, and / or a micro serial advanced technology attachment (mSATA) interface, among others. However, in at least one embodiment, interface 103 is a PCIe 5.0 interface that complies with the Compute Express Link (CXL) protocol standard. Thus, in some embodiments, interface 103 may support a transfer speed of at least 32 gigabit transfers per second.

[0034] In some embodiments, the interface 103 may be configured so that signaling may be selectively transmitted via the interface 103 according to a variety of protocols. For example, signaling may be selectively transmitted via the interface 103 according to a cache protocol in which data is transmitted between the host and the memory system 110 and a memory protocol in which data is transmitted between the host and the memory device 130. In some embodiments, the cache protocol may be invoked to effectively cache data associated with the host memory 105 according to a request and response method. In contrast, the memory protocol may be invoked to provide access to the memory device 130 by the host using read / write commands, wherein the host processor acts as a primary device and the memory device 130 acts as a secondary (e.g., slave) device.

[0035] In several embodiments, memory device 130 may reside on memory system 110, however, embodiments are not limited thereto, and in some embodiments, memory device 130 may be external to memory system 110. Furthermore, more than one memory device may be included in computing system 100, such as Figure 1 As used herein, the term "resides on" refers to something that is physically located on a particular component. For example, memory device 130 "resides on" memory system 110 refers to a condition in which memory device 130 is physically within memory system 110. In this document, the term "resides on" may be used interchangeably with other terms such as "deployed on" or "located on."

[0036] The host 120 may include a host memory and a central processing unit (not illustrated). The host 120 may be a host system, such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, a memory card reader, and / or a device with Internet of Things (IoT) capabilities, as well as various other types of hosts, and may include a memory access device, such as a processor (or processing device). It should be understood by those skilled in the art that a "processor" may mean one or more processors, such as a parallel processing system, a number of coprocessors, etc.

[0037] Host 120 may include a system motherboard and / or backplane and may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). System 100 may include separate integrated circuits, or host 120, memory system 110, controller 115, and memory device 130 may be on the same integrated circuit. System 100 may be, for example, a server system and / or a high performance computing (HPC) system and / or a portion thereof. Although Figure 1 The example shown in illustrative embodiments illustrates a system having a Von Neumann architecture, but embodiments of the present disclosure may be implemented in a non-Von Neumann architecture, which may not include one or more components (eg, CPU, ALU, etc.) typically associated with a Von Neumann architecture.

[0038] Figure 1 Embodiments of the present disclosure may include additional circuitry that is not illustrated so as not to obscure the embodiments of the present disclosure. For example, the memory controller 110 may include address circuitry for latching address signals provided by the I / O circuitry via the I / O connections. The address signals may be received and decoded by the row decoder and the column decoder to access the memory device 130. Those skilled in the art will appreciate that the number of address input connections may depend on the density and architecture of the memory device 130.

[0039] Figure 22 is a functional block diagram of a computing system 201 including a host portion 221 and a memory portion 223, the memory portion 223 including an array 230, an ECC encoder 211, a parity modifier component 222, and an ECC decoder 213, according to several embodiments of the present disclosure. The host portion 221 indicates a parity modifier component 222 from a host (e.g., Figure 1 host 120 in the memory portion 223 (e.g., to Figure 1 130 in the memory device 130). Dashed lines are illustrated, where arrows crossing the dashed lines indicate that communication has occurred between the host and the memory device, both to and from the memory device and from and to the host. Although the host is described in this example, the embodiments are not limited thereto. For example, a separate host from the memory device (e.g., Figure 1 An external device (separate from the memory device 130 in the memory device) can communicate with the memory device.

[0040] In some embodiments, data may be sent from a host (e.g., from host 221) to a memory device (e.g., to memory 223). Poison data unit 227 (also referred to herein as the second set of at least one bit) may be sent from the host as part of a write command. The value of the poison data unit (e.g., "1" or "0") indicates whether the data (e.g., data 225, also referred to as the first set of bits containing the data) is poison data. Figure 2 In the example shown in , data 225 is poisonous data, so the poisonous data unit (bit) will have a value of "1" (assuming that "1" indicates poisonous and "0" indicates non-toxic).

[0041] Although the data is described as poisonous data associated with a specific value of a poisonous data unit (e.g., binary "1") in this example, the example is not limited thereto. For example, in another example, the received data 225 may not be poisonous data, in which case the value of the poisonous data unit may be a different bit value (e.g., binary "0"). In an example where the data 225 is non-toxic, the parity data 229 may not be modified. That is, in this example, if the data is poisonous, the parity data 229 will be modified, and if the data is non-toxic, the parity data 229 will not be modified. In addition, the poisonous data 225 may be sent from the host to the ECC encoder 211 and to the array 230 of the memory cells of the memory device. The ECC encoder 211 may generate parity data from the received poisonous data. The parity data 229 transmitted from the ECC encoder 211 to the parity modifier component 222 does not yet indicate whether the poisonous data 225 is poisonous (e.g., the parity data 229 has not yet been incorporated into the poisonous data unit).

[0042] Parity modifier component 222 can be hardware (e.g., circuitry, combinational circuitry, circuitry with a state machine, etc.), firmware, and / or software configured to perform operations to generate modified parity data 231. Parity modifier component 222 can receive parity data 229 and poisonous bits 227 and modify parity data 229 using poisonous bits 227, as described below with reference to FIG. Figure 4 Modified parity data 231 may be sent to array 230 along with poisoned data 225 to be stored in memory cells of array 230 .

[0043] In response to an external device (e.g., a host) requesting data from array 230, data (in this example, poisonous data) 235-1 may be sent to ECC decoder 213 along with modified parity data 233. In the event that modified parity data 231 sent to array 230 is correctly stored and transmitted out of array 230 without error, modified parity data 231 will be identical to modified parity data 233. Likewise, poisonous data 235-1 will be identical to poisonous data 225 as long as poisonous data 225 is correctly stored in array 230. ECC decoder 213 may decode modified parity data 233 and poisonous data 235-1 (as will be described below in conjunction with Figure 4 ) in order to transmit the poison data 235 - 2 and the poison bit 227 back to the host.

[0044] In some embodiments, the Figure 2 The ECC in the system described in may use an extended shortened Hamming code. The original binary Hamming code may be used with parameters N=511, K=502, where N (or n) is the size (or length) of the codeword including parity data, and K (or k) is the size (or length) of the codeword data without parity data (N and K refer to the values ​​of the original binary Hamming code, while n and k refer to the values ​​of the shortened binary Hamming code). The Hamming code may be generated by shortening or reducing the original 511 positions of the code by 245 positions to match the data payload, where k=257 (256 data bits + 1 flip bit). An extension of the Hamming code may include adding a checksum bit, resulting in a code including parameters n=267, k=257, where there are 10 parity bits including 1 checksum bit. As an example, the data payload may be a factor of a page of data, such as in terms of the amount of data accessed in a single operation (e.g., a read or write operation). The data payload may be the size used by the ECC decoder to make corrections to the data. The size of the data payload can affect the decoding latency of the data.

[0045] The encoding operation may include performing a calculation p=d'R', where p is a 9-bit parity row vector, d' is a 257-bit data row vector, and R' is an encoding matrix having 257 rows and 9 columns. The rows of R' may be a subset of all non-zero patterns having 9 binary elements. Each pattern may correspond to a data position, and the pattern linked to the shortened position may not be in R'. The decoding operation of decoding the data and the corresponding parity data may include calculating a syndrome, which may be a 9-bit vector. In response to the syndrome matching a pattern in R', it may be determined that the position corresponding to that pattern contains an error, such as with Figure 3 More specifically stated in relation.

[0046] Figure 3 334-4, 334-5, 334-6, 334-7, 334-8, 334-9, 334-10, 334-20, 334-30, 334-40, 334-11, 334-20, 334-31, 334-40, 334-32, 334-41, 334-12, 334-23, 334-33, 334-41, 334-13, 334-40, 334-31, 334-40, 334-14, 334-25, 334-32, 334-41, 334-33, 334-41, 334-15, 334-33, 334-41, 334-16, 334-27, 334-34, 334-41, 334-33, 334-41, 334-33, 334-41, 334-33, 334-41, 334-17, 334-34, 334-41, 334-34 ... 3 The 33rd column 336 may correspond to a flipped bit and may not include a pattern like the other previous 32 columns (e.g., the columns of the first section 332-1 and the second section 332-2). Due to the flipped bit at the last column 336, the poisonous data unit of the data may not be indicated by inverting the data because the decoder can only correct the flipped bit.

[0047] In this example of encoding and decoding, a 9-bit pattern called p* can be used to incorporate poisonous data units into the parity data. For example, the 9-bit pattern p* corresponds to a pattern that does not exist in the table mentioned above. As an example, p*=000010001 (which will not exist in the table mentioned above). The modification of the parity data can be performed by the following formula:

[0048] p m =p+p*

[0049] In this way, the ECC decoder can correct the shortened position corresponding to p*. If the above formula is performed on the data and parity data and p* matches the predetermined p*, then a specific poisonous data unit is detected for the data (eg, if a specific poisonous data unit is detected, the data is indicated as poisonous).

[0050] In some embodiments, the p* pattern is used in the following manner. The pattern p* is a pattern associated with a shortened position, i.e., p*=[0,0,0…1…0]R. When the user data u reaches the encoding operation, its parity p=[u,f,0]R is calculated. However, we add p* to the initial parity data to modify the parity data, so that we add p* to the initial parity data. c =p+p* is stored in the array. Therefore, p+p*=[u,f,0…1…0]R, that is, p c is the parity that the encoder will calculate if there is already an error in the shortened position. For this reason, when the decoder receives the codeword [p c ,u,f,0] (0 is actually implicit), the decoder calculates the syndrome and obtains S = p c +[u,f,0]R=p c +p = p*. If the decoder adds pattern recognition logic for p*, then the error in the shortened position can be detected, ie, we explicitly detect parity corruption in the poisoned bits.

[0051] In one embodiment, X data bits are received, and Z error correction bits (ECC) bits are generated from the X data bits. The sum of the X data bits and the Z ECC bits is equal to Y bits. Although Y bits will be stored about the X data bits received in the scenario where there is no poisonous data to be monitored, in the example described in this article, Y bits will still be stored about the X data bits received. In addition, no extra bits are stored to indicate whether the received data is poisonous data. Moreover, if the received data is poisonous data, Y bits are stored, and if the received data is not poisonous data, Y bits are still stored. The number of bits read from the array is the same, whether the data is poisoned and whether we determine whether the data is poisonous by decoding that same number (Y) bits.

[0052] Figure 4 4 is a functional block diagram illustrating encoding parity data into modified parity data according to several embodiments of the present disclosure. A plurality of parity bits 441-0 (p0) to 441-8 (p8) and a checksum bit 445, which may be collectively referred to as a parity bit 441, are modified using a poisonous bit 427. The parity bit 441 and the checksum bit 445 constitute the above-mentioned Figure 2 Parity bit 441 is modified using poison bit 427 and a checksum bit ("csb") to produce modified parity bit 443-0 (p m ,0) to 443-8(p m ,8).

[0053] As an example, if Figure 4As shown in FIG. 4 , the ninth parity bit 441-8 (p8) may be XORed with the poisoned bit 427 (indicated by XOR gate 442) to produce a ninth modified parity bit p m ,8 443-8. Similarly, the fifth parity bit p4 441-4 may be XORed with the poisoned data unit 427 (indicated by XOR gate 444) to produce a fifth modified parity bit p m ,4 443-4. In addition, the checksum bit ("csb") 445 may be modified by performing an XOR operation (indicated by XOR gate 446) on the poisonous data unit 427 and the checksum bit 445, thereby generating a modified checksum bit ("csb m ”)447. These operations are not described in detail but are Figure 4 The results of those operations described in may be used during the decoding operation described below with Figure 4 Further described in association.

[0054] Figure 5 is another functional block diagram illustrating decoding of modified parity data according to several embodiments of the present disclosure. Figure 5 Before performing the logic operation indicated by the logic gates illustrated in , the syndrome of the modified parity data described above is determined. In some examples, using a Hamming code may include checking for errors in the data by checking all parity bits. An error pattern called an error syndrome identifies the bit with an error. If all parity bits are correct, then there is no error. Otherwise, the sum of the positions of the parity bits with an error may identify the bit with an error. For example, if the parity bits in positions 1, 2, and 8 indicate an error, then bit 1+2+8=11 is in error. If only one parity bit indicates an error, then the parity bit itself is in error.

[0055] like Figure 5 As shown in FIG. 1 , syndrome 551 (S), predetermined pattern 555 (p*) and decoder (e.g. Figure 1The error vector 557(e) generated by the decoder 113 in FIG. 5 may be used to determine the poisonous bit 527 corresponding to the data. For example, the syndrome 551 may be used as an input to a number of logic gates, such as a NOR gate 556-1, an OR gate 552-1, and a XOR gate 554-1. The pattern 555 may be used as an input to the XOR gate 554-1 together with the syndrome 551. The result of the XOR gate 554-1 is used as an input to the OR gate 552-2. In this example, the error vector 557 is used as an input to the XOR gate 554-2. In addition, the sum of the checksum bits 553 is used as an input to the NOT gate 558. The results of the NOR gate 556-1 and the NOT gate 558 are used as inputs to the AND gate 559-1. Moreover, the sum of the check bits 553 and the results of the OR gates 552-1, 552-2, and the XOR gate 554-2 is used as an input to the AND gate 559-2. The result of XOR gate 554-2 may be referred to as an erroneous parity check (w e ). As an example, the parity (even or odd) of a binary vector v can be defined as a binary value: w(v) mod 2), where w(v) is a weighting function, i.e., a function of the number of "1"s in the return vector. Therefore, if the number of "1"s in the vector is even, the parity is "0", and if the number of "1"s in the vector is odd, the parity is "1". For example, the parity of [0110100101010010] is "1". In other words, the parity is a bit ("0" or "1") concatenated to the vector in order to obtain a vector consisting of an even number of "1". The results of AND gates 559-1, 559-2 are used as inputs to XOR gate 556-2. The result of XOR gate 556-2 is poisonous bit 527. In this way, the modified parity bit can be decoded to obtain poisonous bit 527.

[0056] and Figure 5 The operations described in association may indicate that specific characteristics of data are stored in memory and transferred out of memory. For example, it may be determined whether the data is toxic, whether the data contains a specific number of errors, etc. Table 1 illustrates such determinations:

[0057]

[0058] Table 1

[0059] For example, in the case where S=0 and the differential checksum=0, it can be determined that the data is regular data with zero errors. Likewise, in the case where S=0 and the differential checksum=1, it can be determined that the data is poisonous, where the data is poisonous data from the host or contains more than 1 error. In the case where the differential checksum is 1 and S≠0 or p*, a unique case occurs. In this example, if w e=1, then the data can be considered as regular data with 1 error. In this example, if w e =0, then the data can be considered as poisonous data from the host.

[0060] Figure 6 is a flow chart representing an example method for encoding parity data using poisonous data units according to several embodiments of the present disclosure. Method 660 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 660 is performed by Figure 1 115 described in the embodiment of the present invention. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, in various embodiments, one or more processes may be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0061] At block 661, method 660 may include receiving, from a controller at logic of a memory device, a first set of bits including data and a second set of at least one bit associated with the first set of bits (eg, a poison data unit). The controller may be similar to that described herein. Figure 1 The memory device may be similar to the controller 115 in this article. Figure 1 In some examples, a first group of bits and at least one bit of a second group (e.g., poison data) are received via a compute fast link (CXL) compatible interface. The value of the poison data unit may indicate whether the first group of bits has been corrupted or has become uncorrectable. The first group of bits (e.g., data) may be determined to be uncorrupted or corrupted based on the value of the poison data unit. For example, in some examples, a poison bit value of "1" may be used to indicate that the data is corrupted, and a poison bit value of "0" may be used to indicate that the data is not corrupted.

[0062] At block 663, method 660 may include generating parity data associated with a first set of bits (eg, data) at an encoder of the memory device. The encoder may be similar to the one described herein. Figure 1 The encoder component 111 in the embodiment of the present invention generates the parity check data, which may include generating an extended shortened Hamming code.

[0063] At block 665, method 660 may include generating modified parity data at logic of the memory device using the parity data and the second set of at least one bit (e.g., the poisonous data unit). Generating the modified parity may include performing a number of logical operations on the poisonous data unit and the parity data, thereby generating the modified parity data.

[0064] At block 667, method 660 may include writing the first set of bits and the modified parity data in an array of a memory device. The array may be similar to Figure 1 A memory cell array in the memory device 130 in FIG.

[0065] Method 660 may further include reading the written modified parity data and the first set of bits from the array. Method 660 may further include generating poison data units via a decoder component. The decoder component may be similar to the one described herein. Figure 1 The decoder component 113 in. The method 660 may further include providing the poisonous data unit and the data to the host.

[0066] Figure 7 is a flow chart representing an example method for decoding modified parity data using poisonous data units according to several embodiments of the present disclosure. Method 770 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 770 is performed by Figure 1 115 described in the embodiment of the present invention. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, in various embodiments, one or more processes may be omitted. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0067] At block 771, method 770 may include receiving modified parity data from a controller at logic of a memory device, wherein the modified parity data is generated using parity data and poison data units associated with the data. The modified parity data may have been previously generated by combining, via an error correction code (ECC) encoder, parity data associated with a first set of bits and a second set of at least one bit indicating whether the first set of bits includes at least one erroneous or corrupted bit (e.g., a poison data unit). The parity data and the poison data unit may initially be received from a host. The controller may be similar to that described herein. Figure 1 The memory system may be similar to the controller 115 in this article. Figure 11. In some examples, data and poison data units are received via a compute fast link (CXL) compatible interface. The poison data unit may indicate whether the data has been corrupted or has become uncorrectable. The data may be determined to be uncorrupted or corrupted based on the poison data unit being a particular data value. In some examples, the data may be determined to be corrupted based on the poison data unit being a "1" bit and determined to be uncorrupted based on the poison data unit being a "0" bit.

[0068] At block 773, method 770 may include decoding the received modified parity data at a decoder of the memory device, thereby generating a poison data unit. In some examples, the modified parity data may include a modified checksum value. The poison data unit may indicate whether the data is corrupted. The decoder component may be similar to the one described herein. Figure 1 The decoder component 113 in the decoder component 113. The initial parity data before modification may be generated using an extended shortened Hamming code. The decoding may include determining whether the syndrome of the modified parity data includes a pattern indicating that the data is poison data.

[0069] At block 775, method 770 may include sending the poison data unit to an external device, such as Figure 1 The method 770 may further include decoding the received modified parity data by determining a checksum value from the modified checksum value. Determining the checksum value may include determining a characteristic of the data. The determined characteristic of the data may include one of the following: whether the data is regular data or poisonous data or whether the data is correct data or corrupted data. The method 770 may further include reading the stored modified parity data and the data from the array. The method 770 may further include generating a poisonous data unit via a decoder component. The decoder component may be similar to the one described herein. Figure 1 The decoder component 113 in. The method 770 may further include providing the poisonous data unit and the data to the host.

[0070] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative manner and not in a restrictive manner. After reviewing the above description, those of ordinary skill in the art will understand the combination of the above embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents authorized by such claims.

[0071] In the foregoing detailed description, some features are grouped together in a single embodiment in order to simplify the disclosure. The disclosed method should not be interpreted as reflecting the intention that the disclosed embodiments of the disclosure must use more features than those explicitly stated in each claim. Rather, as the appended claims reflect, the inventive subject matter lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A method comprising: receiving, from a controller at logic of a memory device, a first set of bits including data and a second set of at least one bit indicating whether the first set of bits includes one or more erroneous or corrupted bits; generating, at an encoder of the memory device, parity data associated with the first set of bits; generating modified parity data at the logic of the memory device with the parity data and the second set of at least one bit, wherein: In response to the second set of at least one bit indicating that the data is poison data, the modified parity data includes a sum of the parity data and a pattern, wherein incorrect or corrupted data is referred to as poison data; and The pattern indicates whether the first set of bits includes one or more erroneous or corrupted bits; and The first set of bits and the modified parity data are written in an array of the memory device.

2. The method according to claim 1, wherein: The received first group of bits includes X number of data bits; The parity data includes Z number of parity bits; and the first set of bits includes X data bits, and the stored modified parity data includes Z parity bits; Where X and Z are integers.

3. The method of claim 2, wherein a sum of the X data bits and the Z parity bits equals Y bits, and the Y bits stored with respect to the received data indicate whether the received data is poison data, wherein Y is an integer. 4 . The method of claim 1 , wherein the number of bits of the parity data and the number of bits of the modified parity data are equal.

5. The method according to claim 1, further comprising: reading the written modified parity data and the first set of bits from the array; generating, via a decoder of the memory device, the second set of at least one bit; and The second set of at least one bit and the first set of bits are provided to a host.

6. The method of claim 1, wherein the first set of bits and the second set of at least one bit are received via an interface configured to communicate using a Compute Express Link (CXL) protocol.

7. The method of claim 1, wherein the second set of at least one bit indicates whether the data has been corrupted.

8. The method of claim 1, wherein generating the modified parity data comprises performing a number of logical operations on the second set of at least one bit and the parity data, thereby generating the modified parity data.

9. The method of claim 1, further comprising determining that the first set of bits is not corrupted based on the second set of at least one bit being a particular data value.

10. The method of claim 1, further comprising determining that the first set of bits is corrupted based on the second set of at least one bit being a particular data value.

11. The method of claim 1, wherein generating the parity data comprises generating an extended shortened Hamming code.

12. A method comprising: receiving modified parity data from a controller at logic of a memory device, wherein the modified parity data is generated by combining a first set of bits including data and parity data associated with the first set of bits; decoding the received modified parity data at a decoder of the memory device, thereby producing a second set of at least one bit, wherein: Based on whether the modified parity data includes a pattern, the second set of at least one bit indicates whether the first set of bits includes at least one error or is poisonous data, where incorrect or corrupted data is referred to as poisonous data; and The pattern indicates whether the first set of bits includes one or more erroneous or corrupted bits; and The second set of at least one bit is transmitted to an external device.

13. The method of claim 12, further comprising generating the modified parity data by combining the first set of bits with the parity data via an error correction code (ECC) encoder.

14. The method of claim 12, further comprising receiving the first set of bits and the second set of at least one bit from a host.

15. The method of claim 12, further comprising determining whether the first set of bits is corrupted based on the second set of at least one bit.

16. The method of claim 12, wherein the decoding comprises determining whether a syndrome of the modified parity data includes the pattern indicating that the first set of bits is poison data.

17. The method of claim 12, wherein: The modified parity data includes a modified checksum value; and Decoding the received modified parity data includes determining a checksum value from the modified checksum value.

18. The method of claim 17, wherein determining the checksum value comprises determining a characteristic of the first set of bits.

19. The method of claim 18, wherein the determined characteristic of the first set of bits comprises one of: whether the first set of bits is regular data or poisonous data or whether the data is correct data or corrupted data.

20. An apparatus comprising: a controller at the logic of the memory device; an encoder in communication with the controller and configured to: receiving a first set of bits including data and a second set of at least one bit indicating whether the first set of bits is poison data; and The first set of bits and the second set of at least one bit are combined into a modified parity value, wherein: In response to the second set of at least one bit indicating that the data is poison data, the modified parity value comprises a sum of the parity data and a pattern, wherein incorrect or corrupted data is referred to as poison data; and The pattern indicates whether the first set of bits includes one or more erroneous or corrupted bits; and Wherein the controller is configured to cause the modified parity value and the received first set of bits to be written in a memory array of the memory device.

21. The apparatus of claim 20, further comprising a decoder of the memory device in communication with the controller and coupled to the memory array, wherein logic of the decoder is configured to: receiving the first set of bits and the modified parity data; and A subsequent second set of at least one bit is determined from the modified parity data.

22. The apparatus of claim 20, wherein the controller is configured to send the second set of at least one bit and the first set of bits to a host.

23. The apparatus of claim 22, wherein the controller is configured to send the second set of at least one bit and the first set of bits to the host in response to the host requesting retrieval of the first set of bits from the memory array.

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