A kind of double-doped layer TOPCon cell structure and preparation method thereof

Abstract

The application provides a kind of double-doped layer TOPCon cell structure and preparation method thereof, it is related to cell processing preparation technical field.The double-doped TOPCon cell structure includes monocrystalline silicon wafer, diffusion layer, passivation layer, front surface anti-reflection layer, front surface metal electrode are sequentially arranged in the front surface of monocrystalline silicon wafer, and tunneling layer, doped polysilicon layer, back surface anti-reflection layer and back surface metal electrode are sequentially arranged in the back surface of monocrystalline silicon wafer, the doped layer includes the first diffusion doped layer located in the front surface of silicon wafer and the second epitaxial doped layer between the first diffusion doped layer and the front surface metal electrode.The application overcomes the deficiencies of prior art, can guarantee the thickness of P-type doped layer of metal contact area, effectively shield metal area recombination, and reduce metal area contact resistance;At the same time, it can reduce the doping concentration and junction depth of non-metal area, reduce Auger recombination and parasitic light absorption of non-metal area;Therefore, it can effectively improve the conversion efficiency of TOPCon cell.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of battery processing, and particularly relates to a double-doped layer TOPCon battery structure and a preparation method thereof. BACKGROUND

[0002] The existing TOPCon (tunnel oxide passivated contact) battery generally prepares a P-type diffusion layer on the front surface of a silicon wafer, then deposits an aluminum oxide passivation layer with a thickness of 2-6 nm on the surface of the P-type diffusion layer, and finally deposits silicon nitride on the aluminum oxide passivation layer. The structure provides good surface passivation and field passivation performance for the front surface of the silicon wafer. The P-type diffusion layer is formed by diffusing P-type impurities on the N-type substrate to form a PN junction, so that a large number of electron-hole pairs are generated in the silicon wafer under light irradiation. The electron-hole pairs reach the strong electric field region (the PN junction self-built electric field) of the PN junction through migration. The electrons move to the N-type region, and the holes move to the P-type region, so that the N region becomes negative and the P region becomes positive. A stable potential difference (voltage generated by the upper and lower electrodes) is built between the P-N two ends. When the PN junction is connected to an external circuit and light is provided, a continuous current will flow through the circuit, and the PN junction will function as a power source.

[0003] The front surface of the TOPCon battery is usually burned through SiN by Ag paste X The dielectric film and the P-type diffusion layer form an ohmic contact. During the sintering process of the paste, the metal Ag grains may penetrate the P-type diffusion layer, damage the silicon substrate, and cause serious recombination between the metal grid and the silicon substrate, thereby reducing the efficiency. Therefore, in order to reduce the recombination current density of the metal contact area, a sufficient thickness of the P-type diffusion layer is required, which is usually 1-2 um. In order to ensure good field passivation effect and reduced ohmic contact, the P-type diffusion layer needs to have a sufficient doping concentration, which is usually >1e19 cm -3 On the other hand, if the P-type diffusion layer has a large film thickness and doping concentration, the free carrier absorption (FCA) of the diffusion layer to long-wave light will cause a loss of short-circuit current of the TOPCon battery. At the same time, the parasitic absorption of the P-type diffusion layer to the front surface incident light will reduce the bifaciality of the battery. Generally, it is difficult to balance the recombination, resistance loss and optical loss of the P-type diffusion layer. At present, the thickness of the P-type diffusion layer is reduced as much as possible under the premise of ensuring that the metal electrode paste does not burn through the P-type diffusion layer and that the metal electrode and the P-type diffusion layer form a good ohmic contact, so as to reduce the parasitic absorption of photons in the P-type diffusion layer. Or a local heavy doping is formed in the front surface metal contact area by laser doping, so as to reduce the metal area recombination and contact resistance. However, due to the difference in solid solubility between boron and silicon oxide and crystalline silicon, boron is difficult to be doped into silicon, and only laser propulsion redistribution can be used to obtain a deep junction depth to reduce the sheet resistance. Laser doping will cause damage to the silicon wafer and change the surface topography, and high-temperature oxidation for a long time is required to partially repair it, which limits the performance advantage of the selective emitter. SUMMARY

[0004] In order to solve the above problems, the present application provides a double-doped layer TOPCon cell structure and a preparation method thereof.

[0005] To achieve the above object, the technical scheme of the present application is implemented as follows:

[0006] A double-doped layer TOPCon cell structure, comprising a single crystal silicon wafer, a doped layer, a passivation layer, a front surface anti-reflection layer and a front surface metal electrode which are sequentially arranged on the front surface of the single crystal silicon wafer, and a tunneling layer, a doped polysilicon layer, a back surface anti-reflection layer and a back surface metal electrode which are sequentially arranged on the back surface of the single crystal silicon wafer, wherein the doped layer comprises a first diffusion doped layer on the front surface of the silicon wafer and a second epitaxial doped layer between the first diffusion doped layer and the front surface metal electrode; the first diffusion doped layer is a p-type doped layer formed by BCl3 diffusion, with a doping concentration of 0.1e19-1e19 cm -3 -3 and a thickness of 0.1-1 um; the second epitaxial doped layer is a boron-doped p-type crystalline silicon layer selectively grown by epitaxy, with a doping concentration of 1e19-1e20 cm -3 -3 and a thickness of 0.5-1.5 um; the doping concentration of the second epitaxial doped layer is greater than that of the first diffusion doped layer.

[0007] Preferably, the single crystal silicon wafer is a phosphorus-doped N-type single crystal silicon wafer with a resistivity of 0.1-10 Ωcm and a thickness of 100-200 um.

[0008] Preferably, the passivation layer is aluminum oxide with a thickness of 2-6 nm.

[0009] Preferably, the front surface anti-reflection layer and the back surface anti-reflection layer are both composite films composed of one or more of silicon nitride, silicon oxynitride and silicon oxide, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.1.

[0010] Preferably, the front surface metal electrode is an Ag / Al grid electrode, and the back surface metal electrode is an Ag grid electrode.

[0011] Preferably, the tunneling layer is silicon oxide with a thickness of 1-3 nm.

[0012] The preparation method of the double-doped layer TOPCon cell comprises the following steps:

[0013] S1, texturing: using acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer, forming a surface texture on the surface of the silicon wafer to increase the absorption of sunlight and reduce reflection;

[0014] S2, boron diffusion: a first diffusion doped layer doped with boron is formed by BCl3 low pressure diffusion, diffusion temperature 950-1050°C, sheet resistance 150-300Ω / □; the doping concentration is 0.1e19-1e19cm -3 , thickness 0.1-1um;

[0015] S3, BSG: single-sided HF etching, removing back BSG;

[0016] S4, back etching: removing the PN junction formed by the parasitic diffusion on the back, preventing edge leakage;

[0017] S5, LPCVD: in-situ oxidation to form a tunnel oxide layer, and depositing an intrinsic amorphous silicon layer;

[0018] S6, phosphorus diffusion: phosphorus diffusion doping is performed on the back amorphous silicon and amorphous silicon oxide, and the amorphous state is converted into a crystalline state;

[0019] S7, PSG: single-sided HF etching, removing the PSG on the surface of the front screen-printed polysilicon after diffusion;

[0020] S8, front etching: removing the screen-printed polysilicon layer by etching with an alkali solution, and removing the front BSG and the back PSG by cleaning with hydrofluoric acid;

[0021] S9, CVD mask: a SiN X mask with a thickness of 10-25nm is grown on the back by thermal chemical vapor deposition;

[0022] S10, front LCO: etching the SiN X mask barrier layer under the front metal area by laser opening, leaving a thin silicon oxide layer under the etched back metal area;

[0023] S11, HF cleaning: removing the silicon oxide layer under the front metal area by HF cleaning.

[0024] S12, selective epitaxial deposition: a doped layer is selectively epitaxially grown on the diffusion doped layer at the SiNx etching site by chemical vapor deposition; the unetched area is blocked by the SiN X mask layer, and due to the difference in electrochemical potential, epitaxial growth does not occur; a p-type doped crystalline silicon layer is epitaxially grown at the SiNx etching site by the chemical vapor deposition method, forming a second epitaxial doped layer; the second epitaxial doped layer is a boron-doped p-type crystalline silicon layer with a doping concentration of 1e19-1e20cm -3, thickness is 0.5-1.5um; under the condition of pressure <100Torr, temperature 850-950℃, H2 is used as carrier gas, SiH2Cl2 is used as silicon precursor, and in-situ doping is carried out on the epitaxial polysilicon layer by introducing boron hydride (B2H6) gas; HCl formed in the reaction process can etch the silicon on the surface of PECVD SiOx, so as to maintain selective epitaxy, and additional HCl can also be introduced as an etching source in the reaction process; the specific process includes: ① warming up to epitaxial deposition temperature; ② H2 baking; ③ selective silicon deposition; ④ cooling down; wherein the H2 baking is a key step, and must be kept consistent with the subsequent deposition temperature, so that the natural oxide layer on the surface of silicon can be effectively removed by H2 reduction, and the growth quality of the epitaxial layer is ensured.

[0025] S13, unmasking cleaning: using wet chemical method to remove the SiNx mask layer on the surface of the silicon wafer, and cleaning the surface of the silicon wafer;

[0026] S14, ALD: depositing a dense AlOx film on the front surface of the substrate by ALD atomic layer deposition;

[0027] S15, front PECVD: depositing one or more stacked films of silicon nitride and silicon oxynitride on the front surface of the substrate by PECVD;

[0028] S16, back PECVD: depositing one or more stacked films of silicon nitride and silicon oxynitride on the back surface of the substrate by PECVD;

[0029] S17, printing / sintering / light injection: printing Ag / Al paste as negative electrode on the front surface, and printing Ag paste as electrode on the back surface; co-sintering to form good ohmic contact; light injection to repair internal and surface defects of the battery.

[0030] The application provides a double-doped layer TOPCon battery structure and a preparation method thereof.

[0031] (1) The second epitaxial doped layer is arranged between the first diffusion doped layer and the front metal electrode; the concentration of the second epitaxial doped layer is greater than that of the first doped layer, so that a selective emitter is formed in the metal contact area; on the one hand, the heavy doping of the metal contact area can effectively shield the carrier recombination of the front metal contact area, and reduce the metal area recombination current density; on the other hand, the contact resistance between the metal electrode and the emitter can also be reduced; in addition, the first diffusion doped layer in the non-metal area can adopt a lower doping concentration and a smaller junction depth, so as to reduce the Auger recombination and parasitic light absorption in the non-metal area; therefore, the battery conversion efficiency can be effectively improved.

[0032] (2) The laser opening film method is used to open the SiN XEtching groove in the mask blocking layer to open the SiN X Mask layer, exposing the first diffusion doped layer, and then depositing by epitaxy in SiN X Selective growth of boron-doped crystalline silicon layer at the mask groove, SiNx mask protection area will not occur silicon epitaxial deposition due to the difference in electrochemical potential; This method avoids the damage to the silicon wafer and the change of surface morphology caused by laser doping to prepare boron-doped selective emitter; At the same time, selective epitaxy can realize higher doping concentration and greater doping layer thickness; Therefore, the performance advantages of selective emitter can be better played. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 The preparation process flow chart of the TOPCon cell of the present application;

[0034] Figure 2 The structure diagram of the TOPCon cell of the present application;

[0035] Figure 3 The structure diagram of the TOPCon cell of the prior art of the present application;

[0036] In the figure: 1, single crystal silicon wafer; 2, doped layer; 2-1, first diffusion doped layer; 2-2, second epitaxial doped layer; 3, passivation layer; 4, front anti-reflection layer; 5, front metal electrode; 6, tunneling layer; 7, doped polysilicon layer; 8, back anti-reflection layer; 9, back metal electrode. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below in combination with the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0038] Embodiment 1:

[0039] A TOPCon cell structure, as shown in Figure 2 , includes a single crystal silicon wafer 1, a doped layer 2, a passivation layer 3, a front anti-reflection layer 4 and a front metal electrode 5 arranged in sequence on the front of the single crystal silicon wafer, a tunneling layer 6, a doped polysilicon layer 7, a back anti-reflection layer 8 and a back metal electrode 9 arranged in sequence on the back of the single crystal silicon wafer 1; the diffusion doped layer 2 includes a second epitaxial doped layer 2-2 located below the front metal area and a first diffusion doped layer 2-1 located in the front non-metal area.

[0040] The preparation method of the TOPCon cell is:

[0041] S1, Texturing: Selecting phosphorus-doped N-type monocrystalline silicon wafer, resistivity 1.0 Ωcm, thickness 160 um; using acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the wafer, forming surface texture on the surface of the wafer to increase the absorption of sunlight and reduce reflection;

[0042] S2, Boron diffusion: BCl3 low-pressure diffusion is used to form a front PN junction, diffusion temperature 950-1050℃, square resistance 150-250 Ω / □; therefore, secondary boron doping is performed on the second epitaxial doped layer, and the doping concentration is 10e19 cm -3 ;

[0043] S3, BSG: Single-sided HF etching to remove the back BSG;

[0044] S4, Back etching: Alkaline solution etching is used to remove the PN junction formed by the parasitic diffusion on the back, preventing edge leakage;

[0045] S5, LPCVD: In-situ oxidation is used to generate a tunneling oxide layer by LPCVD, temperature 550-650℃, thickness 2nm, and an intrinsic amorphous silicon layer is deposited, thickness 130nm;

[0046] S6, Phosphorus diffusion: POCl3 is used as the diffusion source to perform phosphorus diffusion doping on the back amorphous silicon and amorphous silicon oxide at a diffusion temperature of 850℃, and convert them from amorphous state to crystalline state;

[0047] S7, PSG: Single-sided HF etching to remove the PSG on the surface of the front plated polysilicon after diffusion;

[0048] S8, Front etching: Alkaline solution etching is used to remove the plated polysilicon layer, and hydrofluoric acid cleaning is used to remove the front BSG and the back PSG;

[0049] S9, CVD mask: A SiN X mask is grown on the back by thermal chemical vapor deposition (CVD); appropriate amounts of SiH4 and NH3 are introduced, and a solid thin film (SiN x ) is formed on the surface of the sample through chemical reaction and plasma reaction; the thickness is 20nm, preparing for subsequent selective epitaxial deposition;

[0050] S10, Front LCO: The SiN X mask barrier layer under the front metal area is etched and grooved by laser opening method, aiming to open the SiN X mask layer and expose the diffusion doped layer, preparing for subsequent growth of silicon epitaxial layer;

[0051] S11, HF cleaning: Since the SiNX The mask layer thus leaves a thin silicon oxide layer under the backside metal region of the slot, and the silicon oxide layer under the frontside metal region is removed by HF cleaning;

[0052] S12, selective epitaxy deposition: a doped layer is selectively epitaxially grown on the diffusion doped layer at the SiNx slot by chemical vapor deposition; the unslotted region is blocked by the SiN X mask layer, and epitaxial growth does not occur due to the difference in electrochemical potential; the chemical vapor deposition epitaxially grows a p-type doped crystalline silicon layer at the SiNx slot to form a second epitaxial doped layer; the second epitaxial doped layer is a boron-doped p-type crystalline silicon layer with a doping concentration of 3e19cm -3 -80 Torr and a temperature of 850°C, using H2 as the carrier gas and SiH2Cl2 as the silicon precursor, and in-situ doping of the epitaxial polysilicon layer is performed by introducing boron hydride (B2H6) gas; HCl formed during the reaction can etch the silicon on the surface of the PECVD SiOx, maintaining selective epitaxy, and additional HCl can also be introduced as an etching source during the reaction. The specific process includes: (1) warming up to the epitaxial deposition temperature; (2) H2 baking; (3) selective silicon deposition; (4) cooling down. The H2 baking is a critical step, and must be consistent with the subsequent deposition temperature, which can effectively remove the natural oxide layer on the silicon surface through H2 reduction, ensuring the quality of the epitaxial layer growth.

[0053] S13, demasking and cleaning: the SiNx mask layer on the surface of the silicon wafer is removed by wet chemical method, and the surface of the silicon wafer is cleaned;

[0054] S14, ALD: a dense AlO X thin film is deposited on the front surface of the substrate by ALD atomic layer deposition;

[0055] S15, front PECVD: a silicon nitride stack film is deposited on the front surface of the substrate by PECVD;

[0056] S16, back PECVD: a silicon nitride stack film is deposited on the back surface of the substrate by PECVD;

[0057] S17, printing / sintering / photoluminescence injection: printing negative electrode Ag / Al paste on the front surface and Ag paste on the back surface; co-sintering to form a good ohmic contact; photoluminescence injection to repair internal and surface defects of the cell.

[0058] Comparative Example 1:

[0059] As a conventional TOPCon cell, as shown in Figure 3 the front surface of the silicon wafer is a single diffusion layer, which is different from Example 1.

[0060] Detection:

[0061] The electrical performance parameters of the TOPCon cells in the test examples and the comparative examples are as follows:

[0062]

[0063] Comparing the TOPCon cells prepared in Comparative Example 1 and Example 1, it can be seen that the battery structure and preparation method provided in the application are adopted in the example, and the second epitaxial doping layer below the front metal area and the first diffusion doping layer located in the front non-metal area of the N-type monocrystalline silicon wafer have better high-efficiency conversion efficiency and higher open-circuit voltage compared with Comparative Example 1.

[0064] It should be noted that, in this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0065] The above examples are only used to illustrate the technical solutions of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A dual-doped layer TOPCon cell structure, comprising a single crystal silicon wafer (1), a doped layer (2), a passivation layer (3), a front surface anti-reflection layer (4), and a front surface metal electrode (5) arranged in sequence on the front surface of the single crystal silicon wafer (1), and a tunneling layer (6), a doped polysilicon layer (7), a back surface anti-reflection layer (8), and a back surface metal electrode (9) arranged in sequence on the back surface of the single crystal silicon wafer (1), characterized in that: The doping layer comprises a first diffusion doping layer located at the front surface of the silicon wafer and a second epitaxial doping layer (2-2) located between the first diffusion doping layer (2-1) and the front surface metal electrode. The first diffusion doped layer (2-1) is a p-type doped layer formed by diffusion of BCl3, with a doping concentration of 0.1e19-1e19 cm -3 -1, and a thickness of 0.1-1 um. The second epitaxial doped layer (2-2) is a selectively epitaxially grown boron-doped p-type crystalline silicon layer, with a doping concentration of 1e19-1e20 cm -3 -1, and a thickness of 0.5-1.5 um. The doping concentration of the second epitaxial doped layer (2-2) is greater than that of the first diffusion doped layer (2-1). The preparation method of the double-doped layer TOPCon cell structure comprises the following steps: S1, texturing: using acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer, forming a surface texture on the surface of the silicon wafer to increase the absorption of sunlight and reduce reflection; S2, boron diffusion: BCl3 low pressure diffusion is used to form a boron-doped first diffusion doped layer, diffusion temperature 950-1050℃, square resistance 150-300Ω / □; the doping concentration is 0.1e19~1e19cm -3 , thickness 0.1-1um; S3, BSG: single-sided HF etching to remove the back BSG; S4, back etching: removing the PN junction formed by the parasitic diffusion on the back surface to prevent edge leakage; S5, LPCVD: in-situ oxidation to form a tunneling oxide layer and deposit an intrinsic amorphous silicon layer; S6, phosphorus diffusion: phosphorus diffusion doping of the back amorphous silicon and amorphous silicon oxide, and converting them from amorphous state to crystalline state; S7, PSG: single-sided HF etching to remove the PSG on the surface of the front-side wrap-plated polysilicon after diffusion; S8, front etching: removing the wrap-plated polysilicon layer by etching with an alkali solution, and removing the BSG on the front surface and the PSG on the back surface by hydrofluoric acid cleaning; S9, CVD mask: a layer of SiN with a thickness of 10-25 nm is grown on the back side by chemical vapor deposition X masking S10, front LCO: laser opening film method is used to open the SiN under the front metal area X Etching the mask barrier layer to form a groove, leaving a thin silicon oxide layer under the groove of the back metal area; S11, HF cleaning: removing the silicon oxide layer under the front metal area by HF cleaning; S12, selective epitaxy deposition: using chemical vapor deposition to selectively epitaxially grow a doped layer on the diffusion doped layer at the SiNx slot; the unslotted area is blocked by SiN X Mask layer barrier, due to the difference in electrochemical potential, epitaxial growth will not occur; S13, mask removal cleaning: removing the SiNx mask layer on the surface of the silicon wafer by wet chemical method, and cleaning the surface of the silicon wafer; S14, ALD: depositing a dense AlOx film on the front surface of the substrate by ALD atomic layer deposition; S15, front PECVD: depositing one or more stacked films of silicon nitride and silicon oxynitride on the front surface of the substrate by PECVD; S16, back PECVD: depositing one or more stacked films of silicon nitride and silicon oxynitride on the back surface of the substrate by PECVD; S17, printing / sintering / photoinjection: printing the negative electrode Ag / Al paste on the front surface and the electrode Ag paste on the back surface; co-sintering to form a good ohmic contact; and photoinjection to repair internal and surface defects of the cell.

2. The dual-doped layer TOPCon cell structure of claim 1, wherein: The single crystal silicon wafer (1) is a phosphorus-doped N-type single crystal silicon wafer with a resistivity of 0.1-10 Ωcm and a thickness of 100-200 um.

3. The dual-doped layer TOPCon cell structure of claim 1, wherein: The passivation layer is aluminum oxide with a thickness of 2-6 nm.

4. The dual-doped layer TOPCon cell structure of claim 1, wherein: The front anti-reflection layer (4) and the back anti-reflection layer (8) have a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.

1.

5. The dual-doped layer TOPCon cell structure of claim 1, wherein: The tunneling layer (6) is silicon oxide with a thickness of 1-3 nm.

6. The dual-doped layer TOPCon cell structure of claim 1, wherein: In step S9, SiNx is formed by introducing SiH4 and NH3, and through chemical reaction and plasma reaction, a solid SiNx film is formed on the surface of the sample.

7. The dual-doped layer TOPCon cell structure of claim 1, wherein: In the step S12, the chemical vapor deposition method is used to epitaxially grow a p-type doped crystalline silicon layer at the SiNx slot, to form a second epitaxial doped layer; the second epitaxial doped layer is a boron-doped p-type crystalline silicon layer, with a doping concentration of 1e19~1e20cm -3 , and a thickness of 0.5-1.5um; the process is carried out under a pressure of <100Torr and a temperature of 850-950℃, with H2 as the carrier gas and SiH2Cl2 as the silicon precursor; in-situ doping of the epitaxial polysilicon layer is performed by introducing diborane gas; HCl formed in the reaction process can etch the silicon on the surface of the PECVD SiOx, to maintain selective epitaxy; additional HCl is introduced as an etching source in the reaction process. The specific process includes: ① heating to epitaxial deposition temperature; ② H2 baking; ③ selective silicon deposition; ④ cooling.

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