Device communication method and apparatus based on fsi bus protocol, device, and medium

Abstract

The application relates to the technical field of bus communication, and discloses a device communication method and device based on an FSI bus protocol, a device and a medium, which are applied to a programmable logic device connected with a master device and a slave device, and the method comprises the following steps: acquiring a command clock signal sent by the master device through a first FSI bus; the first FSI bus is a bus connected with the master device and the programmable logic device; matching the command clock signal with a command signal format in a locally stored command reliability list; the command signal format is a message format supported by the FSI bus protocol; if the matching is successful, performing corresponding processing on the command clock signal based on the operation type of the command reliability list. It can be seen that the application can effectively filter the error command clock signal caused by misoperation, and improve the reliability of FSI bus communication.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of bus communication, in particular to a device communication method and device based on FSI bus protocol, equipment and medium. BACKGROUND

[0002] FSI(Field Replaceable Unit Service Interface, replaceable unit interface) bus protocol is a point-to-point two-wire serial bus operating in half-duplex mode, which can support up to 4 meters of distance transmission at a bus frequency of up to 166MHZ. FSI bus is superior to other standard interfaces in the industry in terms of ease of use, ease of expansion, robustness, transmission speed and transmission distance. It can provide a seamless upgrade path from small systems to enterprise systems for service access to all chips in the system. FSI bus operation is divided into master operation and slave operation, Figure 1 For the point-to-point interconnection structure between the existing FSI communication master and slave, the basic transmission process of the master includes transmission start, transmission command data (including slave ID, sent data content, read / write enable, read / write address, write data, CRC check, etc.), waiting for the response of the slave. The basic transmission process of the slave includes waiting for the transmission start, receiving the command data sent by the master, and issuing the response of the read / write data state. In the above communication mode, misoperation will occur when configuring FSI connection equipment, which will cause malicious operation, interruption or data loss of the equipment connected with the FSI bus, etc., making the FSI communication unreliable.

[0003] Therefore, how to improve the reliability of FSI bus communication is a technical problem to be solved by those skilled in the art. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a device communication method, device and storage medium based on FSI bus protocol, which can effectively filter the error command clock signal caused by misoperation and improve the reliability of FSI bus communication. The specific scheme is as follows:

[0005] The first aspect of the present application provides a device communication method based on FSI bus protocol, applied to a programmable logic device connected with a master device and a slave device, comprising:

[0006] obtaining a command clock signal sent by the master device through a first FSI bus; the first FSI bus is a bus connected with the master device and the programmable logic device;

[0007] matching the command clock signal with a command signal format in a command reliability list stored locally; the command signal format is a message format supported by the FSI bus protocol;

[0008] if the matching is successful, performing corresponding processing on the command clock signal based on the operation type of the command reliability list.

[0009] Optionally, the matching of the command clock signal with the command signal format in the locally-stored command reliability list comprises:

[0010] matching the command clock signal with a send command signal format in a locally-stored send command reliability list; the operation type of the send command reliability list is sending;

[0011] The if the matching is successful, performing corresponding processing on the command clock signal based on the operation type of the command reliability list, comprises:

[0012] if the matching is successful, sending the command clock signal to the slave device through a second FSI bus so that the slave device responds to the command clock signal; the second FSI bus is a bus connecting the slave device and the programmable logic device.

[0013] Optionally, after the sending of the command clock signal to the slave device through the second FSI bus, the method further comprises:

[0014] acquiring a response clock signal sent by the slave device through the second FSI bus;

[0015] matching the response clock signal with a response signal format in a locally-stored response reliability list; the response signal format is a message format supported by the FSI bus protocol;

[0016] if the matching is successful, sending the response clock signal to the master device through the first FSI bus.

[0017] Optionally, the matching of the command clock signal with the command signal format in the locally-stored command reliability list comprises:

[0018] matching the command clock signal with a reset command signal format in a locally-stored reset command reliability list; the operation type of the reset command reliability list is resetting;

[0019] The if the matching is successful, performing corresponding processing on the command clock signal based on the operation type of the command reliability list, comprises:

[0020] resetting the first FSI bus according to the command clock signal.

[0021] Optionally, the resetting the first FSI bus according to the command clock signal comprises:

[0022] According to the command clock signal, a reset enable signal is enabled in the programmable logic device, and the first FSI bus is pulled high to reset the first FSI bus.

[0023] Optionally, the matching the command clock signal with a command signal format in a locally stored command reliability list comprises:

[0024] The command clock signal is matched with a sending command signal format in a locally stored sending command reliability list.

[0025] If the matching fails, the command clock signal is matched with a reset command signal format in a locally stored reset command reliability list, and if the matching fails, the command clock signal is determined as an abnormal command.

[0026] Optionally, after the command clock signal is determined as an abnormal command, the method further comprises:

[0027] The command clock signal is discarded and a corresponding error interrupt is generated to terminate the current communication.

[0028] A second aspect of the present application provides a device communication apparatus based on a FSI bus protocol, applied to a programmable logic device connected with a master device and a slave device, comprising:

[0029] A first obtaining module is configured to obtain a command clock signal sent by the master device through a first FSI bus; the first FSI bus is a bus connecting the master device and the programmable logic device;

[0030] A first matching module is configured to match the command clock signal with a command signal format in a locally stored command reliability list; the command signal format is a message format supported by the FSI bus protocol;

[0031] A processing module is configured to, if the matching is successful, perform corresponding processing on the command clock signal based on an operation type of the command reliability list.

[0032] A third aspect of the present application provides an electronic device, comprising a processor and a memory; wherein the memory is configured to store a computer program, the computer program is loaded and executed by the processor to implement the foregoing device communication method based on the FSI bus protocol.

[0033] The fourth aspect of the present application provides a computer readable storage medium, wherein computer executable instructions are stored in the computer readable storage medium, and the computer executable instructions are loaded and executed by a processor to implement the foregoing device communication method based on the FSI bus protocol.

[0034] In the present application, the programmable logic device applied to connect the master device and the slave device first acquires the command clock signal sent by the master device through the first FSI bus; the first FSI bus is the bus connecting the master device and the programmable logic device; then the command clock signal is matched with the command signal format in the locally stored command reliability list; the command signal format is the message format supported by the FSI bus protocol; if the matching is successful, the command clock signal is processed according to the operation type of the command reliability list. It can be seen that the programmable logic device is embedded between the master device and the slave device in the FSI bus communication of the present application, which confirms the accuracy of the command clock signal by matching the command clock signal with the command reliability list set in advance, thereby effectively filtering the error command clock signal caused by misoperation and improving the reliability of the FSI bus communication. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0036] Figure 1 A flow chart of a device communication method based on the FSI bus protocol provided by the present application is provided;

[0037] Figure 2 A flow chart of a device communication method based on the FSI bus protocol provided by the present application is provided;

[0038] Figure 3 A specific transmission diagram of the master device sending messages to the FPGA provided by the present application is provided;

[0039] Figure 4 A specific transmission diagram of the FPGA sending messages to the slave device provided by the present application is provided;

[0040] Figure 5 A specific transmission diagram of the master device sending messages to the FPGA provided by the present application is provided;

[0041] Figure 6This application provides a specific schematic diagram of FPGA sending messages to a slave device.

[0042] Figure 7 A schematic diagram illustrating a specific device communication method based on the FSI bus protocol provided in this application;

[0043] Figure 8 This application provides a specific schematic diagram of a master device sending a message to an FPGA.

[0044] Figure 9 This application provides a specific schematic diagram of FPGA sending messages to a slave device.

[0045] Figure 10 This application provides a schematic diagram of a specific device communication system structure based on the FSI bus protocol;

[0046] Figure 11 A schematic diagram illustrating a specific device communication method based on the FSI bus protocol provided in this application;

[0047] Figure 12 A schematic diagram of a device communication device based on the FSI bus protocol is provided in this application;

[0048] Figure 13 This application provides a structural diagram of a device communication electronic device based on the FSI bus protocol. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] In existing FSI communication systems, communication between master and slave devices is susceptible to errors during FSI connection configuration. These errors can lead to malicious operation, interruptions, or data loss in the connected devices, rendering FSI communication unreliable. To address these shortcomings, this application provides a device communication scheme based on the FSI bus protocol. A programmable logic device is embedded between the master and slave devices in the FSI bus communication. This programmable logic device verifies the accuracy of the command clock signal by matching it against a pre-defined command reliability list, effectively filtering out erroneous command clock signals caused by erroneous operations and improving the reliability of FSI bus communication.

[0051] Figure 2A flow chart of a device communication method based on FSI bus protocol is provided for the embodiments of the present application. Referring to Figure 2 As shown in the figure, the device communication method based on FSI bus protocol is applied to a programmable logic device connected with a master device and a slave device, and includes the following steps.

[0052] S11: Obtain a command clock signal sent by the master device through a first FSI bus; the first FSI bus is a bus connecting the master device and the programmable logic device.

[0053] In the embodiment, the programmable logic device first obtains a command clock signal sent by the master device through a first FSI bus. The first FSI bus is a bus connecting the master device and the programmable logic device, and the first FSI bus includes CLK and DATA. The master device is an FSI device. The programmable logic device includes but is not limited to FPGA and PLC. Because the programmable logic device is set, the master device sends the command clock signal to the programmable logic device instead of the slave device, so that an error command can be passed.

[0054] S12: Match the command clock signal with a command signal format in a locally stored command reliability list; the command signal format is a message format supported by the FSI bus protocol.

[0055] In the embodiment, after the programmable logic device obtains the command clock signal, the programmable logic device matches the command clock signal with a command signal format in a locally stored command reliability list. It can be understood that the command reliability list needs to be pre-set and stored in the programmable logic device, that is, the command reliability list needs to be sorted according to the FSI bus protocol. The command reliability list includes a message format supported by the FSI bus protocol. In the embodiment, the command reliability list has at least two types, one is a sending command reliability list, and the other is a reset command reliability list. The two lists can be stored simultaneously or only one type can be stored. Table 1 shows the sending command reliability list, and Table 2 shows the reset command reliability list.

[0056] Table 1: Sending command reliability list

[0057] Command Description BREAK Initialize all FSI slave interfaces ABS_ADR Absolute address command mode for data transfer SAME_ADR Same address command mode for data transfer REL_ADR Relative address command mode for data transfer TERM Terminate data transfer D_POLL Data poll command in response to slave busy

[0058] Table 2: Reset command reliability list

[0059] Command Description RESET FSI system reset

[0060] In the case of only storing the sending command reliability list, the sending command clock signal is mainly matched, specifically, the command clock signal is matched with the sending command signal format in the locally stored sending command reliability list. The operation type of the sending command reliability list is sending. In the case of only storing the reset command reliability list, the reset command clock signal is mainly matched, specifically, the command clock signal is matched with the reset command signal format in the locally stored reset command reliability list. The operation type of the reset command reliability list is reset. In the case of simultaneously storing, the sending command clock signal and the reset command clock signal can be simultaneously matched, and the specific implementation process is referred to the following embodiments.

[0061] S13: If the matching is successful, the command clock signal is processed according to the operation type of the command reliability list.

[0062] In the embodiment, if the matching is successful, the programmable logic device processes the command clock signal according to the operation type of the command reliability list. Specifically, the following two cases are included:

[0063] In one embodiment, when the command reliability list is the sending command reliability list, if the matching is successful, the command clock signal is sent to the slave device through a second FSI bus, so that the slave device responds to the command clock signal; the second FSI bus is a bus connecting the slave device and the programmable logic device. At this time, the command clock signal is a sending command clock signal, that is, if the comparison with the sending command reliability list in the programmable logic device is successful, the sending command clock signal is allowed to be sent to the slave device, and a SEND_OK state interrupt is output at the same time. For details, refer to the content disclosed in the following embodiments. Taking an FPGA as an example, when the FPGA outputs a SEND_OK state interrupt, the transmission schematic diagram of the master device sending a message to the FPGA is as shown in Figure 3 , and the transmission schematic diagram of the FPGA sending a message to the slave device is as shown in Figure 4 .

[0064] In another embodiment, when the command reliability list is the reset command reliability list, if the matching is successful, the first FSI bus is reset according to the command clock signal. Further, a reset enable signal in the programmable logic device is enabled and the first FSI bus is pulled high to reset the first FSI bus. At this time, the command clock signal is a reset command clock signal, that is, if the comparison with the reset command reliability list in the programmable logic device is successful, the state of SEND_RESET output by the programmable logic device is interrupted, and the reset enable signal in the programmable logic device is enabled, and the CLK and DATA of the FSI bus are pulled high to reset the FSI bus. The operation of the reset enable module can enable the operator to confirm whether to reset the FSI bus, and better improve the reliability of FSI communication. Taking an FPGA as an example, when the state of SEND_RESET output by the FPGA is interrupted, the transmission schematic of the FPGA sending a message to a master device is as shown in Figure 5 and the transmission schematic of the FPGA sending a message to a slave device is as shown in Figure 6 .

[0065] It can be seen that the embodiment of the present application is applied to a programmable logic device connected between a master device and a slave device, which first acquires a command clock signal sent by the master device through a first FSI bus; the first FSI bus is a bus connecting the master device and the programmable logic device; then matches the command clock signal with a command signal format in a locally stored command reliability list; the command signal format is a message format supported by the FSI bus protocol; if the matching is successful, the command clock signal is processed according to the operation type of the command reliability list. The embodiment of the present application embeds a programmable logic device between a master device and a slave device in FSI bus communication. The programmable logic device matches the command clock signal with a command reliability list set in advance to confirm the accuracy of the command clock signal, thereby effectively filtering error command clock signals caused by misoperation and improving the reliability of FSI bus communication.

[0066] Figure 7 A specific device communication method flowchart based on the FSI bus protocol is provided for the embodiment of the present application. Referring to FIG. 17, the device communication method based on the FSI bus protocol is applied to a programmable logic device connected between a master device and a slave device, and includes the following steps. Figure 7

[0067] S21: Acquire a command clock signal sent by the master device through a first FSI bus; the first FSI bus is a bus connecting the master device and the programmable logic device.

[0068] ​S22: match the command clock signal with a transmission command signal format in a locally stored transmission command reliability list; the operation type of the transmission command reliability list is transmission.

[0069] S23: if the matching is successful, send the command clock signal to the slave device through a second FSI bus so that the slave device responds to the command clock signal; the second FSI bus is a bus connecting the slave device and the programmable logic device.

[0070] In the embodiment, the specific process of steps S21 to S23 can refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0071] S24: obtain a response clock signal sent by the slave device through the second FSI bus.

[0072] S25: match the response clock signal with a response signal format in a locally stored response reliability list; the response signal format is a message format supported by the FSI bus protocol.

[0073] S26: if the matching is successful, send the response clock signal to the master device through the first FSI bus.

[0074] In the embodiment, after the programmable logic device sends the command clock signal to the slave device, the slave device will respond to the signal, and the programmable logic device only needs to wait for the response of the slave device. That is, the programmable logic device needs to obtain the response clock signal sent by the slave device through the second FSI bus, then match the response clock signal with a response signal format in a locally stored response reliability list, and if the matching is successful, send the response clock signal to the master device through the first FSI bus. Similarly, the response signal format is a message format supported by the FSI bus protocol, and Table 3 shows an example of the response reliability list.

[0075] Table 3: Response reliability list

[0076] Command Description ACK Acknowledge successful write data ACK_D Acknowledge successful read data BUSY Indicate FSI slave cannot complete data transfer ERR_A Indicate FSI data transfer error ERR_C Indicate FSI data CRC error

[0077] Specifically, the programmable logic device needs to match the response clock signal with the response signal format in the response reliability list of Table 3. If the comparison is correct, the slave device response is received, and the FSI communication is normal. Further, the programmable logic device can also output a REV_OK state interrupt to indicate that the communication is normal. Taking an FPGA as an example, when the FPGA outputs a REV_OK state interrupt, the transmission diagram of the master device sending a message to the FPGA is as shown in Figure 8 The transmission diagram of the FPGA sending a message to the slave device is as shown in Figure 9

[0078] Therefore, the overall system structure diagram of the embodiment is as shown in Figure 10 The main device is a server management main chip, a programmable logic device (such as an FPGA), and a slave device. The programmable logic device includes a reliability list, a reset enable logic, and an interrupt state output module. If the matching fails, it means that the response of the slave device is abnormal, and at this time, the server management main chip cannot be fed back to prevent signal interference to the main chip. At this time, the interrupt state module of the programmable logic device outputs a REV_ERR error interrupt, and the CLK and DATA signals are pulled high to terminate the FSI communication.

[0079] It can be seen that the command clock signal sent by the master device through the first FSI bus is first acquired; then the command clock signal is matched with the sending command signal format in the locally stored sending command reliability list; the operation type of the sending command reliability list is sending. If the matching is successful, the command clock signal is sent to the slave device through the second FSI bus, so that the slave device responds to the command clock signal; then the response clock signal sent by the slave device through the second FSI bus is acquired, and the response clock signal is matched with the response signal format in the locally stored response reliability list. If the matching is successful, the response clock signal is sent to the master device through the first FSI bus. The above steps solve the problem of malicious running, interruption or data information loss of the device connected with the FSI bus caused by misoperation, and also solve the problem of interference of abnormal slave device response data to the server management main chip when receiving the response of the slave device connected with the FSI bus, thereby effectively improving the reliability of the FSI system bus communication.

[0080] Figure 11 A specific FSI bus protocol-based device communication method flowchart is provided for the embodiment of the application. Referring to Figure 11 The FSI bus protocol-based device communication method is applied to a programmable logic device connected with a master device and a slave device, and includes the following steps. ​

[0081] S31: acquire a command clock signal sent by the host device through a first FSI bus; the first FSI bus is a bus connecting the host device and the programmable logic device.

[0082] S32: match the command clock signal with a sending command signal format in a locally stored sending command reliability list.

[0083] S33: if the matching fails, match the command clock signal with a reset command signal format in a locally stored reset command reliability list, and if the matching fails, determine the command clock signal as an abnormal command.

[0084] S34: discard the command clock signal and generate a corresponding error interrupt to terminate the current communication.

[0085] In the embodiment, when the programmable logic device simultaneously stores the sending command reliability list and the reset command reliability list, upon acquiring the command clock signal sent by the host device through the first FSI bus, the command clock signal is first matched with a sending command signal format in the locally stored sending command reliability list. In the case of matching failure, the command clock signal is then matched with a reset command signal format in the locally stored reset command reliability list, and in the case of matching failure in both lists, the command clock signal is determined as an abnormal command.

[0086] In the embodiment, the abnormal command is discarded, and a corresponding error interrupt is generated to terminate the current communication. That is, if the sending command reliability list and the reset command reliability list cannot be correctly matched, the command clock signal is considered as an abnormal instruction, the error interrupt of SEND_ERR is output by the interrupt state module of the programmable logic device, the CLK and DATA signals are pulled high, and the FSI communication is stopped.

[0087] Referring to Figure 12 The embodiment of the application also discloses a device communication apparatus based on an FSI bus protocol, which is applied to a programmable logic device connecting a host device and a slave device, and includes:

[0088] A first acquisition module 11 is configured to acquire a command clock signal sent by the host device through a first FSI bus; the first FSI bus is a bus connecting the host device and the programmable logic device.

[0089] A first matching module 12 is configured to match the command clock signal with a command signal format in a locally stored command reliability list; the command signal format is a message format supported by the FSI bus protocol.

[0090] The processing module 13 is configured to perform corresponding processing on the command clock signal based on the operation type of the command reliability list if the matching is successful.

[0091] It can be seen that, in the embodiment of the application, the programmable logic device connected with the master device and the slave device first acquires a command clock signal sent by the master device through a first FSI bus; the first FSI bus is a bus connecting the master device and the programmable logic device; then the command clock signal is matched with a command signal format in a locally stored command reliability list; the command signal format is a message format supported by the FSI bus protocol; if the matching is successful, corresponding processing is performed on the command clock signal based on the operation type of the command reliability list. In the embodiment of the application, the programmable logic device is embedded between the master device and the slave device in the FSI bus communication, the programmable logic device confirms the accuracy of the command clock signal by matching the command clock signal with the command reliability list set in advance, thereby effectively filtering the error command clock signal caused by misoperation and improving the reliability of the FSI bus communication.

[0092] In some specific embodiments, the first matching module 12 specifically includes:

[0093] The first matching unit is configured to match the command clock signal with a sending command signal format in a locally stored sending command reliability list; the operation type of the sending command reliability list is sending.

[0094] The second matching unit is configured to match the command clock signal with a reset command signal format in a locally stored reset command reliability list; the operation type of the reset command reliability list is reset.

[0095] In some specific embodiments, the processing module 13 specifically includes:

[0096] The first processing unit is configured to, if the matching is successful, send the command clock signal to the slave device through a second FSI bus, so that the slave device responds to the command clock signal; the second FSI bus is a bus connecting the slave device and the programmable logic device.

[0097] The second processing unit is configured to reset the first FSI bus according to the command clock signal.

[0098] In some specific embodiments, the second processing unit is specifically configured to turn on a reset enable signal in the programmable logic device according to the command clock signal, and pull up the first FSI bus to reset the first FSI bus.

[0099] In some embodiments, the FSI bus protocol-based device communication apparatus further comprises:

[0100] a second acquisition module, configured to acquire a response clock signal sent by the slave device through the second FSI bus;

[0101] a second matching module, configured to match the response clock signal with a response signal format in a locally stored response reliability list; the response signal format is a message format supported by the FSI bus protocol;

[0102] a sending module, configured to send the response clock signal to the master device through the first FSI bus if the matching is successful.

[0103] In some embodiments, the first matching module 12 is further configured to match the command clock signal with a sending command signal format in a locally stored sending command reliability list, and if the matching fails, match the command clock signal with a reset command signal format in a locally stored reset command reliability list, and if the matching fails, determine the command clock signal as an abnormal command.

[0104] In some embodiments, the FSI bus protocol-based device communication apparatus further comprises:

[0105] a communication termination module, configured to discard the command clock signal and generate a corresponding error interrupt to terminate the current communication.

[0106] Further, the embodiments of the present application also provide an electronic device. Figure 13 FIG. 1 is a structural diagram of an electronic device 20 according to an exemplary embodiment, and the contents in the figure should not be considered as any limitation on the use range of the present application.

[0107] Figure 13 FIG. 1 is a structural diagram of an electronic device 20 according to an exemplary embodiment, and the contents in the figure should not be considered as any limitation on the use range of the present application. The electronic device 20, specifically, can include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is configured to store a computer program, and the processor 21 is configured to load and execute the computer program to implement the related steps in the FSI bus protocol-based device communication method disclosed in any of the preceding embodiments.

[0108] In this embodiment, the power supply 23 is configured to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 is configured to create a data transmission channel between the electronic device 20 and external devices, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solution of the present application, which is not limited specifically herein; the input and output interface 25 is configured to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application requirement, which is not limited specifically herein.

[0109] In addition, the memory 22 as a carrier of resource storage can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon can include an operating system 221, a computer program 222 and data 223, etc., and the storage mode can be temporary storage or permanent storage.

[0110] The operating system 221 is configured to manage and control each hardware device on the electronic device 20 and the computer program 222, so as to realize the operation and processing of the processor 21 on the mass data 223 in the memory 22, and the operating system 221 can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program capable of completing the device communication method based on the FSI bus protocol executed by the electronic device 20 disclosed in any one of the preceding embodiments, the computer program 222 can further include a computer program capable of completing other specific work. The data 223 can include clock signal data collected by the electronic device 20.

[0111] Further, the embodiment of the present application further discloses a storage medium, and the storage medium stores a computer program. When the computer program is loaded and executed by a processor, the steps of the device communication method based on the FSI bus protocol disclosed in any one of the preceding embodiments are realized.

[0112] In the specification, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0113] Finally, it needs to be pointed out that in this document, relational terms such as first and second and the like can only be intended to distinguish one entity or operation from another entity or operation without necessarily requiring or implying any such actual relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article, or apparatus including the stated element.

[0114] The above describes in detail the FSI bus protocol-based device communication method, device, equipment and medium provided by the present application. The principles and implementation manners of the present application are described by applying specific examples in this document. The above description of the embodiments is only for helping to understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed. In summary, the content of the present description should not be understood as a limitation of the present application.

Claims

1. A method of communicating between devices based on a FSI bus protocol, characterized by, A programmable logic device for connecting a master device and a slave device, comprising: obtaining a command clock signal sent by the master device through a first FSI bus; the first FSI bus being a bus connecting the master device and the programmable logic device; matching the command clock signal with a command signal format in a locally stored command reliability list; the command signal format being a message format supported by an FSI bus protocol; if the matching is successful, performing corresponding processing on the command clock signal based on an operation type of the command reliability list.

2. The method of claim 1, wherein, The matching the command clock signal with a command signal format in a locally stored command reliability list comprises: matching the command clock signal with a send command signal format in a locally stored send command reliability list; the operation type of the send command reliability list being sending; The if the matching is successful, performing corresponding processing on the command clock signal based on an operation type of the command reliability list comprises: if the matching is successful, sending the command clock signal to the slave device through a second FSI bus so that the slave device responds to the command clock signal; the second FSI bus being a bus connecting the slave device and the programmable logic device.

3. The method of claim 2, wherein, After the sending the command clock signal to the slave device through a second FSI bus, further comprising: obtaining a response clock signal sent by the slave device through the second FSI bus; matching the response clock signal with a response signal format in a locally stored response reliability list; the response signal format being a message format supported by an FSI bus protocol; if the matching is successful, sending the response clock signal to the master device through the first FSI bus.

4. The method of claim 1, wherein, The matching the command clock signal with a command signal format in a locally stored command reliability list comprises: matching the command clock signal with a reset command signal format in a locally stored reset command reliability list; the operation type of the reset command reliability list being reset; The if the matching is successful, performing corresponding processing on the command clock signal based on an operation type of the command reliability list comprises: if the matching is successful, resetting the first FSI bus according to the command clock signal.

5. The method of claim 4, wherein, The resetting the first FSI bus according to the command clock signal comprises: turning on a reset enable signal in the programmable logic device according to the command clock signal, and pulling up the first FSI bus to reset the first FSI bus.

6. The method of claim 1 to 5, wherein, The matching the command clock signal with a command signal format in a locally stored command reliability list comprises: matching the command clock signal with a send command signal format in a locally stored send command reliability list; if the matching fails, matching the command clock signal with a reset command signal format in a locally stored reset command reliability list, and if the matching fails, determining the command clock signal as an abnormal command.

7. The method of claim 6, wherein, The determining the command clock signal as an abnormal command further comprises: discarding the command clock signal and generating a corresponding error interrupt to terminate the current communication.

8. A device communication apparatus based on FSI bus protocol, characterized by, The application is applied to a programmable logic device connected with a master device and a slave device, and comprises: a first acquisition module, configured to acquire a command clock signal sent by the master device through a first FSI bus; the first FSI bus is a bus connecting the master device and the programmable logic device; a first matching module, configured to match the command clock signal with a command signal format in a command reliability list stored locally; the command signal format is a message format supported by an FSI bus protocol; a processing module, configured to, if the matching is successful, perform corresponding processing on the command clock signal based on an operation type of the command reliability list.

9. An electronic device, comprising: The electronic device comprises a processor and a memory; wherein the memory is configured to store a computer program, the computer program is loaded and executed by the processor to implement the device communication method based on the FSI bus protocol as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer executable instructions are loaded and executed by the processor to implement the device communication method based on the FSI bus protocol as claimed in any one of claims 1 to 7.

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