Display panel and display device

Abstract

The application provides a display panel and a display device. A gate drive circuit of the display panel comprises a plurality of gate drive modules which are sequentially cascaded. Each gate drive module comprises a first gate drive unit and a second gate drive unit. The second gate drive unit comprises a first switch element. A first end of the first switch element is connected to a low-level signal of the display panel. A second end of the first switch element is connected to a corresponding pixel unit row to output a gate drive signal of the current stage. A control end of the first switch element receives a first start signal. The first start signal is a gate drive signal of the current stage provided by a gate drive module of a next stage which is one stage away from the current stage. The application guarantees the row driving capability of the display panel, reduces the size of the display device, effectively reduces the product cost, and improves the user experience.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of screen display, in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous development of electronic devices, people's requirements for display pictures are also getting higher and higher. As a kind of light emitting device, electrical display screens are applied in high performance display. The display devices with display panels are also used more and more widely. People's application of display panels is more diversified, and at the same time, higher requirements are put forward for the size, definition and stability of display panels and other aspects.

[0003] In the process of conceiving and implementing the present application, the inventors found that at least the following problems exist: the edge of the display panel needs to be provided with a gate drive circuit. For example, when each row of pixels of the display panel is scanned, a gate drive circuit needs to be provided with a set of same complex gate drive units in the peripheral area of each row of pixels to charge the corresponding row of pixels. With the wider application range of narrow frame display products, the size of the gate drive circuit is too large to restrict the further development of narrow frame display panels. SUMMARY

[0004] In view of the above technical problems, the present application provides a display panel, comprising a display area and a peripheral area surrounding the display area;

[0005] The display area comprises a plurality of pixel unit rows; the peripheral area is provided with a gate drive circuit, and the gate drive circuit comprises a plurality of gate drive modules connected in cascade;

[0006] Each gate drive module comprises a first gate drive unit and a second gate drive unit, and each pixel unit row is connected between the first gate drive unit and the second gate drive unit;

[0007] The first gate drive unit comprises an input circuit, a pull-down circuit, an output circuit and a stabilizing circuit; the second gate drive unit comprises a first switch, a second switch, a third switch and a fourth switch; the first end of the first switch is connected to a low level signal of the display panel; the second end of the first switch is connected to the corresponding pixel unit row to output a gate drive signal of the current stage; the control end of the first switch receives a first start signal; the first start signal is a gate drive signal of the current stage provided by a next stage gate drive module which is separated by one stage.

[0008] Optionally, the second gate drive unit further comprises a second switch, a third switch and a fourth switch;

[0009] The control end of the second switch element is connected with the second end of the first switch element and the second end of the third switch element, the first end of the second switch element is connected with the first end of the third switch element and the first end of the fourth switch element, and the second end of the second switch element is connected with the control end of the third switch element and the control end of the fourth switch element, so as to access the high-level signal of the display panel; and the second end of the fourth switch element is connected with the first end of the first switch element, so as to access the low-level signal.

[0010] Optionally, the output circuit comprises a fifth switch element and a first capacitor, and the first capacitor is connected between the control end and the second end of the fifth switch element.

[0011] The control end of the fifth switch element is connected with the input circuit through a first node, the first end of the fifth switch element accesses a first clock signal, and the second end of the fifth switch element outputs the gate drive signal of the current stage.

[0012] Optionally, the input circuit comprises a sixth switch element and a seventh switch element.

[0013] The control end and the first end of the sixth switch element receive the first start signal; the first end of the seventh switch element accesses a second clock signal, and the control end of the seventh switch element receives a second start signal, which is the gate drive signal of the current stage provided by a gate drive module of a previous stage separated by one stage.

[0014] The second end of the sixth switch element and the second end of the seventh switch element are connected with the first node.

[0015] Optionally, the pull-down circuit comprises an eighth switch element and a ninth switch element.

[0016] The control ends of the eighth switch element and the ninth switch element are connected with the first node.

[0017] The first end of the eighth switch element and the first end of the ninth switch element access the low-level signal, the second end of the eighth switch element is connected with the stabilization circuit through a second node, and the second end of the ninth switch element is connected with the stabilization circuit through a third node.

[0018] Optionally, the stabilization circuit comprises a tenth switch element, an eleventh switch element, a fourteenth switch element and a fifteenth switch element.

[0019] The first ends of the tenth switch element and the eleventh switch element are connected with the first node, and the second end of the tenth switch element and the second end of the eleventh switch element are connected with the low-level signal.

[0020] The control end of the tenth switch element is connected to the second node, and the control end of the eleventh switch element is connected to the third node.

[0021] The control end and the second end of the fourteenth switch element are connected to the first control signal, the control end and the second end of the fifteenth switch element are connected to the second control signal, the first end of the fourteenth switch element is connected to the second node, and the first end of the fifteenth switch element is connected to the third node.

[0022] Optionally, the stabilizing circuit further comprises twelfth and thirteenth switch elements, the control end of the twelfth switch element is connected to the first control signal, the control end of the thirteenth switch element is connected to the second control signal, the first end of the twelfth switch element is connected to the second node, the first end of the thirteenth switch element is connected to the third node, and the second ends of the twelfth and thirteenth switch elements are connected to the low-level signal.

[0023] Optionally, the stabilizing circuit further comprises sixteenth and seventeenth switch elements.

[0024] The first ends of the sixteenth and seventeenth switch elements are connected to the gate drive signal of the current stage, and the second ends of the sixteenth and seventeenth switch elements are connected to the low-level signal.

[0025] The control end of the sixteenth switch element is connected to the second node, and the control end of the seventeenth switch element is connected to the third node.

[0026] Optionally, the output circuit further comprises a twentieth switch element, the control end of the twentieth switch element is connected to the first node, the first end of the twentieth switch element is connected to the first clock signal, and the second end of the twentieth switch element outputs a transmission signal.

[0027] Optionally, the stabilizing circuit further comprises eighteenth and nineteenth switch elements.

[0028] The first ends of the eighteenth and nineteenth switch elements are connected to the second end of the twentieth switch element, and the second ends of the eighteenth and nineteenth switch elements are connected to the low-level signal.

[0029] The control end of the eighteenth switch element is connected to the second node, and the control end of the nineteenth switch element is connected to the third node.

[0030] Optionally, the first gate driving unit corresponding to each pixel unit row is arranged in the peripheral area of the first side of the display panel, and the second gate driving unit corresponding to each pixel unit row is arranged in the peripheral area of the second side of the display panel, wherein the first side and the second side are arranged on opposite sides of the display area.

[0031] Optionally, the first gate driving unit and the second gate driving unit are arranged in the peripheral area of the first side of the display panel in a preset alternating order.

[0032] The first gate driving unit and the second gate driving unit are arranged in the peripheral area of the second side of the display panel in an order corresponding to the preset alternating order, so that the first gate driving unit and the second gate driving unit are arranged on opposite sides of each pixel unit row.

[0033] Optionally, the preset alternating order is a one-to-one alternating manner, or the alternating order is a two-to-two alternating manner.

[0034] The present application also provides a display device, which comprises:

[0035] A data driving circuit is configured to provide a plurality of gray scale data.

[0036] The display area of the display panel has a plurality of pixel units arranged in an array, a plurality of gate lines, and a plurality of data lines.

[0037] According to the display panel described above, the gate driving circuit is capable of providing a plurality of gate driving signals.

[0038] The display panel receives the plurality of gate driving signals via the plurality of gate lines to select the plurality of pixel units in rows, and receives the plurality of gray scale data via the plurality of data lines to provide the selected pixel units to realize image display.

[0039] As described above, the display panel and the display device of the present application have the first gate driving unit and the second gate driving unit corresponding to each pixel unit row, which correspond to the main charging circuit and the auxiliary charging circuit of the pixel unit row, respectively, so that each row of pixels can be mutually assisted by different gate driving unit circuits, which ensures the row driving capability of the display panel while effectively reducing the size of the display device, effectively reducing the product cost, and improving the user experience. BRIEF DESCRIPTION OF DRAWINGS

[0040] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate preferred embodiments of the present application and, together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0041] Figure 1 A schematic diagram of a display panel of an embodiment of the present application.

[0042] Figure 2 A schematic diagram of the architecture of the nth stage gate drive module of the gate drive circuit of an embodiment of the present application.

[0043] Figure 3 A schematic diagram of the second gate drive unit circuit of an embodiment of the present application.

[0044] Figure 4 A schematic diagram of the first gate drive unit circuit of an embodiment of the present application Figure 1 .

[0045] Figure 5 A schematic diagram of the first gate drive unit circuit of an embodiment of the present application Figure 2 .

[0046] Figure 6 A schematic diagram of the first gate drive unit circuit of an embodiment of the present application Figure 3 .

[0047] Figure 7 A schematic diagram of the first gate drive unit circuit of an embodiment of the present application Figure 4 .

[0048] Figure 8 A timing diagram of the operation of the gate drive circuit of an embodiment of the present application.

[0049] Figure 9 A schematic diagram of the layout of the display panel of an embodiment of the present application Figure 1 .

[0050] Figure 10 A schematic diagram of the layout of the display panel of an embodiment of the present application Figure 2 .

[0051] Figure 11 A schematic diagram of the layout of the display panel of an embodiment of the present application Figure 3 .

[0052] The objectives, features and advantages of the present application will be further illustrated in conjunction with the embodiments, with reference to the drawings. The above-mentioned drawings have shown the specific embodiments of the present application, and will be described in more detail hereinafter. These drawings and the written description are not intended to restrict the scope of the present application in any way, but to illustrate the concept of the present application for those skilled in the art by referring to the specific embodiments. DETAILED DESCRIPTION

[0053] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, the same or similar components are designated by the same or similar reference numerals, and the description of the same or similar components will not be repeated. The embodiments described in the following exemplary embodiments do not represent all the embodiments consistent with the present application. Rather, they are merely examples in accordance with some aspects of the present application, as detailed in the appended claims.

[0054] It should be noted that, in this document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element, and the same applies to other similar terms such as "comprising", "includes" and "including". Components, features, elements with the same name in different embodiments of the present application can have the same meaning or different meanings, and the specific meaning thereof should be determined in the explanation of the specific embodiment or further in conjunction with the context of the specific embodiment.

[0055] It should be understood that, although terms first, second, third, etc. can be used herein to describe various information, the information should not be limited to these terms. These terms are used only to distinguish one category of information from another category of information. For example, a first information can also be termed a second information, similarly, a second information can also be termed a first information without departing from the scope of this document. The word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining" depending on the context. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", as used herein, specify the presence of stated features, steps, operations, elements, components, items, and / or groups but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, items, and / or groups thereof. The term "or", "and / or", "at least one of", and the like as used herein can be interpreted as inclusive or as meaning any one or any combination. For example, "A, B or C" or "A, B, and / or C" can mean "A; B; C; A and B; A and C; B and C; A, B and C" in an inclusive sense. An exception to this definition will occur if the combination of elements, functions, steps or acts to achieve a given result is inherently mutually exclusive.

[0056] The word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if detecting (a stated condition or event)" can be interpreted as "when determined" or "in response to determining" or "when detecting (a stated condition or event)" or "in response to detecting (a stated condition or event)" depending on the context.

[0057] It should be understood that the specific embodiments described herein are merely illustrative of the present application and should not be used to limit the present application in any manner.

[0058] In the following description, suffixes "module", "part" or "unit" used for components are merely intended for facilitating description of the present application, and are not intended to limit the present application. Therefore, "module", "part" or "unit" can be mixedly used.

[0059] In the following description, a mobile terminal will be used as an example, and those skilled in the art will understand that the configuration according to the embodiments of the present application can be applied to a terminal of a stationary type, except for elements particularly used for mobile purposes.

[0060] First embodiment

[0061] To solve the above technical problems, the present application provides a display panel, Figure 1 A schematic diagram of the display panel according to an embodiment of the present application is shown.

[0062] As Figure 1 shown, in an embodiment, the display panel PNL includes a display area AA and a peripheral area BB surrounding the display area.

[0063] The display area includes a plurality of pixel unit rows. In the display area AA, a pixel array and a pixel driving circuit PDC for driving the pixel array are provided. Each pixel in the pixel array can be a liquid crystal light valve or a self-luminous element. Under the control of the pixel driving circuit PDC, each pixel emits light independently, so that the display panel PNL can display images.

[0064] Exemplarily, the display panel PNL can be a liquid crystal display panel or an LED display panel. Taking a liquid crystal panel as an example, it includes a correspondingly arranged array substrate and a color film substrate, and a liquid crystal molecule is filled in the liquid crystal box formed by the array substrate and the color film substrate, so that each pixel can be a liquid crystal unit as a light valve. Each liquid crystal unit includes two electrodes for controlling the electric field and liquid crystal deflected under the control of the electric field. Among the two electrodes, one can be a pixel electrode providing a pixel signal, and the other can be a common electrode. The common electrodes of the liquid crystal units can be electrically connected to each other to load a common voltage. The pixel driving circuit PDC can be electrically connected to each pixel electrode one by one to adjust the electric field of the pixel electrode corresponding area by controlling the voltage on the pixel electrode, and then control the deflection degree of the liquid crystal in the pixel electrode corresponding area. In this way, the display panel PNL can control the light transmittance of each liquid crystal unit under the cooperation of the upper polarizer and the lower polarizer. In another embodiment, the display panel PNL can be a display panel with a self-luminous element, which can be selected from OLED, PLED, QLED, Q-OLED, Micro LED, Mini LED, etc. The display panel PNL can include a substrate BP, a driving layer and a pixel layer which are sequentially stacked. Among them, the light emitting element is arranged in the pixel layer as a sub-pixel, and the pixel driving circuit PDC for driving each pixel is arranged in the driving layer. The pixel driving circuit PDC can control the size of the current flowing through the light emitting element, and then control the luminous intensity of the light emitting element.

[0065] The peripheral area is provided with a gate driving circuit, and the gate driving circuit includes a plurality of gate driving modules which are sequentially cascaded.

[0066] Please continue to see Figure 1The display panel PNL can further be provided with scan lines GL extending along the row direction DH and driving data lines extending along the column direction DV, and the pixel driving circuit PDC can be electrically connected with the scan lines GL and the driving data lines. Under the control of a scan signal on the scan line GL, the pixel driving circuit PDC can receive driving data loaded on the driving data line, and then control the brightness of the sub-pixel according to the received driving data. For example, the pixel driving circuit PDC can include a data writing transistor, a control terminal of the data writing transistor being electrically connected with the scan line GL, and an input terminal of the data writing transistor being electrically connected with the driving data line. When a scan signal is loaded on the scan line GL, the data writing transistor is turned on, and then the driving data loaded on the driving data line is written into the capacitor of the pixel driving circuit PDC. When no scan signal is loaded on the scan line GL, the data writing transistor is electrically cut off, and then the driving data loaded on the driving data line cannot be written into the capacitor of the pixel driving circuit PDC.

[0067] For example, the display panel PNL can include a plurality of pixel units arranged in a matrix form, each pixel unit including a plurality of sub-pixels arranged in a matrix form. Figure 1 The peripheral area around the display area AA can be provided with a gate driving circuit GDC for loading a scan signal to each scan line GL. Optionally, the gate driving circuit GDC is arranged at one side of the display area AA along the row direction DH, and can include a plurality of gate driving modules GOA cascaded in sequence, and each scan line GL can be electrically connected with an output terminal of one gate driving module GOA. In this way, when the shift register unit GOA outputs a scan signal, the scan signal can be loaded to the scan line GL. In the related art, each gate driving module GOA in the gate driving circuit GDC is the same, and arranged in sequence along the column direction DV. However, this arrangement mode can cause the gate driving circuit GDC to occupy a larger area, and then can cause the frame of the display panel PNL to increase, which is not conducive to the narrow frame of the display panel PNL.

[0068] For example, the display panel PNL can include a plurality of pixel units arranged in a matrix form, each pixel unit including a plurality of sub-pixels arranged in a matrix form. Figure 2 In an embodiment, each gate driving module includes a first gate driving unit and a second gate driving unit, and each pixel unit row is connected between the first gate driving unit and the second gate driving unit.

[0069] The gate driving circuit GDC is provided with two different gate driving units, i.e., the first gate driving unit GOAA and the second gate driving unit GOAB. For example, in the cascading relationship, the first gate driving unit GOAA and the second gate driving unit GOAB are spaced apart from each other and arranged alternately.

[0070] Figure 2 The architecture schematic diagram of the nth gate driving module of the gate driving circuit of an embodiment of the present application.

[0071] For example, the display panel PNL can include a plurality of pixel units arranged in a matrix form, each pixel unit including a plurality of sub-pixels arranged in a matrix form. Figure 2The first gate driving unit GOAA comprises an input circuit, a pull-down circuit, an output circuit and a stabilizing circuit; the second gate driving unit GOAB comprises a first switch T1, a first end of the first switch T1 is connected to a low voltage signal VGL of the display panel, a second end of the first switch T1 is connected to a corresponding pixel unit row to output a gate driving signal Gn of the current stage, and a control end of the first switch T1 receives a first start signal Gn+2, the first start signal being a gate driving signal of the current stage provided by a gate driving module of a next stage.

[0072] Exemplarily, the first gate driving unit GOAA can have a conventional input circuit, a pull-down circuit, an output circuit and a stabilizing circuit, thus having rich and stable driving functions and a relatively large number of transistors for main charging of the corresponding pixel row. The second gate driving circuit GOAB is provided with a transistor as a first switch for auxiliary charging of the corresponding pixel row. In this way, by providing the corresponding main charging unit and auxiliary charging unit for each column of pixel units, the rich functions and stable effects of the first gate driving unit GOAA with more switches can be utilized, and the total number of switches required by the driving circuit GDC can be reduced by providing the second gate driving unit GOAB. The second gate driving unit GOAB can also suppress the noise of the first gate driving unit GOAA and improve the stability of the gate driving signal Gn output by the gate driving module GOA. Since the first gate driving unit is used to improve the working stability, the problem of insufficient functions when all the second gate driving units GOAB are used can be avoided. Thus, each row of pixels can be mutually assisted by different gate driving unit circuits, the row driving capability of the display panel is ensured, the size of the display device is effectively reduced, the product cost is effectively reduced, and the user experience is improved.

[0073] Please refer to Figure 2 The gate driving circuit of one embodiment comprises a plurality of stages of gate driving modules GOA, and the nth stage of gate driving module GOA is used to drive a corresponding gate line of the display panel. Figure 2 Figure 2 ​As shown, the first gate driving unit GOAA of each stage of the gate driving module includes a front-to-back stage signal input terminal 11, a first clock signal input terminal 12, a second clock signal input terminal 13, a low-level signal input terminal 14, and a local stage signal output terminal 15. The front-to-back stage signal input terminal 11 can be used to receive the local stage gate driving signal and local stage transmission signal from the previous k-stage or subsequent k-stage gate driving units, where k is a positive integer. In some other embodiments, the front-to-back stage signal input terminal 11 can also be used to receive a start signal. The first clock signal input terminal 12 and the second clock signal input terminal 13 can be used to receive clock signals. The low-level signal input terminal 14 is used to receive the low-level signal VGL. The local stage signal output terminal 15 can be used to output the local stage gate driving signal Gn and the local stage transmission signal Zn. The local stage gate driving signal Gn is used to drive the gate line of a pixel row corresponding to the nth stage gate driving display panel, and the local stage transmission signal Zn can be used to control the pre-charging process of the next stage gate driving module.

[0074] For example, in the first gate drive unit GOAA, the input circuit and Figure 2 The input terminals 11 of the input circuit are connected to the front and rear stage signal inputs, and are used to receive the front k stage Gn-k or rear k stage drive signal Gn+k and the front k stage transfer signal Zn-k or rear k stage transfer signal Zn-k, etc. The output terminal of the input circuit is connected to the first node Q, and is used to pre-charge the first node Q according to the front and rear stage drive signals and the front and rear stage transfer signals. In one embodiment, the input circuit also simultaneously receives the second clock signal CLK2.

[0075] Please continue to refer to this. Figure 3 For example, the output circuit is connected to the first node Q and the first clock signal input terminal 12 to output the received first clock signal CLK1 as the gate drive signal Gn and the transmission signal Zn of the current stage according to the control voltage of the first node Q.

[0076] For example, the pull-down circuit is connected to the first node Q, the low-level signal input terminal 14, and the stabilization circuit to receive the control voltage of the first node Q and the low-level signal VGL, respectively, and to provide the low-level signal VGL to the stabilization circuit according to the control voltage of the first node Q.

[0077] For example, the stabilizing circuit is connected to the control signal input terminal and the low-level signal input terminal, and can alternately provide the low-level signal VGL to the first node Q, the gate drive signal output terminal of this stage, and the transmission signal output terminal of this stage according to the control of the control signal.

[0078] Figure 3 This is a schematic diagram of the second gate driving unit circuit according to an embodiment of this application.

[0079] Please refer to Figure 4Optionally, the second gate driving unit GOAB further comprises a second switch T2, a third switch T3 and a fourth switch T4.

[0080] The control end of the second switch T2 is connected with the second end of the first switch T1 and the second end of the third switch T3, the first end of the second switch T2 is connected with the first end of the third switch T3 and the first end of the fourth switch T4, and the second end of the second switch T2 is connected with the control end of the third switch T3 and the control end of the fourth switch T4, so as to access the high level signal of the display panel; the second end of the fourth switch T4 is connected with the first end of the first switch T1, so as to access the low level signal.

[0081] Exemplarily, the second switch T2, the third switch T3 and the fourth switch T4 constitute a pull-down circuit of the second gate driving unit GOAB, which can enhance the noise suppression of the first gate driving unit GOAA, improve the stability of the gate driving signal Gn output by the gate driving module GOA, improve the high-temperature stability of the gate driving module GOA, and make the product adapt to more stringent high-temperature reliability tests.

[0082] Figure 1 The first gate driving unit circuit of an embodiment of the present application Figure 4 .

[0083] Please refer to Figure 3 Optionally, the output circuit comprises a fifth switch T5 and a first capacitor C. The first capacitor C is connected between the control end and the second end of the fifth switch T5.

[0084] The control end of the fifth switch T5 is connected with the input circuit through the first node, the first end of the fifth switch T5 accesses the first clock signal CLK1, and the second end of the fifth switch T5 outputs the gate driving signal Gn of the current stage.

[0085] The first capacitor C is the parasitic capacitor between the control end and the second end of the fifth switch T5. Understandably, in another embodiment, an independent capacitor can also be arranged between the control end and the second end of the fifth switch T5, and at this time, the first capacitor C is the sum of the parasitic capacitor and the independent storage capacitor between the control end and the second end of the fifth switch T5. Please refer to Figure 4 The output circuit is connected with the first node Q and the first clock signal input end 12, so as to output the gate driving signal Gn of the current stage according to the control voltage of the first node Q and the received first clock signal CLK1.

[0086] Please continue to refer to Figure 4 Optionally, the input circuit comprises a sixth switch T6 and a seventh switch T7.

[0087] The control end and the first end of the sixth switch T6 receive a first start signal Gn-2; the first end of the seventh switch T7 is connected to a second clock signal CLK2, and the control end of the seventh switch T7 receives a second start signal Gn+2, which is a gate drive signal of a next stage provided by a gate drive module of a previous stage;

[0088] The second end of the sixth switch T6 and the second end of the seventh switch T7 are connected to the first node Q.

[0089] Exemplarily, the input end of the input circuit receives the first start signal Gn-2, the second start signal Gn+2 and the second clock signal CLK2, and the output end is connected to the first node Q to pre-charge the first node Q according to the first start signal Gn-2, the second start signal Gn+2 and the second clock signal CLK2.

[0090] Please continue to refer to Figure 4 Optionally, the pull-down circuit comprises an eighth switch T8 and a ninth switch T9.

[0091] The control ends of the eighth switch T8 and the ninth switch T9 are connected to the first node Q.

[0092] The first end of the eighth switch T8 and the first end of the ninth switch T9 are connected to a low-level signal VGL, the second end of the eighth switch T8 is connected to a stabilizing circuit through a second node QB2, and the second end of the ninth switch T9 is connected to the stabilizing circuit through a third node QB3.

[0093] Exemplarily, the pull-down circuit is connected to the second node QB2 and the third node QB3, so as to provide the low-level signal VGL to the first node Q to pull down the potential of the first node Q according to the control voltage of the second node QB2 and the third node QB3.

[0094] Please continue to refer to Figure 5 Optionally, the stabilizing circuit comprises a tenth switch T10, an eleventh switch T11, a fourteenth switch T14 and a fifteenth switch T15.

[0095] The first ends of the tenth switch T10 and the eleventh switch T11 are connected to the first node Q, and the second ends of the tenth switch T10 and the eleventh switch T11 are connected to the low-level signal VGL.

[0096] The control end of the tenth switch T10 is connected to the second node QB2, and the control end of the eleventh switch T11 is connected to the third node QB3.

[0097] The control end and the second end of the fourteenth switch T14 are connected to the first control signal V1, the control end and the second end of the fifteenth switch T15 are connected to the second control signal V2, the first end of the fourteenth switch T14 is connected to the second node QB2, and the first end of the fifteenth switch T15 is connected to the third node QB3.

[0098] Figure 2 A first gate driving unit circuit of an embodiment of the present application is shown in FIG. 1. Figure 5 .

[0099] Referring to FIG. 1, the first gate driving unit circuit includes a first node Q, a second node QB2, a third node QB3, a first control signal V1, a second control signal V2, a low-level signal VGL, a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, a fifth switch T5, a sixth switch T6, a seventh switch T7, an eighth switch T8, a ninth switch T9, a tenth switch T10, an eleventh switch T11, a twelfth switch T12, a thirteenth switch T13, a fourteenth switch T14, and a fifteenth switch T15. Figure 6 The first end of the twelfth switch T12 is connected to the second node QB2, the first end of the thirteenth switch T13 is connected to the third node QB3, and the second end of the twelfth switch T12 and the second end of the thirteenth switch T13 are connected to the low-level signal VGL.

[0100] The first end of the twelfth switch T12 is connected to the second node QB2, the first end of the thirteenth switch T13 is connected to the third node QB3, and the second end of the twelfth switch T12 and the second end of the thirteenth switch T13 are connected to the low-level signal VGL.

[0101] Figure 3 A first gate driving unit circuit of an embodiment of the present application is shown in FIG. 1. Figure 6 .

[0102] Referring to FIG. 1, the first gate driving unit circuit includes a first node Q, a second node QB2, a third node QB3, a first control signal V1, a second control signal V2, a low-level signal VGL, a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, a fifth switch T5, a sixth switch T6, a seventh switch T7, an eighth switch T8, a ninth switch T9, a tenth switch T10, an eleventh switch T11, a twelfth switch T12, a thirteenth switch T13, a fourteenth switch T14, and a fifteenth switch T15. Figure 7 The first end of the twelfth switch T12 is connected to the second node QB2, the first end of the thirteenth switch T13 is connected to the third node QB3, and the second end of the twelfth switch T12 and the second end of the thirteenth switch T13 are connected to the low-level signal VGL.

[0103] The control end of the twelfth switch T12 is connected to the second node QB2, and the control end of the thirteenth switch T13 is connected to the third node QB3.

[0104] The first end of the twelfth switch T12 is connected to the second node QB2, the first end of the thirteenth switch T13 is connected to the third node QB3, and the second end of the twelfth switch T12 and the second end of the thirteenth switch T13 are connected to the low-level signal VGL.

[0105] The first end of the twelfth switch T12 is connected to the second node QB2, the first end of the thirteenth switch T13 is connected to the third node QB3, and the second end of the twelfth switch T12 and the second end of the thirteenth switch T13 are connected to the low-level signal VGL.

[0106] Figure 4 A first gate driving unit circuit of an embodiment of the present application is shown in FIG. 1. Figure 7 .

[0107] As Figure 7 Optionally, the output circuit further comprises a twentieth switch T20. A control terminal of the twentieth switch T20 is connected to the first node Q, a first terminal of the twentieth switch T20 is connected to the first clock signal CLK1, and a second terminal of the twentieth switch T20 outputs the transfer signal Zn.

[0108] Exemplarily, the output circuit receives the first clock signal, and outputs the transfer signal Zn according to the control voltage of the first node Q, through the twentieth switch T20.

[0109] Optionally, the stabilizing circuit further comprises an eighteenth switch T18 and a nineteenth switch T19.

[0110] The first terminals of the eighteenth switch T18 and the nineteenth switch T19 are connected to the second terminal of the twentieth switch T20, and the second terminals of the eighteenth switch T18 and the nineteenth switch T19 are connected to the low-level signal VGL.

[0111] The control terminal of the eighteenth switch T18 is connected to the second node QB2, and the control terminal of the nineteenth switch T19 is connected to the third node QB3.

[0112] Exemplarily, the stabilizing circuit outputs the low-level signal VGL to the second terminal of the twentieth switch T20 according to the control signals of the second node QB2 and the third node QB3, through the eighteenth switch T18 and the nineteenth switch T19, so as to stabilize the output signal of the transfer signal Zn.

[0113] Please continue to refer to Figure 8 Optionally, the eighth switch T8, the ninth switch T9, the tenth switch T10, the eleventh switch T11, the twelfth switch T12 and the thirteenth switch T13 can also not be connected to the low-level signal VGL, but be connected to a preset voltage signal VSQ instead. Exemplarily, the preset voltage signal VSQ can be a negative voltage.

[0114] Figure 8 The timing diagram of the gate driving circuit of an embodiment of the present application.

[0115] As Figure 9As shown, the first clock signal CLK1 and the second clock signal CLK2 are both square wave signals. According to system requirements, the system can also set a third clock signal CLK3 and a fourth clock signal CLK4. Exemplarily, the clock period is 4T, and the duty cycle is 1 / 2. T is a predetermined clock period, for example, the minimum clock period of a system clock signal or an integer multiple of the minimum clock period. The first clock signal CLK1 is 1 / 4T earlier than the second clock signal CLK2. The first control signal V1 is a high-low level signal, and the second control signal V2 is a high-low level signal, wherein the first control signal V1 and the second control signal V2 change simultaneously and in opposite directions.

[0116] The gate drive circuit of the embodiment can sequentially cascade, pre-charge the pixels one level away from the pixel column charging when one of the gate drive modules charges the pixel column, reduce the number of simultaneously opened gate lines, reduce the overlapping period of the output waveforms of adjacent gate drive units, avoid the horizontal stripe phenomenon during display, and improve the display quality of the display panel.

[0117] It should be noted that the first to twentieth switch elements T1-T20 can be implemented by using, for example, amorphous silicon TFT, oxide TFT, or low-temperature polysilicon N-TFT, etc. For example, in the embodiment of the application, the first to twentieth switch elements T1-T20 can be N-type thin film transistors, and the drain and gate of each transistor can be interchanged, but the application is not limited thereto.

[0118] In the embodiment, by designing a corresponding first gate drive unit and a second gate drive unit for each pixel unit row, respectively corresponding to the main charging circuit and the auxiliary charging circuit of the pixel unit row, each row of pixels can be mutually assisted by different gate drive unit circuits, while ensuring the row driving capability of the display panel, effectively reducing the size of the display device, effectively reducing the product cost, and improving the user experience.

[0119] Second Embodiment

[0120] On the basis of the first embodiment, the application further provides a layout mode of the display panel. Figure 1 Layout of the display panel of an embodiment of the application Figure 9 .

[0121] Optionally, the first gate drive unit corresponding to each pixel unit row is arranged in the peripheral area of the first side of the display panel, and the second gate drive unit corresponding to each pixel unit row is arranged in the peripheral area of the second side of the display panel, wherein the first side and the second side are arranged on the two sides of the display area.

[0122] As Figure 10As shown, optionally, the first gate driving unit corresponding to each pixel unit row is unit A, which is disposed in the peripheral area on the left side of the display panel, and the second gate driving unit corresponding to each pixel unit row is unit B, which is disposed in the peripheral area on the right side of the display panel. As can be seen from the first embodiment, since unit B has fewer components, its occupied area can be relatively small, thus effectively reducing the area of ​​the peripheral area on the second side of the display panel, which is beneficial to the narrow bezel design of the display device.

[0123] Optionally, in the peripheral area on the first side of the display panel, the first gate driving unit and the second gate driving unit are alternately arranged in a preset alternating order.

[0124] In the peripheral area on the second side of the display panel, the first gate driving unit and the second gate driving unit are alternately arranged in a sequence corresponding to a preset alternation order, so that the first gate driving unit and the second gate driving unit are respectively located on both sides of each pixel unit row.

[0125] Figure 2 This is a schematic diagram of the display panel layout according to an embodiment of this application. Figure 11 . Figure 3 This is a schematic diagram of the display panel layout according to an embodiment of this application. Figure 10 .

[0126] Please refer to Figure 11 Optionally, the default alternation order is one-to-one alternation. Please refer to [reference needed]. ​ Optionally, the alternation order can be a pairwise alternation.

[0127] By setting the alternating order of unit A and unit B in a preset alternation sequence, the circuit characteristics of unit A and unit B can be effectively combined to create a layout that saves more space, thereby effectively reducing the peripheral area of ​​the display panel and facilitating the narrow-bezel design of the display device. It should be noted that this application is not limited to these arrangements; other layouts combining multiple switching components are also possible. The display panel can select a suitable alternation order based on specific circumstances.

[0128] Third Embodiment

[0129] This application also provides a display device, the display device comprising:

[0130] Data driving circuitry is used to provide multiple grayscale data.

[0131] The display area of ​​the display panel has multiple pixel units arranged in an array, as well as multiple gate lines and multiple data lines.

[0132] According to the aforementioned display panel, the gate drive circuit is capable of providing multiple gate drive signals.

[0133] The display panel receives a plurality of gate driving signals via a plurality of gate lines to select a plurality of pixel units in rows, and receives a plurality of gray scale data via a plurality of data lines to provide the selected pixel units to realize image display.

[0134] The display device provided in the application can work by two clock signals and two control signals, thereby reducing the number of signal lines and signal line load, reducing the required wiring area, facilitating the design of narrow frame, and facilitating the reduction of power consumption of the circuit.

[0135] In the display device provided in the application, the transmission signal and the gate driving signal of the gate driving circuit are output through different terminals, reducing the influence of signal transmission on the gate driving, so that the output capacity of the gate driving unit is strong.

[0136] In the preferred display device embodiment, a bidirectional scanning gate driving circuit is provided, which has two modes of forward scanning and reverse scanning, can increase the use degree of freedom of the display panel, and provides a flexible driving mode for the display device.

[0137] As described above, the display panel and the display device of the application, by designing a corresponding first gate driving unit and a second gate driving unit for each pixel unit row, respectively corresponding to the main charging circuit and the auxiliary charging circuit of the pixel unit row, so that each row of pixels can be mutually assisted by different gate driving unit circuits, while ensuring the row driving capability of the display panel, effectively reducing the size of the display device, effectively reducing the product cost, and improving the user experience.

[0138] The above-mentioned examples are only for reference, and in order to avoid redundancy, they are not listed one by one here, and in actual development or application, they can be flexibly combined according to actual needs, but any combination belongs to the technical solutions of the application, and is covered within the protection scope of the application.

[0139] It can be understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided by the embodiments of the application. The technical solutions provided by the embodiments of the application can also be applied to other scenarios. For example, those skilled in the art can know that, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of the application are also applicable to similar technical problems.

[0140] The above-mentioned application example serial numbers are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0141] The steps in the method of the embodiments of the application can be adjusted, combined and deleted according to actual needs.

[0142] The units in the device of the embodiments of the present application can be combined, divided, and deleted according to actual needs.

[0143] In the present application, for the same or similar term concept, technical solution and / or application scenario description, generally only the first time is described in detail, and the repeated description is not repeated in order to be brief, and in understanding the technical solutions of the present application, the same or similar term concept, technical solution and / or application scenario description which is not described in detail can be referred to the previous related description.

[0144] In the present application, the description of each embodiment has its own emphasis, and the part not described or recorded in a certain embodiment can be referred to the related description of other embodiments.

[0145] The technical features of the technical solutions of the present application can be combined arbitrarily, in order to make the description simple, the above-mentioned technical features of each embodiment are not described all possible combinations, however, as long as the combination of these technical features does not exist contradictory, should be considered as the range recorded in the present application.

[0146] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is the better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of software product, and the computer software product is stored in the above-mentioned storage medium (such as ROM / RAM, magnetic disc, optical disc), including a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server, controlled terminal, or network device, etc.) execute the method of each embodiment of the present application.

[0147] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a storage medium or transferred from one storage medium to another storage medium, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) mode. The storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (such as floppy disk, storage disk, magnetic tape), optical media (such as DVD), or semiconductor media (such as solid state disk (SSD)) and the like.

[0148] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a peripheral area surrounding the display area; The display area comprises a plurality of pixel unit rows; the peripheral area is provided with a gate drive circuit, and the gate drive circuit comprises a plurality of gate drive modules connected in series; Each gate drive module comprises a first gate drive unit and a second gate drive unit, and each pixel unit row is connected between the first gate drive unit and the second gate drive unit; The first gate drive unit comprises an input circuit, a pull-down circuit, an output circuit and a stabilization circuit; The output circuit comprises a fifth switch element and a first capacitor, the first capacitor is connected between the control end and the second end of the fifth switch element, the control end of the fifth switch element is connected with the input circuit through a first node, the first end of the fifth switch element is connected with a first clock signal, and the second end of the fifth switch element outputs a gate drive signal of the current stage; The input circuit comprises a sixth switch element and a seventh switch element, the control end and the first end of the sixth switch element receive a first start signal; the first end of the seventh switch element is connected with a second clock signal, the control end of the seventh switch element receives a second start signal, the second start signal is a gate drive signal of the current stage provided by a gate drive module of a previous stage which is separated by one stage; and the second end of the sixth switch element and the second end of the seventh switch element are connected with the first node; The pull-down circuit comprises an eighth switch element and a ninth switch element, the control ends of the eighth switch element and the ninth switch element are connected with the first node, the first ends of the eighth switch element and the ninth switch element are connected with a low-level signal, the second end of the eighth switch element is connected with the stabilization circuit through a second node, and the second end of the ninth switch element is connected with the stabilization circuit through a third node; The stabilization circuit comprises a tenth switch element, an eleventh switch element, a fourteenth switch element and a fifteenth switch element, the first ends of the tenth switch element and the eleventh switch element are connected with the first node, the second ends of the tenth switch element and the eleventh switch element are connected with the low-level signal; the control end of the tenth switch element is connected with the second node, and the control end of the eleventh switch element is connected with the third node; the control end and the second end of the fourteenth switch element are connected with a first control signal, the control end and the second end of the fifteenth switch element are connected with a second control signal, the first end of the fourteenth switch element is connected with the second node, and the first end of the fifteenth switch element is connected with the third node, wherein the first control signal and the second control signal change simultaneously and in opposite directions; The second gate drive unit comprises a first switch element, the first end of the first switch element is connected with a low-level signal of a display panel, the second end of the first switch element is connected with a corresponding pixel unit row to output a gate drive signal of the current stage, and the control end of the first switch element receives a first start signal, the first start signal is a gate drive signal of the current stage provided by a gate drive module of a next stage which is separated by one stage.

2. The display panel of claim 1, wherein, The second gate drive unit further comprises a second switch element, a third switch element and a fourth switch element. The control end of the second switch element is connected with the second end of the first switch element and the second end of the third switch element, the first end of the second switch element is connected with the first end of the third switch element and the first end of the fourth switch element, the second end of the second switch element is connected with the control end of the third switch element and the control end of the fourth switch element, so as to access the high-level signal of the display panel; the second end of the fourth switch element is connected with the first end of the first switch element, so as to access the low-level signal.

3. The display panel of claim 2, wherein, The stabilizing circuit further comprises a twelfth switch element and a thirteenth switch element, the control end of the twelfth switch element accesses the first control signal, the control end of the thirteenth switch element accesses the second control signal, the first end of the twelfth switch element is connected with the second node, the first end of the thirteenth switch element is connected with the third node, and the second ends of the twelfth switch element and the thirteenth switch element are connected with the low-level signal; and / or, The stabilizing circuit further comprises a sixteenth switch element and a seventeenth switch element, the first ends of the sixteenth switch element and the seventeenth switch element access the gate drive signal of the current stage, and the second end of the sixteenth switch element and the second end of the seventeenth switch element are connected with the low-level signal. The control end of the sixteenth switch element is connected with the second node, and the control end of the seventeenth switch element is connected with the third node.

4. The display panel of claim 3, wherein, The output circuit further comprises a twentieth switch element, the control end of the twentieth switch element is connected with the first node, the first end of the twentieth switch element accesses the first clock signal, and the second end of the twentieth switch element outputs a transfer signal.

5. The display panel of claim 4, wherein, The stabilizing circuit further comprises an eighteenth switch element and a nineteenth switch element; The first ends of the eighteenth switch element and the nineteenth switch element are connected with the second end of the twentieth switch element, and the second end of the eighteenth switch element and the second end of the nineteenth switch element are connected with the low-level signal; The control end of the eighteenth switch element is connected with the second node, and the control end of the nineteenth switch element is connected with the third node.

6. The display panel of any one of claims 1-5, wherein, The first gate drive unit corresponding to each pixel unit row is arranged in the peripheral area of the first side of the display panel, and the second gate drive unit corresponding to each pixel unit row is arranged in the peripheral area of the second side of the display panel, wherein the first side and the second side are oppositely arranged on the two sides of the display area. And / or, In the peripheral area of the first side of the display panel, the first gate drive unit and the second gate drive unit are alternately arranged in a preset alternating order; In the peripheral area of the second side of the display panel, the first gate drive unit and the second gate drive unit are alternately arranged in an order corresponding to the preset alternating order, so that the first gate drive unit and the second gate drive unit respectively correspond to each pixel unit row on the two sides.

7. The display panel of claim 6, wherein, The preset alternating order is a one-to-one alternating manner, or the alternating order is a two-by-two alternating manner.

8. A display device, characterized by comprising: The display device comprises: a data driving circuit configured to provide a plurality of gray scale data; The display panel has a display area with a plurality of pixel units arranged in an array, a plurality of gate lines and a plurality of data lines, The display panel according to any one of claims 1-7, wherein the gate driving circuit is capable of providing a plurality of gate driving signals. The display panel receives the plurality of gate driving signals via the plurality of gate lines to select the plurality of pixel units in rows, and receives the plurality of gray scale data via the plurality of data lines to provide to the selected pixel units to realize image display.

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