Gate drive circuit and display device

Abstract

The invention discloses a gate driving circuit and a display device, the gate driving circuit comprises multiple levels of cascaded gate driving units, and each level of gate driving unit comprises an input module which generates a first node voltage according to a preceding-level gate driving signal, a preceding-level gate transmission signal, a backward-level gate driving signal and a third clock signal; the output module is used for generating a current-stage gate driving signal and a transmission signal according to the first node voltage and a second clock signal; the chamfering module is used for adjusting the current-stage gate driving signal according to the first node voltage and the second clock sub-signal; wherein the falling edge of the second clock sub-signal is earlier than the falling edge of the second clock signal, the second clock sub-signal is adopted to perform chamfering on the gate driving signal through the chamfering module, so that the gate driving signal with the chamfering characteristic is generated, and the gate driving signal can effectively suppress the fluctuation amplitude of feed-through voltage of the display panel; the problem of non-uniform display pictures is improved, and the display quality is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, more particularly, to a gate driving circuit and a display device. BACKGROUND

[0002] As a common core carrier of information presentation, the basic structure of a display device usually includes a display panel, a gate driving circuit and a source driving circuit. The display panel has a pixel array composed of a plurality of pixel units, each of which includes a thin film transistor. In the pixel array of the display panel, the gate of the thin film transistor of the same row of pixel units is connected to the same scan line and the gate driving circuit, and the gate driving circuit can realize the row-by-row selection of each row of pixel units in the pixel array through a plurality of scan lines. The source or drain of the thin film transistor of the same column of pixel units in the pixel array is connected to the same data line and the source driving circuit, and the source driving circuit applies a data voltage (gray scale voltage) to each column of pixel units through a plurality of data lines, so as to finally make the display panel display the corresponding target image.

[0003] With the evolution of display technology towards high integration, thin and small size, the application of integrated gate driving technology (Gate Driver In Array, GIA) is also becoming more and more widespread. By integrating the gate driving circuit and the display panel on the same substrate, not only can a large number of external wires be reduced, the structural symmetry and overall compactness of the display device can be significantly improved, but also the cost of bottom production and manufacturing can be reduced, and the resolution and bendable performance of the display panel can be improved. However, in the transistor panel using this technology, the gate scan line has inherent resistance-capacitance delay characteristics, which will cause the waveform of the "near-end" scan pulse signal of the gate line close to the signal application end to be inconsistent with the "far-end" scan pulse signal away from the signal application end; and as the size of the display panel increases, its gate load also increases, and the signal difference between the "near-end" and "far-end" will further expand, thereby causing the in-plane feedthrough voltage of the display panel to be unbalanced, and finally causing the display picture to flicker. In the prior art, a dedicated integrated chip is usually used to process the signal in the driving circuit, to realize the corner cutting modulation of the gate voltage signal to generate a corner cutting voltage signal, and then provide the signal to the gate driver to adjust the waveform of the gate pulse signal, so as to improve the above problems. However, although this scheme is easy to implement, the introduction of the dedicated integrated chip will significantly increase the hardware cost of the display device and increase the width of the frame of the display panel.

[0004] Therefore, it is urgent to design a gate driving circuit to cut the corners of the gate voltage to improve the uniformity of the in-plane feedthrough voltage of the display panel and improve the display quality. SUMMARY

[0005] The purpose of this invention is to provide a gate driving circuit that can bevel the gate voltage, improve the uniformity of the in-plane feedthrough voltage of the display panel, and enhance the display quality.

[0006] According to one aspect of the present invention, a gate driving circuit is provided, comprising multiple cascaded gate driving units, each of the gate driving units comprising:

[0007] The input module generates the first node voltage based on the front-stage gate drive signal, the front-stage gate transfer signal, the rear-stage gate drive signal, and the third clock signal.

[0008] The output module generates the gate drive signal and the gate transfer signal of this stage based on the first node voltage and the second clock signal.

[0009] The corner-cutting module adjusts the gate drive signal of this stage according to the first node voltage and the second clock sub-signal;

[0010] Wherein, the second clock sub-signal is a derived signal of the second clock signal, the rising edge of the second clock sub-signal is in phase with the rising edge of the second clock signal, and the falling edge of the second clock sub-signal is earlier than the falling edge of the second clock signal.

[0011] Optionally, each stage of the gate drive unit further includes:

[0012] The pull-down module generates a first pull-down signal and a second pull-down signal based on the first node voltage and the first reference signal;

[0013] The stabilization module generates a first stabilization signal and a second stabilization signal based on the first pull-down signal, the second pull-down signal, the first timing signal, the second timing signal, the first reference signal, and the second reference signal, so as to stabilize the gate drive signal and the gate transmission signal of the current stage, respectively.

[0014] Optionally, the input module includes:

[0015] The first transistor has a control terminal that receives the signal transmitted by the front gate, a first path terminal that receives the front gate drive signal, and a second path terminal that outputs the first node voltage.

[0016] The third transistor has a control terminal that receives the subsequent gate drive signal, a first path terminal that receives the third clock signal, and a second path terminal that is connected to the second path terminal of the first transistor.

[0017] The output module includes:

[0018] The second transistor has a control terminal connected to the first node, a first path terminal receiving the second clock signal, and a second path terminal outputting the gate drive signal of this stage.

[0019] The fourteenth transistor has its control terminal connected to the first node, its first path terminal receiving the second clock signal, and its second path terminal outputting the gate transmission signal of this stage.

[0020] A first capacitor is connected between the first node and the second path terminal of the second transistor. The first capacitor is composed solely of the parasitic capacitance of the second transistor, or is composed of the parasitic capacitance and an additional capacitor connected in parallel.

[0021] Optionally, the beveling module includes: a seventeenth transistor, whose control terminal is connected to the first node, a first path terminal receives the second clock sub-signal, and a second path terminal is connected to the gate drive signal of this stage.

[0022] Optionally, the dropdown module includes:

[0023] The twelfth transistor has its control terminal connected to the first node, its first path terminal receiving the first reference signal, and its second path terminal outputting the first pull-down signal.

[0024] The thirteenth transistor has its control terminal connected to the first node, its first path terminal receiving the first reference signal, and its second path terminal outputting the second pull-down signal.

[0025] Optionally, the stabilization module includes:

[0026] The first stabilization submodule is used to generate the first stable signal and the second stable signal according to the first pull-down signal, the first reference signal and the second reference signal when the first timing signal is valid.

[0027] The second stabilization submodule is used to generate the first stable signal and the second stable signal according to the second pull-down signal, the first reference signal and the second reference signal when the second timing signal is valid.

[0028] The first timing signal is out of phase with the second timing signal.

[0029] Optionally, the first stabilizing submodule includes:

[0030] The eighth transistor has its control terminal connected to the first path terminal and receiving the first timing signal, and its second path terminal outputting the first pull-down signal.

[0031] The tenth transistor has a control terminal that receives the first timing signal, a first path terminal that receives the first reference signal, and a second path terminal that outputs the second pull-down signal.

[0032] The fourth transistor has a control terminal that receives the first pull-down signal, a first path terminal that receives the first reference signal, and a second path terminal that is connected to the first node.

[0033] The sixth transistor has a control terminal that receives the first pull-down signal, a first path terminal that outputs the first stable signal, and a second path terminal that receives the second reference signal.

[0034] The fifteenth transistor has a control terminal that receives the first pull-down signal, a first path terminal that outputs the second stable signal, and a second path terminal that receives the second reference signal.

[0035] The second stabilizing submodule includes:

[0036] The ninth transistor has its control terminal connected to the first path terminal and receives the second timing signal, while the second path terminal outputs the second pull-down signal.

[0037] The eleventh transistor has a control terminal that receives the second timing signal, a first path terminal that receives the first reference signal, and a second path terminal that outputs the first pull-down signal.

[0038] The fifth transistor has a control terminal that receives the second pull-down signal, a first path terminal that receives the first reference signal, and a second path terminal that is connected to the first node.

[0039] The seventh transistor has a control terminal that receives the second pull-down signal, a first path terminal that outputs the first stable signal, and a second path terminal that receives the second reference signal.

[0040] The sixteenth transistor has a control terminal that receives the second pull-down signal, a first path terminal that outputs the second stable signal, and a second path terminal that receives the second reference signal.

[0041] Optionally, the time by which the falling edge of the second clock sub-signal precedes the falling edge of the second clock signal is equal to the chamfering time of the gate drive signal at this stage.

[0042] Optionally, the chamfer depth of the gate drive signal at this stage is adjusted by the channel dimensions of the second transistor and the seventeenth transistor, and the difference between the low-level voltage of the second clock sub-signal and the low-level voltage of the second clock signal.

[0043] According to another aspect of the present invention, a display device is provided, comprising: a display panel having pixel units arranged in an array; a source driving circuit for providing data voltage to the pixel units; the aforementioned gate driving circuit for providing gate driving signals to the pixel units; and a timing control circuit for providing clock signals and control signals to the gate driving circuit and the source driving circuit; wherein the gate driving circuit and the display panel are integrated on the same substrate.

[0044] The gate driving circuit and display device provided by the present invention, by adding a chamfering module to the gate driving circuit and using a clock sub-signal to chamfer the gate driving signal through the chamfering module, generates a gate driving (scanning) signal with chamfering characteristics. This gate driving (scanning) signal with chamfering characteristics can effectively suppress the fluctuation amplitude of the near-end and far-end voltage feedthrough voltage on the display panel, improve the problem of uneven display screen, and enhance display quality.

[0045] Furthermore, the gate driving circuit can be integrated into the substrate of the display panel, eliminating the need for separate chips and wiring required by traditional solutions. This significantly reduces costs and helps to reduce the size of the display panel bezel, thereby increasing the screen-to-body ratio of the display device, simplifying connections and wiring, and improving product yield and reliability. Attached Figure Description

[0046] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0047] Figure 1 A schematic diagram of the structure of a display device according to an embodiment of the present invention is shown;

[0048] Figure 2 A schematic block diagram of the nth gate driving unit in a display device according to an embodiment of the present invention is shown.

[0049] Figure 3 This diagram illustrates the structure of the nth gate driving unit in a display device according to an embodiment of the present invention.

[0050] Figure 4 This diagram illustrates the timing of the first three gate drive signals in a display device according to an embodiment of the present invention.

[0051] Figure 5 This diagram illustrates the beveled waveform of the gate driving unit in a display device according to an embodiment of the present invention. Detailed Implementation

[0052] The present invention will now be described in more detail with reference to the accompanying drawings. To facilitate understanding of this application, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application may be implemented in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0053] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0054] In the description of this application, the words "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. "And / or" in this document describes an association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. "Connection" describes a connection relationship between related objects. For example, A and B are connected, which can indicate a direct connection between A and B, or an indirect connection between A and B through other devices / units / modules. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0055] Furthermore, the same reference numerals in the figures denote the same or similar structures, thus repeated descriptions of them will be omitted. That is, the various parts in this specification are described using a combination of parallel and progressive methods, with each part focusing on its differences from the others. Similar or identical parts can be referred to interchangeably. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings in this application are for illustrating relative positional relationships only and do not represent actual scale.

[0056] This application describes many specific details of the invention, such as the specific structure, dimensions, connection relationships, and techniques of the modules, in order to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0057] This invention can be presented in various forms, some of which will be described below.

[0058] Figure 1 A schematic diagram of the structure of a display device according to an embodiment of the present invention is shown; as follows: Figure 1 As shown, the display device includes a display panel 100, a timing control circuit 200, a gate driving circuit 300, and a source driving circuit 400. The gate driving circuit 300 can, for example, be integrated with the display panel 100 on the same substrate to form an integrated gate driving structure. The timing control circuit 200 provides multiple clock signals and control signals such as a start signal (StartVertical, STV) to the source driving circuit 400 and the gate driving circuit 300. Specifically, the start signal can be an enable signal for one frame. The gate driving circuit 300 provides gate driving signals to the display panel 100, and the source driving circuit 400 provides source driving signals to the display panel 100.

[0059] Furthermore, the gate driving circuit 300 includes, for example, multiple gate driving units GIA1 to GIAN. Each gate driving unit has a front-stage driving terminal receiving the previous stage gate driving signal G(n-2); a front-stage transmission terminal receiving the previous stage gate transmission signal Z(n-2); a rear-stage driving terminal receiving the subsequent stage gate driving signal G(n+2); a clock terminal receiving the clock signal corresponding to each stage gate driving unit; and a timing terminal and a reference terminal receiving timing signals and reference signals. The current stage driving terminal outputs the current stage gate driving signal Gn and the current stage gate transmission signal Zn according to the signals from the above terminals. In the following description of the embodiments of the present invention, unless otherwise specified, n is a natural number greater than or equal to 3. When n is less than 3, that is, the signals of the front-stage driving terminal and the front-stage transmission terminal of the first and second stage gate driving units are provided by the start signals STV1 and STV2 respectively. Starting from the third stage gate driving unit, the gate driving signal and the previous stage gate transmission signal can be obtained through cascading design.

[0060] Figure 2 This is a schematic block diagram of the nth gate driving unit in a display device according to an embodiment of the present invention. Figure 3 This diagram illustrates the structure of the nth gate driving unit in a display device according to an embodiment of the present invention.

[0061] It should be noted that the transistors mentioned in this embodiment are all N-type transistors, and the first and second terminals of each transistor can be interchanged (i.e., the drain and source terminals can be interchanged). Of course, the implementation of the present invention is not limited to this.

[0062] like Figure 2 As shown, the gate driving unit GIAn includes an input module 310, a pull-down module 320, a stabilization module 330, a chamfering module 340, and an output module 350. The connection and signal relationships of each module in the nth-stage gate driving unit GIAn are described in detail below.

[0063] The input module 310 is used to receive the front-stage gate drive signal G(n-2) from the front-stage drive terminal of the gate drive unit, the front-stage gate transmission signal Zn-2 from the front-stage transmission terminal, the rear-stage gate drive signal G(n+2) from the rear-stage drive terminal, and the third clock signal CLK3 corresponding to the gate drive unit of this stage from the clock terminal, thereby providing the voltage of the first node Q. The output terminal of the input module 310 is connected to the first node Q.

[0064] The chamfering module 340 is used to generate a chamfering signal based on the second clock sub-signal CLK2-2 and the voltage signal of the first node Q received by the clock terminal of the gate driving unit of this stage. The output terminal of the chamfering module 340 is connected to the gate driving signal Gn of this stage, and the voltage and waveform of the gate driving signal Gn of this stage are adjusted according to the chamfering signal.

[0065] One input terminal of the output module 350 is connected to the first node Q. Based on the voltage of the first node Q and the second clock signal CLK2 received at the clock terminal corresponding to the gate drive unit of this stage, the module generates the gate drive signal Gn at the drive terminal and the gate transfer signal Zn at the transfer terminal.

[0066] One input terminal of the pull-down module 320 is connected to the first node Q, and a first pull-down signal c1 and a second pull-down signal c2 are generated based on the voltage of the first node Q and the first reference signal VSQ.

[0067] The two input terminals of the stabilization module 330 receive a first pull-down signal c1 and a second pull-down signal c2, respectively. At the same time, based on the first timing signal V1 received by the first timing terminal of the gate driving unit, the second timing signal V2 received by the second timing terminal of the gate driving unit, the first reference signal VSQ received by the first reference terminal of the gate driving unit, and the second reference signal VGL received by the second reference terminal of the gate driving unit, a first stable signal s1 and a second stable signal s2 are generated. The first stable signal s1 is used to stabilize the gate driving signal Gn output by the driving terminal of the current stage, and the second stable signal s2 is used to stabilize the gate transmission signal Zn output by the transmission terminal of the current stage.

[0068] like Figure 3 As shown, the input module 310 includes transistors M1 and M3. The gate of transistor M1 receives the gate drive signal Z(n-2) from the previous stage, and the source of transistor M1 receives the gate drive signal G(n-2) from the previous stage. The gate of transistor M3 receives the gate drive signal G(n+2) from the next stage, and the source of transistor M3 receives the third clock signal CLK3. The drains of transistors M1 and M3 are connected and provide the voltage of the first node Q.

[0069] The chamfering module 340 includes a transistor M17. The gate of transistor M17 receives the voltage of the first node Q, and the source of transistor M17 receives a second clock sub-signal CKL2-2. The second clock sub-signal is a derivative signal of the second clock signal CKL2. The rising edge of the second clock sub-signal CKL2-2 is in phase with the rising edge of the second clock signal CKL2, and the falling edge of the second clock sub-signal CKL2-2 is earlier than the falling edge of the second clock signal CKL2. The time difference between the two is the chamfering time of the gate drive signal Gn. The drain of transistor M17 is connected to the gate drive signal Gn of this stage to adjust the voltage and waveform of the gate drive signal Gn of this stage.

[0070] The output module 350 includes transistor M2, transistor M14 and a first capacitor C1. The gates of transistors M2 and M14 and the first terminal of the first capacitor C1 are connected to the first node Q. The drains of transistors M2 and M14 receive the second clock signal CLK2. The source of transistor M2 is connected to the second terminal of the first capacitor C1 and outputs the gate drive signal Gn of this stage. The source of transistor M14 outputs the gate transmission signal Zn of this stage.

[0071] The pull-down module 320 includes transistors M12 and M13. The gates of transistors M12 and M13 are respectively connected to the first node Q to receive the voltage of the first node Q. The drains of transistors M12 and M13 receive the first reference signal VSQ. The source of transistor M12 is connected to the second node QB1 to generate the voltage of the second node QB1 and output the first pull-down signal c1. The source of transistor M13 is connected to the third node QB2 to generate the voltage of the third node QB2 and output the second pull-down signal c2.

[0072] like Figure 3 As shown, the stabilization module 330 includes a first stabilization module and a second stabilization module.

[0073] The first stabilization module includes transistors M8, M10, M4, M6, and M15. The gate and drain of transistor M8 are connected to receive a first timing signal V1. The source of transistor M8 is connected to the second node QB1 to adjust the voltage of the second node QB1. The gate of transistor M10 receives the first timing signal V1. The drain of transistor M10 receives a first reference signal VSQ. The source of transistor M10 is connected to the third node QB2 to adjust the voltage of the third node QB2. The gates of transistors M4, M6, and M15 are connected to the second node QB1 to receive the voltage of the second node QB1. The source of transistor M4 receives the first reference signal VSQ. The drain of transistor M4 is connected to the first node Q to adjust the voltage of the first node Q. The sources of transistors M6 and M15 receive a second reference signal VGL. The drain of transistor M6 generates a first stabilization signal s1 to stabilize the gate drive signal Gn of this stage. The drain of transistor M15 generates a second stabilization signal s2 to stabilize the gate transmission signal Zn of this stage.

[0074] The second stabilization module includes transistors M9, M11, M5, M7, and M16. The gate and source of transistor M9 are connected to receive the second timing signal V2. The drain of transistor M9 is connected to the third node QB2 to adjust the voltage of the third node QB2. The gate of transistor M11 receives the second timing signal V2. The source of transistor M11 receives the first reference signal VSQ. The drain of transistor M11 is connected to the second node QB1 to adjust the voltage of the second node QB1. The gates of transistors M5, M7, and M16 are connected to the third node QB2 to receive the voltage of the third node QB2. The drain of transistor M5 receives the first reference signal VSQ. The source of transistor M5 is connected to the first node Q to adjust the voltage of the first node Q. The drains of transistors M7 and M16 receive the second reference signal VGL. The source of transistor M7 generates a first stabilization signal s1 to stabilize the gate drive signal Gn of this stage. The source of transistor M16 generates a second stabilization signal s2 to stabilize the gate transmission signal Zn of this stage.

[0075] In embodiments of the present invention, both the first timing signal V1 and the second timing signal V2 are low-frequency signals. The periods and duty cycles of the first timing signal V1 and the second timing signal V2 are equal. When the first timing signal V1 is high, the second timing signal V2 is low, and when the first timing signal V1 is low, the second timing signal V2 is high, thereby enabling the first stabilizing module and the second stabilizing module to work alternately. Specifically, for example, the case where the first timing signal V1 is high and the second timing signal V2 is low, thereby enabling the second node QB1 to be high, is as follows.

[0076] The second clock signal CLK2 and the third clock signal CLK3 have the same period and the duty cycle of both clock signals CLK2 and CLK3 is 50%. However, the second clock signal CLK2 and the third clock signal CLK3 are one-third of a cycle apart. Therefore, when the second clock signal CLK2 changes from high level to low level, that is, when it is at the falling edge, the third clock signal CLK3 is high level.

[0077] Furthermore, the operation of each gate drive unit is divided into four stages: pre-charge stage, pull-up stage, pull-down stage, and stabilization stage.

[0078] Pre-charge stage: The gate drive signal Z(n-2) output by the gate drive unit changes from low to high, and transistor M1 turns on. When the gate drive signal G(n-2) changes from low to high, the first node Q is pre-charged through the turned-on transistor M1. Furthermore, the transition of the gate drive signal G(n-2) output by the gate drive unit (from low to high) couples the parasitic capacitance between the source and gate of transistor M1, further pulling up the voltage at the control terminal of transistor M1, allowing transistor M1 to conduct more fully. Moreover, since the first node Q is pre-charged, transistors M2, M14, M12, and M13 are all turned on. The voltages at the second node QB1 and the third node QB2 are pulled down to the first reference low voltage VSQ through the turned-on transistors M12 and M13, respectively. Therefore, transistors M4, M6, M15, M5, M7, and M16 are all turned off.

[0079] In this invention, the gate of transistor M1 receives the gate transfer signal Z(n-2) from the previous stage, and the source of transistor M1 receives the gate drive signal G(n-2) from the previous stage. Since the load of the gate transfer signal Z(n-2) from the previous stage is smaller than that of the gate drive signal G(n-2), it jumps slightly earlier than the gate drive signal G(n-2), which allows the parasitic capacitance between the source and gate of transistor M1 to couple, and the voltage of the first node Q is further increased, thereby making the pre-charging effect of the first node Q better.

[0080] Pull-up phase: When the level of the second clock signal CLK2 changes from low to high, since the first node Q has been precharged during the precharge phase, transistors M2, M14, and M17 are all turned on. Due to the turn-on of transistor M2 and the bootstrap effect of the first capacitor C1, the voltage at the first node Q is further pulled up, making transistor M2 more fully conductive. As a result, the gate drive signal Gn output by the gate drive unit of this stage is pulled up by the second clock signal CLK2 through the turned-on transistor M2.

[0081] Similarly, the further increase in voltage at the first node Q makes transistor M14 more fully conductive, thereby allowing the current stage transmission signal Zn output by the gate drive unit to be pulled high by the second clock signal CLK2 through the conductive transistor M14.

[0082] Furthermore, the rising edge of the second clock sub-signal CLK2-2 is in phase with that of the second clock signal CLK2, but the falling edge of the second clock sub-signal CLK2-2 falls earlier than that of the second clock signal CLK2. When the gate drive signal Gn of this stage is pulled high by the second clock signal CLK2, the second clock sub-signal CLK2-2 falls first before the second clock signal CLK2 falls. The gate drive signal Gn of this stage is partially pulled down through the conducting transistor M17, and the corner is chopped to form a gate drive signal Gn with a chopped waveform at the end.

[0083] In one embodiment of the present invention, the parasitic capacitance between the source and gate of transistor M2 can be directly used as the first capacitor C1. Alternatively, to improve the pull-up effect, an independent storage capacitor can be provided between the gate and source of transistor M2. The independent storage capacitor and the parasitic capacitance of transistor M2 are connected in parallel and together serve as the first capacitor C1. That is, the first capacitor C1 is equal to the sum of the parasitic capacitance of transistor M2 and the independent storage capacitor.

[0084] Pull-down phase: When the level of the second clock signal CLK2 changes from high to low, since transistors M2, M14, and M17 are all turned on during the pull-up phase, and the third clock signal CLK3 and the subsequent gate drive signal G(n+2) are at a high level at this time, the current stage gate drive signal Gn and the current stage gate transfer signal Zn output by the current stage gate drive unit are pulled low by the second clock signal CLK2 through the turned-on transistors M2 and M14, respectively, thereby rapidly pulling down the current stage gate drive signal Gn and the current stage gate transfer signal Zn output by the current stage gate drive unit. Furthermore, since the subsequent stage gate drive signal G(n+2) changes from low to high, the third transistor M3 is turned on. Therefore, when the third clock signal CLK3 changes from high to low, the first node Q is pulled low by the third clock signal CLK3 through the turned-on third transistor M3.

[0085] In this invention, the control terminal of the third transistor M3 receives the rear gate drive signal G(n+2) instead of the rear gate transmission signal Z(n+2) which has relatively large coupling noise due to the small load. This allows the transistor M3 to work more stably, thereby making the gate drive circuit more stable.

[0086] Stabilization Phase: During the pull-down phase, the gate drive signal Gn and gate transfer signal Zn output by the current gate drive unit are pulled low by the second clock signal CLK2 through the conducting transistors M2 and M14, respectively, and the voltage of the first node Q is pulled low through the conducting transistor M3. Therefore, in the subsequent time, i.e., the stabilization phase, it is necessary to keep the first node Q, the gate transfer signal Zn of the current gate drive unit, and the gate drive signal Gn output by the current gate drive unit at a low level to obtain the ideal waveform.

[0087] However, since the second clock signal CLK2 is a clock signal, it will continue to generate pulses in the subsequent time (i.e. after the stabilization phase), which will affect the gate transfer signal Zn output by the gate driving unit of this stage and the gate driving signal Gn output by the gate driving unit of this stage. The second clock sub-signal CLK2-2 will also affect the gate driving signal Gn of this stage. In order to eliminate these effects, the embodiments of the present invention utilize the first stabilization module and the second stabilization module for improvement.

[0088] Specifically, in the subsequent time, when the second clock signal CLK2 changes from low to high, due to the parasitic capacitance between transistor M2 and the first node Q and the second clock signal CLK2, the first node Q will be coupled by the parasitic capacitance and generate noise. However, when the first timing signal Vl is high, transistors M8 and M10 are turned on, thereby pulling the second node QB1 high through the turned-on transistor M8 and pulling the third node QB2 low through the turned-on transistor M10. This causes transistors M4, M6, and M15 to be turned on, while transistors M15, M7, and M16 are turned off. As a result, the first node Q is pulled low through the turned-on transistor M4, the gate drive signal Gn output by the gate drive unit is pulled low through the turned-on transistor M6, and the gate transfer signal Zn output by the gate drive unit is pulled low through the turned-on transistor M15.

[0089] In the embodiments of the present invention, during the stable phase, the phases of the first timing signal V1 and the second timing signal V2 are always opposite, so that the voltages of the second node QB1 and the third node QB2 can alternately be at a high level, thereby causing transistors M4, M6, and M15 to work alternately with transistors M5, M7, and M16. This ensures the stability of the gate drive circuit while reducing the impact of threshold drift and ensuring the reliability of the gate drive circuit.

[0090] Therefore, although the first node Q, the gate transmission signal Zn of the current gate driving unit, and the current gate driving signal Gn output by the current gate driving unit will be pulled high due to the high level of the second clock signal CLK2, the first node Q, the gate transmission signal Zn of the current gate driving unit, and the current gate driving signal Gn output by the current gate driving unit can be kept at a low level through the action of the transistors in the pull-down module 320 and the stabilization module 330.

[0091] Figure 4 This diagram illustrates the timing of the first three gate drive signals in a display device according to an embodiment of the present invention. The clock signal CLK of the gate drive circuit 300 includes, for example, eight clock signals: a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, a fourth clock signal CLK4, a first clock sub-signal CLK1-1, a second clock sub-signal CLK2-2, a third clock sub-signal CLK3-3, and a fourth clock sub-signal 4-4. Of course, it can also have 12, 16, or other numbers of clock signals.

[0092] Wherein, CLKx-x is a derived signal of CLKx. Taking the first clock signal CLK1 and the first clock sub-signal CLK1-1 as an example, the high level duration of the first clock signal CLK1 in a single cycle is 2T, the low level duration is 2T, the rising edge of the first clock sub-signal CLK1-1 is in phase with the rising edge of the first clock signal CLK1, and the falling edge of the first clock sub-signal CLK1-1 is Tx earlier than the falling edge of the first clock signal CLK1. Tx is the chamfering time of the gate drive signal.

[0093] See Figure 5 If CLK1 and CLK1-1 have the same high level (VGH) and the same low level (VHL), taking the gate drive signal G1 as an example, the magnitude of the bevel voltage difference Vx of the gate drive signal G1 is determined by... Figure 3 The size (channel size) of transistors M2 and M17 in the circuit shown is determined. If the channel size of transistors M2 and M17 is the same, then the beveled voltage difference Vx = (VGH + VGL) / 2; the voltage of the gate drive signal G1 after beveling is VGH-x = VGH - Vx.

[0094] Of course, if CLK1 and CLK1-1 have the same high level and are both VGH, their low levels are different. The low level of CLK1 is VGL, and the low level of CLK1-1 is VGL1, and VGL1 > VGL. If transistors M2 and M17 have been designed in advance, the actual chamfer voltage difference Vx is determined by the magnitudes of VGL1 and VGL, and the chamfer voltage difference Vx can be adjusted by adjusting the value of VGL1.

[0095] The gate driving circuit and display device provided by the present invention, by adding a chamfering module to the gate driving circuit and using a clock sub-signal to chamfer the gate driving signal through the chamfering module, generates a gate driving (scanning) signal with chamfering characteristics. This gate driving (scanning) signal with chamfering characteristics can effectively suppress the fluctuation amplitude of the near-end and far-end voltage feedthrough voltage on the display panel, improve the problem of uneven display screen, and enhance display quality.

[0096] Furthermore, the gate driving circuit can be integrated into the substrate of the display panel, eliminating the need for separate chips and wiring required by traditional solutions. This significantly reduces costs and helps to reduce the size of the display panel bezel, thereby increasing the screen-to-body ratio of the display device, simplifying connections and wiring, and improving product yield and reliability.

[0097] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications.

Claims

1. A gate drive circuit characterized by comprising: The gate drive unit comprises a plurality of cascaded stages, each stage of the gate drive unit comprising: an input module configured to generate a first node voltage according to a previous-stage gate drive signal, a previous-stage gate transfer signal, a next-stage gate drive signal, and a third clock signal; an output module configured to generate a current-stage gate drive signal and a current-stage gate transfer signal according to the first node voltage and a second clock signal; a corner cutting module configured to adjust the current-stage gate drive signal according to the first node voltage and a second clock sub-signal; wherein the second clock sub-signal is a derivative signal of the second clock signal, the rising edge of the second clock sub-signal is in the same phase as the rising edge of the second clock signal, and the falling edge of the second clock sub-signal is earlier than the falling edge of the second clock signal.

2. The gate drive circuit according to claim 1, characterized by Each stage of the gate drive unit further comprises: a pull-down module configured to generate a first pull-down signal and a second pull-down signal according to the first node voltage and a first reference signal; a stabilizing module configured to generate a first stabilizing signal and a second stabilizing signal according to the first pull-down signal, the second pull-down signal, a first timing signal, a second timing signal, a first reference signal, and a second reference signal, so as to stabilize the current-stage gate drive signal and the current-stage gate transfer signal, respectively.

3. The gate drive circuit according to claim 2, characterized by The input module comprises: a first transistor having a control terminal configured to receive the previous-stage gate transfer signal, a first passage terminal configured to receive the previous-stage gate drive signal, and a second passage terminal configured to output the first node voltage; a third transistor having a control terminal configured to receive the next-stage gate drive signal, a first passage terminal configured to receive the third clock signal, and a second passage terminal connected to the second passage terminal of the first transistor. The output module comprises: a second transistor having a control terminal connected to the first node, a first passage terminal configured to receive the second clock signal, and a second passage terminal configured to output the current-stage gate drive signal; a fourteenth transistor having a control terminal connected to the first node, a first passage terminal configured to receive the second clock signal, and a second passage terminal configured to output the current-stage gate transfer signal; a first capacitor connected between the first node and the second passage terminal of the second transistor, the first capacitor being formed by a parasitic capacitor of the second transistor alone or by the parasitic capacitor and an additional capacitor in parallel.

4. The gate drive circuit according to claim 3, characterized by The corner cutting module comprises:

5. The gate drive circuit according to claim 4, characterized in that a seventeenth transistor having a control terminal connected to the first node, a first passage terminal configured to receive the second clock sub-signal, and a second passage terminal connected to the current-stage gate drive signal. The pull-down module comprises: a twelfth transistor having a control terminal connected to the first node, a first passage terminal configured to receive the first reference signal, and a second passage terminal configured to output the first pull-down signal; 6. The gate drive circuit according to claim 5, characterized by a thirteenth transistor having a control terminal connected to the first node, a first passage terminal configured to receive the first reference signal, and a second passage terminal configured to output the second pull-down signal. The stabilizing module comprises: a first stabilizing sub-module configured to generate the first stabilizing signal and the second stabilizing signal according to the first pull-down signal, the first reference signal, and the second reference signal when the first timing signal is active. a second stabilizing sub-module, configured to generate the first stabilizing signal and the second stabilizing signal according to the second pull-down signal, the first reference signal and the second reference signal when the second timing signal is active; wherein the first timing signal and the second timing signal are opposite in phase.

7. The gate drive circuit according to claim 6, characterized in that The first stabilizing sub-module comprises: an eighth transistor, having a control terminal connected to the first path terminal and receiving the first timing signal, and a second path terminal outputting the first pull-down signal; a tenth transistor, having a control terminal receiving the first timing signal, a first path terminal receiving the first reference signal, and a second path terminal outputting the second pull-down signal; a fourth transistor, having a control terminal receiving the first pull-down signal, a first path terminal receiving the first reference signal, and a second path terminal connected to the first node; a sixth transistor, having a control terminal receiving the first pull-down signal, a first path terminal outputting the first stabilizing signal, and a second path terminal receiving the second reference signal; a fifteenth transistor, having a control terminal receiving the first pull-down signal, a first path terminal outputting the second stabilizing signal, and a second path terminal receiving the second reference signal; The second stabilizing sub-module comprises: a ninth transistor, having a control terminal connected to the first path terminal and receiving the second timing signal, and a second path terminal outputting the second pull-down signal; an eleventh transistor, having a control terminal receiving the second timing signal, a first path terminal receiving the first reference signal, and a second path terminal outputting the first pull-down signal; a fifth transistor, having a control terminal receiving the second pull-down signal, a first path terminal receiving the first reference signal, and a second path terminal connected to the first node; a seventh transistor, having a control terminal receiving the second pull-down signal, a first path terminal outputting the first stabilizing signal, and a second path terminal receiving the second reference signal; a sixteenth transistor, having a control terminal receiving the second pull-down signal, a first path terminal outputting the second stabilizing signal, and a second path terminal receiving the second reference signal.

8. The gate drive circuit according to claim 1, characterized by The time difference between the falling edge of the second clock sub-signal and the falling edge of the second clock signal is the corner cutting time of the current stage gate driving signal.

9. The gate drive circuit according to claim 7, characterized by The corner cutting depth of the current stage gate driving signal is adjusted by the channel size of the second transistor and the seventeenth transistor, and the difference between the low voltage of the second clock sub-signal and the low voltage of the second clock signal.

10. A display device, characterized by comprising: comprises: a display panel having pixel units arranged in an array; a source driving circuit configured to provide data voltages to the pixel units; the gate driving circuit according to any one of claims 1-12, configured to provide gate driving signals to the pixel units; a timing control circuit configured to provide clock signals and control signals to the gate driving circuit and the source driving circuit; wherein the gate driving circuit and the display panel are integrated on the same substrate.

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