A source driver circuit and a display device

Abstract

The present application provides a source driver circuit and a display device. The source driver circuit includes a first power signal terminal and a second power signal terminal that are independently arranged, and a switching unit and a first valve tube that are connected in series. The input end of the source driver chip is connected to the pipeline between the switching unit and the first valve tube. At the same time, the first output end of the first power signal terminal is connected to the input end of the switching unit, and the first output end of the second power signal terminal is connected to the control end of the switching unit. When voltages are output from both first output ends and the voltage difference is less than a certain value, the switching unit is turned on at this time so that the voltage can enter the source driver chip. In addition, the second output end of the second power signal terminal is connected to the input end of the first valve tube. It can be understood that when the second power signal terminal is fully boosted, the first valve tube is turned on, and at this time, the voltage output by the second power signal terminal can enter the source driver chip to achieve the purpose of supplying voltage to the source driver chip.

Description

Technical Field

[0001] The present application relates to the field of display panels, and particularly to a source driver circuit and a display device. Background Art

[0002] A display panel usually realizes the display of a picture by means of progressive scanning. During the display time of one frame, a control chip needs to progressively scan all pixel units within the display area.

[0003] Nowadays, due to the increase in panel resolution and refresh rate and the increase in the liquid crystal saturation voltage, the voltages of AVDD (analog circuit power supply) and HAVDD (half-value analog circuit power supply) also need to be increased accordingly. This causes the in-plane voltage load of the panel to be too heavy, resulting in a slow boost of the voltage of HAVDD (half-value analog circuit power supply) supplied to the Source Driver IC (source driver chip), and thus causing too large a voltage difference between AVDD (analog circuit power supply) and HAVDD (half-value analog circuit power supply). It is clearly specified in the chip specification that the voltage difference between AVDD (source driver chip) and HAVDD (half-value analog circuit power supply) must always be lower than 6V, otherwise it will damage the internal circuit of the Source Driver IC (source driver chip). Summary of the Invention

[0004] Embodiments of the present application provide a source driver circuit and a display device to solve the problem that the existing source driver chip has a slow boost of the voltage of HAVDD (half-value analog circuit power supply) due to the overheavy in-plane voltage load of the panel, and further cause damage to the internal circuit of the source driver chip.

[0005] In a first aspect, embodiments of the present application provide a native driver circuit for connecting to a source driver chip, including:

[0006] A first power signal terminal and a second power signal terminal that are independently arranged, and a switch unit and a first valve tube that are arranged in series; wherein,

[0007] A first input end of the source driver chip is connected to the pipeline between the switch unit and the first valve tube, a first output end of the first power signal terminal is connected to the input end of the switch unit, a first output end of the second power signal terminal is connected to the control end of the switch unit, and a second output end of the second power signal terminal is connected to the input end of the first valve tube.

[0008] Optionally, in an embodiment, a second output end of the first power signal terminal is connected to a second input end of the source driver chip.

[0009] Optionally, in one embodiment, the source driver circuit further includes a second valve tube, which is disposed between the switching unit and the first valve tube, is disposed opposite to the first valve tube, and the first input terminal of the source driver chip is connected to the pipeline between the first valve tube and the second valve tube.

[0010] Optionally, in one embodiment, the second output terminal of the second power signal terminal is connected to the input terminal of the first valve tube through a first pipeline, where the first pipeline includes a first branch pipeline, a second branch pipeline, and a third branch pipeline that are arranged in parallel. The first branch pipeline is used to connect the output terminal of the switching unit, the second branch pipeline is used to connect the first input terminal of the source driver chip, and the third branch pipeline is used to connect the input terminal of the first valve tube.

[0011] Optionally, in one embodiment, the source driver circuit further includes a first resistor, a first filter circuit, and a second resistor. The first resistor is disposed in the first branch pipeline, the first filter circuit is disposed in the second branch pipeline, and the second resistor is disposed in the third branch pipeline, where the resistance value of the first resistor is greater than the resistance value of the second resistor.

[0012] Optionally, in one embodiment, the first output terminal of the first power signal terminal is connected to the input terminal of the switching unit through a second pipeline, where the second pipeline includes a fourth branch pipeline and a fifth branch pipeline that are arranged in parallel. The source driver circuit further includes a third resistor and a second filter circuit. The third resistor is disposed in the fourth branch pipeline, and the second filter circuit is disposed in the fifth branch pipeline.

[0013] Optionally, in one embodiment, the source driver circuit further includes a fourth resistor, and the fourth resistor is disposed between the first output terminal of the first power signal terminal and the fourth branch pipeline, where the resistance ratio of the fourth resistor to the third resistor is 4:5.

[0014] Optionally, in one embodiment, the source driver circuit further includes a fifth resistor, and the fifth resistor is disposed between the first output terminal of the second power signal terminal and the control terminal of the switching unit.

[0015] Optionally, in one embodiment, the switching unit is a PMOS transistor, and the first valve tube is a Schottky diode.

[0016] In a second aspect, an embodiment of the present application further provides a display device, including: a source driver chip, where the source driver chip includes the source driver circuit as described in any one of the above.

[0017] The source driver circuit provided by the embodiment of the present application can be used to connect to a source driver chip to achieve the display effect of a display panel. The source driver circuit includes a first power signal terminal and a second power signal terminal that are independently arranged, and a switching unit and a first valve tube that are connected in series. The first input terminal of the source driver chip is connected to the pipeline between the switching unit and the first valve tube. Among them, the voltage output by the first power signal terminal can be AVDD generated by a PMIC

[0018] (Power Management IC, power management chip), and the voltage output by the second power signal terminal can be HAVDD generated by an OP (operational amplifier circuit) (i.e., the half-value analog circuit power supply generated by the steady state of the original circuit).

[0019] At the same time, the first output terminal of the first power signal terminal is connected to the input terminal of the switching unit, and the first output terminal of the second power signal terminal is connected to the control terminal of the switching unit. When the first output terminals of both the first power signal terminal and the second power signal terminal output voltages and the voltage difference between the two is less than a certain value, the switching unit is turned on at this time so that the voltage can enter the source driver chip. It can be understood that since the switching unit will play a voltage dividing role, the AVDD (analog circuit power supply) after the voltage drop of the switching unit can replace the slowly boosting HAVDD (half-value analog circuit power supply) at this time, so that when the HAVDD (half-value analog circuit power supply) has not been fully boosted, the AVDD (analog circuit power supply) can realize the replacement of the HAVDD (half-value analog circuit power supply), thereby avoiding the problem that the voltage difference between the AVDD (analog circuit power supply) and the HAVDD (half-value analog circuit power supply) is greater than 6V, causing damage to the internal circuit of the source driver chip.

[0020] In addition, the second output terminal of the second power signal terminal is connected to the input terminal of the first valve tube. It can be understood that when the second power signal terminal (i.e., HAVDD - half-value analog circuit power supply) is fully boosted, the first valve tube is turned on (i.e., when the voltage on the right side of the first valve tube is greater than the voltage on the left side of the first valve tube), and the voltage output by the second power signal terminal can enter the source driver chip at this time to achieve the purpose of supplying voltage to the source driver chip, thereby avoiding the problem that the unboosted HAVDD (half-value analog circuit power supply) enters the source driver chip, resulting in the voltage difference between the AVDD (analog circuit power supply) and the HAVDD (half-value analog circuit power supply) being greater than 6V and causing damage to the internal circuit of the source driver chip. Description of the Drawings

[0021] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0022] Figure 1 It is a schematic diagram of the voltage difference between AVDD (analog circuit power supply) and HAVDD (half-value analog circuit power supply) when the display device in the prior art is powered on.

[0023] Figure 2 It is a schematic structural diagram of the source driver circuit provided by the embodiment of the present application.

[0024] Figure 3 For Figure 2 It is a schematic diagram of the voltage difference between AVDD (analog circuit power supply) and HAVDD (half-value analog circuit power supply) when the shown source driver circuit is powered on.

[0025] Reference numerals:

[0026] 100. Source driver circuit; 110. First power signal terminal; 120. Second power signal terminal; 130. Switch unit; 140. First valve tube; 150. Second valve tube; 160. First pipeline; 161. First branch pipeline; 162. Second branch pipeline; 163. Third branch pipeline; 164. First resistor; 165. First filter circuit; 166. Second resistor; 170. Second pipeline; 171. Fourth branch pipeline; 172. Fifth branch pipeline; 173. Third resistor; 174. Second filter circuit; 175. Fourth resistor; 200. Source driver chip. Detailed implementation manners

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0028] Nowadays, display panels usually implement the display of images by progressive scanning. During the display time of one frame, the control chip needs to progressively scan all pixel units in the display area.

[0029] Please refer to Figure 1 , Figure 1 It is a schematic diagram of the voltage difference between AVDD (analog circuit power supply) and HAVDD (half-value analog circuit power supply) when the display device in the prior art is powered on. As Figure 1As shown, due to the increase in panel resolution and refresh rate and the increase in the liquid crystal saturation voltage, the voltages of AVDD (analog circuit power supply) and HAVDD (half-value analog circuit power supply) also need to be increased accordingly. This causes an excessive in-plane voltage load on the panel, resulting in a slow boost of the voltage of HAVDD (half-value analog circuit power supply) supplied to the Source Driver IC (source driver chip), thus causing a large voltage difference between AVDD (analog circuit power supply) and HAVDD (half-value analog circuit power supply) ( Figure 1 The dashed part in

[0030] is the maximum voltage difference between AVDD and HAVDD. At this time, the voltage difference is too large). It is clearly stipulated in the chip specification that the voltage difference between AVDD (source driver chip) and HAVDD (half-value analog circuit power supply) must always be lower than 6V, otherwise it will damage the internal circuit of the Source Driver IC (source driver chip). Figure 2 , Figure 2 is the structural schematic diagram of the source driver circuit provided by the embodiment of the present application.

[0031] As Figure 2 shown, in this embodiment, the source driver circuit 100 includes a first power signal terminal 110 and a second power signal terminal 120 that are independently arranged, and a switch unit 130 and a first valve tube 140 that are connected in series. The input end of the source driver chip 200 is connected to the pipeline between the switch unit 130 and the first valve tube 140. Among them, the voltage output by the first power signal terminal 110 can be AVDD (i.e., the analog circuit power supply generated by the integrated power management circuit) generated by the PMIC (Power Management IC, power management chip), and the voltage output by the second power signal terminal 120 can be HAVDD (i.e., the half-value analog circuit power supply generated by the original line in the steady state) generated by the OP (operational amplifier circuit).

[0032] Meanwhile, the first output terminal of the first power signal terminal 110 is connected to the input terminal of the switching unit 130, and the first output terminal of the second power signal terminal 120 is connected to the control terminal of the switching unit 130. When both the first output terminal of the first power signal terminal 110 and the first output terminal of the second power signal terminal 120 output voltages and the voltage difference between them is less than a certain value, the switching unit 130 is turned on at this time, so that the voltage can enter the source driver chip 200. It can be understood that since the switching unit 130 will play a voltage-dividing role, the AVDD (analog circuit power supply) after the voltage drop through the switching unit 130 can replace the HAVDD (half-value analog circuit power supply) with slow voltage boost at this time. So that when the HAVDD (half-value analog circuit power supply) has not been fully boosted, the AVDD (analog circuit power supply) can realize the substitution effect on the HAVDD (half-value analog circuit power supply), thereby avoiding the problem that the voltage difference between the AVDD (analog circuit power supply) and the HAVDD (half-value analog circuit power supply) is greater than 6V, resulting in damage to the internal circuit of the source driver chip 200.

[0033] In addition, please continue to refer to Figure 2 In this embodiment, the second output terminal of the second power signal terminal 120 is connected to the input terminal of the first valve tube 140. It can be understood that when the second power signal terminal 120 (i.e., the HAVDD - half-value analog circuit power supply) is fully boosted, the first valve tube 140 is turned on (i.e., when the voltage on the right side of the first valve tube 140 is greater than the voltage on the left side of the first valve tube 140), and the voltage output by the second power signal terminal 120 can enter the source driver chip 200 at this time to achieve the purpose of supplying voltage to the source driver chip 200, thereby avoiding the problem that the un-boosted-fully HAVDD (half-value analog circuit power supply) enters the source driver chip 200, resulting in the voltage difference between the AVDD (analog circuit power supply) and the HAVDD (half-value analog circuit power supply) being greater than 6V, causing damage to the internal circuit of the source driver chip 200.

[0034] Meanwhile, please combine with Figure 3 Figure 3 For Figure 2 the schematic diagram of the voltage difference between AVDD (analog circuit power supply) and HAVDD (half-value analog circuit power supply) when the source driver circuit shown is powered on. As Figure 3 shown, when the source driver circuit 100 in this embodiment is adopted and the HAVDD is not fully boosted, the voltage difference between the AVDD and the HAVDD can be greatly reduced at this time. And when the HAVDD is fully boosted (i.e., Figure 3 the rising part shown by the dotted line in Figure 3 ), the fully-boosted HAVDD can maintain a small voltage difference with the AVDD at this time (i.e., the voltage difference is always less than 6V, meeting the chip specification requirements), thereby protecting the internal circuit of the source driver chip 200 and avoiding damage to the source driver chip 200 during operation.

[0035] It should be noted that, in this embodiment, the switching unit 130 may be a PMOS transistor, and the first valve tube 140 may be a Schottky diode. The conduction voltage thresholds at the switching unit 130 and the first valve tube 140 can be set according to different types of PMOS transistors and Schottky diodes, and can be specifically adjusted according to the actual situation.

[0036] Optionally, as Figure 2 shown, in an embodiment, the second output terminal of the first power signal terminal 110 may be connected to the second input terminal of the source driver chip 200 to output the AVDD (analog circuit power supply) required by itself to the source driver chip 200.

[0037] Optionally, please continue to refer to Figure 2 , in an embodiment, the source driver circuit 100 may include a second valve tube 150. The second valve tube 150 is disposed between the switching unit 130 and the first valve tube 140, and is disposed opposite to the first valve tube 140. The first input terminal of the source driver chip 200 is connected to the pipeline between the first valve tube 140 and the second valve tube 150.

[0038] It should be noted that the "opposite setting" described in this embodiment means that the negative electrodes of the first valve tube 140 and the second valve tube 150 are oppositely arranged. Specifically, as Figure 2 shown, when the voltage generated by the first power signal terminal 110 passes through the switching unit 130, it will continue to pass through the second valve tube 150 until the first input terminal of the source driver chip 200 to provide the source driver chip 200 with the AVDD after voltage division (which can be regarded as HAVDD at this time); and as the HAVDD generated by the second power signal terminal 120 is fully boosted, at this time, the HAVDD can pass through the first valve tube 140 until the first input terminal of the source driver chip 200. Generally, the boosted HAVDD (generated by the second power signal terminal 120) has a higher voltage value compared to the AVDD after voltage division (generated by the first power signal terminal 110). At this time, the voltage difference across the second valve tube 150 is less than its conduction threshold, so the second valve tube 150 will close at this time, so that only the fully boosted HAVDD generated by the second power signal terminal 120 supplies power to the source driver chip 200.

[0039] It should be noted that the switching unit 130, the first valve tube 140, and the second valve tube 150 in this embodiment can all play a voltage division effect in the source driver circuit 100 to avoid damage to the circuit due to excessive voltage values during passage. At the same time, the second valve tube 150 in this embodiment may also be a Schottky diode, and the conduction voltage threshold of the second valve tube 150 can be set according to different types of Schottky diodes, and can be specifically adjusted according to the actual situation.

[0040] In this embodiment, the voltage output by the first power signal terminal 110 may be 10.08V, and the rise time is 12ms; the voltage output by the second power signal terminal 120 may be 5.68V, and the rise time is 100ms (considering that the voltage drop across the first valve tube 140 after conduction is 0.28V, so at this time the voltage of the second power signal terminal 120 increases by 0.28V additionally, that is, the original voltage of the second power signal terminal 120 is 5.4V); the conduction voltage of the switching unit 130 may be -1.14V. It should be noted that the above values are not limited in this embodiment, that is, the relevant values of the above components can be adjusted according to the actual situation.

[0041] Specifically, the voltage output by the first power signal terminal 110, that is, AVDD (analog circuit power generated by the integrated power management circuit) generated by the PMIC (Power Management IC, power management chip), and the voltage output by the second power signal terminal 120, that is, HAVDD (half-value analog circuit power generated by the original line in the steady state) generated by the OP (operational amplifier circuit) are in the climbing process. When the voltage difference between the control end and the input end of the switching unit 130 < -1.14V, the switching unit 130 conducts; at the same time, when the voltage on the left side of the second valve tube 150 reaches 0.7V, the second valve tube 150 conducts. At this time, due to the slow boost of the voltage output by the second power signal terminal 120, that is, HAVDD (half-value analog circuit power generated by the original line in the steady state) generated by the OP (operational amplifier circuit), the voltage on the left side of the first valve tube 140 is greater than the voltage on the right side of the first valve tube 140. At this time, the first valve tube 140 does not conduct. At this time, the voltage received by the first input terminal of the source driver chip 200 is the voltage output by the first power signal terminal 110, the voltage drop across the switching unit 130 and the second valve tube 150. When the voltage output by the second power signal terminal 120 completes the boost, when the voltage on the right side of the first valve tube 140 is greater than the voltage on the left side of the first valve tube 140, the voltage received by the first input terminal of the source driver chip 200 is the voltage after passing through the first valve tube 140 output by the second power signal terminal 120.

[0042] Optionally, as Figure 2 shown, the second output terminal of the second power signal terminal 120 is connected to the input end of the first valve tube 140 through the first pipeline 160, and the first pipeline 160 may include a first branch pipeline 161, a second branch pipeline 162, and a third branch pipeline 163 arranged in parallel. Among them, the first branch pipeline 161 is used to connect the output end of the switching unit 130, the second branch pipeline 162 is used to connect the first input end of the source driver chip 200, and the third branch pipeline 163 is used to connect the output end of the first valve tube 140 to achieve the voltage division effect on the first power signal terminal 110.

[0043] In addition, please continue to refer to Figure 2 , in this embodiment, the source driving circuit 100 may further include a first resistor 164, a first filtering circuit 165, a second resistor 166, and a fifth resistor 167. The first resistor 164 is disposed on the first branch 161, the first filtering circuit 165 is disposed on the second branch 162, and the second resistor 166 is disposed on the third branch 163. The fifth resistor 167 is disposed between the first output terminal of the second power signal terminal 120 and the control terminal of the switching unit 130. It can be understood that the first resistor 164, the first filtering circuit 165, the second resistor 166, and the fifth resistor 167 in this embodiment can all play a further voltage dividing effect on the first power signal terminal 110, so as to ensure the stability of the source driving circuit 100.

[0044] At the same time, in this embodiment, the resistance value of the first resistor 164 can be set to be greater than that of the second resistor 166, so as to avoid the HAVDD generated by the first power signal terminal 110 from entering the switching unit 130 through the first branch 161, and further avoid the problem of affecting the conduction effect of the switching unit 130.

[0045] It should be noted that, in this embodiment, the resistance value of the first resistor 164 can be 10 MΩ, and the resistance value of the second resistor 166 can be 100 KΩ.

[0046] Optionally, as Figure 2 shown, in an embodiment, the first output terminal of the first power signal terminal 110 may be connected to the input terminal of the switching unit 130 through a second pipeline 170, where the second pipeline 170 may include a fourth branch 171 and a fifth branch 172 connected in parallel to achieve a voltage dividing effect on the AVDD generated by the first power signal terminal 110. At the same time, the source driving circuit 100 may include a third resistor 173 and a second filtering circuit 174. The third resistor 173 is disposed on the fourth branch 171, and the second filtering circuit 174 is disposed on the fifth branch 172, so as to achieve a further voltage dividing effect on the AVDD generated by the first power signal terminal 110 and ensure the stability of the source driving circuit 100.

[0047] It should be noted that the first filtering circuit 165 and the second filtering circuit 174 in this embodiment may be composed of existing reactance elements. For example, a capacitor C is connected in parallel at both ends of the load resistor, or an inductor is connected in series with the load, as well as various complex filtering circuits composed of capacitors and inductors. It can be understood that when the first filtering circuit 165 and the second filtering circuit 174 are provided in this embodiment, the filtering effect can be achieved through the generated inductance, so as to reduce the pulsation of the load current and voltage in the source driving circuit 100 and make the waveform smoother.

[0048] In addition, please continue to refer to Figure 2 , in the above embodiment, the source driver circuit 100 may further include a fourth resistor 175. The fourth resistor 175 may be disposed between the first output terminal of the first power signal terminal 110 and the fourth branch circuit 171. Among them, both the fourth resistor 175 and the third resistor 173 are resistors with small resistance values, and the resistance ratio between the two is 4:5. Thereby, the AVDD generated by the first power signal terminal 110 can obtain a faster power-on ramp slope in the second pipeline 170, and further, the power supply rate of the first power signal terminal 110 to the source driver chip 200 is faster, avoiding the situation that the voltage difference between AVDD and HAVDD (half-value analog circuit power supply) is too large, thereby further realizing the protection of the source driver circuit 100.

[0049] It should be noted that, in this embodiment, the resistance value of the third resistor 173 may be 125 Ω, and the resistance value of the fourth resistor 175 may be 100 Ω.

[0050] An embodiment of the present application further provides a display device, including a source driver chip 200, where the source driver chip 200 includes the source driver circuit 100 mentioned in any of the above embodiments.

[0051] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0052] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features.

[0053] The above has introduced in detail the source driver circuit and the display device provided by the embodiments of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A source driver circuit for connecting to a source driver chip, characterized in that, Comprising: A first power signal terminal and a second power signal terminal which are independently arranged, and a switch unit and a first valve tube which are arranged in series; wherein, The first input terminal of the source driver chip is connected to the pipeline between the switch unit and the first valve tube, the first output terminal of the first power signal terminal is connected to the input terminal of the switch unit, the second output terminal of the first power signal terminal is connected to the second input terminal of the source driver chip, the first output terminal of the second power signal terminal is connected to the control terminal of the switch unit, and the second output terminal of the second power signal terminal is connected to the input terminal of the first valve tube; wherein, the first power signal terminal is an analog circuit power supply, and the second power signal terminal is a half-value analog circuit power supply.

2. The source driver circuit according to claim 1, wherein The source driver circuit further includes a second valve tube, the second valve tube is arranged between the switch unit and the first valve tube, and is arranged opposite to the first valve tube, and the first input terminal of the source driver chip is connected to the pipeline between the first valve tube and the second valve tube.

3. The source driver circuit according to claim 1, wherein The second output terminal of the second power signal terminal is connected to the input terminal of the first valve tube through a first pipeline, wherein, the first pipeline includes a first branch pipeline, a second branch pipeline and a third branch pipeline which are arranged in parallel, the first branch pipeline is used for connecting the output terminal of the switch unit, the second branch pipeline is used for connecting the first input terminal of the source driver chip, and the third branch pipeline is used for connecting the input terminal of the first valve tube.

4. The source driver circuit according to claim 3, wherein The source driver circuit further includes a first resistor, a first filter circuit and a second resistor, the first resistor is arranged in the first branch pipeline, the first filter circuit is arranged in the second branch pipeline, and the second resistor is arranged in the third branch pipeline, wherein, the resistance value of the first resistor is greater than the resistance value of the second resistor.

5. The source driver circuit according to claim 1, characterized in that The first output terminal of the first power signal terminal is connected to the input terminal of the switch unit through a second pipeline, wherein, the second pipeline includes a fourth branch pipeline and a fifth branch pipeline which are arranged in parallel, the source driver circuit further includes a third resistor and a second filter circuit, the third resistor is arranged in the fourth branch pipeline, and the second filter circuit is arranged in the fifth branch pipeline.

6. The source driver circuit according to claim 5, wherein The source driver circuit further includes a fourth resistor, the fourth resistor is arranged between the first output terminal of the first power signal terminal and the fourth branch pipeline, wherein, the resistance ratio of the fourth resistor to the third resistor is 4:

5.

7. The source driving circuit according to claim 1, wherein The source driver circuit further includes a fifth resistor, the fifth resistor is arranged between the first output terminal of the second power signal terminal and the control terminal of the switch unit.

8. The source driver circuit according to claim 1, wherein The switch unit is a PMOS transistor, and the first valve tube is a Schottky diode.

9. A display device, characterized in that, Including a source driver chip, wherein, the source driver chip includes the source driver circuit according to any one of claims 1-8.

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