A semiconductor package structure and a method of manufacturing the same

Abstract

A semiconductor package structure and a method for manufacturing the same, wherein the semiconductor package structure comprises: a redistribution structure, the redistribution structure comprising a wiring layer, a cavity extending from a side surface of the redistribution structure to a partial thickness of the redistribution structure, and a bottom of the cavity exposing a partial wiring layer; a first chip flip-chip mounted on a side of the redistribution structure, the first chip having a first conductive member on a side of an active surface of the first chip, the first conductive member being located in the cavity and connected with the wiring layer at the bottom of the cavity, and an edge region of the active surface of the first chip being attached to a surface of the redistribution structure at a periphery of the cavity; and a molding layer covering the side of the redistribution structure and covering the first chip, the molding layer not being in contact with the active surface of the first chip. The semiconductor package structure can realize integration of a functional chip and other chips by using a fan-out process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] With the development of information technology, radio frequency (RF) modules are becoming increasingly compact and high-speed. Fan-out semiconductor packaging structures, with their advantages of small size, low parasitic parameters, and ability to achieve high-speed interconnection between chips, have broad application prospects in the field of RF module packaging.

[0003] As a crucial component of radio frequency (RF) modules, surface acoustic wave (SAW) filter chips require a cavity structure beneath them during packaging to prevent contamination of their functional areas. To achieve this enclosure, a film is typically formed on the back of the SAW chip using a coating process, followed by plastic encapsulation. However, the coating process has poor compatibility with fan-out packaging, making it difficult to integrate the RF module with other functional chips and limiting the functionality of the semiconductor package structure. Therefore, a new semiconductor package structure is needed. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the shortcomings of the existing semiconductor packaging structure in terms of limited functionality, thereby providing a semiconductor packaging structure and its preparation method.

[0005] This invention provides a semiconductor packaging structure, comprising: a redistribution structure including a wiring layer; a cavity extending from one side surface of the redistribution structure to a portion of its thickness, the bottom of which exposes a portion of the wiring layer; a first chip flip-chip on one side of the redistribution structure, the first chip having a first conductive element on its active side, the first conductive element being located in the cavity and connected to the wiring layer at the bottom of the cavity, the edge region of the active side of the first chip being bonded to the surface of the redistribution structure on the outer periphery of the cavity; and a molding compound covering one side of the redistribution structure and the first chip, the molding compound not contacting the active side of the first chip.

[0006] Optionally, the depth of the cavity is equal to the height of the first conductive element.

[0007] Optionally, the redistribution structure at the bottom of the cavity may also have a through hole that communicates with the cavity.

[0008] Optionally, the width of the through hole is 10μm-50μm.

[0009] Optionally, it further includes: a second chip flip-chip on one side of the redistribution structure, the second chip being located on the same side of the redistribution structure as the first chip, the second chip being electrically connected to the redistribution structure, and the thickness of the redistribution structure at the bottom of the second chip being greater than the thickness of the redistribution structure at the bottom of the first chip; an underfill layer located between the second chip and the redistribution structure; and the molding compound further covering the second chip and the underfill layer.

[0010] Optionally, the second chip has a second conductive element on its active side, and the second conductive element is connected to the redistribution structure; the underfill layer surrounds the sidewall of the second conductive element.

[0011] Optionally, the first chip includes a surface acoustic wave (SAW) filter chip.

[0012] The present invention also provides a method for fabricating a semiconductor package structure, comprising: forming a redistribution structure, the redistribution structure including a wiring layer; forming a cavity of the redistribution structure extending from one side surface of the redistribution structure to a portion of its thickness, the bottom of the cavity exposing a portion of the wiring layer; providing a first chip, the first chip having a first conductive element on one side of its active surface; flip-chip bonding the first chip to one side of the redistribution structure, the first conductive element being placed in the cavity and connected to the wiring layer at the bottom of the cavity, the edge region of the active surface of the first chip being bonded to the surface of the redistribution structure on the outer periphery of the cavity; and forming a molding compound covering the first chip on one side of the redistribution structure, the molding compound not contacting the active surface of the first chip.

[0013] Optionally, it also includes: forming a through-hole communicating with the cavity in the redistribution structure at the bottom of the cavity before flipping the first chip onto one side of the redistribution structure.

[0014] Optionally, before forming a molding compound covering the first chip on one side of the redistribution structure, the method further includes: flip-chip bonding a second chip on one side of the redistribution structure, the second chip being located on the same side of the redistribution structure as the first chip, the second chip being electrically connected to the redistribution structure, and the thickness of the redistribution structure at the bottom of the second chip being greater than the thickness of the redistribution structure at the bottom of the first chip; forming an underfill layer between the second chip and the redistribution structure; and after forming the molding compound, the molding compound further covers the second chip and the underfill layer.

[0015] Optionally, the active side of the second chip has a second conductive element, and after the second chip is flip-chip mounted on the redistribution structure side, the second conductive element is connected to the redistribution structure; during the formation of an underfill layer between the second chip and the redistribution structure, the underfill layer surrounds the sidewall of the second conductive element.

[0016] The technical solution of this invention has the following advantages:

[0017] The semiconductor packaging structure provided by this invention includes a redistribution structure comprising a wiring layer and a cavity extending from one side surface of the redistribution structure to a portion of its thickness. A portion of the wiring layer is exposed at the bottom of the cavity. A first chip is flip-chip mounted on one side of the redistribution structure. The active side of the first chip has a first conductive element located within the cavity and connected to the wiring layer at the bottom of the cavity. The edge region of the active side of the first chip is bonded to the surface of the redistribution structure surrounding the cavity. A molding compound covers one side of the redistribution structure and also covers the first chip, without contacting the active side of the first chip. The edge region of the active side of the first chip is bonded to the surface of the redistribution structure surrounding the cavity, and the molding compound does not contact the active side of the first chip. The cavity ensures that the functional areas of the first chip are not contaminated, thus protecting the functional areas of the first chip. The first chip is connected to the redistribution structure via the first conductive element, which facilitates integration of the first chip with other functional chips. The semiconductor packaging structure can utilize fan-out technology to integrate functional chips with other chips.

[0018] Furthermore, the depth of the cavity is equal to the height of the first conductive element. This ensures that while the first conductive element is partially connected to the bottom of the cavity through exposed wiring layers, the edge region of the active surface of the first chip is also bonded to the surface of the redistribution structure around the cavity. This prevents contamination of the functional areas of the first chip, thus protecting them.

[0019] Furthermore, the redistribution structure at the bottom of the cavity also has a through hole that communicates with the cavity. This avoids the sidewalls of the cavity from being subjected to external atmospheric pressure, eliminating the risk of the semiconductor packaging structure breaking due to excessive pressure difference between the cavity and the external atmospheric pressure. Therefore, the semiconductor packaging structure has good reliability.

[0020] The semiconductor packaging structure fabrication method provided by this invention forms a cavity in the redistribution structure extending from one side surface to a certain thickness. A first conductive element is placed in the cavity and connected to the wiring layer at the bottom of the cavity. The edge region of the active surface of the first chip is bonded to the surface of the redistribution structure on the outer periphery of the cavity. Therefore, while forming the cavity, good electrical connection between the first chip and the redistribution structure is ensured. A molding compound layer covering the first chip is formed on one side of the redistribution structure, and the molding compound layer does not contact the active surface of the first chip. This avoids contamination of the functional area of ​​the first chip during the molding compound layer formation process and better controls the gap between the functional area of ​​the first chip and the redistribution structure after flip-chip bonding. Therefore, the semiconductor packaging structure fabrication method can utilize a simple fan-out packaging process to integrate a first chip with functional areas with other chips. Thus, the semiconductor packaging structure fabrication method is not only simple in process but also allows for the formation of a semiconductor packaging structure with multiple functions. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of a semiconductor packaging structure provided in another embodiment of the present invention;

[0024] Figure 3 A flowchart illustrating a method for fabricating a semiconductor packaging structure according to an embodiment of the present invention;

[0025] Figure 4 - Figure 8 This is a schematic diagram of the fabrication process of a semiconductor packaging structure provided in an embodiment of the present invention;

[0026] Figure 9 This is a schematic diagram of the fabrication process of a semiconductor packaging structure provided in another embodiment of the present invention. Detailed Implementation

[0027] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0029] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0030] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0031] Example 1

[0032] This embodiment provides a semiconductor packaging structure, referencing... Figure 1 ,include:

[0033] A rewiring structure 1, the rewiring structure including a wiring layer 11, a cavity 2 of the rewiring structure extending from one side surface of the rewiring structure 1 to a portion of its thickness, the bottom of the cavity 2 exposing a portion of the wiring layer 11;

[0034] A first chip 3 is flip-mounted on one side of the redistribution structure 1. The active side of the first chip 3 has a first conductive element 31. The first conductive element 31 is located in the cavity 2 and connected to the wiring layer 11 at the bottom of the cavity 2. The edge region of the active side of the first chip 3 is attached to the surface of the redistribution structure 1 on the outer periphery of the cavity 2.

[0035] A molding layer 4 covers one side of the redistribution structure 1 and the first chip 3, and the molding layer 4 does not contact the active surface of the first chip 3.

[0036] In the semiconductor packaging structure provided in this embodiment, the edge region of the active surface of the first chip 3 is bonded to the surface of the redistribution structure 1 on the outer periphery of the cavity 2, and the molding layer 4 does not contact the active surface of the first chip 3. The cavity 2 can ensure that the functional area of ​​the first chip 3 is not contaminated, thus protecting the functional area of ​​the first chip 3. The first chip 3 is connected to the redistribution structure 1 through the first conductive element 31, which is conducive to the integration of the first chip 3 with other functional chips. The semiconductor packaging structure can use the fan-out process to integrate functional chips with other chips.

[0037] In one embodiment, continue to refer to Figure 1 The rewiring structure 1 also includes a dielectric layer 12.

[0038] In one embodiment, the dielectric layer 12 is made of polyimide; the wiring layer 11 is made of metal, such as copper.

[0039] In one embodiment, the first chip 3 includes a surface acoustic wave filter chip.

[0040] In one embodiment, the material of the molding layer 4 includes epoxy resin and additives, the additives including hardeners, fillers, flame retardants, etc.

[0041] In one embodiment, the depth of the cavity 2 is equal to the height of the first conductive element 31. This ensures that while the first conductive element 31 is partially connected to the bottom of the cavity 2 through exposed wiring layers, the edge region of the active surface of the first chip is also bonded to the surface of the redistribution structure around the cavity. This prevents contamination of the functional areas of the first chip, thus protecting them.

[0042] In one embodiment, the height of the first conductive element 31 is 20μm-150μm, for example 80μm; if the height of the first conductive element is less than 20μm, the effect of improving the connection strength between the first conductive element and the rewiring structure is not obvious; if the height of the first conductive element is greater than 150μm, the effect of preventing short circuits between the first conductive elements is not obvious.

[0043] In one embodiment, the semiconductor package structure further includes: a second chip 5 flip-chip mounted on one side of the redistribution structure 1, the second chip 5 being located on the same side of the redistribution structure 1 as the first chip 3, the second chip 5 being electrically connected to the redistribution structure 1, and the thickness of the redistribution structure 1 at the bottom of the second chip 5 being greater than the thickness of the redistribution structure 1 at the bottom of the first chip 3.

[0044] In one embodiment, the semiconductor package structure further includes an underfill layer 6 located between the second chip 5 and the redistribution structure 1; the molding compound 4 also covers the second chip 5 and the underfill layer 6. The underfill layer 6 helps to improve the stability of the semiconductor package structure.

[0045] In one embodiment, the second chip 5 has a second conductive element 51 on the active side, and the second conductive element 51 is connected to the redistribution structure 1; the underfill layer 6 surrounds the sidewall of the second conductive element 51.

[0046] In one embodiment, continue to refer to Figure 1 The semiconductor packaging structure further includes a plurality of solder balls 7 located on the side surface of the redistribution structure 1 facing away from the first chip 3 and the second chip 5, the solder balls 7 being electrically connected to the redistribution structure 1.

[0047] Example 2

[0048] The difference between the semiconductor packaging structure provided in this embodiment and the semiconductor packaging structure provided in Embodiment 1 is that, referring to... Figure 2 The redistribution structure 1 at the bottom of the cavity 2 also has a through hole 8, which communicates with the cavity 2. This avoids the sidewalls of the cavity 2 from being subjected to external atmospheric pressure, eliminating the risk of the semiconductor packaging structure breaking due to excessive pressure difference between the cavity 2 and the external atmospheric pressure. Therefore, the semiconductor packaging structure has good reliability.

[0049] In one embodiment, the width of the through hole 8 is 10μm-50μm, for example, 30μm. If the width of the through hole is less than 10μm, the degree to which the risk of the semiconductor packaging structure breaking due to excessive pressure difference between the cavity and the external atmospheric pressure is reduced is small. If the width of the through hole is greater than 30μm, the effect of increasing the arrangement density of the first conductive element is not obvious, and the effect of improving the connection strength between the first conductive element and the redistribution structure is not obvious.

[0050] The parts of this embodiment that are the same as the previous embodiment will not be described in detail.

[0051] Example 3

[0052] This embodiment provides a method for fabricating a semiconductor packaging structure, referencing... Figure 3 This includes the following steps:

[0053] Step S1: Form a rewiring structure, the rewiring structure including a wiring layer;

[0054] Step S2: Form a cavity in the redistribution structure extending from one side surface of the redistribution structure to a portion of its thickness, with a portion of the wiring layer exposed at the bottom of the cavity;

[0055] Step S3: Provide a first chip, wherein the active side of the first chip has a first conductive element;

[0056] Step S4: The first chip is flip-chip mounted on one side of the redistribution structure, the first conductive element is placed in the cavity and connected to the wiring layer at the bottom of the cavity, and the edge region of the active surface of the first chip is attached to the surface of the redistribution structure on the outer periphery of the cavity.

[0057] Step S5: A molding compound layer covering the first chip is formed on one side of the redistribution structure, wherein the molding compound layer does not contact the active surface of the first chip.

[0058] The semiconductor packaging structure fabrication method provided in this embodiment forms a cavity in the redistribution structure extending from one side surface of the redistribution structure to a certain thickness. The first conductive element is placed in the cavity and connected to the wiring layer at the bottom of the cavity. The edge region of the active surface of the first chip is bonded to the surface of the redistribution structure on the outer periphery of the cavity. Therefore, while forming the cavity, a good electrical connection between the first chip and the redistribution structure is ensured. A molding compound layer covering the first chip is formed on one side of the redistribution structure. The molding compound layer does not contact the active surface of the first chip. This avoids contamination of the functional area of ​​the first chip during the molding compound layer formation process and also better controls the gap between the functional area of ​​the first chip and the redistribution structure after flip-chip bonding. Therefore, the semiconductor packaging structure fabrication method can integrate the first chip with functional areas with other chips using a simple fan-out packaging process. Thus, the semiconductor packaging structure fabrication method is not only simple in process but also produces a semiconductor packaging structure that can achieve multiple functions.

[0059] In one embodiment, the process of flipping the first chip onto one side of the redistribution structure includes a thermo-bonding process.

[0060] In one embodiment, before forming a molding compound covering the first chip on one side of the redistribution structure, the method further includes: flip-chip bonding a second chip to one side of the redistribution structure, the second chip being located on the same side of the redistribution structure as the first chip, the second chip being electrically connected to the redistribution structure, and the thickness of the redistribution structure at the bottom of the second chip being greater than the thickness of the redistribution structure at the bottom of the first chip; forming an underfill layer between the second chip and the redistribution structure; and after forming the molding compound, the molding compound further covering the second chip and the underfill layer.

[0061] In one embodiment, the second chip has a second conductive element on the active side, and after the second chip is flip-chip mounted on the redistribution structure side, the second conductive element is connected to the redistribution structure; during the formation of an underfill layer between the second chip and the redistribution structure, the underfill layer surrounds the sidewall of the second conductive element.

[0062] The following is for reference. Figures 4 to 8 The fabrication method of the semiconductor packaging structure is described in detail.

[0063] refer to Figure 4 A carrier board 100 is provided, a bonding layer 200 is formed on one side surface of the carrier board 100, and then a redistribution structure 1 is formed on the side surface of the bonding layer 200 opposite to the carrier board 100, the redistribution structure 1 including a wiring layer 11; a cavity 2 is formed extending from one side surface of the redistribution structure 1 to a certain thickness of the redistribution structure 1, and a portion of the wiring layer 11 is exposed at the bottom of the cavity 2.

[0064] In one embodiment, the rewiring structure 1 further includes a dielectric layer 12.

[0065] In one embodiment, the dielectric layer 12 is made of polyimide; the wiring layer 11 is made of metal, such as copper.

[0066] refer to Figure 5 A first chip 3 is provided, and the active side of the first chip 3 has a first conductive element 31; the first chip 3 is flip-mounted on one side of the redistribution structure 1, the first conductive element 31 is placed in the cavity 2 and connected to the wiring layer 11 at the bottom of the cavity 2, and the edge region of the active side of the first chip 3 is attached to the surface of the redistribution structure 1 on the outer periphery of the cavity 2.

[0067] The depth of the cavity 2 is equal to the height of the first conductive element 31. In this way, while the first conductive element 31 is partially connected to the bottom of the cavity 2 with exposed wiring layers, it also ensures that the edge area of ​​the active surface of the first chip is in close contact with the surface of the redistribution structure on the outer periphery of the cavity. This ensures that the functional area of ​​the first chip is not contaminated, thus protecting the functional area of ​​the first chip.

[0068] Continue to refer to Figure 5A second chip 5 is flip-chip mounted on one side of the redistribution structure 1. The second chip 5 and the first chip 3 are located on the same side of the redistribution structure 1, and the second chip 5 is electrically connected to the redistribution structure 1. The thickness of the redistribution structure 1 at the bottom of the second chip 5 is greater than the thickness of the redistribution structure 1 at the bottom of the first chip 3. The active side of the second chip 5 has a second conductive element 51, which is connected to the redistribution structure 1 after the second chip 5 is flip-chip mounted on one side of the redistribution structure 1.

[0069] refer to Figure 6 An underfill layer 6 is formed between the second chip 5 and the redistribution structure 1; during the formation of the underfill layer 6 between the second chip 5 and the redistribution structure 1, the underfill layer 6 surrounds the sidewall of the second conductive element 51.

[0070] refer to Figure 7 A molding compound 4 is formed on one side of the redistribution structure 1 to cover the first chip 3. The molding compound 4 does not contact the active surface of the first chip 3. After the molding compound 4 is formed, it also covers the second chip 5 and the underfill layer 6.

[0071] refer to Figure 8 After forming a molding layer 4 covering the first chip 3 on one side of the redistribution structure 1, the carrier board 100 and the bonding layer 200 are removed. Then, a plurality of solder balls 7 are formed on the surface of the redistribution structure 1 away from the first chip 3 and the second chip 5. The solder balls 7 are electrically connected to the redistribution structure 1.

[0072] Example 4

[0073] This embodiment provides a method for fabricating a semiconductor package structure, which differs from the method for fabricating a semiconductor package structure provided in Embodiment 3 in that it further includes: [reference] Figure 9 Before flipping the first chip onto one side of the redistribution structure, a through-hole 8 communicating with the cavity is formed in the redistribution structure at the bottom of the cavity.

[0074] The parts of this embodiment that are the same as the previous embodiment will not be described in detail.

[0075] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: A rewiring structure, the rewiring structure including a wiring layer, a cavity of the rewiring structure extending from one side surface of the rewiring structure to a portion of the thickness of the cavity, the bottom of the cavity exposing a portion of the wiring layer; A first chip is flip-chip mounted on one side of the redistribution structure. The active side of the first chip has a first conductive element. The first conductive element is located in the cavity and connected to the wiring layer at the bottom of the cavity. The edge region of the active side of the first chip is attached to the surface of the redistribution structure on the outer periphery of the cavity. A molding compound covers one side of the redistribution structure and the first chip, wherein the molding compound does not contact the active surface of the first chip.

2. The semiconductor packaging structure according to claim 1, characterized in that, The depth of the cavity is equal to the height of the first conductive element.

3. The semiconductor packaging structure according to claim 1, characterized in that, The redistribution structure at the bottom of the cavity also has a through hole, which communicates with the cavity.

4. The semiconductor packaging structure according to claim 3, characterized in that, The width of the through hole is 10μm-50μm.

5. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A second chip is flip-chip mounted on one side of the redistribution structure. The second chip and the first chip are located on the same side of the redistribution structure. The second chip is electrically connected to the redistribution structure. The thickness of the redistribution structure at the bottom of the second chip is greater than the thickness of the redistribution structure at the bottom of the first chip. The underfill layer is located between the second chip and the rewiring structure; The molding compound also covers the second chip and the underfill layer.

6. The semiconductor packaging structure according to claim 5, characterized in that, The second chip has a second conductive element on its active side, and the second conductive element is connected to the redistribution structure; The underfill layer surrounds the sidewall of the second conductive element.

7. The semiconductor packaging structure according to claim 1, characterized in that, The first chip includes a surface acoustic wave (SAW) filter chip.

8. A method for fabricating a semiconductor packaging structure, characterized in that, include: A rewiring structure is formed, the rewiring structure including a wiring layer; A cavity is formed in the rewiring structure, extending from one side surface of the rewiring structure to a portion of its thickness, with a portion of the wiring layer exposed at the bottom of the cavity; A first chip is provided, wherein the active side of the first chip has a first conductive element; The first chip is flip-chip mounted on one side of the redistribution structure, the first conductive element is placed in the cavity and connected to the wiring layer at the bottom of the cavity, and the edge region of the active surface of the first chip is attached to the surface of the redistribution structure on the outer periphery of the cavity. A molding compound is formed on one side of the redistribution structure to cover the first chip, and the molding compound does not contact the active surface of the first chip.

9. The method for preparing a semiconductor packaging structure according to claim 8, characterized in that, Also includes: Before flipping the first chip onto one side of the redistribution structure, a through-hole communicating with the cavity is formed in the redistribution structure at the bottom of the cavity.

10. The method for preparing a semiconductor packaging structure according to claim 8, characterized in that, Before forming a molding compound covering the first chip on one side of the redistribution structure, the method further includes: flip-chip bonding a second chip on one side of the redistribution structure, the second chip being located on the same side of the redistribution structure as the first chip, the second chip being electrically connected to the redistribution structure, and the thickness of the redistribution structure at the bottom of the second chip being greater than the thickness of the redistribution structure at the bottom of the first chip. An underfill layer is formed between the second chip and the rewiring structure; After the molding compound is formed, it also covers the second chip and the underfill layer.

11. The method for fabricating a semiconductor packaging structure according to claim 10, characterized in that, The second chip has a second conductive element on its active side. After the second chip is flip-chip mounted on the redistribution structure, the second conductive element is connected to the redistribution structure. During the formation of an underfill layer between the second chip and the redistribution structure, the underfill layer surrounds the sidewall of the second conductive element.

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