High-gain heteroamplifier based on cascode circuit and preparation method thereof

Abstract

The application belongs to the technical field of semiconductor devices, and particularly relates to a high-gain heterojunction amplifier based on an SOI-graphene common-source common-gate circuit and a preparation method thereof. The high-gain heterojunction amplifier comprises a substrate, a buried oxide layer, a top silicon channel region, an oxide layer isolation region, a gate oxide layer, a gate, a gate metal contact, a source metal contact, a drain metal contact on the channel region, and a graphene channel region, a gate oxide layer, a gate, a gate metal contact, a source metal contact and a drain metal contact on the oxide layer isolation region. The application adopts an SOI-graphene heterojunction on the basis of the common-source common-gate circuit, connects the graphene to the gate of the input end of the device, utilizes the high gm of the graphene, connects the high output resistance of the SOI transistor to the output end, so as to improve the output resistance, the voltage and the power gain; the device process cost is lower, and the device can be applied to a radio frequency transistor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a high-gain heterogeneous amplifier and its fabrication method. Background Technology

[0002] Over the past few decades, silicon on insulator (SOI) technology has taken the radio frequency (RF) field by storm. By offering high performance and low cost, it has steadily replaced silicon on gallium arsenide and sapphire as the mainstream technology for RF switch groups in mobile applications. Today, almost 100% of modern smartphones include RF switches implemented on partially depleted (PD) SOI, which are mounted on a designed and optimized trap-rich (TR) silicon substrate. SOI, or silicon on insulator, is a sandwich structure consisting of a silicon substrate, an insulating layer, and a top monocrystalline silicon layer.[6]

[0003] 5G communication is an international initiative aimed at providing next-generation services. It consumes a lot of power and is data-intensive. The performance indicators for achieving 5G goals will depend on phased array MIMO (multiple-input multiple-output) antennas, new spectrum availability and small cell technology, which not only enhance broadband connectivity but also enable IoT services to achieve intelligent coverage manufacturing applications and provide ultra-reliable and low-latency services. This mode will impose strict design requirements on system architecture and RF front end. The RF front end (RFFE), as one of the key components, is an important part of various wireless transmitters. A key design requirement is the need for high output power [1]. The most critical performance indicator of RF transistors is the cutoff frequency, which is determined by transconductance gm and gate capacitance Cg [2]. The transconductance gm and gate capacitance Cg can be increased by increasing the channel carrier mobility and reducing the channel length. Due to the small phonon scattering of the graphene monolayer structure, graphene has an ultra-high carrier mobility, which is measured to be over 100,000 cm2 / (V·s) at room temperature. Such high mobility gives graphene a very broad application prospect in the high frequency field. In addition, graphene has an ultra-high strong field drift velocity and can withstand the ultra-high channel electric field strength caused by the reduction of gate length. Therefore, graphene transistors have great application potential in the radio frequency field. However, graphene has poor ID-VD saturation characteristics and low output resistance, resulting in very small voltage gain and power gain. Existing research has invented a new type of semiconductor device with a different working mechanism from ordinary radio frequency amplifiers. Based on the cascode circuit of CVD graphene field-effect transistor, gm can be maintained and go can be reduced at the same time through the cascode circuit. The cascode circuit is composed of a common source and a common gate [3][4][5]. However, the problem of low output resistance has not been solved well. Therefore, it is necessary to continue to study new devices to improve their performance. Summary of the Invention

[0004] The purpose of this invention is to provide a high-gain heterogeneous amplifier with excellent electrical performance and high compatibility with ordinary MOSFETs, as well as a method for its fabrication.

[0005] This invention provides a high-gain heterojunction amplifier, which proposes a novel heterojunction structure based on the cascode circuit to improve upon the shortcomings of cascode circuits based on CVD graphene FETs. By introducing a key SOI substrate, NLDD doping forms an n-type channel, creating an SOI-graphene heterojunction. The input gate is connected to graphene, utilizing the high gm of graphene. The output is connected to the high output resistance of the SOI transistor, ultimately achieving the goal of increasing output resistance and improving voltage and power gain. The SOI-graphene-based cascode high-gain heterojunction amplifier not only possesses excellent electrical performance and high compatibility with ordinary MOSFETs, but also features simple and mature fabrication processes that avoid photolithographic alignment errors.

[0006] The high-gain heterogeneous amplifier provided by this invention is configured as follows: Figure 1 As shown, it specifically includes:

[0007] Substrate 1;

[0008] Buried oxide layer 2 formed on substrate 1;

[0009] The drain 6, top channel region 3, source 7, and graphene channel region 5 are arranged from left to right on the buried oxide layer 2.

[0010] A shallow trench isolation 4 between the source electrode 7 and the graphene channel region 5, the shallow trench isolation 4 penetrating the buried oxide layer 2 and the substrate 1;

[0011] A gate oxide layer 11, a gate 15, and a gate metal contact 17 are sequentially formed on the top channel region 3;

[0012] A gate oxide layer 12, a gate 16, and a gate metal contact 18 are sequentially formed on the graphene channel region 5.

[0013] Two gate sidewalls 13 and 14 are formed on both sides of the gate oxide layer 11, the gate 15, and the gate metal contact 17;

[0014] A drain metal contact 8 is formed on the drain electrode 6 and outside the gate sidewall 13;

[0015] A common metal contact 9 is formed on the source 7 and the shallow trench isolation 4, between the gate sidewall 14 and the gate oxide layer 12;

[0016] The source metal contact 10 is formed on the graphene channel region 5 and outside the gate oxide layer 12.

[0017] Furthermore:

[0018] The substrate 1 is a semiconductor, such as silicon, and can be weakly p-type doped silicon with a doping concentration of 10. 15 cm -2 Up to 10 19 cm -2 The substrate can also be made of materials such as germanium silicon, gallium nitride, or indium gallium arsenide.

[0019] The buried oxide layer 2 is a silicon dioxide insulating material with a thickness between 5 nm and 500 nm.

[0020] The top channel region 3 is also a semiconductor, specifically it can be silicon, germanium silicon, gallium nitride or indium gallium arsenide, etc.; the thickness is between 5nm and 100nm.

[0021] The shallow trench isolation 4 is used to isolate silicon, and the shallow trench isolation 4 is filled with silicon nitride or silicon dioxide.

[0022] The drain 6 and source 7 are N-type ion implanted, and the implanted ions are generally phosphorus or arsenic; the implanted ion dose is 10. 13 cm -2 Up to 10 16 cm -2 between.

[0023] The gate oxide layer 11 is made of hafnium oxide high-K dielectric material; the gate oxide layer 12 is made of hafnium oxide or aluminum oxide high-K dielectric material.

[0024] The device structure is symmetrical. Both the SOI device and the graphene device are n-type, that is, one is an n-type doped SOI device and the other is an n-type graphene device.

[0025] Using gate sidewalls 13 and 14 as a mask, the metal contact area is formed in a self-symmetrical manner.

[0026] The method for fabricating a high-gain heterojunction amplifier proposed in this invention is described in reference to... Figure 2 The specific steps are as follows:

[0027] (1) On the initial insulating layer, a silicon substrate is photolithographically etched and grooved. Then, a silicon dioxide isolation sidewall STI structure is formed by chemical vapor deposition (CVD) to fill the groove. The STI structure isolates SOI devices and graphene devices.

[0028] (2) The initial substrate and positive gate pattern are formed by photolithography and etching; including substrate 1, buried oxide layer 2 and top channel region 3, and then gate oxide layer and positive gate material are deposited;

[0029] (3) Using the gate as a mask, ion implantation is performed in a self-aligned manner to form a low-drain doped region;

[0030] (4) Deposit a layer of sidewall dielectric on the gate and perform dry anisotropic etching to form the gate sidewall;

[0031] (5) Using the gate and gate sidewall as masks, deposit metal contacts and anneal them to form metal contacts for the source, drain and gate;

[0032] (6) Transfer two-dimensional material graphene to form graphene channel regions;

[0033] (7) After photolithography and etching, metal contacts are deposited and annealed to form metal contacts for the source and drain.

[0034] (8) After photolithography and etching, the gate oxide layer and gate material are deposited. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the high-gain heterogeneous amplifier structure of the present invention.

[0036] Figure 2 This is a flowchart illustrating the fabrication process of the high-gain heterogeneous amplifier of the present invention.

[0037] Figure 3 This is the structure of a semiconductor transistor according to Embodiment 2 of the present invention. Detailed Implementation

[0038] Based on the same working principle, the structure of the device can be different, and the specific implementation methods are reflected in different embodiments.

[0039] Example 1 (corresponding) Figure 1 Device structure and Figure 2 (The process flow).

[0040] (1) such as Figure 2 As shown in (a), this is a silicon wafer on an insulating layer; its substrate is typically weakly p-type doped silicon with a doping concentration of 10. 15 cm -2 Up to 10 19 cm -2 Between; the substrate can also be germanium silicon, gallium nitride, or indium gallium arsenide, etc.;

[0041] Its buried layer is generally silicon dioxide, with a thickness between 5nm and 500nm;

[0042] The upper channel is typically made of materials such as silicon, germanium silicon, gallium nitride, or indium gallium arsenide; the thickness is between 5nm and 100nm.

[0043] (2) The window for the STI isolation layer on the substrate sidewall is photolithographically opened, and then the buried oxide layer is etched to the substrate silicon using photoresist as a mask to form a trench structure. Silicon dioxide is then deposited to fill the trench. This oxide isolation layer can be formed using chemical vapor deposition (CVD), such as... Figure 2 (b).

[0044] (3) Photolithography is performed to open the window of the substrate contact area, and then photoresist is used as a mask to etch the buried oxide layer down to the substrate silicon. Figure 2 (c) Etching can be done using either dry or wet methods: dry etching generally uses fluorine-based or halogen gases, such as SF6, Cl2, etc.; while wet etching generally uses strong acid or strong alkali solutions such as HF, NH4HF2, etc.

[0045] (4) Deposit a gate oxide layer, such as Figure 2 As shown in (d); the gate oxide layer is generally silicon dioxide (SiO2), but can also be silicon nitride, aluminum oxide, or hafnium oxide, etc.; the thickness is generally between 1 nm and 30 nm; the deposition method is atomic layer deposition; the positive gate is generally polysilicon or metal, or a composite layer of polysilicon and metal, and its thickness can be 10 nm to 500 nm; photolithography is used to open the window of the positive gate pattern, and then photoresist is used as a mask to etch the positive gate to form the gate pattern, such as Figure 2 As shown in (e), etching can be performed using either dry or wet methods. Dry etching generally uses fluorine-based or halogen gases, such as SF6, CHF3, HBr, or Cl2, while wet etching generally uses solutions such as TMAH and KOH.

[0046] (5) Self-aligned ion implantation is performed using a gate-based self-aligned mask to form low-drain doped regions on both sides of the channel, such as... Figure 2 (f) shows that arsenic or phosphorus is typically used for ion implantation, with a dose of 10. 13 cm -2 Up to 10 16 cm -2 The energy ranges from 1 keV to 100 keV, and the ion activation annealing temperature is generally between 900 degrees and 1200 degrees, with a time of 1 microsecond to 10 seconds.

[0047] (6) Deposit a gate sidewall material, such as commonly used silicon nitride, silicon dioxide, or low dielectric constant dielectrics such as SiOCN and SiBCN; deposition can be performed using processes such as chemical vapor deposition and atomic layer deposition; then etching is performed to form a structure such as Figure 2 (g) shows the gate sidewall; etching generally uses reactive ion etching with vertical orientation, while dry etching generally uses fluorine-based gases, such as SF6, CHF3 or CH3F.

[0048] (7) Photolithography is used to deposit metal contacts and annealing is performed to form the source and drain metal contact electrodes, such as... Figure 2 (h); Commonly used metals are nickel, titanium, or metal silicides, such as nickel silicon, titanium silicon, etc., and the annealing temperature is between 300 degrees and 900 degrees.

[0049] (8) Transferring two-dimensional graphene materials to form graphene channel regions, typically monolayer graphene; such as Figure 2 (i).

[0050] (9) After photolithography, metal contacts are deposited and annealed to form the source and drain metal contacts as follows: Figure 2 (j) Commonly used metals are nickel, titanium or metal silicides, such as nickel silicon, titanium silicon, etc., and the annealing temperature is between 300 degrees and 900 degrees; the active region of graphene is formed by photolithography.

[0051] (10) After photolithography, a gate oxide layer is deposited as follows: Figure 2 (k); typically hafnium oxide or aluminum oxide; thickness between 2 nm and 20 nm.

[0052] (11) Photolithography is performed to open the gate contact area, metal is deposited, and annealing is carried out to form a structure as shown in the figure. Figure 2 (l) shows the electrode; the commonly used metals are aluminum, nickel, titanium or metal silicides, such as nickel silicon, titanium silicon, etc., and the annealing temperature is between 300 degrees and 900 degrees.

[0053] Figure 3 This is an embodiment of the structure of the novel semiconductor transistor of the present invention.

[0054] Example 2 is similar to Example 1, except that Example 2 uses a p-type device, while Example 1 uses an n-type device; the substrate and low-drain doped region are n-type, while the channel is p-type doped. This structure can be achieved simply by replacing the substrate with an n-type substrate, changing the channel doping to p-type, and replacing the ion implantation of the LDD with n-type. Arsenic or phosphorus is typically used for ion implantation, with a dose of 10-1. 12 cm -2 Up to 10 14 cm -2 The energy ranges from 1 keV to 50 keV. The transferred graphene material does not require annealing and is a p-type device.

[0055] References

[0056] [1] Maryam Sajedin 1,2,*, I.T.E. Elfergani 1,* , Jonathan Rodriguez1,2, Raed Abd-Alhameed 3 and Monica Fernandez Barciela 4.“A Survey on RF andMicrowave Doherty Power Amplifier for Mobile Handset Applications”,inelectronics , 25 June 2019,doi: 10.3390 / electronics8060717.

[0057] [2]Zainal Arif Burhanudin ,” Assessing the Figures of Merit ofGraphene-Based Radio Frequency Electronics: A Review of GFET in RFTechnology”,in IEEE Access, January 31, 2022, doi :10.1109 / ACCESS.2022.314783[3] M. Iannazzo, V. Lo Muzzo, S. Rodriguez, A. Rusu, M. Lemme, and E.Alarcon, “Design Exploration of Graphene-FET based Ring Oscillator Circuits :A Test- Bench for Large-Signal Compact Models,” in IEEE InternationalSymposium on Circuits And Systems (ISCAS), 2015, pp. 2716–2719.

[0058] [4] S. Kataria, S. Wagner, J. Ruhkopf, A. Gahoi, H. Pandey, R.Bornemann, S. Vaziri, A. D. Smith, M. Ostling, and M. C. Lemme, “Chemicalvapor deposited graphene: From synthesis to applications,” Phys. StatusSolidi, vol. 211, no. 11, pp. 2439–2449, Nov. 2014.

[0059] [5] N. Petrone, T. Chari, I. Meric, L. Wang, K. L. Shepard, and J.Hone, “Flexible Graphene Field-Effect Transistors Encapsulated in Hexago

[0060] [6] K. Cheng and A. Khakifirooz, "Fully depleted SOI (FDSOI)technology. " in Science China Information Sciences, vol. 59, pp. 61402:1-061402:15, Apr.il 2016, doi: 10.1007 / s11432-016-5561-5。

Claims

1. A high-gain heteroamplifier based on SOI - graphene common-source common-gate circuit, characterized in that, By introducing an SOI substrate, NLDD doping forms an n-type channel and an SOI-graphene heterojunction. The input gate of the device is connected to graphene, utilizing the high gm of graphene. The output is connected to the high output resistance of the SOI transistor to improve output resistance, voltage, and power gain. Specifically, this includes: Substrate (1); Buried oxide layer (2) formed on substrate (1); The drain (6), top channel region (3), source (7), and graphene channel region (5) are arranged from left to right on the buried oxide layer (2). Shallow trench isolation (4) between the source electrode (7) and the graphene channel region (5), the shallow trench isolation (4) extending through the buried oxide layer (2) and the substrate (1); A first gate oxide layer (11), a first gate (15), and a first gate metal contact (17) are sequentially formed on the top channel region (3). A second gate oxide layer (12), a second gate (16), and a second gate metal contact (18) are sequentially formed on the graphene channel region (5). First gate sidewall (13) and second gate sidewall (14) are formed on both sides of the first gate oxide layer (11), the first gate (15) and the first gate metal contact (17). A drain metal contact (8) is formed on the drain (6) and outside the first gate sidewall (13). A common metal contact (9) is formed on the source (7) and the shallow trench isolation (4) between the second gate sidewall (14) and the second gate oxide layer (12). The source metal contact (10) is formed on the graphene channel region (5) and outside the second gate oxide layer (12).

2. The high-gain heterogenous amplifier of claim 1, wherein, The substrate (1) is a semiconductor, selected from silicon; the top channel region (3) is also a semiconductor, selected from silicon.

3. The high-gain heterogenous amplifier of claim 1, wherein, The buried oxide layer (2) is a silicon dioxide insulating material with a thickness between 5 nm and 500 nm.

4. The high-gain heterogenous amplifier of claim 1, wherein, The shallow trench isolation (4) is used to isolate silicon, and the shallow trench isolation (4) is filled with silicon nitride or silicon dioxide.

5. The high-gain heterogenous amplifier of claim 1, wherein, The drain (6) and source (7) are N-type ion implants, the implanted ions being phosphorus or arsenic, the implanted ion dose being between 10 13 cm -2 and 10 16 cm -2 .

6. The high-gain heterogenous amplifier of claim 1, wherein, The first gate oxide layer (11) is made of hafnium oxide; the second gate oxide layer (12) is made of hafnium oxide or aluminum oxide.

7. The high-gain heterogenous amplifier of claim 1, wherein, The device structure is symmetrical. Both the SOI device and the graphene device are n-type, that is, one is an n-type doped SOI device and the other is an n-type graphene device.

8. The high-gain heterogenous amplifier of claim 1, wherein, The metal contact area is formed in a self-symmetrical manner by using the first gate sidewall (13) and the second gate sidewall (14) on both sides as a mask.

9. A method of manufacturing a high-gain heteroamplifier according to one of claims 1 to 8, characterized in that, The specific steps are as follows: (1) On the initial insulating layer, a silicon substrate is photolithographically etched and grooved. Then, a silicon dioxide isolation sidewall STI structure is formed by chemical vapor deposition (CVD) to fill the groove. The STI structure isolates SOI devices and graphene devices. (2) The initial substrate and positive gate pattern are formed by photolithography and etching, including substrate (1), buried oxide layer (2) and top channel region (3), and then gate oxide layer and positive gate material are deposited; (3) Using the gate as a mask, ion implantation is performed in a self-aligned manner to form a low-drain doped region; (4) Deposit a layer of sidewall dielectric on the gate and perform dry anisotropic etching to form the gate sidewall; (5) Using the gate and gate sidewall as masks, deposit metal contacts and anneal them to form metal contacts for the source, drain and gate; (6) transferring the two-dimensional material graphene to form a graphene channel region; (7) after photoetching and etching, depositing metal contacts and annealing to form source and drain metal contacts; (8) after photoetching and etching, depositing a gate oxide layer and a gate material.

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