A clock generation circuit

Abstract

The present invention belongs to the technical field of integrated circuits, and specifically relates to a clock generation circuit. The clock generation circuit of the present invention does not require an external reference voltage to be provided as in the traditional structure. The reference voltage is determined inside the comparator, and the reference voltage is independent of temperature, enhancing the temperature stability and accuracy of the output clock frequency; embedding the reference voltage in the comparator structure greatly simplifies the circuit structure and optimizes the area and power consumption; therefore, the clock generation circuit of the present invention has the characteristics of simple structure, low power consumption, high accuracy, strong independence, and high reliability.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit technology, and particularly relates to a clock generation circuit. Background Art

[0002] With the continuous development of integrated circuit technology, clock signals are increasingly widely used in many chips. For example, in analog-to-digital converters (ADCs), clock signals are used to control the on and off of switches, thereby realizing the sampling and amplification functions of analog signals. The frequency of the clock signal determines the speed of sampling the analog signal. Therefore, the clock circuit will directly affect the overall performance of the circuit.

[0003] Refer to Figure 1 , which shows a schematic structural diagram of a conventional on-chip clock generation circuit, specifically including two comparators COMP1 and COMP2, current source I N and current source I P , two switches S1 and S2, a charging capacitor C, and an RS flip-flop. Figure 1 The working mode of the shown conventional on-chip clock generation circuit is as follows: The opening and closing of switches S1 and S2 are controlled by the output signals CLK and CLK_B of the RS flip-flop, and the charging capacitor C is repeatedly charged and discharged by current source I N and current source I P . The voltage VC on the charging capacitor C is respectively compared with the reference voltages VH and VL of comparators COMP1 and COMP2 to realize the flip of the clock.

[0004] Figure 1 The working process of the shown conventional on-chip clock generation circuit is as follows:

[0005] In the initial state, the charge on capacitor C is 0, the output of comparator COMP1 is low level, the output of comparator COMP2 is high level, the output signal CLK of the RS flip-flop is low level, the output signal CLK_B signal is high level, switch S1 is turned on, switch S2 is turned off, and current source I P charges capacitor C. When the voltage VC on capacitor C rises above the reference voltage VH at the inverting terminal of comparator COMP1, the output signal of comparator COMP1 is high level, the RS flip-flop is in the set state, the output signal CLK becomes high level, and the output signal CLK_B becomes low level. At this time, switch S1 is turned off, switch S2 is turned on, and current source I NDischarge the capacitor C. The potential VC on the capacitor starts to drop. When the potential VC drops below the reference voltage VL connected to the non-inverting terminal of the comparator COMP2, the comparator COMP2 outputs a high level. The RS flip-flop is in the reset state, the output signal CLK becomes low level, and CLK_B becomes high level. Thereafter, the circuit continuously repeats the above process, and the voltage VC on the capacitor C repeatedly oscillates back and forth between VH and VL, and the RS flip-flop generates a clock signal.

[0006] Figure 1 A conventional on-chip clock generation circuit as shown has three main problems: First, using a dual comparator, the structure is relatively complex, and it will bring relatively large power consumption loss and area loss; Second, the mismatch between the two comparators will have an adverse effect on the clock frequency stability; Third, due to the presence of the two comparators, two reference voltages are required for voltage comparison, which increases the complexity of the circuit, and the clock kickback noise will interfere with the reference voltage, which may affect the normal operation of other circuit modules that require reference voltage supply. Therefore, there is still room for continuous improvement and optimization in the structure, power consumption, stability, independence and reliability of the conventional on-chip clock generation circuit. Summary of the Invention

[0007] In view of the problems existing in the circuit structure complexity, independence and stability of the above-mentioned conventional on-chip clock generation circuit, the present invention proposes a clock generation circuit.

[0008] The technical solution of the present invention is:

[0009] A clock generation circuit includes a start-up circuit, a charge and discharge circuit, a comparator circuit with a built-in reference voltage, and a timing logic circuit;

[0010] The start-up circuit includes a first inverter INV1, a second inverter INV2, a second NMOS transistor MN2, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5;

[0011] The input terminal of the first inverter INV1 is connected to the external input enable signal EN, and the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2 and the gate of the second NMOS transistor MN2; the output terminal of the second inverter INV2 is respectively connected to the gate of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP5; the source electrodes of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are connected to the power supply;

[0012] The timing logic circuit includes a third inverter INV3, a fourth inverter INV4, and a D flip-flop DFF1;

[0013] The output terminal of the third inverter INV3 is connected to the input terminal of the fourth inverter INV4. The output terminal of the fourth inverter INV4 is connected to the CK terminal of the D flip-flop DFF1. The D terminal of the D flip-flop DFF1 and terminal are connected, and the Q terminal of the D flip-flop DFF1 outputs a clock signal;

[0014] The comparator circuit with a built-in reference voltage includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NPN transistor Q1, a second NPN transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3;

[0015] The source electrode of the first PMOS transistor MP1 is connected to the power supply. Its gate electrode is connected to the drain electrode of the fourth PMOS transistor MP4, the gate and drain electrodes of the second PMOS transistor MP2, and the collector of the first NPN transistor Q1. The drain electrode of the first PMOS transistor MP1 is connected to the collector of the second NPN transistor Q2 and the gate of the third PMOS transistor MP3. The source electrode of the second PMOS transistor MP2 is connected to the power supply. The bases of the first NPN transistor Q1 and the second NPN transistor Q2 are connected and connected to the drain electrode of the second NMOS transistor MN2. The emitter of the first NPN transistor Q1 is grounded through the first resistor R1 and the third resistor R3 in sequence. The emitter of the second NPN transistor Q2 is grounded through the third resistor R3. The source electrode of the third PMOS transistor MP3 is connected to the power supply, its drain electrode is connected to one end of the second resistor R2 and the input terminal of the third inverter INV3, and the other end of the second resistor R2 is grounded;

[0016] The charge and discharge circuit includes a current source I cst 、a first NMOS transistor MN1, and a capacitor C;

[0017] The gate of the first NMOS transistor MN1 is connected to the output terminal of the fourth inverter INV4. The drain of the first NMOS transistor MN1 is connected to one end of the current source I cst 、one end of the capacitor C, and the drain of the second NMOS transistor MN2. The source of the first NMOS transistor MN1 is grounded. The other end of the current source I cst is connected to the power supply, and the other end of the capacitor C is grounded.

[0018] Further, the ratio of the number of the first NPN transistor Q1 to the second NPN transistor Q2 is 8:1.

[0019] Further, the capacitor C is a MIM capacitor or a MOM capacitor.

[0020] Further, the first resistor R1 is a P-type Poly resistor or a well resistor, the second resistor R2 is a P-type Poly resistor or a well resistor, the third resistor R3 is a P-type Poly resistor or a well resistor, the fourth resistor R4 is a P-type Poly resistor or a well resistor, and the resistors R1 and R3 need to be of the same type.

[0021] Further, the substrates of all NMOS transistors are grounded, and the substrates of all PMOS transistors are connected to the power supply.

[0022] Regarding the current source I in the clock generation circuit cst which needs an external bias circuit to implement, resulting in the problem of increased circuit complexity. One solution is to replace the fourth resistor R4 with the current source I. One end of the fourth resistor R4 is connected to one end of the capacitor C, and the other end of the fourth resistor R4 is connected to the output terminal of the third inverter INV3. cst Replace the fourth resistor R4. One end of the fourth resistor R4 is connected to one end of the capacitor C, and the other end of the fourth resistor R4 is connected to the output terminal of the third inverter INV3.

[0023] The beneficial effects of the present invention are that the clock generation circuit of the present invention does not require an external input reference voltage. The reference voltage is determined by the internal structure of the comparator, with a simple structure, small area, low power consumption, high reliability, and strong independence. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of the structure of a conventional clock generation circuit.

[0025] Figure 2 is a schematic diagram of the circuit structure of Embodiment 1 of the present invention.

[0026] Figure 3 is a circuit simulation result diagram of Embodiment 1 of the present invention.

[0027] Figure 4 is a schematic diagram of the circuit structure of Embodiment 2 of the present invention.

[0028] Figure 5 is a circuit simulation result diagram of Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] The technical principles and solutions of the present invention will be described in detail below in conjunction with the drawings and embodiments:

[0030] Embodiment 1

[0031] As Figure 2 shown, a clock generation circuit in Embodiment 1 of the present invention includes a startup circuit, a comparator circuit with a built-in reference voltage, a charge and discharge circuit, and a timing logic circuit.

[0032] The startup circuit in the present invention includes a first inverter INV1, a second inverter INV2, a second NMOS transistor MN2, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5. When the external input enable signal EN is at a low level, through the first inverter INV1 and the second inverter INV2 respectively, the second NMOS transistor MN2, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are turned on, connecting the common terminal VC of the first NMOS transistor MN1, the capacitor C, the first NPN transistor Q1, and the second NPN transistor Q2 to the reference ground GND. Therefore, VC is at zero potential, and at this time, no charge is stored on the capacitor C. At the same time, the gates of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are connected to the power supply VDD, making MP1, MP2, and MP3 in the cut-off region, and the entire circuit is in the off state. The first NPN transistor Q1 and the second NPN transistor Q2 are not turned on and are in the cut-off state. Therefore, VO1 is at a high potential. When VO1 is at a high potential, the third PMOS transistor MP3 is not turned on, and the third PMOS transistor MP3 and the second resistor R2 form a common-source inverter amplifier with a resistive load. Therefore, the signal VOUT is at a low potential. The signal VOUT passes through two inversions of the third inverter INV3 and the fourth inverter INV4, making V ctrl at a low potential. When V ctrl is at a low potential, the first NMOS transistor MN1 is not turned on.

[0033] When the external input enable signal EN is at a high level, the second NMOS transistor MN2, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are turned off and are in the cut-off region. At this time, the current source I cst starts to charge the upper plate of the capacitor C, and the charge stored on the capacitor C gradually increases, and the voltage value of VC gradually rises. As the voltage value of VC keeps rising, the base voltages of the first NPN transistor Q1 and the second NPN transistor Q2 increase. The emitter junction areas of the first NPN transistor Q1 and the second NPN transistor Q2 are in a ratio of 8:1. Therefore, g m1 = 8g m2 , and the equivalent transconductances of the first NPN transistor Q1 and the second NPN transistor Q2 can be respectively expressed as:

[0034]

[0035]

[0036] Usually, g m2 R3 >> 1. Therefore, G m2 > G m1 , and the collector current I C2 flowing through the second NPN transistor Q2 changes more significantly with the change of the base voltage VC than the collector current I C1 of the first NPN transistor Q1. Therefore, at the same VC, IC2 >I C1 The width-to-length ratio of the second PMOS transistor MP2 and the first PMOS transistor MP1 is 1:1, forming a 1:1 current mirror. Therefore, the drain current I D2 of the second PMOS transistor MP2 and the drain current I D1 of the first PMOS transistor are equal, resulting in I D1 = I D2 = I C1 Therefore, there is a gate voltage of ΔI current with a value of I C2 - I C1 extracted at the gate of the third PMOS transistor MP3, causing the voltage VO1 to decrease.

[0037] When the voltage of VC rises to a certain value, the first NPN transistor Q1, the second NPN transistor Q2, the first resistor R1, the third resistor R3, the first PMOS transistor MP1, and the second PMOS transistor MP2 form a comparator structure with a fixed flip threshold, and its threshold voltage can be expressed as:

[0038]

[0039] The collector current I C of the NPN transistor can be expressed as where I0 is the reverse saturation current, which is positively correlated with the emitter junction area. The emitter junction voltage of the NPN transistor can be obtained as Since the ratio of the emitter junction areas of the first NPN transistor Q1 and the second NPN transistor Q2 is 8:1, therefore, at the same collector current I C , the reverse saturation current I 01 > I 02 , resulting in Therefore, ΔV BE(Q1、Q2) has a positive temperature coefficient, and its voltage value increases with the increase of temperature; while V BE,Q2 is a negative temperature coefficient voltage, and its voltage value decreases with the increase of temperature; by setting the resistors R1 and R3 and adjusting the proportional relationship between ΔV BE(Q1、Q2) and V BE,Q2 , a comparator fixed flip threshold voltage V ref that does not change with temperature can be obtained.

[0040] As the current source I cst continuously charges the capacitor C, the voltage of VC increases continuously, and the voltage of VO1 decreases. Since the third PMOS transistor MP3 and the second resistor R2 form a common-source amplifier with a resistive load, the decrease in the voltage of VO1 causes the voltage of VOUT to increase. When the voltage of VC exceeds the comparator fixed flip threshold voltage V refWhen the VOUT voltage is high, the VOUT voltage is high. Through the double flipping of the third inverter INV3 and the fourth inverter INV4, Vctrl is high. Since the gate of the first NMOS tube MN1 is connected to Vctrl, the first NMOS tube MN1 is turned on, so that the charge on the capacitor C is instantly discharged to the reference ground GND, and the VC voltage becomes 0. At this time, VC <Vref,VO1为高电位,通过第三PMOS管MP3和第二电阻R2形成的共源反相放大器,使得VOUT为低电位,此时Vctrl也为低电位,因此第一NMOS管MN1关断。电容C与参考地GND断开连接,电流源I cst The capacitor C continues to be charged, and the VC voltage continues to increase. Repeating the above process, the VC voltage shows a stable periodic signal, and then a stable output pulse wave Vctrl is obtained. The two ends are connected, so when the stable pulse wave Vctrl signal rises, the output signal is flipped to obtain a stable clock output signal CLK.

[0041] In this example, the period of the clock output signal CLK is:

[0042]

[0043] The frequency is:

[0044]

[0045] It can be seen that the current source I cst and capacitor C, a fixed output clock frequency can be obtained, and the current source I cst As a current source, due to the capacitance C and the reference voltage V ref It has good temperature characteristics and the temperature stability of the clock frequency is good.

[0046] Attached Figure 3 The simulation result diagram of the clock generation circuit in Example 1 is shown in FIG. cst Charging, VC voltage rises, reaching the comparator's built-in reference voltage V ref The charge is discharged to generate a VC signal with a periodic rise and fall. The Vctrl signal is a stable pulse wave signal. Through the D flip-flop DFF1, a stable clock output signal CLK is obtained. The clock period is 5μs and the cycle is 200KHz.

[0047] Example 2

[0048] like Figure 4 As shown, a clock generating circuit in Embodiment 2 of the present invention includes a starting circuit, a comparator circuit with a built-in reference voltage, a charging and discharging circuit, and a sequential logic circuit.

[0049] The startup circuit in the present invention includes a first inverter INV1, a second inverter INV2, a second NMOS transistor MN2, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5. When the external input enable signal EN is at a low level, through the inversion of the first inverter INV1 and the second inverter INV2 respectively, the second NMOS transistor MN2, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are turned on, connecting the common terminal VC of the first NMOS transistor MN1, the capacitor C, the first NPN transistor Q1, and the second NPN transistor Q2 to the reference ground GND. At this time, no charge is stored on the capacitor C, so VC is at zero potential. At the same time, the gates of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are connected to the power supply VDD, making MP1, MP2, and MP3 in the cut-off region, and the entire circuit is in the off state. The first NPN transistor Q1 and the second NPN transistor Q2 are not conducting and are in the cut-off state, so VO1 is at a high level. When VO1 is at a high level, the third PMOS transistor MP3 is not conducting, and the third PMOS transistor MP3 and the second resistor R2 form a common-source inverter amplifier with a resistive load, so the signal VOUT is at a low level. The signal VOUT is inverted twice through the third inverter INV3 and the fourth inverter INV4, making Vctrl at a low level. When Vctrl is at a low level, the first NMOS transistor MN1 is not conducting.

[0050] Since the current source I used in Embodiment 1 cst requires an external biasing circuit to be realized, which increases the complexity of the circuit. Therefore, in Embodiment 2, a fourth resistor R4 is used to replace the current source I cst and the other end of the resistor R4 is connected to the output terminal of the third inverter INV3, which can greatly simplify the circuit and enhance the independence of the circuit.

[0051] When the external input enable signal EN is at a high level, the second NMOS transistor MN2, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are turned off and are in the cut-off region. At this time, the output of the third inverter INV3 is at a high level VDD, and the fourth resistor R4 and the capacitor C form an RC charging circuit, starting to charge the upper plate of the capacitor C. The charge stored on the capacitor C gradually increases, and the voltage value of VC gradually rises.

[0052] As the VC voltage value continuously increases, the base voltages of the first NPN transistor Q1 and the second NPN transistor Q2 increase, and they are in the conducting state. The width-to-length ratios of the second PMOS transistor MP2 and the first PMOS transistor MP1 are 1:1, forming a 1:1 current mirror. When the VC voltage rises to a certain voltage value, the first NPN transistor Q1, the second NPN transistor Q2, the first resistor R1, the third resistor R3, the first PMOS transistor MP1, and the second PMOS transistor MP2 constitute a comparator structure with a fixed flip threshold, and its threshold voltage can be expressed as:

[0053]

[0054] The collector current I of the NPN transistor C can be expressed as where I0 is the reverse saturation current, which is positively correlated with the emitter junction area. The emitter junction voltage of the NPN transistor can be obtained as Since the emitter junction area ratio of the first NPN transistor Q1 and the second NPN transistor Q2 is 8:1, therefore, at the same collector current I C the reverse saturation current I 01 >I 02 , and we get Therefore, △V BE(Q1、Q2) has a positive temperature coefficient, and its voltage value increases with the increase of temperature; while V BE,Q2 is a negative temperature coefficient voltage, and its voltage value decreases with the increase of temperature; by setting the resistors R1 and R3 to adjust the proportional relationship between △V BE(Q1、Q2) and V BE,Q2 , a comparator fixed flip threshold voltage V ref that does not change with temperature can be obtained.

[0055] The change of the voltage VC on the upper plate of the capacitor C with time can be expressed as:

[0056] VC = VDD * [1 - exp(-t / τ)]

[0057] τ = R4C

[0058] where τ is the time constant of the RC charging circuit formed by the fourth resistor R4 and the capacitor C.

[0059] As the RC charging circuit continuously charges the capacitor C, the voltage VC increases continuously and the voltage VO1 decreases. Since the third PMOS transistor MP3 and the second resistor R2 form a common-source inverting amplifier with a resistive load, when the voltage VO1 decreases, the voltage VOUT increases. When the voltage VC exceeds the fixed flip threshold voltage Vref of the comparator, the voltage VOUT is at a high level. Through two inversions by the third inverter INV3 and the fourth inverter INV4, Vctrl is at a high level. Since the gate of the first NMOS transistor MN1 is connected to Vctrl, the first NMOS transistor MN1 conducts, causing the charge on the capacitor C to be instantaneously discharged to the reference ground GND, and the voltage VC becomes 0. At this time, VC < Vref, VO1 is at a high level. Through the common-source inverting amplifier formed by the third PMOS transistor MP3 and the second resistor R2, VOUT is at a low level. At this time, Vctrl is also at a low level, so the first NMOS transistor MN1 is turned off. The capacitor C is disconnected from the reference ground GND, and the RC charging circuit formed by the fourth resistor R4 and the capacitor C continues to charge the capacitor C, and the voltage VC increases continuously. Repeating the above process, a stable output pulse wave Vctrl is obtained. Since the D terminal of the D flip-flop DFF1 is connected to the terminal, at the rising edge of the stable pulse wave Vctrl signal, the output is inverted to obtain a stable clock output signal CLK.

[0060] In this example, the period of the clock output signal CLK is:

[0061]

[0062] The frequency is:

[0063]

[0064] Attached Figure 5 is the simulation result of the clock generation circuit in Embodiment 2, where the capacitor C is continuously charged and discharged. When the voltage VC exceeds the reference voltage, the output of the comparator is inverted to obtain a stable pulse wave signal Vctrl, and a stable clock output signal CLK is obtained through the D flip-flop DFF1. The clock period is 2 μs and the frequency is 500 KHz.

[0065] In summary, the clock generation circuit has the following advantages:

[0066] The clock generation circuit of the present invention does not require an externally provided reference voltage as in the traditional structure. The reference voltage is determined inside the comparator and is independent of temperature, enhancing the temperature stability and accuracy of the output clock frequency. Embedding the reference voltage in the comparator structure greatly simplifies the circuit structure and optimizes the area and power consumption. The circuit structure in Embodiment 2 does not even require an externally provided current source, making the circuit even more simplified and independent. Therefore, the clock generation circuit of the present invention has the characteristics of simple structure, low power consumption, high accuracy, strong independence, and high reliability.

Claims

1. A clock generation circuit, characterized in that, It includes a startup circuit, a charge-discharge circuit, a comparator circuit with a built-in reference voltage, and a timing logic circuit; The startup circuit includes a first inverter INV1, a second inverter INV2, a second NMOS transistor MN2, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5; The input terminal of the first inverter INV1 is connected to an external input enable signal EN, and the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2 and the gate of the second NMOS transistor MN2; the output terminal of the second inverter INV2 is respectively connected to the gate of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP5; the source terminals of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are connected to the power supply; The timing logic circuit includes a third inverter INV3, a fourth inverter INV4, and a D flip-flop DFF1; The output terminal of the third inverter INV3 is connected to the input terminal of the fourth inverter INV4, and the output terminal of the fourth inverter INV4 is connected to the CK terminal of the D flip-flop DFF1. The D terminal of the D flip-flop DFF1 and terminal are connected, and the Q terminal of the D flip-flop DFF1 outputs a clock signal; The comparator circuit with a built-in reference voltage includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NPN transistor Q1, a second NPN transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3; The source terminal of the first PMOS transistor MP1 is connected to the power supply, and its gate is connected to the drain of the fourth PMOS transistor MP4, the gate and drain of the second PMOS transistor MP2, and the collector of the first NPN transistor Q1. The drain of the first PMOS transistor MP1 is connected to the collector of the second NPN transistor Q2 and the gate of the third PMOS transistor MP3; the source terminal of the second PMOS transistor MP2 is connected to the power supply; the bases of the first NPN transistor Q1 and the second NPN transistor Q2 are connected together and connected to the drain of the second NMOS transistor MN2; the emitter of the first NPN transistor Q1 is grounded through the first resistor R1 and the third resistor R3 in sequence; the emitter of the second NPN transistor Q2 is grounded through the third resistor R3; the source terminal of the third PMOS transistor MP3 is connected to the power supply, and its drain is connected to one end of the second resistor R2 and the input terminal of the third inverter INV3, and the other end of the second resistor R2 is grounded; The charge and discharge circuit includes a current source I cst , a first NMOS transistor MN1, and a capacitor C; The gate of the first NMOS transistor MN1 is connected to the output terminal of the fourth inverter INV4, and the drain of the first NMOS transistor MN1 is connected to one end of the current source I cst , one end of the capacitor C, and the drain of the second NMOS transistor MN2. The source of the first NMOS transistor MN1 is grounded; the other end of the current source I cst is connected to the power supply, and the other end of the capacitor C is grounded.

2. The clock generation circuit according to claim 1, characterized in that, The emitter junction area ratio of the first NPN transistor Q1 to the second NPN transistor Q2 is 8:

1.

3. A clock generation circuit according to claim 1, characterized in that, The capacitor C is a MIM capacitor or a MOM capacitor.

4. A clock generation circuit according to claim 1, characterized in that The first resistor R1 is a P-type Poly resistor or a well resistor, the second resistor R2 is a P-type Poly resistor or a well resistor, the third resistor R3 is a P-type Poly resistor or a well resistor, the fourth resistor R4 is a P-type Poly resistor or a well resistor, and the resistors R1 and R3 need to be of the same type.

5. A clock generation circuit according to claim 1, characterized in that The substrates of all NMOS transistors are grounded, and the substrates of all PMOS transistors are connected to the power supply.

6. A clock generation circuit according to claim 1, wherein Replace the current source I cst with a fourth resistor R4, one end of the fourth resistor R4 is connected to one end of the capacitor C, and the other end of the fourth resistor R4 is connected to the output terminal of the third inverter INV3.

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