Video processing apparatus, method and device

Abstract

The present disclosure provides a video processing apparatus, method and device. The apparatus includes: a pixel merging unit, a caching unit and a video processing unit; wherein, the pixel merging unit is configured to perform pixel merging on the pixels included in each of a plurality of pixel rows to obtain pixel blocks of the respective pixel rows; the caching unit is configured to cache the pixel blocks of the respective pixel rows among the plurality of pixel rows except the last pixel row; the video processing unit is configured to, when receiving the pixel block of the last pixel row, obtain the pixel blocks of the respective other pixel rows from the caching unit to obtain an image block, and sequentially process each pixel block in the image block. A video processing apparatus, method and device provided by the present disclosure are used to save the logic resources of an IC chip.

Description

Technical Field

[0001] The present disclosure relates to the technical fields of displays, video processing, etc., and particularly relates to a video processing apparatus, method, and device. Background Art

[0002] Currently, integrated circuit (IC) chips are usually provided in display devices such as televisions (TVs), notebook computers (NoteBooks), monitors (MNTs), etc. The IC chip is used to implement a video compression algorithm for frame overdrive. The IC chip includes a processing unit, and the processing unit includes algorithm modules. Usually, the algorithm module includes (N / M) identical algorithm sub-modules, where N is the width of an image block in the video compression algorithm, and M is the number of pixels input to the IC chip in parallel in one clock cycle. When the algorithm module receives an image block of size (N×N), it expands the image block into (N / M) data blocks of (N×M), and uses (N / M) algorithm sub-modules with exactly the same functions to process the (N / M) data blocks of (N×M) in parallel, where one algorithm sub-module processes one data block of N×M.

[0003] In the above processing unit, since the algorithm module includes multiple algorithm sub-modules with exactly the same functions, it causes waste of the logic resources of the IC chip. Summary of the Invention

[0004] The present disclosure provides a video processing apparatus, method, and device to solve the defect of waste of the logic resources of the IC chip in the prior art, and to save the logic resources of the IC chip.

[0005] In a first aspect, the present disclosure provides a video processing apparatus, including: a pixel merging unit, a buffer unit, and a video processing unit; where

[0006] The pixel merging unit is configured to perform pixel merging on the pixels included in each pixel row among multiple pixel rows to obtain pixel blocks of the multiple pixel rows, where the multiple pixel rows are multiple pixel rows of a frame of an image in a video;

[0007] The buffer unit is configured to buffer the pixel blocks of the other pixel rows except the last pixel row among the multiple pixel rows;

[0008] The video processing unit is configured to, when receiving the pixel block of the last pixel row, obtain the pixel blocks of the other pixel rows from the buffer unit to obtain an image block, and sequentially process each pixel block in the image block.

[0009] A video processing device provided according to the present disclosure, the pixel merging unit includes: a plurality of merging modules; wherein, the plurality of merging modules correspond to the plurality of pixel rows one by one;

[0010] The merging module is configured to receive a preset number of pixels for pixel merging in the corresponding pixel row, perform pixel merging on the preset number of pixels for pixel merging, and obtain a pixel block of the pixel row.

[0011] A video processing device provided according to the present disclosure, the buffer unit: includes a plurality of buffer modules; wherein, the plurality of buffer modules correspond to the other pixel rows one by one;

[0012] The buffer module is configured to buffer the pixel block of one pixel row.

[0013] A video processing device provided according to the present disclosure, the video processing unit is specifically configured to:

[0014] In the case of receiving the pixel block of the last pixel row, obtain the pixel blocks of the other pixel rows from the buffer unit, so as to obtain the image block within one clock cycle.

[0015] A video processing device provided according to the present disclosure, the video processing unit is specifically configured to:

[0016] Within the first number of clock cycles, process each pixel block of the image block in sequence, where the first number is equal to the ratio of the preset number of pixels for pixel merging to the preset number of pixels received.

[0017] A video processing device provided according to the present disclosure, the video processing unit includes an algorithm module;

[0018] The algorithm module is configured to process each pixel block of the image block in sequence within the first number of clock cycles.

[0019] In a second aspect, the present disclosure further provides a display device, including the video processing device according to any one of the first aspect.

[0020] In a third aspect, the present disclosure further provides a video processing method, including:

[0021] Perform pixel merging on the pixels included in each pixel row of a plurality of pixel rows to obtain the pixel blocks of the plurality of pixel rows, where the plurality of pixel rows are the plurality of pixel rows of one frame of image in the video;

[0022] Buffer the pixel blocks of the other pixel rows except the last pixel row among the plurality of pixel rows;

[0023] When the pixel block of the last pixel row is received, obtain the pixel blocks of the other pixel rows cached to obtain an image block, and process each pixel block in the image block in sequence.

[0024] According to a video processing method provided by the present disclosure, pixel merging is performed on the pixels included in each pixel row among a plurality of pixel rows to obtain the pixel blocks of the plurality of pixel rows respectively, including:

[0025] Receive a preset number of pixels for pixel merging in the corresponding pixel row, and perform pixel merging on the preset number of pixels to obtain the pixel block of the pixel row.

[0026] According to a video processing method provided by the present disclosure, obtain the pixel blocks of the other pixel rows cached to obtain an image block, including:

[0027] In the case of receiving the pixel block of the last pixel row, obtain the pixel blocks of the other pixel rows cached to obtain the image block within one clock cycle.

[0028] According to a video processing method provided by the present disclosure, process each pixel block in the image block in sequence, including:

[0029] Within the first number of clock cycles, process each pixel block of the image block in sequence, where the first number is equal to the ratio of the preset number of pixels for pixel merging to the preset number of pixels received.

[0030] In a fourth aspect, the present disclosure further provides a display device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the video processing method according to any one of the above-mentioned third aspects.

[0031] In a fifth aspect, the present disclosure further provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the video processing method according to any one of the above-mentioned third aspects.

[0032] For a video processing device, method, and device provided by the present disclosure, a pixel merging unit performs pixel merging on the pixels included in each pixel row among a plurality of pixel rows to obtain the pixel blocks of the plurality of pixel rows respectively. A caching unit caches the pixel blocks of the other pixel rows among the plurality of pixel rows except the last pixel row. When the pixel block of the last pixel row is received, a video processing unit obtains the pixel blocks of the other pixel rows from the caching unit to obtain an image block, and processes each pixel block in the image block in sequence, thereby saving the logic resources of the IC chip. Description of the Drawings

[0033] To more clearly illustrate the technical solutions in the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0034] Figure 1 is a schematic structural diagram of a video processing device in the related art provided by the present disclosure;

[0035] Figure 2 is one of the schematic structural diagrams of the video processing device provided by the present disclosure;

[0036] Figure 3 is another schematic structural diagram of the video processing device provided by the present disclosure;

[0037] Figure 4 is yet another schematic structural diagram of the video processing device provided by the present disclosure;

[0038] Figure 5 is still another schematic structural diagram of the video processing device provided by the present disclosure;

[0039] Figure 6 is a working timing diagram of the IC chip provided by the present disclosure;

[0040] Figure 7 is a schematic flowchart of the video processing method provided by the present disclosure;

[0041] Figure 8 is a schematic physical structure diagram of the display device provided by the present disclosure. Detailed implementation manners

[0042] To make the objectives, technical solutions, and advantages of the present disclosure clearer, the following will clearly and completely describe the technical solutions in the present disclosure in conjunction with the drawings in the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

[0043] In the present disclosure, the term "comprising" and its variations may refer to non - restrictive inclusion; the term "or" and its variations may refer to "and / or". In the present disclosure, terms such as "first", "second", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence. In the present disclosure, "at least one" means two or more. "And / or" describes the relationship between related objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship.

[0044] Next, in conjunction with Figure 1 , the video processing device of the prior art will be described.

[0045] Figure 1 is a schematic structural diagram of a video processing device in the related art provided by the present disclosure. As Figure 1 shown, the IC chip includes: a video processing unit and cache blocks 1 to (N - 1). Each pixel row (e.g., pixel rows L1 to L N ) caches pixels into the cache blocks corresponding to the pixel rows according to M, where M is the number of pixels input into the IC chip in parallel within one clock cycle. The video processing unit includes an algorithm module.

[0046] In the prior art, for example, in order to achieve a more efficient video processing speed, the algorithm module includes multiple algorithm sub - modules with exactly the same functions. When an image block is input into the algorithm module, multiple algorithm sub - modules process the image block in parallel, and each algorithm sub - module is only used to process a data block with a size of (N×M) in the image block.

[0047] In Figure 1 the video processing unit shown, the algorithm module includes multiple algorithm sub - modules with exactly the same functions, resulting in a relatively large amount of logic resources occupied by the video processing unit and causing waste of the logic resources of the IC chip.

[0048] It should be noted that Figure 1 it is described by taking the video processing unit including algorithm module A as an example. In actual applications, the video processing unit may not only include algorithm module A, but may also include algorithm modules B and C for implementing other functions, etc. Optionally, the number of algorithm sub - modules included in algorithm modules (A, B, and C) with different functions may be different. For example, algorithm module A includes multiple (N / M) algorithm sub - modules A1 to A N / M , algorithm module B includes multiple algorithm sub - modules B1 to B5 with exactly the same functions, and algorithm module C includes multiple algorithm sub - modules C1 to C5 with exactly the same functions.

[0049] From Figure 1As can be seen from the IC chip shown, there are many repetitive algorithm sub - modules in the video processing unit, which occupy a large amount of logic resources. If the number of algorithm modules is large, more logic resources will be occupied, further exacerbating the waste of logic resources in the IC chip.

[0050] Based on Figure 1 this, the inventor thought of setting an algorithm sub - module in the algorithm module. However, the processing speed of a single algorithm sub - module is limited, and a single algorithm sub - module cannot process an image block in a timely manner within one clock cycle, which will lead to abnormal video display. In response to this, the inventor continued to think deeply and provided a video processing device in the present disclosure. Under the condition of ensuring normal video display, the video processing unit occupies less logic resources to achieve the purpose of saving the logic resources of the IC chip. Next, the video processing device provided by the present disclosure will be described in detail with reference to specific embodiments.

[0051] Figure 2 is one of the schematic structural diagrams of the video processing device provided by the present disclosure. As Figure 2 shown, the video processing device provided in this embodiment includes: a pixel merging unit 210, a buffer unit 220, and a video processing unit 230.

[0052] The pixel merging unit 210 is used to perform pixel merging on the pixels included in each pixel row among multiple pixel rows to obtain pixel blocks of each of the multiple pixel rows. The multiple pixel rows are the multiple pixel rows of a frame of image in the video.

[0053] The number of the multiple pixel rows is, for example, N, where N is an integer greater than or equal to 1 and less than or equal to K, and K is the total number of all pixel rows in a frame of image. Optionally, N can be 16, 8, 4, or 2, etc.

[0054] The buffer unit 220 is used to buffer the pixel blocks of each of the other pixel rows except the last pixel row among the multiple pixel rows.

[0055] Optionally, the buffer unit 220 buffers the pixel blocks of pixel rows 1 to (N - 1) among the multiple pixel rows.

[0056] The video processing unit 230 is used to, when receiving the pixel block of the last pixel row, obtain the pixel blocks of the other pixel rows from the buffer unit 220 to obtain an image block, and sequentially process each pixel block in the image block.

[0057] For example, when the image block includes pixel blocks PB1, PB2, and PB3, the video processing unit 230 first processes PB1, then processes PB2, and finally processes PB3.

[0058] In Figure 2In the video processing device provided by the embodiment, the pixel merging unit 210 merges the pixels included in each pixel row to obtain pixel blocks of each pixel row. When the video processing unit 230 receives the pixel block of the last pixel row, it obtains the pixel blocks of the other pixel rows from the buffer unit 220 to obtain an image block, and sequentially processes each pixel block in the image block, which can avoid setting a large number of algorithm sub-modules with exactly the same functions in the video processing unit, reduce the logic resources occupied by the video processing unit, and save the logic resources of the IC chip.

[0059] Figure 3 It is the second structural schematic diagram of the video processing device provided by the present disclosure. On the Figure 2 basis, as Figure 3 shown, the pixel merging unit 210 includes: a plurality of merging modules; wherein, the plurality of merging modules correspond to the plurality of pixel rows one by one;

[0060] The merging module is configured to receive a preset number of pixels to be merged in the corresponding pixel row, and merge the preset number of pixels to obtain a pixel block of the pixel row.

[0061] It should be noted that Figure 3 it is exemplified by taking the plurality of pixel rows including pixel rows L1 to L N , and the plurality of merging modules including merging modules 1 to N.

[0062] Optionally, the preset number of pixels to be merged may be equal to N.

[0063] Next, taking the merging module N as an example, the working process of the merging module will be described.

[0064] In the case where the preset number of pixels to be merged is equal to N, the merging module N receives the pixels in the pixel row L N based on the preset number of pixels to be received M, and merges the N pixels every time N pixels are received to obtain the pixel block of the pixel row L N .

[0065] In Figure 3 the video processing device provided by the embodiment, the pixels in the pixel row are merged by the merging module to obtain a pixel block, and the pixel blocks of the other pixel rows except the last pixel row in the plurality of pixel rows are cached in the buffer unit. When the pixel block of the last pixel row arrives, the read enable of the buffer unit is raised for one clock, ensuring that the video processing unit can read the pixel blocks cached in the buffer unit in one clock cycle to obtain an image block, and further ensuring that the video processing unit can sequentially process the multiple pixel blocks in the image block in multiple clock cycles.

[0066] Figure 4 This is the third schematic structural diagram of the video processing device provided by the present disclosure. Among Figure 3 this, as Figure 4 shown, the buffer unit 220 includes: a plurality of buffer modules; wherein, the plurality of buffer modules correspond to other pixel rows one by one;

[0067] The buffer module is used to buffer the pixel blocks of one pixel row.

[0068] It should be noted that Figure 4 this is an exemplary illustration taking that the plurality of merging modules include merging modules 1 to N, and the plurality of buffer modules include buffer modules 1 to (N - 1) as an example.

[0069] Optionally, the data width of each buffer module is N, and the data depth of each buffer module is the width of one frame of image divided by N.

[0070] In some embodiments, the video processing unit 230 is configured to sequentially process each pixel block of the image block within a first number of clock cycles, and the first number (N / M) is equal to the ratio of the preset pixel merging number N to the preset pixel receiving number M. For example, when M = 2 and N = 8, the first number is equal to 4.

[0071] In some embodiments, the video processing unit 230 is configured to, when receiving the pixel blocks of the last pixel row, obtain the pixel blocks of the other pixel rows from the buffer unit, so as to obtain the image block within one clock cycle.

[0072] Specifically, when the video processing unit 230 receives the pixel blocks of pixel row N, it obtains the pixel blocks of the first to N - 1 pixel rows from the buffer unit 220 within one clock cycle, so as to obtain the image block within one clock cycle.

[0073] In the present disclosure, the video processing unit 230 can obtain the image block within one clock cycle, improving the acquisition speed of the image block, thereby ensuring that the image block remains unchanged within the first number of clock cycles, and further ensuring that the video processing unit 230 can sequentially process the multiple pixel blocks in the image block within the first number of clock cycles.

[0074] Figure 5 This is the fourth schematic structural diagram of the video processing device provided by the present disclosure. Among Figure 4 this, as Figure 5 shown, the video processing unit 230 includes: an algorithm module.

[0075] The algorithm module is configured to sequentially process each pixel block of the image block within the first number of clock cycles.

[0076] Optionally, the algorithm module may include X algorithm sub-modules with exactly the same functions, where X is an integer greater than or equal to 1 and less than (N / M). In the case of X = 1, the algorithm module may be referred to as an algorithm sub-module.

[0077] Optionally, in the video processing unit 230, the number of algorithm modules may be one or more. When the number of algorithm modules is multiple, the functions of the multiple algorithm modules are different.

[0078] In the case where the multiple algorithm modules include algorithm modules A, B, and C, for example, algorithm module A includes algorithm sub-modules A1 to A2 with exactly the same functions, algorithm module B includes algorithm sub-modules B1 to B3 with exactly the same functions, and algorithm module C includes algorithm sub-modules C1 to C2 with exactly the same functions.

[0079] In Figure 5 the embodiment, the algorithm module may process each pixel block of the image block in sequence, that is, based on the principle of time-division multiplexing, different pixel blocks are processed by one algorithm module in different clock cycles, without setting multiple algorithm sub-modules with exactly the same functions in the algorithm module, reducing the logic resources occupied by the video processing unit, thereby saving the logic resources of the IC chip.

[0080] Different from the prior art, in the prior art, the Figure 1 shown video processing device, the logic area occupied by the video processing unit in the IC chip is (N×N). While in the present disclosure, the logic area occupied by the video processing unit in the IC chip is (N×M).

[0081] Compared with the prior art, although the pixel merging unit is added in the video processing device of the present disclosure, the logic area occupied by the pixel merging unit in the IC chip can be ignored compared to the logic area occupied by the video processing unit in the IC chip. Therefore, the video processing unit in the present disclosure can reduce the occupied % of the logic area, thereby achieving the purpose of saving the logic resources of the IC chip.

[0082] Furthermore, due to the video processing device provided in the present disclosure, the logic resources of the IC chip are saved, so the power consumption and cost of the IC chip are reduced, and the market competitiveness of the IC chip is improved.

[0083] The present disclosure also provides a display device, and the display device includes the video processing device in any one of the above embodiments. The display device provided in the present disclosure has the same beneficial effects as the video processing device provided in the present disclosure, and the beneficial effects of the display device will not be elaborated here.

[0084] Next, in conjunction with Figure 6 the working timing of the IC chip will be described.

[0085] Figure 6 This is the working timing diagram of the IC chip provided by the present disclosure. As Figure 6 shown, it includes: the clock signal (rd_en) corresponding to the read enable terminal of the video processing unit 230 and the image block (rd_data) read by the video processing unit 230.

[0086] Please refer to rd_en. First, provide a high level for one clock cycle to the read enable terminal, and then provide a low level for (N / M - 1) clock cycles to this read enable terminal.

[0087] For each image block, when receiving the pixel block of the last pixel row in this image block and the rising edge of rd_en, the video processing unit 230 obtains the pixel blocks of the respective other pixel rows from the buffer unit 220 to obtain the image block, so as to obtain the image block within one clock cycle (i.e., one beat).

[0088] First, provide a high level for one clock cycle to the read enable terminal, and then provide a low level for (N / M - 1) clock cycles to this read enable terminal, so that the pixel blocks cached in the buffer unit 220 can be updated every (N / M) clock cycles. Please refer to rd_data.

[0089] For example, in the case where the image block Data1 is cached in the buffer unit 220 first and then the image block Data2 is cached, when receiving the pixel block of the last pixel row in Data1 and the first rising edge of rd_en, the video processing unit 230 obtains the pixel blocks of the respective other pixel rows of Data1 from the buffer unit 220 to obtain Data1; when receiving the pixel block of the last pixel row in Data2 and the second rising edge of rd_en, the video processing unit 230 obtains the pixel blocks of the respective other pixel rows of Data2 from the buffer unit 220 to obtain Data2.

[0090] In Figure 6 the shown timing, it can be seen that Data1 can remain unchanged in the first number (N / M) of clock cycles, and thus it can be ensured that the video processing unit 230 can process multiple pixel blocks in Data1 sequentially within the first number of clock cycles without display anomalies occurring.

[0091] Figure 7 This is the schematic flowchart of the video processing method provided by the present disclosure. As Figure 7 shown, this method includes:

[0092] Step 701: Perform pixel merging on the pixels included in each pixel row among multiple pixel rows to obtain the pixel blocks of the respective multiple pixel rows, and the multiple pixel rows are the multiple pixel rows of one frame of an image in the video.

[0093] Optionally, for the video processing method provided by the present disclosure, the execution subject may be a display device or a video processing device provided in the display device. The video processing device may be implemented by a combination of software and / or hardware. Optionally, the video processing device may be the video processing device in any of the above Figures 2 to 5 embodiment of the video processing device.

[0094] Step 702: Cache the pixel blocks of each of the other pixel rows except the last pixel row among multiple pixel rows.

[0095] Step 703: When receiving the pixel block of the last pixel row, obtain the pixel blocks of the other cached pixel rows to obtain an image block, and sequentially process each pixel block in the image block.

[0096] It should be noted here that the video processing device provided by the present disclosure can implement the above video processing method, and the video processing device and the video processing method can achieve the same technical effects. The same parts and beneficial effects as those in the device embodiment in this embodiment will not be described in detail here.

[0097] According to a video processing method provided by the present disclosure, pixel merging is performed on the pixels included in each pixel row among multiple pixel rows to obtain pixel blocks of each of the multiple pixel rows, including:

[0098] Receive a preset number of pixels for pixel merging in the corresponding pixel row, and perform pixel merging on the preset number of pixels to obtain the pixel block of the pixel row.

[0099] According to a video processing method provided by the present disclosure, obtaining the pixel blocks of the other cached pixel rows to obtain an image block includes:

[0100] When receiving the pixel block of the last pixel row, obtain the pixel blocks of the other cached pixel rows to obtain an image block within one clock cycle.

[0101] According to a video processing method provided by the present disclosure, sequentially processing each pixel block in the image block includes:

[0102] Within the first number of clock cycles, sequentially process each pixel block in the image block.

[0103] Figure 8 is a schematic structural diagram of an entity of a display device provided by the present disclosure. As Figure 8As shown, the display device may include: a processor 810, a communications interface 820, a memory 830, and a communication bus 840. Among them, the processor 810, the communications interface 820, and the memory 830 communicate with each other through the communication bus 840. The processor 810 may call the logic instructions in the memory 830 to execute a video processing method, which includes: performing pixel merging on the pixels included in each pixel row among a plurality of pixel rows to obtain pixel blocks of each of the plurality of pixel rows, where the plurality of pixel rows are the pixel rows of a frame image in the video; caching the pixel blocks of the other pixel rows except the last pixel row among the plurality of pixel rows; when receiving the pixel block of the last pixel row, obtaining the pixel blocks of the other cached pixel rows to obtain an image block, and sequentially processing each pixel block in the image block.

[0104] In addition, when the logic instructions in the above-mentioned memory 830 are implemented in the form of software functional units and sold or used as an independent product, they may be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present disclosure, in essence, or the part that contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present disclosure. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc that can store program codes.

[0105] On the other hand, the present disclosure also provides a computer program product. The computer program product includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the video processing method provided by the above-mentioned various methods. The method includes: performing pixel merging on the pixels included in each pixel row among a plurality of pixel rows to obtain pixel blocks of each of the plurality of pixel rows, where the plurality of pixel rows are the pixel rows of a frame image in the video; caching the pixel blocks of the other pixel rows except the last pixel row among the plurality of pixel rows; when receiving the pixel block of the last pixel row, obtaining the pixel blocks of the other cached pixel rows to obtain an image block, and sequentially processing each pixel block in the image block.

[0106] In another aspect, the present disclosure also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the video processing method provided by the above-mentioned various methods. The method includes: performing pixel merging on the pixels included in each pixel row among a plurality of pixel rows to obtain pixel blocks of each of the plurality of pixel rows, where the plurality of pixel rows are the pixel rows of a frame image in a video; caching the pixel blocks of the other pixel rows except the last pixel row among the plurality of pixel rows; when receiving the pixel block of the last pixel row, obtaining the pixel blocks of the other cached pixel rows to obtain an image block, and sequentially processing each pixel block in the image block.

[0107] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative effort.

[0108] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, and are not intended to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A video processing device, characterized in that, Comprising: A pixel merging unit, a cache unit, and a video processing unit; wherein, The pixel merging unit is configured to perform pixel merging on the pixels included in each pixel row among a plurality of pixel rows, to obtain pixel blocks of the respective pixel rows, and the plurality of pixel rows are multiple pixel rows of a frame of image in a video; The cache unit is configured to cache the pixel blocks of the respective pixel rows among the plurality of pixel rows except the last pixel row; The video processing unit is configured to, when receiving the pixel block of the last pixel row, obtain the pixel blocks of the respective other pixel rows from the cache unit, to obtain an image block, and sequentially process each pixel block in the image block; The pixel merging unit includes: a plurality of mutually independent merging modules; wherein, the plurality of merging modules correspond one by one to the plurality of pixel rows; The merging module is configured to receive a preset number of pixels for pixel merging in the corresponding pixel row, and perform pixel merging on the preset number of pixels for pixel merging, to obtain the pixel block of the pixel row.

2. The video processing device according to claim 1, wherein The cache unit: includes a plurality of cache modules; wherein, the plurality of cache modules correspond one by one to the respective other pixel rows; The cache module is configured to cache the pixel block of one pixel row.

3. The video processing device according to claim 1, wherein The video processing unit specifically is configured to: When receiving the pixel block of the last pixel row, obtain the pixel blocks of the respective other pixel rows from the cache unit, to obtain the image block within one clock cycle.

4. The video processing device according to claim 1, wherein The video processing unit specifically is configured to: Within a first number of clock cycles, sequentially process each pixel block in the image block, and the first number is equal to the ratio of the preset number of pixels for pixel merging to the preset number of received pixels.

5. The video processing device according to claim 4, wherein The video processing unit includes an algorithm module; The algorithm module is configured to, within the first number of clock cycles, sequentially process each pixel block in the image block.

6. A display device, characterized in that, Comprising: The video processing device according to any one of claims 1 to 5.

7. A video processing method, characterized in that, The method includes: Performing pixel merging on the pixels included in each pixel row among a plurality of pixel rows, to obtain pixel blocks of the respective pixel rows, and the plurality of pixel rows are multiple pixel rows of a frame of image in a video; Caching the pixel blocks of the respective pixel rows among the plurality of pixel rows except the last pixel row; In the case of receiving the pixel block of the last pixel row, obtaining the pixel blocks of the respective cached other pixel rows, to obtain an image block, and sequentially processing each pixel block in the image block; Performing pixel merging on the pixels included in each pixel row among a plurality of pixel rows, to obtain pixel blocks of the respective pixel rows, including: Receiving a preset number of pixels for pixel merging in the corresponding pixel row, and performing pixel merging on the preset number of pixels for pixel merging, to obtain the pixel block of the pixel row.

8. A display device, characterized in that, Comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, it implements the video processing method according to claim 7.

9. A non-transitory computer-readable storage medium, characterized in that, A computer program is stored thereon, and when the computer program is executed by a processor, it implements the video processing method according to claim 7.

Images