Voltage regulator with power supply noise cancellation

Abstract

A power supply noise reduction method and low dropout (LDO) voltage regulator utilizing a capacitively coupled power supply noise reduction component. An illustrative voltage regulator includes a pass transistor having an n-type conduction channel, the pass transistor coupling a supply voltage to an output node; an operational amplifier deriving a control signal for the pass transistor from a difference between a reference voltage at the output node and a scaled or unscaled voltage, the control signal being provided to a gate or base of the pass transistor; a buffer deriving a ripple cancellation signal from the supply voltage; and a coupling capacitor coupling the buffer to the base or gate of the pass transistor to apply the ripple cancellation signal to the control signal.

Description

Background Technology

[0001] Most integrated circuit devices have become so complex that it is impractical for electronics designers to design them from scratch. Instead, electronics designers rely on predefined modular cells of integrated circuit layout design, arranging and connecting them as needed to achieve the various functions required by the device. Each modular cell has a well-defined interface and behavior that has been validated by its creator. While each modular cell may require significant time and investment to create, its reusability and further development greatly shorten product cycle time and lead to better products. Predefined cells can be organized hierarchically, where a given cell is incorporated into one or more lower-level cells, and then in turn incorporated into higher-level cells. Many organizations have libraries of such predefined modular cells for sale or licensing, including, for example, embedded processors, memories, interfaces for different bus standards, power converters, frequency multipliers, sensor transducer interfaces, to name just a few. Predefined modular cells are also called cells, blocks, cores, and macros; these terms have different meanings and variations (“IP core”, “soft macro”), but are often used interchangeably.

[0002] Modular cells can be represented in different ways, such as as Hardware Description Language (HDL) files or as fully routed designs that can be directly printed onto a range of manufacturing process masks. Fully routed design files are typically process-specific, meaning additional design work is often required to migrate modular cells to different processes or manufacturers. Conversely, modular cells in HDL form require subsequent synthesis, placement, and routing steps but are process-independent, meaning different manufacturers can apply their preferred automated synthesis, placement, and routing processes to implement cells using various manufacturing processes. Due to their higher-level representation, HDL cells may be better suited for modification and use with variable design parameters, while fully routed cells may offer better predictability in terms of area requirements, reliability, and performance. While there are no fixed rules, digital module designs are more often specified in HDL form, while analog and mixed-signal cells are more often specified in lower-level physical descriptions.

[0003] Many modular units, such as high-bandwidth serializer / deserializer (SerDes) modules, are sensitive to power supply noise. This noise is typically caused by signal transitions in high-bandwidth circuits, increasing jitter in the transmit and receiver clocks and affecting the operation of amplifiers used for equalization and symbol determination. While various techniques exist to limit power supply noise to acceptable levels, they are either too complex, power-intensive, or simply not feasible as part of predefined modular units. Summary of the Invention

[0004] Therefore, this paper discloses a power supply noise reduction method and a low dropout (LDO) voltage regulator utilizing a capacitively coupled power supply noise reduction component. An illustrative voltage regulator includes: a transfer transistor having an n-type conduction channel that couples a power supply voltage to an output node; an operational amplifier that derives a control signal for the transfer transistor from the difference between a reference voltage at the output node and a scaled or unscaled voltage, the control signal being provided to the gate or base of the transfer transistor; a buffer that derives a ripple cancellation signal from the power supply voltage; and a coupling capacitor that couples the buffer to the base or gate of the transfer transistor to apply the ripple cancellation signal to the control signal.

[0005] An illustrative voltage regulation method includes: coupling a power supply voltage to an output node using a transfer transistor having an n-type conduction channel; deriving a control signal for the transfer transistor from the difference between a reference voltage at the output node and a scaled or unscaled voltage using an operational amplifier; deriving a ripple cancellation signal from the power supply voltage using a buffer; providing the control signal to the gate or base of the transfer transistor; and applying the ripple cancellation signal to the control signal by coupling a buffer to the base or gate of the transfer transistor using a coupling capacitor.

[0006] An illustrative computer-readable information storage medium stores a hardware description language (HDL) design for a low-dropout (LDO) voltage regulation circuit, specifying: a transfer transistor having an n-type conduction channel that couples a supply voltage to an output node; an operational amplifier that derives a control signal for the transfer transistor from the difference between a reference voltage at the output node and a scaled or unscaled voltage, the control signal being provided to the gate or base of the transfer transistor; a buffer that derives a ripple cancellation signal from the supply voltage; and a coupling capacitor that couples the buffer to the base or gate of the transfer transistor to apply the ripple cancellation signal to the control signal.

[0007] Each of the aforementioned regulators, methods, and designs can be implemented individually or in combination, and can be implemented in any suitable combination with any one or more of the following features: 1. A feedforward capacitor that couples the supply voltage to the input of the buffer. 2. A bias voltage provided to the input of the buffer via a feedforward resistor. 3. The feedforward resistor and the feedforward capacitor together act as a high-pass filter. 4. The transfer transistor is an n-type metal-oxide-semiconductor (NMOS) transistor. 5. The buffer is an inverting buffer comprising a first NMOS transistor connected in series with a second NMOS transistor having a fixed bias, and the second NMOS transistor having a gate capacitively coupled to the supply voltage to generate a ripple cancellation signal at an intermediate node between the first and second NMOS transistors. 6. The buffer has a gain of approximately -1. 7. The transfer transistor has a gate capacitance, and the ratio of this gate capacitance to the coupling capacitance determines the scaling factor of the ripple cancellation signal. 8. A resistor divider that provides a scaled voltage from the output node to the inverting node of the operational amplifier. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of an illustrative low dropout (LDO) voltage regulator circuit.

[0009] Figure 2 It is a schematic diagram of a relatively complex voltage regulator circuit.

[0010] Figure 3 This is a schematic diagram of an illustrative voltage regulator circuit with capacitively coupled power supply noise cancellation. Detailed Implementation

[0011] Please note that the specific embodiments given in the accompanying drawings and the following description do not limit this disclosure. Rather, they provide a basis for those skilled in the art to identify alternatives, equivalents, and modifications included within the scope of the claims.

[0012] Figure 1 A voltage regulator circuit 100 is shown, which may be a circuit block specified in the form of an HDL design and implemented as an integrated circuit on a semiconductor substrate. The voltage regulator circuit 100 is a low-dropout (LDO) voltage regulator; therefore, it includes functions to regulate the supply voltage V. IN Coupled to the regulated voltage node V OUT The transfer transistor M0 supplies power to the load circuit 102. The load circuit is represented here as the output capacitor C. OUT and variable current absorber I OUT The variable current absorber consumes current from the regulated voltage node V. OUT The power. For SerDes modules, even when the current consumption varies from near zero to hundreds of milliamps, it is desirable to maintain the regulated voltage V.OUT Maintain a constant value.

[0013] Transmission transistor M0 is an n-channel metal-oxide-semiconductor (NMOS) transistor that receives a control signal V from operational amplifier 104. C The gate of the operational amplifier 104. The operational amplifier 104 at its non-inverting input V... + Received reference voltage V REF And it receives an unscaled or scaled regulated voltage V at its inverting input V_. OUT This amplifies the difference between the two to drive the gate of the transfer transistor M0. Many academic documents describe the generation of the reference voltage V. REF While a suitable method may be found, the bandgap reference voltage may be preferred due to its stability and ease of implementation.

[0014] Since such a reference voltage is typically the desired regulated voltage V OUT As part of the voltage divider, resistor divider 106 can be used for scaling. Voltage divider 106 will scale the voltage V... OUT R2 / (R1+R2) provides the inverting input V_ of operational amplifier 104. This is provided as long as the supply voltage V_... IN Sufficiently exceeding the expected voltage V OUT Amplifier 104 will provide negative feedback when the inverting input voltage V_ is less than the non-inverting input voltage V_. + Increase control signal voltage V C (and the adjusted voltage V) OUT And when the inverting input voltage V_ is greater than the non-inverting input voltage V_ + Reduce control signal voltage (and V) OUT In this way, amplifier 104 forces the difference between its input terminals to zero, thereby setting V. OUT =V REF *(R1+R2) / R2 Ideally, after adjusting the voltage V OUT With power supply voltage V IN Regardless of the voltage supply change rate, the performance is close to ideal as long as it does not exceed the amplifier's ability to regulate the control voltage. However, the inherent gate capacitance C of the transfer transistor... G Combined with the amplifier's output conductance, an upper limit is imposed on the rate of change that can be corrected, thereby imposing an upper limit on the noise frequency that can be suppressed.

[0015] However, it should be noted that the intrinsic input capacitance (which may be enhanced by discrete or integrated input capacitors) C INIn conjunction with the power supply impedance, it acts as a low-pass filter to suppress power supply noise above a certain cutoff frequency. For the feasible combination of input capacitance and power supply impedance, this cutoff frequency is well above the upper limit that amplifier 104 can handle. These two frequencies define an intermediate value of the noise frequency, which can leak through the illustrative voltage regulator, resulting in the regulated voltage V... OUT Undesirable variations in frequency range. As an example, for some envisioned voltage regulator embodiments, the intermediate frequency range is 2 MHz to 10 MHz.

[0016] Figure 2 An illustrative voltage regulator circuit 200 is shown, which adds complexity to improve suppression of intermediate noise frequencies. Unlike voltage regulator circuit 100, voltage regulator circuit 200 uses a p-channel metal-oxide-semiconductor (PMOS) transistor as its transfer transistor M. P (NMOS transistors perform better at higher voltages, while PMOS transistors perform better at lower voltages.) To realize a PMOS transfer transistor M... P Negative feedback, reference voltage V REF The inverting input V_ of operational amplifier 204 is supplied, and the scaled output voltage V_ is... OUT *R2 / (R1+R2) is provided to the non-inverting input V. + Amplifier 204 amplifies V + The difference between V and V_ provides the feedback signal V. FB .

[0017] The summing amplifier 208 will feed back the signal V FB With feedforward signal V FF Combined to generate control signal V S And provide to the transmission transistor M P The gate. Control signal V S It can be represented as

[0018]

[0019] Feedforward amplifier 210 generates feedforward signal V FF It can be represented as

[0020]

[0021] For more than approximately 1 / 2πR FF1 C FF The frequency at which the feedforward amplifier acts as a high-pass filter can be selected so that the feedforward signal V... FF The resistor in the summing amplifier 208 represents the intermediate frequency noise component of the power supply voltage. The resistor in the summing amplifier allows the control voltage to suppress noise from the regulated voltage V. OUT These noise components.

[0022] Using two additional operational amplifiers and their supporting components significantly increases circuit complexity, consumes more area and power, and requires careful calibration to achieve correct performance. Using a PMOS transport transistor M that relies on reduced charge carrier mobility... P This further limits the efficiency and performance of the regulator circuit 200.

[0023] In comparison, Figure 3 The illustrative voltage regulator circuit 300 retains most of the simplicity of circuit 100, only adding an AC coupling capacitor C. FF and C C The inverting buffer 310 can be implemented as two NMOS transistors M1 and M2 connected in series. Transistor M1 is coupled between ground and an intermediate node, while transistor M2 is coupled between the intermediate node and the power supply voltage V. IN Between. Bias voltage V B2 Coupled to the gate of transistor M2, it essentially acts as a constant current source. Resistor R FF The corresponding bias voltage V B1 The gate of transistor M1 is coupled to the transistor so that M1 acts as a current sink matched to a constant current source M2 in the absence of a change in the power supply voltage.

[0024] Coupling capacitor C FF The power supply voltage V IN The change in voltage is coupled to the gate of the current sink transistor M1, generating a ripple cancellation signal voltage V at the intermediate node. RC Coupling capacitor C FF With resistance R FF Combined, it can act as a high-pass filter. For frequencies higher than 1 / 2πR FF C FF The power supply voltage change eliminates the signal voltage V RC This includes negative changes at the corresponding frequencies. The inverting buffer 310 can be configured to provide a gain of -1 for the aforementioned intermediate noise frequency range. Coupling capacitor C C and gate capacitance C G It can act as an impedance divider to eliminate signal V. RC Scaling 1 / (1+C) G / C C The gate voltage of the transmission transistor M0 is a superimposed, scaled cancellation signal V. RC control signal V C (see Figure 1 ):

[0025]

[0026] Accordingly, select coupling capacitor C C This is to ensure that the negative changes in the signal voltage are matched with the corresponding power supply voltage changes within the intermediate noise frequency range.

[0027] In this way, the regulator shown directly subtracts the power supply voltage noise from the regulated voltage, significantly improving the power supply rejection ratio (PSRR) at the intermediate noise frequency, resulting in a significant reduction in jitter and a significant reduction in the bit error rate in the SerDes module using the voltage regulator shown. (With regulator circuit 200) Figure 2 Compared to capacitive coupling, the use of inverting buffers significantly reduces complexity, area, and power consumption.

[0028] Once the foregoing disclosure is fully understood, many alternatives, equivalents, and modifications will become apparent to those skilled in the art. For example, the voltage regulator circuit 300 is implemented using an NMOS transistor, but those skilled in the art will recognize how the disclosed principles can be used with other semiconductor technologies, including PMOS, CMOS, JFET, and BJT. This disclosure is intended to be construed as including all such alternatives, equivalents, and modifications covered within the scope of the appended claims.

Claims

1. A low dropout (LDO) voltage regulation circuit, comprising: A transmission transistor having an n-type conduction channel, the transmission transistor coupling the power supply voltage to the output node; An operational amplifier derives a control signal for the transmission transistor from the difference between a reference voltage at the output node and a scaled or unscaled voltage, the control signal being provided to the gate or base of the transmission transistor; A buffer that derives a ripple cancellation signal from the power supply voltage; as well as A coupling capacitor having a first terminal connected to the output of the buffer and a second terminal connected to the base or gate of the transmission transistor, for applying the ripple cancellation signal to the control signal. The buffer is an inverting buffer, comprising a first NMOS transistor connected in series with a second NMOS transistor, the first NMOS transistor having a fixed bias, and the second NMOS transistor having a gate capacitively coupled to the power supply voltage to generate the ripple cancellation signal at an intermediate node between the first and second NMOS transistors.

2. The circuit of claim 1 further includes a feedforward capacitor that couples the power supply voltage to the input of the buffer.

3. The circuit according to claim 2, wherein, The bias voltage is provided to the input of the buffer through a feedforward resistor, wherein the feedforward resistor and the feedforward capacitor together act as a high-pass filter.

4. The circuit according to claim 1, wherein, The transmission transistor is an n-type metal-oxide-semiconductor (NMOS) transistor.

5. The circuit of claim 4, wherein the transmission transistor has a gate capacitance, wherein the buffer has a gain of approximately -1, and wherein the ratio of the gate capacitance to the coupling capacitor determines the scaling factor of the ripple cancellation signal.

6. The circuit of claim 1 further includes a resistor divider that provides the scaled voltage of the output node to the inverting node of the operational amplifier.

7. A low-dropout (LDO) voltage regulation method, comprising: The power supply voltage is coupled to the output node using a transmission transistor with an n-type conduction channel; The operational amplifier is used to derive the control signal for the transmission transistor from the difference between the reference voltage of the output node and the scaled or unscaled voltage; A ripple cancellation signal is derived from the power supply voltage using a buffer. The control signal is provided to the gate or base of the transmission transistor; as well as The ripple cancellation signal is applied to the control signal via a coupling capacitor, the coupling capacitor having a first terminal connected to the output of the buffer and a second terminal connected to the base or gate of the transmission transistor. The buffer is an inverting buffer, comprising a first NMOS transistor connected in series with a second NMOS transistor, the first NMOS transistor having a fixed bias, and the second NMOS transistor having a gate capacitively coupled to the power supply voltage to generate the ripple cancellation signal at an intermediate node between the first and second NMOS transistors.

8. The method according to claim 7, further comprising: The power supply voltage is capacitively coupled to the input of the buffer using a feedforward capacitor.

9. The method according to claim 8, further comprising: A bias voltage is provided to the input of the buffer via a feedforward resistor, wherein the feedforward resistor and the feedforward capacitor together act as a high-pass filter.

10. The method of claim 7, wherein the transmission transistor is an n-type metal-oxide-semiconductor (NMOS) transistor.

11. The method of claim 10, wherein the transmission transistor has a gate capacitance, wherein the buffer has a gain of approximately -1, and wherein the ratio of the gate capacitance to the coupling capacitor determines the scaling factor of the ripple cancellation signal.

12. The method of claim 7, further comprising using a resistor divider to provide the scaled voltage of the output node to the inverting node of the operational amplifier.

13. A computer-readable information storage medium storing a hardware description language design of a low-dropout (LDO) voltage regulation circuit, the design specifying: A transmission transistor having an n-type conduction channel, the transmission transistor coupling the power supply voltage to the output node; An operational amplifier derives a control signal for the transmission transistor from the difference between a reference voltage at the output node and a scaled or unscaled voltage, the control signal being provided to the gate or base of the transmission transistor; A buffer that derives a ripple cancellation signal from the power supply voltage; as well as A coupling capacitor having a first terminal connected to the output of the buffer and a second terminal connected to the base or gate of the transmission transistor, for applying the ripple cancellation signal to the control signal. The buffer is an inverting buffer, which includes a first NMOS transistor connected in series with a second NMOS transistor. The first NMOS transistor has a fixed bias, and the second NMOS transistor has a gate capacitively coupled to the power supply voltage to generate the ripple cancellation signal at an intermediate node between the first and second NMOS transistors.

14. The dielectric of claim 13, wherein the design further specifies a feedforward capacitor that couples the power supply voltage to the input of the buffer.

15. The dielectric of claim 14, wherein the design further specifies a feedforward resistor that provides a bias voltage to the input of the buffer, and wherein the feedforward resistor and the feedforward capacitor together act as a high-pass filter.

16. The medium of claim 13, wherein the transmission transistor is an n-type metal-oxide-semiconductor (NMOS) transistor.

17. The medium of claim 16, wherein the transmission transistor has a gate capacitance, wherein the buffer has a gain of approximately -1, and wherein the ratio of the gate capacitance to the coupling capacitor determines the scaling factor of the ripple cancellation signal.

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