Display panel and display device

Abstract

The present invention provides a display panel and a display device. The operation of the pixel circuit in the display panel includes a first mode and a second mode. The time length Ld1 of the non-light-emitting phase of the data writing frame and the time length Lm1 of the holding frame in the first mode, and the time length Ld2 of the non-light-emitting phase of the data writing frame and the time length Lm2 of the holding frame in the second mode are flexibly adjusted in accordance with Ld1 > Ld2 and / or Lm1 > Lm2, so that the time length of the non-light-emitting phase in the data writing frame and the holding frame reaches an optimal state, ensuring that the display panel can achieve a better display effect in different modes.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Pixel circuits provide the driving current required for the light-emitting elements of a display panel and control whether the light-emitting elements enter the light-emitting stage, thus becoming an indispensable component in most display panels. With the continuous development of science and technology, how to realize a multifunctional display panel to meet the diverse needs of different application scenarios is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0003] In view of this, in order to solve the above problems, the present invention provides a display panel and a display device, the technical solution of which is as follows:

[0004] A display panel, the display panel comprising:

[0005] Pixel circuits and light-emitting elements;

[0006] The pixel circuit includes a driving module and a signal conditioning module;

[0007] The driving module includes a driving transistor;

[0008] One frame of the display panel includes a non-light-emitting phase and a light-emitting phase. The non-light-emitting phase includes a signal conditioning phase. In the signal conditioning phase, the signal conditioning module provides a preset signal to the driving transistor.

[0009] The image refresh frame of the pixel circuit includes a data write frame and a hold frame. The data write frame includes p signal conditioning stages, p≥1, and / or the hold frame includes q signal conditioning stages, q≥0.

[0010] The operation of the pixel circuit includes a first mode and a second mode.

[0011] In the first mode, the duration of the non-light-emitting phase of the data writing frame is Ld1, and the duration of the non-light-emitting phase of the holding frame is Lm1;

[0012] In the second mode, the duration of the non-light-emitting phase of the data writing frame is Ld2, and the duration of the non-light-emitting phase of the holding frame is Lm2;

[0013] Where Ld1 > Ld2, and / or Lm1 > Lm2.

[0014] This application also provides a display device, which includes the display panel described above.

[0015] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0016] The present invention provides a pixel circuit operation process in a display panel including a first mode and a second mode. The time length Ld1 of the non-light-emitting phase of the data writing frame and the time length Lm1 of the holding frame in the first mode, and the time length Ld2 of the non-light-emitting phase of the data writing frame and the time length Lm2 of the holding frame in the second mode are flexibly adjusted in accordance with Ld1 > Ld2 and / or Lm1 > Lm2, so that the time length of the non-light-emitting phase in the data writing frame and the holding frame reaches an optimal state, ensuring that the display panel can achieve a better display effect in different modes. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0019] Figure 2 This is a partial timing diagram of a pixel circuit operation provided in an embodiment of the present invention;

[0020] Figure 3 This is a partial timing diagram illustrating the operation of another pixel circuit according to an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0022] Figure 5 A partial timing diagram illustrating the operation of another pixel circuit provided in an embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of the Id-Vg curve drift of a driving transistor;

[0025] Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0026] Figure 9A partial timing diagram illustrating the operation of another pixel circuit provided in an embodiment of the present invention;

[0027] Figure 10 A partial timing diagram illustrating the operation of another pixel circuit provided in an embodiment of the present invention;

[0028] Figure 11 A partial timing diagram illustrating the operation of another pixel circuit provided in an embodiment of the present invention;

[0029] Figure 12 A partial timing diagram illustrating the operation of another pixel circuit provided in an embodiment of the present invention;

[0030] Figure 13 A partial timing diagram illustrating the operation of another pixel circuit provided in an embodiment of the present invention;

[0031] Figure 14 A partial timing diagram illustrating the operation of another pixel circuit provided in an embodiment of the present invention;

[0032] Figure 15 A partial timing diagram illustrating the operation of another pixel circuit provided in an embodiment of the present invention;

[0033] Figure 16 A partial timing diagram illustrating the operation of another pixel circuit provided in an embodiment of the present invention;

[0034] Figure 17 This is a schematic diagram of a full-screen display panel provided in an embodiment of the present invention;

[0035] Figure 18 This is a schematic diagram of a foldable screen display panel provided in an embodiment of the present invention;

[0036] Figure 19 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] refer to Figure 1 , Figure 1This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. The display panel provided in this embodiment includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes a driving module 11 and a signal conditioning module 12. The driving module 11 is used to provide a driving current to the light-emitting element 20, and the light-emitting element 20 emits light in response to the driving current. The driving module 11 includes a driving transistor T0. It should be noted that the driving transistor T0 can be a PMOS type driving transistor, or an NMOS type driving transistor, or other types of driving transistors. In this embodiment of the present invention, a PMOS type driving transistor is used as an example for explanation.

[0040] refer to Figure 2 , Figure 2 This is a partial timing diagram illustrating the operation of a pixel circuit according to an embodiment of the present invention. One frame of the display panel includes a non-emissive phase and an emissive phase. The non-emissive phase includes a signal conditioning phase. In the signal conditioning phase, the signal conditioning module 12 provides a preset signal VE to the driving transistor T0. That is, different signal conditioning phases within the non-emissive phase apply different signal controls to the driving transistor T0, which can improve the stability of the driving current generated by the driving transistor T0, thereby improving the display effect of the display panel. It should be noted that... Figure 2 EMIT is the light emission control signal for the display panel.

[0041] refer to Figure 3 , Figure 3 This is a partial timing diagram of another pixel circuit operation provided in an embodiment of the present invention. The screen refresh frame of the pixel circuit includes a data write frame and a hold frame. The data write frame includes p signal conditioning stages, p≥1, and / or the hold frame includes q signal conditioning stages, q≥0. That is, the number of signal conditioning stages in the data write frame and the hold frame is determined based on the specific type of the signal conditioning stage, which will be further explained below.

[0042] It should be noted that, Figure 3 The example only shows one data write frame and one hold frame; the number of data write frames and hold frames can be determined according to actual display requirements.

[0043] In one embodiment of the present invention, reference is made to... Figure 4 , Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 4 The pixel circuit 10 shown is illustrated using a PMOS type driving transistor T0 as an example. The drain of the driving transistor T0 is coupled to the light-emitting element 20, and provides driving current to the light-emitting element 20 after the driving transistor T0 is turned on.

[0044] like Figure 4 As shown, the pixel circuit 10 also includes a data writing module 13. In this embodiment of the invention, the signal conditioning module 12 can be the data writing module 13. At this time, the preset signal VE output by the signal conditioning module 12 is the data signal Vdata. The data writing module 13 is connected to the first pole of the driving transistor T0. During the signal conditioning stage, or in other words, during the data writing stage, the data writing module 13 is turned on and provides the data signal Vdata to the driving transistor T0.

[0045] In other words, in the embodiments of the present invention, providing a data signal Vdata to the driving transistor T0 is also part of signal conditioning.

[0046] Specifically, the data writing module 13 includes a data writing transistor T1, which is connected between the source of the driving transistor T0 and the data signal line L1. The source of the data writing transistor T1 is used to receive the data signal Vdata, the drain of the data writing transistor T1 is connected to the source of the driving transistor T0, and the gate of the data writing transistor T1 is used to receive the control signal S1.

[0047] Among them, reference Figure 5 , Figure 5 This is a partial timing diagram illustrating the operation of another pixel circuit according to an embodiment of the present invention. The control signal S1 received by the data writing transistor T1 is a pulse signal. During the data writing phase, when the control signal S1 is in an active pulse phase, it controls the data writing transistor T1 to be in a conducting state, providing the data signal Vdata to the driving transistor T0 through the data signal line L1. During the inactive pulse phase of the control signal S1, it controls the data writing transistor T1 to be in a deactivating state. Therefore, under the control of the control signal S1, the data writing transistor T1 selectively provides the data signal Vdata to the driving transistor T0.

[0048] In one embodiment of the present invention, such as Figure 4 As shown, the pixel circuit 10 also includes a reset module 14. In this embodiment of the invention, the signal conditioning module 12 can be a reset module 14. At this time, the preset signal VE output by the signal conditioning module 12 is a reset signal Vref. The reset module 14 is connected to the gate of the driving transistor T0. During the signal conditioning stage, or in other words, during the reset stage of the driving transistor T0, the reset module 14 is turned on and provides a reset signal Vref to the driving transistor T0.

[0049] In other words, providing a reset signal Vref for the driving transistor T0 in this embodiment of the invention is also part of signal conditioning.

[0050] Specifically, the reset module 14 includes a first reset transistor T2, the source of which receives a reset signal Vref, the drain of which is connected to the gate of the driving transistor T0, and the gate of which receives a control signal S2.

[0051] In this process, the control signal S2 received by the first reset transistor T2 is a pulse signal. During the effective pulse phase of the control signal S2, the first reset transistor T2 is controlled to be in the on state, and the reset signal Vref is written into the gate of the driving transistor T0 through the first reset transistor T2 to reset the gate of the driving transistor T0. During the ineffective pulse phase of the control signal S2, the first reset transistor T2 is controlled to be in the off state.

[0052] It should be noted that when the signal conditioning module 12 is the data writing module 13 or the reset module 14, q = 0; that is, when the signal conditioning module 12 is the data writing module 13 or the reset module 14, the holding frame does not include the signal conditioning stage, that is, the holding frame does not include the data writing stage and the reset stage of the driving transistor T0.

[0053] In one embodiment of the present invention, reference is made to... Figure 6 , Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. The signal conditioning module 12 is a bias conditioning module 15, and the preset signal VE output by the signal conditioning module 12 is a bias conditioning signal VR.

[0054] The bias adjustment module 15 is connected to the first or second terminal of the driving transistor T0. During the signal adjustment phase, the bias adjustment module 15 is turned on and provides a bias adjustment signal VR to the driving transistor T0.

[0055] Specifically, as the pixel circuit 10 is used for a longer period of time, the internal characteristics of the driving transistor T0 in the pixel circuit 10 change slowly, causing the threshold voltage of the driving transistor T0 to drift, which in turn affects the driving current it generates, resulting in an unsatisfactory display effect of the display panel.

[0056] For example, when the display panel switches from a high-frequency data refresh rate driving mode to a low-frequency data refresh rate driving mode, because the display panel uses a high-frequency data refresh rate driving mode, the number of frames held within a data refresh cycle is zero or very small, and the gate of the driving transistor T0 holds the input of the data signal Vdata. In other words, the gate potential of the driving transistor T0 refreshes relatively frequently. When the display panel uses a low-frequency data refresh rate driving mode, the number of frames held within a data refresh cycle becomes relatively larger, and the gate potential of the driving transistor T0 remains unchanged for a long time within a data refresh cycle. When the pixel circuit 10 in the display panel is in the light-emitting stage, the driving transistor T0 may be operating in a non-saturated state. For PMOS type driving transistors, there may be a situation where the gate potential is higher than the drain potential when the driving transistor T0 is turned on; for NMOS type driving transistors, there may be a situation where the gate potential is lower than the drain potential when the driving transistor is turned on. If the above situation is maintained for a long time, it will lead to the polarization of ions inside the driving transistor, thereby forming a built-in electric field inside the driving transistor, causing the threshold voltage of the driving transistor to continuously shift.

[0057] refer to Figure 7 , Figure 7 This is a schematic diagram illustrating the Id-Vg curve drift of a driving transistor, as shown below. Figure 7 As shown, the Id-Vg curve shifts, which in turn causes the threshold voltage Vth of the driving transistor to shift as well. This results in an unstable input signal to the driving transistor, which in turn affects the driving current it generates, leading to an unsatisfactory display effect on the display panel.

[0058] Therefore, in this application, by setting a bias adjustment module 15, during the signal adjustment stage, a bias adjustment signal VR is input to the first or second terminal of the driving transistor T0, that is, a bias adjustment signal VR is input to the source or drain of the driving transistor T0, to adjust the drain potential of the driving transistor T0, improve the potential difference between the gate potential and the drain potential of the driving transistor T0, thereby reducing the degree of ion polarization inside the driving transistor T0, reducing the threshold voltage of the driving transistor T0, ensuring that the Id-Vg curve does not shift as much as possible, ensuring that the driving current generated by it is not affected as much as possible, and thus improving the display effect of the display panel.

[0059] It should be noted that when the signal conditioning module 12 is the bias conditioning module 15, q≥1; that is, when the signal conditioning module 12 is the bias conditioning module 15, both the data writing frame and the holding frame can include a signal conditioning stage for biasing the driving transistor T0, thereby adjusting the threshold voltage of the driving transistor T0 to comprehensively improve the display effect of the display panel in each stage.

[0060] In one embodiment of the present invention, reference is made to... Figure 8 , Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 8 The pixel circuit 10 shown is illustrated using a PMOS type driving transistor T0 as an example. The drain of the driving transistor T0 is coupled to the light-emitting element 20, and provides driving current to the light-emitting element 20 after the driving transistor T0 is turned on.

[0061] like Figure 8 As shown, the display panel provided in this embodiment of the invention includes a data writing module 13 and a bias adjustment module 15.

[0062] The operation of this display panel includes a data writing stage and a signal conditioning stage.

[0063] During the data writing phase, the data writing module 13 is turned on, the bias adjustment module 15 is turned off, and the data writing module 13 provides the data signal Vdata to the driving transistor T0.

[0064] During the signal conditioning phase, the data writing module 13 is turned off, the bias conditioning module 15 is turned on, and the bias conditioning module 15 provides a bias conditioning signal VR to the driving transistor T0.

[0065] Specifically, such as Figure 8 As shown, the data writing module 13 is connected to the data signal line L1, which is used to transmit the data signal Vdata; the bias adjustment module 15 is connected to the bias adjustment signal line LR, which is used to transmit the bias adjustment signal VR. The bias adjustment module 15 is controlled by the control signal SR. The bias adjustment module 15 includes a bias adjustment transistor TR, which is connected between the driving transistor T0 and the bias adjustment signal line LR. One terminal of the bias adjustment transistor TR is used to receive the bias adjustment signal VR, and the other terminal of the bias adjustment transistor TR is connected to the source or drain of the driving transistor T0. The gate of the bias adjustment transistor TR is used to receive the control signal SR. In this embodiment of the invention, the bias adjustment transistor TR is connected to the source of the driving transistor T0 as an example.

[0066] Among them, the control signal SR received by the bias adjustment transistor TR is a pulse signal. During the signal adjustment stage, the control signal SR is in the effective pulse stage to control the bias adjustment transistor TR to be in the on state. The bias adjustment signal line LR provides the bias adjustment signal VR to the drive transistor T0.

[0067] refer to Figure 9 , Figure 9This is a partial timing diagram of another pixel circuit operation provided in an embodiment of the present invention. In the data writing stage, the data writing module 13 is turned on, and the data signal line L1 writes the data signal Vdata to the gate of the driving transistor T0; in the signal adjustment stage, the bias adjustment module TR is turned on, and the bias adjustment signal line LR writes the bias adjustment signal VR to the drain of the driving transistor T0.

[0068] Specifically, in this embodiment of the invention, by adding an additional bias adjustment module 15, it is beneficial to achieve separate control of the bias adjustment module 15 and the data writing module 13, and the magnitude of the bias adjustment signal VR can also be set independently, without being constrained by the data signal Vdata, ensuring that the display panel can achieve a good display effect under different display requirements.

[0069] In one embodiment of the present invention, based on Figure 4 The pixel circuit 10 structure shown has a bias adjustment module 15 that is multiplexed as a data writing module 13. That is, the data writing module 13 provides both the data signal Vdata and the bias adjustment signal VR.

[0070] refer to Figure 10 , Figure 10 This is a partial timing diagram of another pixel circuit operation provided by an embodiment of the present invention. The operation process of the display panel provided by the embodiment of the present invention includes a data writing stage and a signal conditioning stage.

[0071] During the data writing phase, the bias adjustment module 15 is turned on, and the bias adjustment module 15 provides the data signal Vdata to the drive transistor T0.

[0072] In other words, during the data writing phase, the data writing module 13 is turned on, and the data writing module 13 provides the data signal Vdata to the driving transistor T0.

[0073] During the signal conditioning phase, the bias conditioning module 15 is turned on, and the bias conditioning module 15 provides a bias conditioning signal VR to the drive transistor T0.

[0074] In other words, during the signal conditioning phase, the data writing module 13 is turned on, and the data writing module 13 plays the same role as the bias conditioning module 15 at this time, providing the bias conditioning signal VR to the driving transistor T0.

[0075] Specifically, in the embodiments of the present invention, the above method can avoid the need for an additional bias adjustment module 15. The bias adjustment function can be achieved by reusing the data writing module 13. Its structure is simple, which is conducive to simplifying the panel structure and improving the resolution of the display panel.

[0076] Optional, such as Figure 4 and Figure 8 As shown, the pixel circuit 10 may further include: a compensation transistor T3 for compensating the threshold voltage of the driving transistor T0. The source of the compensation transistor T3 is connected to the gate of the driving transistor T0 to form a first node N1, and the drain of the compensation transistor T3 is connected to the drain of the driving transistor T0. The gate of the compensation transistor T3 is used to receive a control signal S3. The control signal S3 received by the compensation transistor T3 is a pulse signal. During the effective pulse phase of the control signal S3, the compensation transistor T3 is controlled to be in the on state to compensate the threshold voltage of the driving transistor T0; during the ineffective pulse phase of the control signal S3, the compensation transistor T3 is controlled to be in the off state. Therefore, under the control of the control signal S3, the compensation transistor T3 selectively compensates the threshold voltage of the driving transistor T0.

[0077] In an optional embodiment of the present invention, the compensation transistor T3 may be an oxide semiconductor transistor, which has a relatively smaller leakage current, thereby helping to stabilize the potential of the driving transistor T0.

[0078] It should be noted that during the data writing phase, when the data writing module 13 writes the data signal Vdata to the gate of the driving transistor T0, the compensation transistor T3 also needs to be in the on state.

[0079] It should be further noted that when the bias adjustment module 15 is multiplexed as the data writing module 13, that is, when the bias adjustment module 15 and the data writing module 13 are the same module, during the data writing stage, when the data writing module 13 writes the data signal Vdata to the gate of the driving transistor T0, the compensation transistor T3 also needs to be in the on state. During the signal adjustment stage, when the data writing module 13 writes the bias adjustment signal VR to the source of the driving transistor T0, the compensation transistor T3 needs to be in the off state.

[0080] Optional, such as Figure 4 and Figure 8 As shown, the pixel circuit 10 may further include: a light-emitting element reset transistor T4; the source of the light-emitting element reset transistor T4 is used to receive an initialization signal Vini, the drain of the light-emitting element reset transistor T4 is connected to the anode of the light-emitting element 20, and the gate of the light-emitting element reset transistor T4 is used to receive a control signal S4. The control signal S4 received by the light-emitting element reset transistor T4 is a pulse signal. During the effective pulse phase of the control signal S4, the light-emitting element reset transistor T4 is in the on state, and the initialization signal Vini is written to the anode of the light-emitting element 20 through the light-emitting element reset transistor T4 to initialize the light-emitting element 20; during the ineffective pulse phase of the control signal S4, the light-emitting element reset transistor T4 is in the off state.

[0081] Optional, such as Figure 4 and Figure 8 As shown, the pixel circuit 10 may further include: a first light-emitting control transistor T5 and a second light-emitting control transistor T6. The first light-emitting control transistor T5 is connected between the first power signal terminal PVDD and the source of the driving transistor T0, and the second light-emitting control transistor T6 is connected between the drain of the driving transistor T0 and the light-emitting element 20, for controlling whether the pixel circuit 10 is in the light-emitting stage or the non-light-emitting stage.

[0082] The cathode of the light-emitting element 20 is connected to the second power signal terminal PVEE.

[0083] The gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 simultaneously receive the light-emitting control signal EMIT. Under the control of the light-emitting control signal EMIT, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are either in an on state or an off state. The light-emitting control signal EMIT received by the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 is a pulse signal. During the light-emitting stage, the light-emitting control signal EMIT outputs an effective pulse to control the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be in an on state, so that the driving current provided by the driving transistor T0 flows into the light-emitting element 20 to make it emit light. During the non-light-emitting stage, the light-emitting control signal EMIT outputs an invalid pulse to control the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be in an off state, so that the light-emitting element 20 does not emit light.

[0084] It should be noted that the light emission control signal EMIT provided in the embodiments of the present invention can be a single control signal that simultaneously controls the first light emission control transistor T5 and the second light emission control transistor T6; or, the light emission control signal EMIT can be divided into two sub-light emission control signals, which control their respective corresponding light emission control transistors, and the longer duration of the invalid pulse output in the two sub-light emission control signals is the effective time length of the non-light emission stage.

[0085] Optional, such as Figure 4 and Figure 8 As shown, the pixel circuit 10 may further include a storage capacitor C1, the first plate of which is connected to the first power signal terminal PVDD, and the second plate of which is connected to the first node N1.

[0086] It should be noted that, for the sake of simplicity, the timing diagrams in this application only show the timing processes related to the core content of this application, and the timing processes of other transistors are omitted here. It should be clear that the operation of the pixel circuit 10 requires the timing processes of each transistor to cooperate with each other.

[0087] In one embodiment of the present invention, reference is made to... Figure 11 , Figure 11 This is a partial timing diagram of another pixel circuit operation provided by an embodiment of the present invention. The operation process of the pixel circuit in the display panel provided by the embodiment of the present invention includes a first mode EMT1 and a second mode EMT2.

[0088] In the first mode EMT1, the duration of the non-light-emitting phase of the data writing frame is Ld1, and the duration of the non-light-emitting phase of the holding frame is Lm1.

[0089] In the second mode EMT2, the duration of the non-light-emitting phase of the data writing frame is Ld2, and the duration of the non-light-emitting phase of the holding frame is Lm2.

[0090] Where Ld1 > Ld2, and / or Lm1 > Lm2.

[0091] Specifically, in the embodiments of the present invention, there are at least the following two schemes: First, when the time length Ld1 of the non-light-emitting phase of the data writing frame in the first mode EMT1 is greater than the time length Ld2 of the non-light-emitting phase of the data writing frame in the second mode EMT2, the time length Lm1 of the holding frame in the first mode EMT1 is also greater than the time length Lm2 of the non-light-emitting phase of the holding frame in the second mode EMT2; Second, the time length Ld1 of the non-light-emitting phase of the data writing frame in the first mode EMT1 is greater than the time length Ld2 of the non-light-emitting phase of the data writing frame in the second mode EMT2, or the time length Lm1 of the non-light-emitting phase of the holding frame in the first mode EMT1 is greater than the time length Lm2 of the non-light-emitting phase of the holding frame in the second mode EMT2.

[0092] It should be noted that, Figure 11 The diagram illustrates the condition Ld1 > Ld2 and Lm1 > Lm2.

[0093] In other words, the operation of the pixel circuit in the display panel provided by the embodiments of the present invention includes a first mode EMT1 and a second mode EMT2. The time length Ld1 of the non-light-emitting phase of the data writing frame and the time length Lm1 of the holding frame in the first mode EMT1, and the time length Ld2 of the non-light-emitting phase of the data writing frame and the time length Lm2 of the holding frame in the second mode EMT2 are flexibly adjusted in accordance with Ld1 > Ld2 and / or Lm1 > Lm2, so that the time length of the non-light-emitting phase in the data writing frame and the holding frame reaches an optimal state, ensuring that the display panel can achieve a better display effect in different modes and realize diversified display.

[0094] Furthermore, when the data write frame and / or hold frame include a signal conditioning phase, the signal conditioning phase is usually located within the non-light-emitting phase. Therefore, by flexibly adjusting the duration of the non-light-emitting phase of the data write frame and / or hold frame under the first mode EMT1 and the second mode EMT2, the allocatable duration of the signal conditioning phase under different modes can also be further flexibly adjusted to ensure the effectiveness of each signal conditioning phase, thereby comprehensively improving the display effect of the display panel.

[0095] In one embodiment of the present invention, in the first mode EMT1, the luminous brightness of the display panel is B1, and in the second mode EMT2, the luminous brightness of the display panel is B2.

[0096] Where B1 < B2.

[0097] Specifically, the duration of the non-light-emitting phase varies in different modes of the display panel under different light-emitting brightness. In the embodiment of the present invention, when B1 < B2, there exists a relationship of Ld1 > Ld2 and / or Lm1 > Lm2.

[0098] In the first mode EMIT1, the duration Ld1 of the non-light-emitting phase of the data writing frame is greater than the duration Ld2 of the non-light-emitting phase of the data writing frame in the second mode EMIT2, and / or, the duration Lm1 of the non-light-emitting phase of the holding frame in the first mode EMIT1 is greater than the duration Lm2 of the non-light-emitting phase of the holding frame in the second mode EMIT2. Therefore, if the total duration of the non-light-emitting and light-emitting phases in a single frame is the same or similar, the duration of the light-emitting phase in the first mode EMIT1 will be less than the duration of the light-emitting phase in the second mode EMIT2. That is, the duration of the light-emitting phase in the first mode EMIT1 will be less than the duration of the light-emitting phase in the second mode EMIT2. The duration of the light emission phase of the data writing frame in mode 1 is shorter than that in mode 2 (EMIT2), and / or the duration of the light emission phase of the holding frame in mode 1 (EMIT1) is shorter than that in mode 2 (EMIT2). Therefore, the duration of the light emission phase of each frame in mode 2 (EMIT2) will be longer, resulting in a higher total brightness of the entire image observed by the human eye in mode 2 (EMIT2), i.e., there is a relationship of B1 < B2. The display panel can switch the brightness mode by switching between mode 1 (EMIT1) and mode 2 (EMIT2).

[0099] It should be noted that the luminance B1 under the first mode EMIT1 and the luminance B2 under the second mode EMIT2 refer to the total brightness of the final displayed image as perceived by the human eye.

[0100] For example, in scenarios where watching a game is required, the display panel can be displayed in high brightness in the second mode EMT2; in scenarios where reading an e-book is required, the display panel can be displayed in low brightness in the first mode EMT1. In other words, the display panel provided in this embodiment of the invention can exhibit different display effects in different brightness display modes to achieve diversified display and meet actual application needs.

[0101] In one embodiment of the present invention, in the first mode EMT1, the frame rate of the screen refresh frame of the display panel is Fv1, and in the second mode EMT2, the frame rate of the screen refresh frame of the display panel is Fv2.

[0102] Where Fv1 < Fv2.

[0103] Specifically, in the second mode EMT2, the frame rate Fv2 of the display panel's screen refresh frame can be 120Hz, etc. In the first mode EMT1, the frame rate Fv1 of the display panel's screen refresh frame can be 60Hz, 30Hz, or 1Hz, etc. The duration of the non-light-emitting phase varies in different modes with different screen refresh frame rates. Generally, when the screen refresh frame rate is relatively high, the duration of the corresponding non-light-emitting phase within a frame will be relatively short. Conversely, when the screen refresh frame rate is relatively low, the duration of the corresponding non-light-emitting phase within a frame will be relatively long. In this embodiment of the invention, when Fv1 < Fv2, there exists a relationship of Ld1 > Ld2 and / or Lm1 > Lm2.

[0104] When the pixel circuit 10 in the display panel is in different modes and displays the corresponding screen refresh frames, it can exhibit different display effects to achieve diversified display and meet practical application needs.

[0105] In one embodiment of the present invention, in the first mode EMT1, the frame time length of the screen refresh frame of the display panel is S1, and in the second mode EMT2, the frame time length of the screen refresh frame of the display panel is S2.

[0106] Where S1 > S2.

[0107] Specifically, the duration of the non-light-emitting phase varies depending on the frame length of the screen refresh frame. Generally, when the frame length of the screen refresh frame is relatively long, the duration of the corresponding non-light-emitting phase within a frame will be relatively long. Conversely, when the frame length of the screen refresh frame is relatively short, the duration of the corresponding non-light-emitting phase within a frame will be relatively short. In this embodiment of the invention, when S1 > S2, there exists a relationship of Ld1 > Ld2 and / or Lm1 > Lm2.

[0108] In other words, by adjusting the frame refresh time in different modes, the display panel can exhibit different display effects to achieve diversified display and meet practical application needs.

[0109] In one embodiment of the present invention, such as Figure 11 As shown, where Ld1 = Lm1, and / or, Ld2 = Lm2.

[0110] Specifically, in the embodiments of the present invention, there are at least two schemes: First, in the first mode EMT1, the duration Ld1 of the non-light-emitting phase of the data writing frame is equal to the duration Lm1 of the non-light-emitting phase of the holding frame, and in the second mode EMT2, the duration Ld2 of the non-light-emitting phase of the data writing frame is equal to the duration Lm2 of the non-light-emitting phase of the holding frame; Second, in the first mode EMT1, the duration Ld1 of the non-light-emitting phase of the data writing frame is equal to the duration Lm1 of the non-light-emitting phase of the holding frame, or in the second mode EMT2, the duration Ld2 of the non-light-emitting phase of the data writing frame is equal to the duration Lm2 of the non-light-emitting phase of the holding frame; that is, when Ld1 = Lm1 and / or Ld2 = Lm2, it indicates that in the embodiments of the present invention, the variation range of the duration of the non-light-emitting phase of the data writing frame and the holding frame is the same in different modes. From the perspective of signal control, this design does not require distinguishing between the data writing frame and the holding frame, but only requires simple adjustment of the effective duration of the timing, without the need for new pulse signals, thereby simplifying the control logic of the display panel.

[0111] It should be noted that, in Figure 11 The diagram illustrates Ld1 = Lm1 and Ld2 = Lm2.

[0112] In one embodiment of the present invention, there is also a relationship of Ld1≠Lm1 and / or Ld2≠Lm2, that is, the variation range of the non-light-emitting phase time length of the data writing frame and the holding frame in different modes is different.

[0113] Specifically, the functions of data write frames and hold frames in a display panel are fundamentally different. A key function of the data write frame is data writing; it includes a data writing phase and, to ensure data writing stability, also includes a reset phase for the driving transistor and other signal conditioning phases. Hold frames, however, do not have these limitations and do not include a data writing phase or a driving transistor reset phase. Therefore, based on the difference in the signal conditioning phases included in the non-light-emitting phases of the data write and hold frames, the duration of the non-light-emitting phases of the data write and hold frames does not need to be exactly the same and can be flexibly adjusted based on the specific signal conditioning phases.

[0114] In one embodiment of the present invention, reference is made to... Figure 12 , Figure 12 This is a partial timing diagram of another pixel circuit operation provided in an embodiment of the present invention, wherein Ld1 > Lm1, and / or Ld2 > Lm2.

[0115] Specifically, in the embodiments of the present invention, there are at least the following two schemes: First, in the first mode EMT1, the duration Ld1 of the non-light-emitting phase of the data writing frame is greater than the duration Lm1 of the non-light-emitting phase of the holding frame, and in the second mode EMT2, the duration Ld2 of the non-light-emitting phase of the data writing frame is greater than the duration Lm2 of the non-light-emitting phase of the holding frame; Second, in the first mode EMT1, the duration Ld1 of the non-light-emitting phase of the data writing frame is equal to the duration Lm1 of the non-light-emitting phase of the holding frame, or in the second mode EMT2, the duration Ld2 of the non-light-emitting phase of the data writing frame is greater than the duration Lm2 of the non-light-emitting phase of the holding frame.

[0116] In a data refresh cycle, there is a data write frame and a hold frame. When the required light intensity is very high or the base frequency changes very quickly, even if the duration of the non-light-emitting phase is very short, in order to ensure the effectiveness of the data write phase and the reset phase of the driving transistor in the data write frame, the duration of the non-light-emitting phase in the data write frame still needs to be kept at a relatively long length. The hold frame does not have these requirements, and it is clear that the duration of the non-light-emitting phase in the hold frame can be shortened even further.

[0117] In summary, in the embodiments of the present invention, based on the functions of the data writing frame and the holding frame, and the differences in the signal conditioning stages they contain, the duration of the non-light-emitting stage in the data writing frame and the holding frame can be adjusted separately to ensure that the duration of the non-light-emitting stage in both the data writing frame and the holding frame reaches an optimal state, thereby ensuring that the display panel can achieve a better display effect in different modes.

[0118] It should be noted that, in Figure 12 The diagram illustrates the condition Ld1 > Lm1 and Ld2 > Lm2.

[0119] In one embodiment of the present invention, reference is made to... Figure 13 , Figure 13 This is a partial timing diagram of another pixel circuit operation provided in an embodiment of the present invention, wherein Ld1 < Lm1, and / or Ld2 < Lm2.

[0120] Specifically, in the embodiments of the present invention, there are at least the following two schemes: First, in the first mode EMT1, the duration Ld1 of the non-light-emitting phase of the data writing frame is less than the duration Lm1 of the non-light-emitting phase of the holding frame, and in the second mode EMT2, the duration Ld2 of the non-light-emitting phase of the data writing frame is less than the duration Lm2 of the non-light-emitting phase of the holding frame; Second, in the first mode EMT1, the duration Ld1 of the non-light-emitting phase of the data writing frame is equal to the duration Lm1 of the non-light-emitting phase of the holding frame, or in the second mode EMT2, the duration Ld2 of the non-light-emitting phase of the data writing frame is less than the duration Lm2 of the non-light-emitting phase of the holding frame.

[0121] For some special functions in the display panel, the hold frame may also contain some special signal conditioning phases with relatively long signal durations. For example, the phase mentioned above that provides the bias conditioning signal VR for the driving transistor. In order to ensure the effectiveness of this signal conditioning phase in the hold frame, the duration of the non-light-emitting phase in the hold frame obviously needs to be appropriately maintained at a relatively long state. For example, if there is a signal conditioning phase in both the data writing frame and the hold frame, the duration of the signal conditioning phase in the data writing frame can be shortened or even eliminated, and this time can be incorporated into the hold frame to extend the duration of the signal conditioning phase in the hold frame. In this case, the duration of the non-light-emitting phase in the hold frame will be greater than the duration of the non-light-emitting phase in the data writing frame, in order to meet the corresponding display requirements.

[0122] It should be noted that, in Figure 13 The diagram illustrates the condition Ld1 < Lm1 and Ld2 < Lm2.

[0123] In one embodiment of the present invention, reference is made to... Figure 14 , Figure 14 This is a partial timing diagram of another pixel circuit operation provided by an embodiment of the present invention. In the first mode EMT1, the total time length of the signal conditioning phase in the data writing frame is Wd1, and the total time length of the signal conditioning phase in the holding frame is Wm1.

[0124] In the second mode EMT2, the total time length of the signal conditioning phase in the data writing frame is Wd2, and the total time length of the signal conditioning phase in the holding frame is Wm2.

[0125] Where Wd1 / Ld1≠Wm1 / Lm1; and / or,

[0126] Wd2 / Ld2≠Wm2 / Lm2.

[0127] It should be noted that, in the embodiments of the present invention, the number of signal conditioning stages can be one or more, and it is only necessary to take the total time length of the signal conditioning stages as the parameter.

[0128] Specifically, in the embodiments of the present invention, at least the following two schemes exist: First, in the first mode EMT1, the ratio of the total time length Wd1 of the signal conditioning phase in the data writing frame to the time length Ld1 of the non-light-emitting phase is not equal to the ratio of the total time length Wm1 of the signal conditioning phase in the hold frame to the time length Lm1 of the non-light-emitting phase; and second, in the second mode EMT2, the ratio of the total time length Wd2 of the signal conditioning phase in the data writing frame to the time length Ld2 of the non-light-emitting phase is not equal to the ratio of the total time length Wm2 of the signal conditioning phase in the hold frame to the time length Lm1 of the non-light-emitting phase. The ratio of the time length Lm2 in the first mode EMT1 to the time length Ld1 in the data writing frame is not equal to the ratio of the time length Wm1 in the holding frame to the time length Lm1 in the holding frame; or, in the second mode EMT2, the ratio of the time length Wd2 in the data writing frame to the time length Ld2 in the holding frame is not equal to the ratio of the time length Wm2 in the holding frame to the time length Lm2 in the holding frame.

[0129] In other words, in at least one of the two modes, the ratio of the total duration of the signal conditioning phase to the duration of the non-light-emitting phase is not equal in the data write frame and the hold frame. This is mainly because the signal conditioning phases included in the data write frame and the hold frame differ. Firstly, the types of signal conditioning phases included in the data write frame and the hold frame differ; for example, the data write frame may include a signal conditioning phase for data writing, while the hold frame may not. Secondly, even if the data write frame and the hold frame include the same type of signal conditioning phase, such as the phase that provides the bias adjustment signal VR for the driving transistor, ... The signal conditioning phase has different durations in the data writing frame and the holding frame. Therefore, in this embodiment of the invention, there will be a relationship of Wd1 / Ld1≠Wm1 / Lm1 and / or Wd2 / Ld2≠Wm2 / Lm2. That is to say, in this embodiment of the invention, based on the function of the data writing frame and the holding frame, and the difference in the signal conditioning phase they contain, the duration of the non-light-emitting phase in the data writing frame and the holding frame can be adjusted separately so that the duration of the non-light-emitting phase in both the data writing frame and the holding frame reaches an optimal state, without being affected by the other, thus ensuring that the display panel can achieve a better display effect in different modes.

[0130] In one embodiment of the present invention, Wd1 / Ld1 > Wm1 / Lm1, and / or Wd2 / Ld2 > Wm2 / Lm2.

[0131] Specifically, in at least one of the two modes, the data writing frame may include a data writing phase, a reset phase for the driving transistor, and a signal conditioning phase such as a phase for providing a bias adjustment signal VR to the driving transistor. In some cases, even if the hold frame includes a signal conditioning phase, it may only include the phase for providing a bias adjustment signal VR to the driving transistor. In some cases, the hold frame may not include a signal conditioning phase at all. Therefore, in the embodiments of the present invention, there may be a relationship of Wd1 / Ld1 > Wm1 / Lm1 and / or Wd2 / Ld2 > Wm2 / Lm2. Based on this relationship, the display panel can achieve the corresponding display requirements.

[0132] In one embodiment of the present invention, Wd1 / Ld1 < Wm1 / Lm1, and / or Wd2 / Ld2 < Wm2 / Lm2.

[0133] Specifically, in at least one of the two modes, for some special functions in the display panel, the hold frame may also contain some special signal conditioning phases with relatively long signal durations, such as the phase mentioned above that provides bias conditioning signal VR for driving transistors. In order to ensure the effectiveness of this signal conditioning phase in the hold frame, the duration of the non-light-emitting phase in the hold frame obviously needs to be appropriately maintained at a relatively long state. For example, if both the data writing frame and the hold frame have signal conditioning phases, the duration of the signal conditioning phase in the data writing frame can be shortened or even canceled, and this time can be incorporated into the hold frame to extend the duration of the signal conditioning phase in the hold frame. Therefore, in the embodiments of the present invention, there will be a relationship of Wd1 / Ld1 < Wm1 / Lm1, and / or Wd2 / Ld2 < Wm2 / Lm2. Based on this relationship, the display panel can achieve the corresponding display requirements.

[0134] In one embodiment of the present invention, Wd1 / Ld1 = Wd2 / Ld2, and / or Wm1 / Lm1 = Wm2 / Lm2.

[0135] Specifically, in the embodiments of the present invention, the ratio of the total time length of the signal conditioning phase in the data writing frame to the time length of the non-light-emitting phase in different modes is equal, and / or, the ratio of the total time length of the signal conditioning phase in the hold frame to the time length of the non-light-emitting phase in different modes is equal. That is, the embodiments of the present invention compare the data writing frames in different modes and the hold frames in different modes. Under the condition that Wd1 / Ld1=Wd2 / Ld2 and / or Wm1 / Lm1=Wm2 / Lm2, the total time length of the signal conditioning phase and the time length of the non-light-emitting phase in the data writing frames and hold frames in different modes can be uniformly adjusted without adjusting them separately, which can greatly simplify the signal control logic.

[0136] In one embodiment of the present invention, there may also be cases where Wd1 / Ld1≠Wd2 / Ld2, and / or Wm1 / Lm1≠Wm2 / Lm2.

[0137] Specifically, in the embodiments of the present invention, the ratio of the total time length of the signal conditioning phase in the data writing frame to the time length of the non-light-emitting phase is not equal in different modes, and / or, the ratio of the total time length of the signal conditioning phase to the time length of the non-light-emitting phase in the frame is not equal in different modes. That is to say, the total time length of the signal conditioning phase and the time length of the non-light-emitting phase are set to change non-proportionally in different modes. For example, when switching from the first mode to the second mode, the time length of the non-light-emitting phase is shortened. At this time, the total time length of the signal conditioning phase is adjusted according to Wd1 / Ld1≠Wd2 / Ld2, and / or Wm1 / Lm1≠Wm2 / Lm2. This can ensure that the total time length of the signal conditioning phase in each mode is in an optimal state, thereby meeting the signal conditioning requirements of different modes and ensuring that the display panel has a good display effect in different modes.

[0138] In one embodiment of the present invention, there may also be cases where Wd1 / Ld1 < Wd2 / Ld2, and / or Wm1 / Lm1 < Wm2 / Lm2.

[0139] Specifically, in the embodiments of the present invention, the ratio of the total time length of the signal conditioning phase in the data writing frame to the time length of the non-light-emitting phase is not equal in different modes, and / or, the ratio of the total time length of the signal conditioning phase to the time length of the non-light-emitting phase in the frame is kept unequal in different modes. That is to say, the total time length of the signal conditioning phase and the time length of the non-light-emitting phase are set to change non-proportionally in different modes. For example, when switching from the first mode to the second mode, the time length of the non-light-emitting phase is shortened. At this time, the total time length of the signal conditioning phase is adjusted according to Wd1 / Ld1 < Wd2 / Ld2, and / or Wm1 / Lm1 < Wm2 / Lm2, so that the change in the total time length of the signal conditioning phase caused by the change of the working mode is relatively small. That is, the total time length of the signal conditioning phase is relatively large in the second mode EMT2, ensuring the effectiveness of the signal conditioning phase in the second mode EMT2. That is, the total time length of the signal conditioning phase in each mode is in an optimal state, thereby meeting the signal conditioning requirements of different modes and ensuring that the display panel has a good display effect in different modes.

[0140] It should be noted that in one embodiment of the present invention, there may also be cases where Wd1 / Ld1 > Wd2 / Ld2, and / or Wm1 / Lm1 > Wm2 / Lm2. Since Ld1 > Ld2, and / or Lm1 > Lm2, that is, the non-light-emitting phase of the first mode EMT1 is relatively long, and the non-light-emitting phase of the second mode EMT2 is relatively short, obviously the total time length of the signal conditioning phase under the first mode EMT1 can be set to be relatively large, and the total time length of the signal conditioning phase under the second mode EMT2 can be set to be relatively small, so as to ensure that the total time length of the signal conditioning phase in each mode is in an optimal state, thereby meeting the signal conditioning requirements of different modes and ensuring that the display panel has a good display effect in different modes.

[0141] In one embodiment of the present invention, reference is made to... Figure 15 , Figure 15 This is a partial timing diagram of another pixel circuit operation provided by an embodiment of the present invention. In the first mode EMT1, the time length between the start of the non-light-emitting phase and the start of the first signal conditioning phase in the data writing frame is Tda1, and the time length between the start of the non-light-emitting phase and the start of the first signal conditioning phase in the holding frame is Tma1.

[0142] In the second mode EMT2, the time length between the start of the non-light-emitting phase and the start of the first signal conditioning phase in the data writing frame is Tda2, and the time length between the start of the non-light-emitting phase and the start of the first signal conditioning phase in the hold frame is Tma2.

[0143] Where Tda1≠Tma1, and / or, Tad2≠Tma2.

[0144] Specifically, in this embodiment of the invention, whether it is the data write frame and hold frame in the first mode EMT1 or the data write frame and hold frame in the second mode EMT2, the adjustment of the time length of the non-light-emitting phase in the data write frame and hold frame in different modes is achieved by adjusting the time length of the time period between the start of the non-light-emitting phase and the start of the first signal conditioning phase. This is mainly because after the signal conditioning phase starts, adjusting the time length of the non-light-emitting phase will involve adjusting the time of the signal conditioning phase. Therefore, adjusting Tda1, Tma1, Tad2, and Tma2 before the start of the signal conditioning phase can fully avoid the adverse effects on the time of the signal conditioning phase and ensure the display effect in different modes.

[0145] In any mode, based on the type of signal conditioning phase included in the data writing frame and the type of signal conditioning phase included in the hold frame, the time length between the start of the non-light-emitting phase and the start of the first signal conditioning phase can be flexibly set according to the principle of Tda1≠Tma1 and / or Tad2≠Tma2. This allows for the adjustment of the time length of the non-light-emitting phase while ensuring the effectiveness of the first signal conditioning phase and preventing interference with the signal of the first signal conditioning phase, thereby improving the display effect of the display panel.

[0146] In one embodiment of the present invention, there are cases where Tda1 < Tma1 and / or Tda2 < Tma2.

[0147] Specifically, in either the first mode EMT1 or the second mode EMT2, when the duration of the non-light-emitting phase is limited, the number of signal conditioning stages included in the data writing frame is relatively large, while the number of signal conditioning stages included in the hold frame is relatively small. In order to ensure that the interval between each signal conditioning stage in the data writing frame can be reasonably allocated and to avoid signal interference between each signal conditioning stage in the data writing frame, in this embodiment of the invention, the duration of the time period between the start of the non-light-emitting phase and the start of the first signal conditioning stage is flexibly set according to Tda1 < Tma1 and / or Tda2 < Tma2. This allows for adjustment of the duration of the non-light-emitting phase while ensuring the effectiveness of each signal conditioning stage, thereby improving the display effect of the display panel.

[0148] It should be noted that in one embodiment of the present invention, there may also be cases where Tda1 > Tma1 and / or Tda2 > Tma2. In either the first mode EMT1 or the second mode EMT2, the time period between the start of the non-light-emitting phase in the data writing frame and the start of the first signal conditioning phase is kept to a relatively long length, so as to ensure the integrity and effectiveness of the first signal conditioning phase, avoid interference with the signal in the first signal conditioning phase, and improve the display effect of the display panel.

[0149] In one embodiment of the present invention, there are cases where Tda1 = Tda2 and / or Tma2 = Tma2.

[0150] Specifically, in the embodiments of the present invention, the time length of the period from the start of the non-light-emitting phase to the start of the first signal conditioning phase in the data writing frame under different modes is equal, and / or, the time length of the period from the start of the non-light-emitting phase to the start of the first signal conditioning phase in the hold frame under different modes is equal. That is, the embodiments of the present invention are based on the comparison of data writing frames under different modes and the comparison of hold frames under different modes. Under the condition that Tda1=Tda2 and / or Tma2=Tma2, the time length of the period from the start of the non-light-emitting phase to the start of the first signal conditioning phase in the data writing frame and hold frame under different modes can be uniformly adjusted without adjusting them separately, which can greatly simplify the signal control logic.

[0151] In one embodiment of the present invention, there may also be cases where Tda1≠Tda2 and / or Tma1≠Tma2.

[0152] Specifically, in the embodiments of the present invention, the time length of the period between the start of the non-light-emitting phase and the start of the first signal conditioning phase in the data writing frame is not equal in different modes, and / or, the time length of the period between the start of the non-light-emitting phase and the start of the first signal conditioning phase in the frame is kept not equal in different modes. That is to say, the time length of the period between the start of the non-light-emitting phase and the start of the first signal conditioning phase is set to change non-comparatively in different modes. For example, when switching from the first mode to the second mode, the time length of the non-light-emitting phase is shortened. At this time, the time length of the period between the start of the non-light-emitting phase and the start of the first signal conditioning phase is adjusted according to Tda1≠Tda2, and / or Tma1≠Tma2, so as to meet the signal conditioning requirements of different modes and ensure that the display panel has a good display effect in different modes.

[0153] In one embodiment of the present invention, there may also be cases where Tda1 > Tda2 and / or Tma1 > Tma2.

[0154] Specifically, in this embodiment of the invention, since Ld1 > Ld2 and / or Lm1 > Lm2, the non-light-emitting phase of the first mode EMT1 is relatively long, and the non-light-emitting phase of the second mode EMT2 is relatively short. Obviously, the time period between the start of the non-light-emitting phase and the start of the first signal conditioning phase in the first mode EMT1 can be set to be relatively large, and the time period between the start of the non-light-emitting phase and the start of the first signal conditioning phase in the second mode EMT2 can be set to be relatively small. This ensures that the time period between the start of the non-light-emitting phase and the start of the first signal conditioning phase in each mode is in an optimal state, thereby meeting the signal conditioning requirements of different modes and ensuring that the display panel has a good display effect in different modes.

[0155] It should be noted that in one embodiment of the present invention, there may be cases where Tda1 < Tda2 and / or Tma1 < Tma2. That is to say, in the embodiment of the present invention, the sizes of Tda1, Tma1, Tda2, and Tma2 can be reasonably set according to the actual display requirements and the type and function of the signal conditioning stages included in the data writing frame and the holding frame, especially the type and function of the first signal conditioning stage, so as to ensure that the time length between the start of the non-light-emitting stage and the start of the first signal conditioning stage in each mode is in an optimal state, thereby meeting the signal conditioning requirements of different modes and ensuring that the display panel has a good display effect in different modes.

[0156] In one embodiment of the present invention, reference is made to... Figure 16 , Figure 16 This is a partial timing diagram of another pixel circuit operation provided by an embodiment of the present invention. In the first mode EMT1, the time length between the end of the last signal conditioning stage and the end of the non-light emission stage in the data writing frame is Tdb1, and the time length between the end of the last signal conditioning stage and the end of the non-light emission stage in the hold frame is Tmb1.

[0157] In the second mode EMT2, the time length between the end of the last signal conditioning phase and the end of the non-emission phase in the data write frame is Tdb2, and the time length between the end of the last signal conditioning phase and the end of the non-emission phase in the hold frame is Tmb2.

[0158] Where Tdb1≠Tmb1, and / or, Tdb2≠Tmb2.

[0159] In this embodiment of the invention, whether it is the data write frame and hold frame in the first mode EMT1 or the data write frame and hold frame in the second mode EMT2, the adjustment of the non-light-emitting phase in the data write frame and hold frame in different modes is achieved by adjusting the time length between the end of the last signal conditioning phase and the end of the non-light-emitting phase. The pulse region to be adjusted does not involve the signal conditioning phase. Therefore, by adjusting Tdb1, Tmb1, Tdb2, and Tmb2 after the end of the last signal conditioning phase, the adverse effects of the signal conditioning phase can be fully avoided, ensuring the display effect in different modes.

[0160] In any mode, based on the type of signal conditioning phase included in the data writing frame and the type of signal conditioning phase included in the hold frame, the time length between the end of the last signal conditioning phase and the end of the non-light-emitting phase can be flexibly set according to the principle that Tdb1≠Tmb1 and / or Tdb2≠Tmb2. This allows for adjustment of the time length of the non-light-emitting phase while ensuring the integrity and effectiveness of the last signal conditioning phase, preventing interference with the signal in the last signal conditioning phase, and thus improving the display effect of the display panel.

[0161] In one embodiment of the present invention, there are cases where Tdb1 < Tmb1 and / or Tdb2 < Tmb2.

[0162] Specifically, in either the first mode EMT1 or the second mode EMT2, when the duration of the non-light-emitting phase is limited, the number of signal conditioning phases included in the data writing frame is relatively large, while the number of signal conditioning phases included in the hold frame is relatively small. In order to ensure that the interval between each signal conditioning phase in the data writing frame can be reasonably allocated and to avoid signal interference between each signal conditioning phase in the data writing frame, in this embodiment of the invention, the duration of the time period between the end of the last signal conditioning phase and the end of the non-light-emitting phase is flexibly set according to Tdb1 < Tmb1 and / or Tdb2 < Tmb2. This allows for adjustment of the duration of the non-light-emitting phase while ensuring the effectiveness of each signal conditioning phase, thereby improving the display effect of the display panel.

[0163] It should be noted that in one embodiment of the present invention, there may also be cases where Tdb1 > Tmb1 and / or Tdb2 > Tmb2. In either the first mode EMT1 or the second mode EMT2, the time period between the end of the last signal conditioning stage and the end of the non-light emission stage in the data writing frame is kept to a relatively long length, so as to ensure the integrity and effectiveness of the last signal conditioning stage, avoid interference with the signal of the last signal conditioning stage, and improve the display effect of the display panel.

[0164] In one embodiment of the present invention, there are cases where Tdb1 = Tdb2 and / or Tmb1 = Tmb2.

[0165] Specifically, in the embodiments of the present invention, the time length between the end of the last signal conditioning stage and the end of the non-light emission stage in the data writing frame under different modes is equal, and / or, the time length between the end of the last signal conditioning stage and the end of the non-light emission stage in the hold frame under different modes is equal. That is, the embodiments of the present invention are for the comparison of data writing frames under different modes and the comparison of hold frames under different modes. Under the condition that Tdb1=Tdb2 and / or Tmb1=Tmb2, the time length between the end of the last signal conditioning stage and the end of the non-light emission stage in the data writing frame and hold frame under different modes can be uniformly adjusted, without having to adjust them separately, which can greatly simplify the signal control logic.

[0166] In one embodiment of the present invention, there may also be cases where Tdb1≠Tdb2 and / or Tmb1≠Tmb2.

[0167] Specifically, in the embodiments of the present invention, the time length between the end of the last signal conditioning phase and the end of the non-light-emitting phase in the data writing frame is not equal in different modes, and / or, the time length between the end of the last signal conditioning phase and the end of the non-light-emitting phase in the frame is kept not equal in different modes. That is to say, the time length between the end of the last signal conditioning phase and the end of the non-light-emitting phase is set to change non-comparatively in different modes. For example, when switching from the first mode to the second mode, the time length of the non-light-emitting phase is shortened. At this time, the time length between the end of the last signal conditioning phase and the end of the non-light-emitting phase is adjusted according to Tdb1≠Tdb2, and / or Tmb1≠Tmb2, so as to meet the signal conditioning requirements of different modes and ensure that the display panel has a good display effect in different modes.

[0168] In one embodiment of the present invention, there may also be cases where Tdb1 > Tdb2 and / or Tmb1 > Tmb2.

[0169] Specifically, in this embodiment of the invention, since Ld1 > Ld2 and / or Lm1 > Lm2, the non-light-emitting phase of the first mode EMT1 is relatively long, and the non-light-emitting phase of the second mode EMT2 is relatively short. Obviously, the time period between the end of the last signal conditioning phase and the end of the non-light-emitting phase in the first mode EMT1 can be set to be relatively large, and the time period between the end of the last signal conditioning phase and the end of the non-light-emitting phase in the second mode EMT2 can be set to be relatively small. This ensures that the time period between the end of the last signal conditioning phase and the end of the non-light-emitting phase in each mode is in an optimal state, thereby meeting the signal conditioning requirements of different modes and ensuring that the display panel has a good display effect in different modes.

[0170] It should be noted that in one embodiment of the present invention, there may be cases where Tdb1 < Tdb2 and / or Tmb1 < Tmb2. That is to say, in the embodiment of the present invention, the sizes of Tdb1, Tmb1, Tdb2, and Tmb2 can be reasonably set according to the actual display requirements and the type and function of the signal conditioning stages included in the data writing frame and the holding frame, especially the type and function of the last signal conditioning stage. This ensures that the time length between the end of the last signal conditioning stage and the end of the non-light-emitting stage in each mode is in an optimal state, thereby meeting the signal conditioning requirements of different modes and ensuring that the display panel has a good display effect in different modes.

[0171] In one embodiment of the present invention, reference is made to... Figure 17 , Figure 17 This is a schematic diagram of a full-screen display panel provided in an embodiment of the present invention, with reference to... Figure 18 , Figure 18 This is a schematic diagram of a foldable screen display panel provided in an embodiment of the present invention. The display panel includes a first pixel circuit and a second pixel circuit.

[0172] During at least a portion of the time period during the operation of the display panel, the first pixel circuit operates in the first mode and the second pixel circuit operates in the second mode.

[0173] The display panel includes a first display area and a second display area, wherein the first display area can be... Figure 17 The AA area in the middle, the second display area can be Figure 17 The BB area, or the first display area, can be Figure 18 The CC area in the middle, the second display area can be Figure 18 The DD region in the middle.

[0174] The first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area.

[0175] Specifically, in the embodiments of the present invention, the first pixel circuit and the second pixel circuit are located in different display areas. For example, the first pixel circuit is located in... Figure 17 In the AA region, the second pixel circuit is located Figure 17 The BB region, or the first pixel circuit, is located in Figure 18 In the CC region, the second pixel circuit is located Figure 18 In the DD area of ​​the display panel, during at least a portion of the working time of the display panel, i.e., within the same time period, the first pixel circuit operates in the first mode, while the second pixel circuit operates in the second mode, enabling the AA area and BB area to achieve differentiated display within the same time period, or enabling the CC area and DD area to achieve differentiated display within the same time period. For example, within the same time period, the area where the first pixel circuit is located displays at low brightness, while the area where the second pixel circuit is located displays at high brightness. In the low brightness display area, e-book reading can be performed, while in the high brightness display area, sports events can be watched, thus achieving differentiated display of the display panel in different zones.

[0176] It should be noted that the first mode and the second mode can be two modes with different light emission brightness, or two modes with different frame rates of screen refresh, etc. In the embodiments of the present invention, the first mode and the second mode are two display modes that exist in two areas of the display panel at the same time.

[0177] Furthermore, in one embodiment of the present invention, the data refresh frequency of the first pixel circuit is Fs1, and the data refresh frequency of the second pixel circuit is Fs2; wherein, Fs1≠Fs2.

[0178] Specifically, in this embodiment of the invention, the first pixel circuit and the second pixel circuit have different data refresh frequencies. When the display panel uses a higher data refresh frequency driving method for display, the number of frames is zero or very small within one data refresh cycle, and the gate of the driving transistor T0 maintains the input of the data signal Vdata. That is, the gate potential of the driving transistor T0 refreshes more frequently, enabling high-brightness dynamic display, etc. When the display panel uses a lower data refresh frequency driving method for display, the number of frames is relatively larger within one data refresh cycle, and the gate potential of the driving transistor T0 remains unchanged for a long time within one data refresh cycle, enabling low-brightness static display, etc. Therefore, in this embodiment of the invention, by setting the data refresh frequencies of the first pixel circuit and the second pixel circuit to be different, the display panel can achieve zoned differentiated display.

[0179] In one embodiment of the present invention, there exists a case where Fs1 < Fs2. The three parameters, namely, data refresh frequency, luminous brightness of the display panel, and frame frequency of the surface refresh frame, are generally positively correlated. For example, a higher data refresh frequency will result in higher luminous brightness and a higher frame frequency of the surface refresh frame.

[0180] It should be noted that in one embodiment of the present invention, there may be a situation where Fs1 > Fs2. For example, under low brightness display, a higher data refresh rate is still required to meet the actual application needs of users and ensure the feasibility of some special display requirements.

[0181] In one embodiment of the present invention, the operation of the display panel includes a first time period and a second time period. During the first time period, the pixel circuit operates in a first mode, and during the second time period, the pixel circuit operates in a second mode.

[0182] Specifically, in the embodiments of the present invention, the first mode and the second mode are two display modes that exist in the same area of ​​the display panel at different time periods. For example, high brightness display is performed in the first time period and low brightness display is performed in the second time period.

[0183] Accordingly, embodiments of the present invention also provide a display device, including the display panel provided in any of the above embodiments.

[0184] refer to Figure 19 , Figure 19 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, wherein the display device 1000 provided in the embodiment of the present invention can be a mobile terminal device.

[0185] In other embodiments of the present invention, the display device provided by the present invention may also be an electronic display device such as a mobile phone, computer, or vehicle terminal, and the present invention does not impose specific limitations on it.

[0186] The above provides a detailed description of the display panel and display device provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0187] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0188] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0189] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, The display panel includes: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module and a signal conditioning module; The driving module includes a driving transistor; One frame of the display panel includes a non-light-emitting phase and a light-emitting phase. The non-light-emitting phase includes a signal conditioning phase. In the signal conditioning phase, the signal conditioning module provides a preset signal to the driving transistor. The image refresh frame of the pixel circuit includes a data write frame and a hold frame. The data write frame includes p signal conditioning stages, p≥1, and / or the hold frame includes q signal conditioning stages, q≥0. The operation of the pixel circuit includes a first mode and a second mode. In the first mode, the duration of the non-light-emitting phase of the data writing frame is Ld1, and the duration of the non-light-emitting phase of the holding frame is Lm1; In the second mode, the duration of the non-light-emitting phase of the data writing frame is Ld2, and the duration of the non-light-emitting phase of the holding frame is Lm2; Where Ld1 > Ld2, and / or Lm1 > Lm2; In the first mode, the total duration of the signal conditioning phase in the data writing frame is Wd1, and the total duration of the signal conditioning phase in the holding frame is Wm1. In the second mode, the total duration of the signal conditioning phase in the data writing frame is Wd2, and the total duration of the signal conditioning phase in the hold frame is Wm2. Where Wd1 / Ld1≠Wm1 / Lm1; and / or, Wd2 / Ld2≠Wm2 / Lm2; or, In the first mode, in the data writing frame, the time length between the start of the non-light-emitting phase and the start of the first signal conditioning phase is Tda1, and in the holding frame, the time length between the start of the non-light-emitting phase and the start of the first signal conditioning phase is Tma1. In the second mode, the time length of the period between the start of the non-light-emitting phase and the start of the first signal conditioning phase in the data writing frame is Tda2, and the time length of the period between the start of the non-light-emitting phase and the start of the first signal conditioning phase in the holding frame is Tma2. Where Tda1≠Tma1; and / or, Tad2≠Tma2; or, In the first mode, in the data writing frame, the time length between the end of the last signal conditioning phase and the end of the non-light emission phase is Tdb1, and in the holding frame, the time length between the end of the last signal conditioning phase and the end of the non-light emission phase is Tmb1. In the second mode, in the data writing frame, the time length between the end of the last signal conditioning phase and the end of the non-light emission phase is Tdb2, and in the holding frame, the time length between the end of the last signal conditioning phase and the end of the non-light emission phase is Tmb2. Where Tdb1≠Tmb1; and / or, Tdb2≠Tmb2.

2. The display panel according to claim 1, characterized in that, In the first mode, the luminous brightness of the display panel is B1, and in the second mode, the luminous brightness of the display panel is B2. Where B1 < B2.

3. The display panel according to claim 1, characterized in that, In the first mode, the frame rate of the screen refresh frame of the display panel is Fv1, and in the second mode, the frame rate of the screen refresh frame of the display panel is Fv2. Where Fv1 < Fv2.

4. The display panel according to claim 1, characterized in that, In the first mode, the duration of one frame of the screen refresh frame of the display panel is S1; in the second mode, the duration of one frame of the screen refresh frame of the display panel is S2. Where S1 > S2.

5. The display panel according to claim 1, characterized in that, The display panel includes a first pixel circuit and a second pixel circuit; During at least a portion of the time period during the operation of the display panel, the first pixel circuit operates in the first mode, and the second pixel circuit operates in the second mode.

6. The display panel according to claim 5, characterized in that, The data refresh frequency of the first pixel circuit is Fs1, and the data refresh frequency of the second pixel circuit is Fs2; Where Fs1≠Fs2.

7. The display panel according to claim 6, characterized in that, Fs1 < Fs2.

8. The display panel according to claim 6, characterized in that, Fs1 > Fs2.

9. The display panel according to claim 5, characterized in that, The display panel includes a first display area and a second display area; The first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area.

10. The display panel according to claim 1, characterized in that, The operation of the display panel includes a first time period and a second time period. During the first time period, the pixel circuit operates in the first mode, and during the second time period, the pixel circuit operates in the second mode.

11. The display panel according to claim 1, characterized in that, Ld1=Lm1, and / or, Ld2=Lm2.

12. The display panel according to claim 1, characterized in that, Ld1≠Lm1, and / or, Ld2≠Lm2.

13. The display panel according to claim 12, characterized in that, Ld1 > Lm1, and / or Ld2 > Lm2.

14. The display panel according to claim 12, characterized in that, Ld1 < Lm1, and / or, Ld2 < Lm2.

15. The display panel according to claim 1, characterized in that, Wd1 / Ld1 > Wm1 / Lm1; and / or, Wd2 / Ld2>Wm2 / Lm2.

16. The display panel according to claim 1, characterized in that, Wd1 / Ld1 < Wm1 / Lm1; and / or, Wd2 / Ld2<Wm2 / Lm2.

17. The display panel according to claim 1, characterized in that, Wd1 / Ld1 = Wd2 / Ld2; and / or, Wm1 / Lm1=Wm2 / Lm2.

18. The display panel according to claim 1, characterized in that, Wd1 / Ld1≠Wd2 / Ld2; and / or, Wm1 / Lm1≠Wm2 / Lm2.

19. The display panel according to claim 18, characterized in that, Wd1 / Ld1 < Wd2 / Ld2; and / or, Wm1 / Lm1 < Wm2 / Lm2.

20. The display panel according to claim 1, characterized in that, Tda1 < Tma1; and / or, Tda2 < Tma2.

21. The display panel according to claim 1, characterized in that, Tda1=Tda2; and / or, Tma2=Tma2.

22. The display panel according to claim 1, characterized in that, Tda1≠Tda2; and / or, Tma1≠Tma2.

23. The display panel according to claim 22, characterized in that, Tda1 > Tda2; and / or, Tma1 > Tma2.

24. The display panel according to claim 1, characterized in that, Tdb1 < Tmb1; and / or, Tdb2 < Tmb2.

25. The display panel according to claim 1, characterized in that, Tdb1=Tdb2; and / or, Tmb1=Tmb2.

26. The display panel according to claim 1, characterized in that, Tdb1≠Tdb2; and / or, Tmb1≠Tmb2.

27. The display panel according to claim 26, characterized in that, Tdb1 > Tdb2; and / or, Tmb1 > Tmb2.

28. The display panel according to claim 1, characterized in that, The signal conditioning module is a data writing module, and the preset signal is a data signal; The data writing module is connected to the first pole of the driving transistor. During the signal conditioning phase, the data writing module is turned on and provides the data signal to the driving transistor.

29. The display panel according to claim 1, characterized in that, The signal conditioning module is a reset module, and the preset signal is a reset signal; The reset module is connected to the gate of the driving transistor. During the signal conditioning phase, the reset module is turned on and provides a reset signal to the driving transistor.

30. The display panel according to claim 28 or 29, characterized in that, q=0。 31. The display panel according to claim 1, characterized in that, The signal conditioning module is a bias conditioning module, and the preset signal is a bias conditioning signal; The bias adjustment module is connected to the first or second terminal of the driving transistor. During the signal adjustment phase, the bias adjustment module is turned on and provides a bias adjustment signal to the driving transistor.

32. The display panel according to claim 31, characterized in that, q≥1。 33. The display panel according to claim 31, characterized in that, The display panel includes a data writing module and the bias adjustment module; The operation of the display panel includes a data writing stage and a signal conditioning stage; During the data writing phase, the data writing module is turned on, the bias adjustment module is turned off, and the data writing module provides a data signal to the driving transistor. During the signal conditioning phase, the data writing module is turned off, the bias conditioning module is turned on, and the bias conditioning module provides the bias conditioning signal to the driving transistor.

34. The display panel according to claim 31, characterized in that, The bias adjustment module is reused as a data writing module; The operation of the display panel includes a data writing stage and a signal conditioning stage; During the data writing phase, the bias adjustment module is activated, and the bias adjustment module provides a data signal to the driving transistor; During the signal conditioning phase, the bias conditioning module is activated, and the bias conditioning module provides the bias conditioning signal to the driving transistor.

35. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1-34.

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