Pixel circuit and driving method thereof

Abstract

A pixel circuit and a driving method thereof. In the pixel circuit, a pulse amplitude control circuit is coupled between a cathode terminal of a light emitting diode and a system low voltage, generates a driving current of the light emitting diode according to a first and a second control signal, a light emitting control signal and a pulse width control signal, and controls a magnitude of the driving current according to a first and a second reference voltage. A pulse width control circuit is coupled between the pulse amplitude control circuit and the first reference voltage, adjusts a voltage level of a first control terminal according to the first and the second control signal and a scanning voltage, adjusts a voltage level of a second control terminal according to a third reference voltage, and generates the pulse width control signal according to the voltage level of the first control terminal, the voltage level of the second control terminal and the light emitting control signal to control a transient time and a light emitting time of the light emitting diode.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device, and particularly relates to a pixel circuit and a driving method thereof. BACKGROUND

[0002] Organic light emitting diode (OLED), mini light emitting diode (Mini LED) and micro light emitting diode (Micro LED) are main elements used in self-luminous display panels at present. However, the light emitting brightness curve of the mini light emitting diode and the micro light emitting diode is different from that of the organic light emitting diode, that is, the light emitting efficiency point of the mini light emitting diode and the micro light emitting diode changes when operating at the same brightness, resulting in poor light emitting efficiency and large power consumption.

[0003] In addition, the mini light emitting diode and the micro light emitting diode require a large driving current. However, the system high voltage is prone to voltage drop (IR drop) due to the line resistance of the transmission path, resulting in different end point voltages of each pixel, and thus the driving current flowing through the light emitting diode in each pixel is prone to error. In the existing display technology, the display panel is prone to be affected by the threshold voltage variation of the transistor in the pixel circuit, thereby reducing the display quality of the display picture.

[0004] Therefore, how to effectively improve the light emitting efficiency, power consumption, voltage drop and the influence of the threshold voltage variation of the transistor on the pixel circuit will be an important issue for the relevant technical personnel in the field. SUMMARY

[0005] The present application provides a pixel circuit and a driving method thereof, which can control the light emitting diode to operate at the optimal light emitting efficiency point to reduce power consumption, and improve the problem of voltage drop caused by the line resistance of the transmission path and the threshold voltage variation of the transistor in the system high voltage, so as to improve the display quality of the display picture.

[0006] The pixel circuit of the present application comprises a light emitting diode, a pulse amplitude control circuit and a pulse width control circuit. The anode terminal of the light emitting diode is coupled to a system high voltage. The pulse amplitude control circuit is coupled between the cathode terminal of the light emitting diode and a system low voltage, generates a driving current of the light emitting diode according to a first control signal, a second control signal, a light emitting control signal and a pulse width control signal, and controls the magnitude of the driving current according to a first reference voltage and a second reference voltage. The pulse width control circuit has a first control terminal and a second control terminal. The pulse width control circuit is coupled between the pulse amplitude control circuit and the first reference voltage, adjusts the voltage level of the first control voltage according to the first control signal, the second control signal and a scanning voltage, adjusts the voltage level of the second control terminal according to a third reference voltage, and generates the pulse width control signal according to the voltage level of the first control voltage, the voltage level of the second control terminal and the light emitting control signal to control the transient time and the light emitting time of the light emitting diode.

[0007] The driving method of the pixel circuit of the present application comprises: causing the pulse amplitude control circuit to generate a driving current of the light emitting diode according to a first control signal, a second control signal, a light emitting control signal and a pulse width control signal, and to control the magnitude of the driving current according to a first reference voltage and a second reference voltage; causing the pulse width control circuit to adjust the voltage level of the first control terminal according to the first control signal, the second control signal and a scanning voltage; causing the pulse width control circuit to adjust the voltage level of the second control terminal according to a third reference voltage; and causing the pulse width control circuit to generate the pulse width control signal according to the voltage level of the first control terminal, the voltage level of the second control terminal and the light emitting control signal to control the transient time and the light emitting time of the light emitting diode.

[0008] Based on the above, the pixel circuit of the embodiments of the present application can control the light emitting brightness (the magnitude of the driving current) of the light emitting diode through the pulse amplitude control circuit, and control the transient time and the light emitting time of the light emitting diode through the fast rising architecture in the pulse width control circuit. In this way, the pixel circuit can reduce the transient time of the light emitting diode through the fast rising architecture, cause the light emitting diode to operate at the optimal light emitting efficiency point to reduce power consumption, and achieve the effect of improving the voltage drop of the system high voltage caused by the line resistance of the transmission path and the variation of the threshold voltage of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic diagram of a pixel circuit according to an embodiment of the present application.

[0010] Figure 2 is a driving waveform schematic diagram of a pixel circuit according to an embodiment of the present application. Figure 1

[0011] Figures 3A to 3F is a driving waveform schematic diagram of a pixel circuit according to an embodiment of the present application.​Figure 1 Equivalent circuit diagram of the pixel circuit of the embodiment.

[0012] Figure 4 Flowchart of the driving method of the pixel circuit according to the embodiment of the present application.

[0013] Figure 5 Schematic diagram of the pixel circuit according to the embodiment of the present application.

[0014] Figure 6 Driving waveform schematic diagram of the pixel circuit according to the embodiment of the present application. Figure 5

[0015] BRIEF DESCRIPTION OF THE DRAWINGS

[0016] 100, 500: pixel circuit

[0017] 120: pulse amplitude control circuit

[0018] 140: pulse width control circuit

[0019] 400: method

[0020] AP: adjustment phase

[0021] C1, C2, C3, C4, C5: capacitor

[0022] CP: compensation phase

[0023] CT1, CT2: control terminal

[0024] EM: emission control signal

[0025] EP: emission phase

[0026] EP1, EP2: sub-phase

[0027] Id: drive current

[0028] LD1: light emitting diode

[0029] N1, N2, N3, N4, N5, N6, N7: node

[0030] PWCS: pulse width control signal

[0031] RP: reset phase

[0032] S420, S440, S460, S480: step

[0033] S1[n], S1[n+1]: control signal

[0034] ​T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15: transistor

[0035] TFR: pixel period

[0036] TP: turn-off phase

[0037] VDATA: data voltage

[0038] VDD: system high voltage

[0039] VH: high voltage

[0040] VL: low voltage

[0041] VREF1, VREF2, VREF3: reference voltage

[0042] VSS: system low voltage

[0043] VSWEEP: sweep voltage

[0044] VSWH: sweep high voltage

[0045] VSWL: sweep low voltage

[0046] ΔV: voltage variation DETAILED DESCRIPTION

[0047] The term "coupled" (or connected) used in the detailed description of the specification including claims should be interpreted broadly to mean directly connected to or indirectly connected through one or more intermediate components. For example, if a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device or that the first device can be indirectly connected to the second device through one or more intermediate devices or components. In addition, where possible, like reference numerals indicate like components throughout the figures and the written description. Components / elements / steps with the same reference numerals or the same terminology in different embodiments can be referred to each other for relevant description.

[0048] Figure 1 is a schematic diagram of a pixel circuit according to an embodiment of the present application. Please refer to Figure 1In this embodiment, the pixel circuit 100 includes a light emitting diode LD1, a pulse amplitude control circuit 120, and a pulse width control circuit 140. The anode terminal of the light emitting diode LD1 is coupled to a system high voltage VDD. The pulse amplitude control circuit 120 is coupled between the cathode terminal of the light emitting diode LD1 and a system low voltage VSS. The pulse width control circuit 140 is coupled between the pulse amplitude control circuit 120 and a reference voltage VREF1. In one embodiment, the light emitting diode LD1 is, for example, an organic light emitting diode, a sub-millimeter light emitting diode, or other micro light emitting diode, but embodiments of the present application are not limited thereto.

[0049] In this embodiment, the pulse amplitude control circuit 120 generates a driving current Id of the light emitting diode LD1 according to the control signal S1[n], the control signal S[n+1], the light emitting control signal EM, and the pulse width control signal PWCS, and controls the magnitude of the driving current Id (i.e., the light emitting brightness of the light emitting diode LD1) according to the reference voltage VREF1 and the reference voltage VREF2.

[0050] Further, the pulse width control circuit 140 has a control terminal CT1 and a control terminal CT2. The pulse width control circuit 140 adjusts the voltage level of the control terminal CT1 according to the control signal S1[n], the control signal S[n+1], and the scanning voltage VSWEEP. In addition, the pulse width control circuit 140 receives the reference voltage VREF3 at the control terminal CT2, and adjusts the voltage level of the control terminal CT2 according to the reference voltage VREF3. The pulse width control circuit 140 further generates the pulse width control signal PWCS according to the voltage level of the control terminal CT1, the voltage level of the control terminal CT2, and the light emitting control signal EM to control the transient time and the light emitting time of the light emitting diode LD1.

[0051] Specifically, the pulse width control circuit 140 includes transistors T1, T2 and capacitors C1, C2. The first terminal of the transistor T1 is coupled to the reference voltage VREF1, the second terminal of the transistor T1 is coupled to a node N1, and the control terminal of the transistor T1 is coupled to the control terminal CT1. The first terminal of the capacitor C1 is coupled to the node N1, and the second terminal of the capacitor C1 is coupled to a low voltage VL. The first terminal of the transistor T2 is coupled to the node N1, the second terminal of the transistor T2 is coupled to a node N2 at which the pulse width control signal PWCS is generated, and the control terminal of the transistor T2 is coupled to the control terminal CT2. The first terminal of the capacitor C2 is coupled to the node N2, and the second terminal of the capacitor C2 receives the light emitting control signal EM.

[0052] In one embodiment, the pulse width control circuit 140 further includes transistors T3-T6 and capacitor C3. The first terminal of transistor T3 is coupled to node N2, the second terminal of transistor T3 is coupled to low voltage VL, and the control terminal of transistor T3 receives control signal S1[n+1]. The first terminal of transistor T4 is coupled to low voltage VL, the second terminal of transistor T4 is coupled to control terminal CT1, and the control terminal of transistor T4 receives control signal S1[n]. The first terminal of capacitor C3 is coupled to scan voltage VSWEEP, and the second terminal of capacitor C3 is coupled to control terminal CT1. The first terminal of transistor T5 is coupled to control terminal CT1, the second terminal of transistor T5 is coupled to node N3, and the control terminal of transistor T5 receives control signal S1[n+1]. The first and control terminals of transistor T6 are coupled to node N3, and the second terminal of transistor T6 is coupled to data voltage VDATA.

[0053] The pulse amplitude control circuit 120 includes transistors T7-T15 and capacitors C4, C5. The first terminal of transistor T7 is coupled to the cathode terminal of light emitting diode LD1, the second terminal of transistor T7 is coupled to reference voltage VREF1, and the control terminal of transistor T7 receives control signal S1[n+1]. The first terminal of transistor T8 is coupled to the cathode terminal of light emitting diode LD1, the second terminal of transistor T8 is coupled to node N4, and the control terminal of transistor T8 is coupled to node N2 to receive pulse width control signal PWCS. The first terminal of transistor T9 is coupled to node N5, the second terminal of transistor T9 is coupled to node N4, and the control terminal of transistor T9 receives emission control signal EM. The first terminal of capacitor C4 is coupled to node N5, and the second terminal of capacitor C4 is coupled to low voltage VL. The first terminal of transistor T10 is coupled to reference voltage VREF2, the second terminal of transistor T10 is coupled to node N5, and the control terminal of transistor T10 receives control signal S1[n]. The first terminal of transistor T11 is coupled to reference voltage VREF2, the second terminal of transistor T11 is coupled to node N5, and the control terminal of transistor T11 receives control signal S1[n+1]. The first terminal of transistor T12 is coupled to node N4, the second terminal of transistor T12 is coupled to node N6, and the control terminal of transistor T12 is coupled to node N7. The first terminal of capacitor C5 is coupled to node N5, and the second terminal of capacitor C5 is coupled to node N7. The first terminal of transistor T13 is coupled to low voltage VL, the second terminal of transistor T13 is coupled to node N7, and the control terminal of transistor T13 receives control signal S1[n]. The first terminal of transistor T14 is coupled to node N6, the second terminal of transistor T14 is coupled to node N7, and the control terminal of transistor T14 receives control signal S1[n+1]. The first terminal of transistor T15 is coupled to node N6, the second terminal of transistor T15 is coupled to system low voltage VSS, and the control terminal of transistor T15 receives emission control signal EM.

[0054] In an embodiment, transistors T1 and T6 are matched to each other. In an embodiment, the matching means that the transistors have the same size and / or the same threshold voltage. In an embodiment, the control signal S1[n+1] is the next stage control signal S1[n]. In an embodiment, all transistors in the pulse amplitude control circuit 120 and all transistors in the pulse width control circuit 140 are the same type of transistors, such as P-type transistors or N-type transistors, but embodiments of the present application are not limited thereto.

[0055] According to the above, the pulse width control circuit 140 controls and reduces the transient time of the light emitting diode within a gray scale by using the fast rise architecture, which can increase the accuracy of gray scale control, and make the light emitting diode operate at the optimal light emitting efficiency point to reduce power consumption, and achieve the effect of improving the voltage drop caused by the line resistance of the transmission path and the threshold voltage variation of the transistors. In addition, the 15T5C circuit architecture proposed in embodiments of the present application uses all P-type transistors or all N-type transistors, which can simplify the related layout and process method of the pixel circuit 100, and simplify the wiring cost of the overall panel.

[0056] Figure 2 is a driving waveform diagram of a pixel circuit according to an embodiment of the present application. Figure 1 In an embodiment, the pixel circuit 100 has a pixel period TFR, which can be divided into a reset phase RP, a compensation phase CP, an adjustment phase AP, a light emitting phase EP, and an off phase TP. The pixel circuit 100 can operate in the reset phase RP, the compensation phase CP, the adjustment phase AP, the light emitting phase EP, and the off phase TP in sequence. The reset phase RP, the compensation phase CP, the adjustment phase AP, the light emitting phase EP, and the off phase TP do not overlap with each other. In particular, the light emitting phase EP can include a sub-phase EP1 and a sub-phase EP2. Figure 2 For details of the operation of the pixel circuit 100 in each phase, please refer to

[0057] and Figure 2 , Figures 3A to 3F Figures 3A to 3F is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present application. Figure 1 In order to facilitate the illustration, in Figures 3A to 3F , the transistors that are turned off are illustrated by crosses, and the transistors that are turned on are illustrated by no crosses.

[0058] For details of the operation of the pixel circuit 100 in each phase, please refer to Figure 2 and Figure 3A In an embodiment, the pixel circuit 100 has a pixel period TFR, which can be divided into a reset phase RP, a compensation phase CP, an adjustment phase AP, a light emitting phase EP, and an off phase TP. The pixel circuit 100 can operate in the reset phase RP, the compensation phase CP, the adjustment phase AP, the light emitting phase EP, and the off phase TP in sequence. The reset phase RP, the compensation phase CP, the adjustment phase AP, the light emitting phase EP, and the off phase TP do not overlap with each other. In particular, the light emitting phase EP can include a sub-phase EP1 and a sub-phase EP2. Figure 3A ​Fig. 6 is an equivalent circuit diagram of the pixel circuit 100 operating in the reset phase RP. Specifically, in the reset phase RP, the control signal S1 [n] and the reference voltage VREF3 can be set to a low voltage level (e.g., a low voltage VL), while the control signal S1 [n+1], the emission control signal EM, and the scan voltage VSWEEP can be set to a high voltage level (e.g., a high voltage VH and a scan high voltage VSWH, respectively).

[0059] In detail, in the reset phase RP, the pulse width control circuit 140 can provide the low voltage VL to the control terminal CT1 through the on-path of the transistor T4 according to the control signal S1 [n] being pulled low, the control signal S1 [n+1] being pulled high, and the scan voltage VSWEEP being pulled high, to pull the voltage level of the control terminal CT1 low, and provide the low voltage VL to the control terminal CT2 according to the reference voltage VREF3 being pulled low, to pull the voltage level of the control terminal CT2 low. In addition, the pulse width control circuit 140 can also provide the reference voltage VREF1 as the pulse width control signal PWCS through the on-paths of the transistors T1 and T2 according to the voltage level of the control terminal CT1, the voltage level of the control terminal CT2, and the emission control signal EM being pulled high.

[0060] The pulse amplitude control circuit 120 can provide the reference voltage VREF2 to the node N5 through the on-path of the transistor T10 according to the control signal S1 [n] being pulled low and the control signal S1 [n+1] being pulled high, whereby the voltage level of the node N5 is correspondingly pulled high to a voltage value equal to the reference voltage VREF2. The pulse amplitude control circuit 120 can provide the low voltage VL to the node N7 through the on-path of the transistor T13 according to the control signal S1 [n] being pulled low.

[0061] It is noted that the reference voltage VREF2 is greater than the system high voltage VDD, the system high voltage VDD is equal to the reference voltage VREF1, the reference voltage VREF1 is greater than the high voltage VH, and the high voltage VH is greater than the low voltage VL.

[0062] After the reset actions of the nodes are completed, then please refer to Figure 2 and Figure 3B In this embodiment, Figure 3B Fig. 7 is an equivalent circuit diagram of the pixel circuit 100 operating in the compensation phase CP. Specifically, in the compensation phase CP, the control signal S1 [n], the emission control signal EM, and the scan voltage VSWEEP can be set to a high voltage level (e.g., a high voltage VH and a scan high voltage VSWH, respectively), while the control signal S1 [n+1] and the reference voltage VREF3 can be set to a low voltage level (e.g., a low voltage VL).

[0063] In detail, in the compensation phase CP, the pulse width control circuit 140 can provide the data voltage VDATA to the control terminal CT1 through the on-path of the transistors T5 and T6 according to the pulled-up control signal S1[n], the pulled-down control signal S1[n+1] and the pulled-up scanning voltage VSWEEP, so as to pull up the voltage level of the control terminal CT1. Since the transistor T1 and the transistor T6 are matched with each other, the control terminal CT1 is further charged, so that the voltage level of the control terminal CT1 is adjusted to be the voltage difference between the data voltage VDATA and the threshold voltage VTH6 of the transistor T6 (i.e., VDATA- |VTH6|). Therefore, storing the threshold voltage VTH6 of the transistor T6 on the control terminal CT1 can compensate the threshold voltage of the transistor T1.

[0064] It is worth noting that the transistor T1 at this time can form a diode through the on-path of the transistor T6 according to the connection mode of the diode connection, so as to compensate the threshold voltage VTH1, thereby improving the compensation accuracy.

[0065] In addition, the pulse width control circuit 140 can provide the low voltage VL to the control terminal CT2 according to the pulled-down reference voltage VREF3, so as to pull down the voltage level of the control terminal CT2. Furthermore, the pulse width control circuit 140 can also discharge the node N1 through the on-path of the transistor T2 according to the voltage level of the control terminal CT1, the voltage level of the control terminal CT2 and the pulled-up emission control signal EM, so that the voltage level of the node N1 is adjusted to be the sum of the low voltage VL and the threshold voltage VTH2 of the transistor T2 (i.e., VL+ |VTH2|), and the voltage level of the node N2 is adjusted to be the low voltage VL to provide the low voltage VL as the pulse width control signal PWCS.

[0066] The pulse amplitude control circuit 120 can provide the reference voltage VREF2 to the node N5 through the on-path of the transistor T11 according to the pulled-up control signal S1[n] and the pulled-down control signal S1[n+1], thereby correspondingly pulling up the voltage level of the node N5 to be equal to the reference voltage VREF2. The pulse amplitude control circuit 120 can charge the node N7 through the on-paths of the transistors T7, T8, T12 and T14 according to the pulled-down control signal S1[n+1] and the voltage level of the node N2, so that the voltage level of the node N7 is adjusted to be the voltage difference between the reference voltage VREF1 and the threshold voltage VTH12 of the transistor T12 (i.e., VREF1- |VTH12|).

[0067] After the compensation actions of the nodes are completed, then please refer to Figure 2 and Figure 3CIn the present embodiment, Figure 3C is an equivalent circuit diagram of the pixel circuit 100 when the pixel circuit 100 operates in the adjustment phase AP. Specifically, in the adjustment phase AP, the control signal S1[n], the control signal S1[n+1], the reference voltage VREF3, and the emission control signal EM can be set to a high voltage level (e.g., a high voltage VH), and the scan voltage VSWEEP can be set to a voltage that decreases at a predetermined slope. In this regard, the present embodiment does not limit the value of the predetermined slope.

[0068] In detail, in the adjustment phase AP, the pulse width control circuit 140 can cause the voltage level of the control terminal CT1 to be adjusted to a voltage difference between the data voltage VDATA1 and the threshold voltage VTH6 of the transistor T6, minus the voltage variation AVSWEEP of the scan voltage VSWEEP, by the coupling effect of the capacitor C3, in accordance with the control signal S1[n] being pulled high, the control signal S1[n+1] being pulled high, and the scan voltage VSWEEP being pulled low at the predetermined slope. That is, the voltage level of the control terminal CT1 at this time is VDATA1 - |VTH5| - AVSWEEP. It should be noted that the voltage variation AVSWEEP of the scan voltage VSWEEP is a voltage difference between the scan high voltage VSWH and the current scan voltage VSWEEP.

[0069] Further, the pulse width control circuit 140 can provide the high voltage VH to the control terminal CT2 to pull up the voltage level of the control terminal CT2, in accordance with the reference voltage VREF3 being pulled high. The pulse width control circuit 140 can also provide the low voltage VL as the pulse width control signal PWCS, in accordance with the voltage level of the control terminal CT1, the voltage level of the control terminal CT2, and the emission control signal EM being pulled high.

[0070] After the adjustment actions of the nodes are completed, then please refer to Figure 2 , Figure 3D and Figure 3E In the present embodiment, Figure 3D is an equivalent circuit diagram of the pixel circuit 100 when the pixel circuit 100 operates in the sub-phase EP1 of the emission phase EP, Figure 3E is an equivalent circuit diagram of the pixel circuit 100 when the pixel circuit 100 operates in the sub-phase EP2 of the emission phase EP. Specifically, in the emission phase EP, the control signal S1[n], the control signal S1[n+1], and the reference voltage VREF3 can be set to a high voltage level (e.g., a high voltage VH), the emission control signal EM can be set to a low voltage level (e.g., a low voltage LH), and the scan voltage VSWEEP can be set to a voltage that decreases at a predetermined slope, which is the same as in the adjustment phase AP.

[0071] In detail, in the sub-stage EP1 of the light emitting stage EP, the pulse width control circuit 140 can provide the voltage difference between the data voltage VDATA1 and the threshold voltage VTH6 of the transistor T6 minus the voltage variation ΔVSWEEP of the scanning voltage VSWEEP to the control terminal CT1 according to the pulled-up control signal S1[n], the pulled-up control signal S1[n+1] and the pulled-down scanning voltage VSWEEP, so as to pull up the voltage level of the control terminal CT1. That is, the voltage level of the control terminal CT1 at this time is also VDATA1 - |VTH5| - ΔVSWEEP.

[0072] Further, the pulse width control circuit 140 can provide the high voltage VH to the control terminal CT2 according to the pulled-up reference voltage VREF3, so as to pull up the voltage level of the control terminal CT2. The pulse width control circuit 140 can also adjust the voltage level of the node N2 to be the low voltage VL minus the voltage variation ΔV of the light emitting control signal EM through the coupling effect of the capacitor C2 as the pulse width control signal PWCS according to the voltage level of the control terminal CT1, the voltage level of the control terminal CT2 and the pulled-down light emitting control signal EM. That is, the voltage level of the node N2 at this time is VL - ΔV. It should be noted that the above-mentioned voltage variation ΔV is the voltage difference between the high voltage value VH and the low voltage value VL (i.e., VH - VL).

[0073] The pulse amplitude control circuit 120 can provide the voltage difference between the system high voltage VDD and the light emitting bias voltage VLED of the light emitting diode LD1 to the node N5 through the conducting paths of the transistors T8 and T9 according to the voltage level of the node N2, the pulled-up control signal S1[n], the pulled-up control signal S1[n+1] and the pulled-down light emitting control signal EM. That is, the voltage level of the node N5 at this time is VDD - VLED. Further, the pulse amplitude control circuit 120 can adjust the voltage level of the node N7 to be the sum of the voltage difference between the voltage level of the node N5 and the reference voltage VREF2 and the voltage value of the reference voltage VREF1 and the voltage difference between the threshold voltage VTH12 of the transistor T12 according to the coupling effect of the capacitor C5. That is, the voltage level of the node N7 at this time is (VDD - VLED - VREF2 + VREF1 - |VTH12|).

[0074] In this case, the transistor T12 of the pulse amplitude control circuit 120 can generate the driving current Id according to the voltage level of the node N7. At this time, the size of the driving current Id flowing through the light emitting diode LD1 can be calculated based on the following equation (1).

[0075] Id = K (VDD - VLED - VDD + VLED + VREF2 - VREF1 + |VTH12| - |VTH12|) 2 = K (VREF2 - VREF1) 2 (1)

[0076] wherein K is a process parameter of transistor T12. According to the above equation, when pixel circuit 100 operates in emission phase EP, the on current Id generated by pixel circuit 100 is independent of the voltage values of threshold voltage VTH12 of transistor T12 and system high voltage VDD. In this way, pixel circuit 100 can improve the effect of the shift of threshold voltage VTH12 of transistor T12 caused by process difference or long-time operation. Moreover, the on current Id generated by pixel circuit 100 is less likely to be affected by the line resistance in the path of system high voltage VDD and system low voltage VSS.

[0077] Next, in the sub-phase EP2 of emission phase EP, the source-gate voltage VSG of transistor T1 of pulse width control circuit 140 is greater than the threshold voltage VTH1 of transistor T1, that is, the voltage level of control terminal CT1 (VREF1 - VDATA + |VTH6| + ΔVSWEEP) is greater than the threshold voltage VTH1 of transistor T1 (|VTH1|). Since transistor T1 and transistor T6 are matched with each other (i.e., threshold voltage VTH1 is equal to threshold voltage VTH6), the voltage variation ΔVSWEEP is greater than the voltage difference between data voltage VDATA and reference voltage VREF1 (i.e., VDATA - VREF1). Accordingly, according to the voltage level of control terminal CT1, the voltage level of control terminal CT2 and the pulled-down emission control signal EM, transistors T1 and T2 of pulse width control circuit 140 are turned on and reference voltage VREF1 is provided to nodes N1 and N2 through the on paths of transistors T1 and T2 to turn off transistor T8. That is, when pixel circuit 100 operates in the sub-phase EP2 of emission phase EP, pixel circuit 100 can turn off transistor T8 according to the voltage level of node N2 and stop generating driving current Id.

[0078] After the emission actions of the nodes are completed, please refer to Figure 2 , Figure 3F In this embodiment, Figure 3Fis an equivalent circuit diagram of the pixel circuit 100 operating in the emission phase TE. Specifically, in the emission phase TE, the control signal S1[n], the control signal S1[n+1], the reference voltage VREF3, the emission control signal EM, and the scan voltage VSWEEP can be set to a low voltage level (e.g., a low voltage VL and a scan low voltage VSLW, respectively).

[0079] In detail, in the emission phase TE, the pulse width control circuit 140 adjusts the voltage level of the control terminal CT1 to be a voltage difference between the data voltage VDATA and the threshold voltage VTH6 of the transistor T6 (i.e., VDATA - |VTH6|) again through the coupling effect of the capacitor C3. The pulse width control circuit 140 can adjust the voltage level of the node N2 to be the emission cutoff voltage VM through the coupling effect of the capacitor C2 according to the emission control signal EM being pulled high, provide the emission cutoff voltage VM to the node N1 through the conduction path of the transistor T2 according to the reference voltage VREF3 being pulled low, and turn off the transistor T8 to stop lighting the light emitting diode LD1.

[0080] It is worth noting that the emission cutoff voltage VM is less than the reference voltage VREF2 and greater than the system high voltage VDD.

[0081] According to the above, the embodiment of the present application can propose a 15T5C circuit architecture for a micro light emitting diode pixel circuit, which is applied to a micro light emitting diode tiled display. The pixel circuit 100 can operate the light emitting diode at the optimal light emitting efficiency point through pulse-width modulation (PWM) control to reduce the power consumption at low gray scale, and compensate for the threshold voltage variation of the transistors T1, T2, and T12 and the voltage drop (I-R Drop) variation of the system high voltage VDD, which can increase the consistency of the driving current and improve the display quality.

[0082] Figure 4 is a flowchart of a driving method of the pixel circuit according to an embodiment of the present application. Please refer to Figure 1 and Figure 4 The method 400 of the embodiment is applicable to the pixel circuit 100 of Figure 1 The detailed steps of the driving method of the pixel circuit of the present application will be described below in combination with the operating relationship between the elements in the pixel circuit 100.

[0083] In step S420, the pulse amplitude control circuit 120 generates the driving current Id of the light-emitting diode LD1 based on the control signals S1[n], S[n+1], the light emission control signal EM, and the pulse width control signal PWCS, and controls the magnitude of the driving current Id based on the reference voltages VREF1 and VREF2. In step S440, the pulse width control circuit 140 adjusts the voltage level of the control terminal CT1 based on the control signals S1[n], S[n+1], and the scanning voltage VSWEEP. In step S460, the pulse width control circuit 140 adjusts the voltage level of the control terminal CT2 based on the reference voltage VREF3. In step S480, the pulse width control circuit 140 generates the pulse width control signal PWCS based on the voltage levels of the control terminals CT1 and CT2, and the light emission control signal EM, to control the transient time and light emission time of the light-emitting diode LD1.

[0084] about Figure 4 The implementation details of each step are explained in detail in the aforementioned embodiments and implementation methods, so they will not be repeated here.

[0085] Figure 5 This is a schematic diagram of a pixel circuit according to an embodiment of the present invention. Please refer to... Figure 5 In this embodiment, Figure 5 Pixel circuit 500 and Figure 1 The only difference between pixel circuit 100 and pixel circuit 500 is the type of transistor; all transistors in pixel circuit 500 are N-type transistors.

[0086] Figure 6 According to the present invention Figure 5 A schematic diagram of the driving waveform of the pixel circuit in the embodiment. (About...) Figure 5 The implementation details of the pixel circuit 500 operation at each stage can be found in Figure 1 The implementation details of the pixel circuit 100 operation at each stage are deduced from the above-mentioned embodiments and implementation methods, and will not be repeated here.

[0087] In summary, the pixel circuits of the embodiments of the present invention can control the luminous brightness (driving current magnitude) of the light-emitting diode (LED) through a pulse amplitude control circuit, and control the transient time and luminous duration of the LED through a fast rise architecture in the pulse width control circuit. In this way, the pixel circuit can reduce the transient time of the LED through this fast rise architecture, enabling the LED to operate at its optimal luminous efficiency point to reduce power consumption, and also achieving the effect of improving the voltage drop caused by the line resistance of the transmission path and the critical voltage variation of the transistor at high system voltage.

[0088] Although the present application has been disclosed in the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present application, and the protection scope of the present application is defined by the claims.

Claims

1. A pixel circuit, comprising: A light-emitting diode, the anode of which is coupled to a system high voltage; A pulse amplitude control circuit is coupled between the cathode of the light-emitting diode and a system low voltage. It generates a driving current for the light-emitting diode according to a first control signal, a second control signal, a light emission control signal and a pulse width control signal, and controls the magnitude of the driving current according to a first reference voltage and a second reference voltage. as well as A pulse width control circuit has a first control terminal and a second control terminal. The pulse width control circuit is coupled between a pulse amplitude control circuit and a first reference voltage. It adjusts the voltage level of the first control terminal based on the first control signal, the second control signal, and a scanning voltage; adjusts the voltage level of the second control terminal based on a third reference voltage; and generates the pulse width control signal based on the voltage levels of the first and second control terminals and the light emission control signal to control the transient time and light emission time of the light-emitting diode. The pulse width control circuit includes: A first transistor, having a first terminal coupled to the first reference voltage, a second terminal coupled to a first node, and a control terminal coupled to the first control terminal; A first capacitor, with its first terminal coupled to the first node and its second terminal coupled to a low voltage; A second transistor, having a first terminal coupled to the first node, a second terminal coupled to a second node generating the pulse width control signal, and a control terminal coupled to a second control terminal; and A second capacitor, the first end of which is coupled to the second node, and the second end of which receives the light emission control signal. The pulse amplitude control circuit includes: A seventh transistor, the first terminal of which is coupled to the cathode of the light-emitting diode, the second terminal of which is coupled to the first reference voltage, and the control terminal of which receives the second control signal; An eighth transistor, the first terminal of which is coupled to the cathode of the light-emitting diode, the second terminal of which is coupled to a fourth node, and the control terminal of which is coupled to the second node to receive the pulse width control signal; A ninth transistor, the first terminal of which is coupled to a fifth node, the second terminal of which is coupled to the fourth node, and the control terminal of which receives the light emission control signal; A fourth capacitor, the first end of which is coupled to the fifth node, and the second end of which is coupled to a low voltage; A tenth transistor, the first terminal of which is coupled to the second reference voltage, the second terminal of which is coupled to the fifth node, and the control terminal of which receives the first control signal; An eleventh transistor, the first terminal of which is coupled to the second reference voltage, the second terminal of which is coupled to the fifth node, and the control terminal of which receives the second control signal; A twelfth transistor, the first terminal of which is coupled to the fourth node, the second terminal of which is coupled to a sixth node, and the control terminal of which is coupled to a seventh node; A fifth capacitor, the first end of which is coupled to the fifth node, and the second end of which is coupled to the seventh node; A thirteenth transistor, the first terminal of which is coupled to the low voltage, the second terminal of which is coupled to the seventh node, and the control terminal of which receives the first control signal; A fourteenth transistor, the first terminal of which is coupled to the sixth node, the second terminal of which is coupled to the seventh node, and the control terminal of which receives the second control signal; and A fifteenth transistor, the first terminal of which is coupled to the sixth node, the second terminal of which is coupled to the system low voltage, and the control terminal of which receives the light emission control signal.

2. The pixel circuit as claimed in claim 1, wherein the pulse width control circuit further comprises: A third transistor, the first terminal of which is coupled to the second node, the second terminal of which is coupled to the low voltage, and the control terminal of which receives the second control signal; A fourth transistor, the first terminal of which is coupled to the low voltage, and the second terminal of which is coupled to the first control terminal, the control terminal receiving the first control signal; A third capacitor, the first end of which is coupled to the scanning voltage, and the second end of which is coupled to the first control terminal; A fifth transistor, the first terminal of which is coupled to the first control terminal, the second terminal of which is coupled to a third node, and the control terminal of which receives the second control signal; and A sixth transistor, the first terminal and its control terminal of which are coupled to the third node, and the second terminal of which is coupled to a data voltage.

3. The pixel circuit of claim 2, wherein the first transistor and the sixth transistor are matched to each other.

4. The pixel circuit as described in claim 2, wherein the second control signal is the first control signal of the next stage.

5. The pixel circuit as claimed in claim 1, wherein all transistors in the pulse amplitude control circuit and all transistors in the pulse width control circuit are P-type transistors or N-type transistors.

6. The pixel circuit of claim 1, wherein when the pixel circuit operates in a reset phase, the pulse width control circuit provides a low voltage to the first control terminal to pull down the voltage level of the first control terminal based on the first control signal that is pulled down, the second control signal that is pulled up, and the scan voltage that is pulled up; provides the low voltage to the second control terminal to pull down the voltage level of the second control terminal based on the third reference voltage that is pulled down; and provides the first reference voltage as the pulse width control signal based on the voltage level of the first control terminal, the voltage level of the second control terminal, and the light emission control signal that is pulled up.

7. The pixel circuit of claim 1, wherein when the pixel circuit operates in a compensation phase, the pulse width control circuit provides a voltage difference between a data voltage and a threshold voltage of a transistor to the first control terminal to raise the voltage level of the first control terminal based on the first control signal that is raised, the second control signal that is lowered, and the scan voltage that is raised, and provides a low voltage to the second control terminal to lower the voltage level of the second control terminal based on the third reference voltage that is lowered, and provides the low voltage as the pulse width control signal based on the voltage level of the first control terminal, the voltage level of the second control terminal, and the light emission control signal that is raised.

8. The pixel circuit of claim 1, wherein when the pixel circuit operates in an adjustment phase, the pulse width control circuit provides a voltage value to the first control terminal by subtracting the voltage change of the scanning voltage from the voltage difference between a data voltage and a threshold voltage of a transistor, based on the first control signal that is pulled up, the second control signal that is pulled up, and the scan voltage that is pulled down at a predetermined slope, to pull up the voltage level of the first control terminal; provides a high voltage to the second control terminal based on the third reference voltage that is pulled up, to pull up the voltage level of the second control terminal; and provides a low voltage as the pulse width control signal based on the voltage level of the first control terminal, the voltage level of the second control terminal, and the light emission control signal that is pulled up.

9. The pixel circuit of claim 1, wherein when the pixel circuit operates in a first sub-stage of a light emission stage, the pulse width control circuit provides a voltage value to the first control terminal by subtracting the voltage change of the scan voltage from the voltage difference between a data voltage and a threshold voltage of a transistor, based on the first control signal that is pulled up, the second control signal that is pulled up, and the scan voltage that is pulled down at a predetermined slope, to pull up the voltage level of the first control terminal; provides a high voltage to the second control terminal based on the third reference voltage that is pulled up, to pull up the voltage level of the second control terminal; and provides a low voltage as the pulse width control signal by subtracting the voltage change of the light emission control signal based on the voltage level of the first control terminal, the voltage level of the second control terminal, and the light emission control signal that is pulled down.

10. The pixel circuit of claim 9, wherein when the pixel circuit operates in a second sub-stage of the light emission stage, the voltage value of the voltage change of the scan voltage is greater than the voltage value of the data voltage minus the voltage value of the first reference voltage to provide the low voltage to pull down the voltage level of the first control terminal and the voltage level of the second control terminal, and the first reference voltage is provided as the pulse width control signal based on the voltage level of the first control terminal, the voltage level of the second control terminal and the pulled-down light emission control signal.

11. A method for driving a pixel circuit, comprising: A pulse amplitude control circuit generates a driving current for a light-emitting diode based on a first control signal, a second control signal, a light emission control signal, and a pulse width control signal, and controls the magnitude of the driving current based on a first reference voltage and a second reference voltage. A pulse width control circuit adjusts the voltage level of a first control terminal based on the first control signal, the second control signal, and a scanning voltage. The pulse width control circuit adjusts the voltage level of the second control terminal according to a third reference voltage. as well as A pulse width control circuit generates a pulse width control signal based on the voltage level of the first control terminal, the voltage level of the second control terminal, and the light emission control signal to control the transient time and light emission time of the light-emitting diode. The pulse width control circuit includes: A first transistor, having a first terminal coupled to the first reference voltage, a second terminal coupled to a first node, and a control terminal coupled to the first control terminal; A first capacitor, with its first terminal coupled to the first node and its second terminal coupled to a low voltage; A second transistor, having a first terminal coupled to the first node, a second terminal coupled to a second node generating the pulse width control signal, and a control terminal coupled to a second control terminal; and A second capacitor, the first end of which is coupled to the second node, and the second end of which receives the light emission control signal. The pulse amplitude control circuit includes: A seventh transistor, the first terminal of which is coupled to the cathode of the light-emitting diode, the second terminal of which is coupled to the first reference voltage, and the control terminal of which receives the second control signal; An eighth transistor, the first terminal of which is coupled to the cathode of the light-emitting diode, the second terminal of which is coupled to a fourth node, and the control terminal of which is coupled to the second node to receive the pulse width control signal; A ninth transistor, the first terminal of which is coupled to a fifth node, the second terminal of which is coupled to the fourth node, and the control terminal of which receives the light emission control signal; A fourth capacitor, the first end of which is coupled to the fifth node, and the second end of which is coupled to a low voltage; A tenth transistor, the first terminal of which is coupled to the second reference voltage, the second terminal of which is coupled to the fifth node, and the control terminal of which receives the first control signal; An eleventh transistor, the first terminal of which is coupled to the second reference voltage, the second terminal of which is coupled to the fifth node, and the control terminal of which receives the second control signal; A twelfth transistor, the first terminal of which is coupled to the fourth node, the second terminal of which is coupled to a sixth node, and the control terminal of which is coupled to a seventh node; A fifth capacitor, the first end of which is coupled to the fifth node, and the second end of which is coupled to the seventh node; A thirteenth transistor, the first terminal of which is coupled to the low voltage, the second terminal of which is coupled to the seventh node, and the control terminal of which receives the first control signal; A fourteenth transistor, the first terminal of which is coupled to the sixth node, the second terminal of which is coupled to the seventh node, and the control terminal of which receives the second control signal; and A fifteenth transistor, the first terminal of which is coupled to the sixth node, the second terminal of which is coupled to a system low voltage, and the control terminal of which receives the light emission control signal.

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